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src/cpu/mips/vm/globals_mips.hpp@3fb3ceb7398f
src/cpu/mips/vm/globals_mips.hpp
Tue, 12 Dec 2017 10:30:27 +0800
- author
- aoqi
- date
- Tue, 12 Dec 2017 10:30:27 +0800
- changeset 8019
- 3fb3ceb7398f
- parent 7994
- 04ff2f6cd0eb
- child 9155
- 30adb9fd9663
- permissions
- -rw-r--r--
#6345 sync is controled by UseSyncLevel instead of Use3A2000
Reviewed-by: fujie
1 /*
2 * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
26 #ifndef CPU_MIPS_VM_GLOBALS_MIPS_HPP
27 #define CPU_MIPS_VM_GLOBALS_MIPS_HPP
29 #include "utilities/globalDefinitions.hpp"
30 #include "utilities/macros.hpp"
32 // Sets the default values for platform dependent flags used by the runtime system.
33 // (see globals.hpp)
35 #ifdef CORE
36 define_pd_global(bool, UseSSE, 0);
37 #endif /* CORE */
38 define_pd_global(bool, ConvertSleepToYield, true);
39 define_pd_global(bool, ShareVtableStubs, true);
40 define_pd_global(bool, CountInterpCalls, true);
42 define_pd_global(bool, ImplicitNullChecks, true); // Generate code for implicit null checks
43 define_pd_global(bool, TrapBasedNullChecks, false); // Not needed on x86.
44 define_pd_global(bool, UncommonNullCast, true); // Uncommon-trap NULLs passed to check cast
45 define_pd_global(bool, NeedsDeoptSuspend, false); // only register window machines need this
47 // See 4827828 for this change. There is no globals_core_i486.hpp. I can't
48 // assign a different value for C2 without touching a number of files. Use
49 // #ifdef to minimize the change as it's late in Mantis. -- FIXME.
50 // c1 doesn't have this problem because the fix to 4858033 assures us
51 // the the vep is aligned at CodeEntryAlignment whereas c2 only aligns
52 // the uep and the vep doesn't get real alignment but just slops on by
53 // only assured that the entry instruction meets the 5 byte size requirement.
54 define_pd_global(intx, CodeEntryAlignment, 16);
55 define_pd_global(intx, OptoLoopAlignment, 16);
56 define_pd_global(intx, InlineFrequencyCount, 100);
57 define_pd_global(intx, InlineSmallCode, 4000); // 2016/5/11 Jin: MIPS generates 3x instructions than X86
59 define_pd_global(uintx, TLABSize, 0);
60 define_pd_global(uintx, NewSize, 1024 * K);
61 define_pd_global(intx, PreInflateSpin, 10);
63 define_pd_global(intx, PrefetchCopyIntervalInBytes, -1);
64 define_pd_global(intx, PrefetchScanIntervalInBytes, -1);
65 define_pd_global(intx, PrefetchFieldsAhead, -1);
67 define_pd_global(intx, StackYellowPages, 2);
68 define_pd_global(intx, StackRedPages, 1);
69 define_pd_global(intx, StackShadowPages, 3 DEBUG_ONLY(+1));
71 define_pd_global(bool, RewriteBytecodes, true);
72 define_pd_global(bool, RewriteFrequentPairs, true);
73 #ifdef _ALLBSD_SOURCE
74 define_pd_global(bool, UseMembar, true);
75 #else
76 define_pd_global(bool, UseMembar, false);
77 #endif
78 // GC Ergo Flags
79 define_pd_global(intx, CMSYoungGenPerWorker, 64*M); // default max size of CMS young gen, per GC worker thread
81 define_pd_global(uintx, TypeProfileLevel, 111);
83 define_pd_global(bool, PreserveFramePointer, false);
84 // Only c2 cares about this at the moment
85 define_pd_global(intx, AllocatePrefetchStyle, 2);
86 define_pd_global(intx, AllocatePrefetchDistance, -1);
88 #define ARCH_FLAGS(develop, product, diagnostic, experimental, notproduct) \
89 \
90 product(bool, UseLoongsonISA, false, \
91 "Use LoongsonISA on Loongson CPUs") \
92 \
93 product(bool, Use3A2000, false, \
94 "Use Loongson 3A2000 CPU") \
95 \
96 product(bool, UseCodeCacheAllocOpt, true, \
97 "Allocate code cache within 32-bit memory address space") \
98 \
99 product(intx, UseSyncLevel, 3000, \
100 "The sync level on Loongson CPUs" \
101 "default: for all Loongson CPUs, UseSyncLevel == 3000, " \
102 "for GS464E, UseSyncLevel == 2000" \
103 "for GS464, UseSyncLevel == 1000") \
104 \
105 develop(bool, UseBoundCheckInstruction, false, \
106 "Use bound check instruction") \
107 \
108 product(intx, SetFSFOFN, 999, \
109 "Set the FS/FO/FN bits in FCSR" \
110 "999 means FS/FO/FN will not be changed" \
111 "=XYZ, with X:FS, Y:FO, Z:FN, X, Y and Z in 0=off, 1=on") \
112 \
113 develop(bool, IEEEPrecision, true, \
114 "Enables IEEE precision (for INTEL only)") \
115 \
116 product(intx, FenceInstruction, 0, \
117 "(Unsafe,Unstable) Experimental") \
118 \
119 product(intx, ReadPrefetchInstr, 0, \
120 "Prefetch instruction to prefetch ahead") \
121 \
122 product(bool, UseStoreImmI16, true, \
123 "Use store immediate 16-bits value instruction on x86") \
124 \
125 product(intx, UseAVX, 99, \
126 "Highest supported AVX instructions set on x86/x64") \
127 \
128 diagnostic(bool, UseIncDec, true, \
129 "Use INC, DEC instructions on x86") \
130 \
131 product(bool, UseNewLongLShift, false, \
132 "Use optimized bitwise shift left") \
133 \
134 product(bool, UseAddressNop, false, \
135 "Use '0F 1F [addr]' NOP instructions on x86 cpus") \
136 \
137 product(bool, UseXmmLoadAndClearUpper, true, \
138 "Load low part of XMM register and clear upper part") \
139 \
140 product(bool, UseXmmRegToRegMoveAll, false, \
141 "Copy all XMM register bits when moving value between registers") \
142 \
143 product(bool, UseXmmI2D, false, \
144 "Use SSE2 CVTDQ2PD instruction to convert Integer to Double") \
145 \
146 product(bool, UseXmmI2F, false, \
147 "Use SSE2 CVTDQ2PS instruction to convert Integer to Float") \
148 \
149 product(bool, UseUnalignedLoadStores, false, \
150 "Use SSE2 MOVDQU instruction for Arraycopy") \
151 \
152 /* assembler */ \
153 product(bool, Use486InstrsOnly, false, \
154 "Use 80486 Compliant instruction subset") \
155 \
156 product(bool, UseCountLeadingZerosInstruction, true, \
157 "Use count leading zeros instruction") \
158 \
159 product(bool, UseCountTrailingZerosInstruction, false, \
160 "Use count trailing zeros instruction") \
161 \
162 product(bool, UseBMI1Instructions, false, \
163 "Use BMI instructions")
165 #endif // CPU_MIPS_VM_GLOBALS_MIPS_HPP
