Tue, 31 May 2016 00:22:06 -0400
[Code Reorganization] load_two_bytes_from_at_bcp -> get_2_byte_integer_at_bcp
remove useless MacroAssembler::store_two_byts_to_at_bcp
change MacroAssembler::load_two_bytes_from_at_bcp to InterpreterMacroAssembler::get_2_byte_integer_at_bcp
change MacroAssembler::get_4_byte_integer_at_bcp to InterpreterMacroAssembler::get_4_byte_integer_at_bcp
1 /*
2 * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
26 #ifndef CPU_MIPS_VM_C1_DEFS_MIPS_HPP
27 #define CPU_MIPS_VM_C1_DEFS_MIPS_HPP
29 // native word offsets from memory address (little endian)
30 enum {
31 pd_lo_word_offset_in_bytes = 0,
32 pd_hi_word_offset_in_bytes = BytesPerWord
33 };
35 // explicit rounding operations are required to implement the strictFP mode
36 // i486 is true here, i dont think gs2 need this
37 // by yjl 8/15/2005
38 enum {
39 pd_strict_fp_requires_explicit_rounding = false
40 };
43 // registers
44 enum {
45 pd_nof_cpu_regs_frame_map = 32, // number of registers used during code emission
46 // v0, v1, t0-t7, s0-s7
47 // now, we just think s# as caller saved. maybe we should change this to allow cache local
48 // pd_nof_caller_save_cpu_regs_frame_map = 18, // number of registers killed by calls
49 // t0-t7, s0-s7, v0, v1
51 pd_nof_caller_save_cpu_regs_frame_map = 18, // number of registers killed by calls
52 pd_nof_cpu_regs_reg_alloc = 18, // number of registers that are visible to register allocator
53 pd_nof_cpu_regs_linearscan = 32, // number of registers visible to linear scan
54 pd_first_cpu_reg = 0,
55 pd_last_cpu_reg = 31,
56 pd_last_allocatable_cpu_reg=20,
57 pd_first_callee_saved_reg = 0,
58 pd_last_callee_saved_reg = 13,
60 #ifdef _LP64
61 pd_nof_fpu_regs_frame_map = 32, // number of registers used during code emission
62 pd_nof_fpu_regs_reg_alloc = 32, // number of registers that are visible to register allocator
63 pd_nof_caller_save_fpu_regs_frame_map = 32, // number of fpu registers killed by calls
64 pd_nof_fpu_regs_linearscan = 32,// number of registers visible linear scan
65 #else
66 pd_nof_fpu_regs_frame_map = 16, // number of registers used during code emission
67 pd_nof_fpu_regs_reg_alloc = 16, // number of registers that are visible to register allocator
68 pd_nof_caller_save_fpu_regs_frame_map = 16, // number of fpu registers killed by calls
69 pd_nof_fpu_regs_linearscan = 16,// number of registers visible linear scan
70 #endif
71 pd_first_fpu_reg = pd_nof_cpu_regs_frame_map,
72 pd_last_fpu_reg = pd_nof_cpu_regs_frame_map + pd_nof_fpu_regs_frame_map - 1,
74 pd_nof_xmm_regs_linearscan = 0,
75 pd_nof_caller_save_xmm_regs = 0,
76 pd_first_xmm_reg = -1,
77 pd_last_xmm_reg = -1
78 };
81 // encoding of float value in debug info:
82 enum {
83 pd_float_saved_as_double = true
84 };
86 #endif // CPU_MIPS_VM_C1_DEFS_MIPS_HPP