Mercurial > jdk8-mips64-public > hotspot / annotate
src/cpu/mips/vm/c1_Defs_mips.hpp@3cedde979d75 (annotated)
src/cpu/mips/vm/c1_Defs_mips.hpp
Tue, 31 May 2016 00:22:06 -0400
- author
- aoqi
- date
- Tue, 31 May 2016 00:22:06 -0400
- changeset 16
- 3cedde979d75
- parent 1
- 2d8a650513c2
- child 6880
- 52ea28d233d2
- permissions
- -rw-r--r--
[Code Reorganization] load_two_bytes_from_at_bcp -> get_2_byte_integer_at_bcp
remove useless MacroAssembler::store_two_byts_to_at_bcp
change MacroAssembler::load_two_bytes_from_at_bcp to InterpreterMacroAssembler::get_2_byte_integer_at_bcp
change MacroAssembler::get_4_byte_integer_at_bcp to InterpreterMacroAssembler::get_4_byte_integer_at_bcp
| aoqi@1 | 1 | /* |
| aoqi@1 | 2 | * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved. |
| aoqi@1 | 3 | * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved. |
| aoqi@1 | 4 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| aoqi@1 | 5 | * |
| aoqi@1 | 6 | * This code is free software; you can redistribute it and/or modify it |
| aoqi@1 | 7 | * under the terms of the GNU General Public License version 2 only, as |
| aoqi@1 | 8 | * published by the Free Software Foundation. |
| aoqi@1 | 9 | * |
| aoqi@1 | 10 | * This code is distributed in the hope that it will be useful, but WITHOUT |
| aoqi@1 | 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| aoqi@1 | 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| aoqi@1 | 13 | * version 2 for more details (a copy is included in the LICENSE file that |
| aoqi@1 | 14 | * accompanied this code). |
| aoqi@1 | 15 | * |
| aoqi@1 | 16 | * You should have received a copy of the GNU General Public License version |
| aoqi@1 | 17 | * 2 along with this work; if not, write to the Free Software Foundation, |
| aoqi@1 | 18 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
| aoqi@1 | 19 | * |
| aoqi@1 | 20 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
| aoqi@1 | 21 | * or visit www.oracle.com if you need additional information or have any |
| aoqi@1 | 22 | * questions. |
| aoqi@1 | 23 | * |
| aoqi@1 | 24 | */ |
| aoqi@1 | 25 | |
| aoqi@1 | 26 | #ifndef CPU_MIPS_VM_C1_DEFS_MIPS_HPP |
| aoqi@1 | 27 | #define CPU_MIPS_VM_C1_DEFS_MIPS_HPP |
| aoqi@1 | 28 | |
| aoqi@1 | 29 | // native word offsets from memory address (little endian) |
| aoqi@1 | 30 | enum { |
| aoqi@1 | 31 | pd_lo_word_offset_in_bytes = 0, |
| aoqi@1 | 32 | pd_hi_word_offset_in_bytes = BytesPerWord |
| aoqi@1 | 33 | }; |
| aoqi@1 | 34 | |
| aoqi@1 | 35 | // explicit rounding operations are required to implement the strictFP mode |
| aoqi@1 | 36 | // i486 is true here, i dont think gs2 need this |
| aoqi@1 | 37 | // by yjl 8/15/2005 |
| aoqi@1 | 38 | enum { |
| aoqi@1 | 39 | pd_strict_fp_requires_explicit_rounding = false |
| aoqi@1 | 40 | }; |
| aoqi@1 | 41 | |
| aoqi@1 | 42 | |
| aoqi@1 | 43 | // registers |
| aoqi@1 | 44 | enum { |
| aoqi@1 | 45 | pd_nof_cpu_regs_frame_map = 32, // number of registers used during code emission |
| aoqi@1 | 46 | // v0, v1, t0-t7, s0-s7 |
| aoqi@1 | 47 | // now, we just think s# as caller saved. maybe we should change this to allow cache local |
| aoqi@1 | 48 | // pd_nof_caller_save_cpu_regs_frame_map = 18, // number of registers killed by calls |
| aoqi@1 | 49 | // t0-t7, s0-s7, v0, v1 |
| aoqi@1 | 50 | |
| aoqi@1 | 51 | pd_nof_caller_save_cpu_regs_frame_map = 18, // number of registers killed by calls |
| aoqi@1 | 52 | pd_nof_cpu_regs_reg_alloc = 18, // number of registers that are visible to register allocator |
| aoqi@1 | 53 | pd_nof_cpu_regs_linearscan = 32, // number of registers visible to linear scan |
| aoqi@1 | 54 | pd_first_cpu_reg = 0, |
| aoqi@1 | 55 | pd_last_cpu_reg = 31, |
| aoqi@1 | 56 | pd_last_allocatable_cpu_reg=20, |
| aoqi@1 | 57 | pd_first_callee_saved_reg = 0, |
| aoqi@1 | 58 | pd_last_callee_saved_reg = 13, |
| aoqi@1 | 59 | |
| aoqi@1 | 60 | #ifdef _LP64 |
| aoqi@1 | 61 | pd_nof_fpu_regs_frame_map = 32, // number of registers used during code emission |
| aoqi@1 | 62 | pd_nof_fpu_regs_reg_alloc = 32, // number of registers that are visible to register allocator |
| aoqi@1 | 63 | pd_nof_caller_save_fpu_regs_frame_map = 32, // number of fpu registers killed by calls |
| aoqi@1 | 64 | pd_nof_fpu_regs_linearscan = 32,// number of registers visible linear scan |
| aoqi@1 | 65 | #else |
| aoqi@1 | 66 | pd_nof_fpu_regs_frame_map = 16, // number of registers used during code emission |
| aoqi@1 | 67 | pd_nof_fpu_regs_reg_alloc = 16, // number of registers that are visible to register allocator |
| aoqi@1 | 68 | pd_nof_caller_save_fpu_regs_frame_map = 16, // number of fpu registers killed by calls |
| aoqi@1 | 69 | pd_nof_fpu_regs_linearscan = 16,// number of registers visible linear scan |
| aoqi@1 | 70 | #endif |
| aoqi@1 | 71 | pd_first_fpu_reg = pd_nof_cpu_regs_frame_map, |
| aoqi@1 | 72 | pd_last_fpu_reg = pd_nof_cpu_regs_frame_map + pd_nof_fpu_regs_frame_map - 1, |
| aoqi@1 | 73 | |
| aoqi@1 | 74 | pd_nof_xmm_regs_linearscan = 0, |
| aoqi@1 | 75 | pd_nof_caller_save_xmm_regs = 0, |
| aoqi@1 | 76 | pd_first_xmm_reg = -1, |
| aoqi@1 | 77 | pd_last_xmm_reg = -1 |
| aoqi@1 | 78 | }; |
| aoqi@1 | 79 | |
| aoqi@1 | 80 | |
| aoqi@1 | 81 | // encoding of float value in debug info: |
| aoqi@1 | 82 | enum { |
| aoqi@1 | 83 | pd_float_saved_as_double = true |
| aoqi@1 | 84 | }; |
| aoqi@1 | 85 | |
| aoqi@1 | 86 | #endif // CPU_MIPS_VM_C1_DEFS_MIPS_HPP |
