Thu, 05 Jun 2008 15:57:56 -0700
6711316: Open source the Garbage-First garbage collector
Summary: First mercurial integration of the code for the Garbage-First garbage collector.
Reviewed-by: apetrusenko, iveresov, jmasa, sgoldman, tonyp, ysr
1 /*
2 * Copyright 2003-2007 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
25 class BiasedLockingCounters;
27 // Contains all the definitions needed for amd64 assembly code generation.
29 #ifdef _LP64
30 // Calling convention
31 class Argument VALUE_OBJ_CLASS_SPEC {
32 public:
33 enum {
34 #ifdef _WIN64
35 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
36 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
37 #else
38 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
39 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... )
40 #endif // _WIN64
41 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
42 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
43 };
44 };
47 // Symbolically name the register arguments used by the c calling convention.
48 // Windows is different from linux/solaris. So much for standards...
50 #ifdef _WIN64
52 REGISTER_DECLARATION(Register, c_rarg0, rcx);
53 REGISTER_DECLARATION(Register, c_rarg1, rdx);
54 REGISTER_DECLARATION(Register, c_rarg2, r8);
55 REGISTER_DECLARATION(Register, c_rarg3, r9);
57 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
58 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
59 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
60 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
62 #else
64 REGISTER_DECLARATION(Register, c_rarg0, rdi);
65 REGISTER_DECLARATION(Register, c_rarg1, rsi);
66 REGISTER_DECLARATION(Register, c_rarg2, rdx);
67 REGISTER_DECLARATION(Register, c_rarg3, rcx);
68 REGISTER_DECLARATION(Register, c_rarg4, r8);
69 REGISTER_DECLARATION(Register, c_rarg5, r9);
71 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
72 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
73 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
74 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
75 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
76 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
77 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
78 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
80 #endif // _WIN64
82 // Symbolically name the register arguments used by the Java calling convention.
83 // We have control over the convention for java so we can do what we please.
84 // What pleases us is to offset the java calling convention so that when
85 // we call a suitable jni method the arguments are lined up and we don't
86 // have to do little shuffling. A suitable jni method is non-static and a
87 // small number of arguments (two fewer args on windows)
88 //
89 // |-------------------------------------------------------|
90 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 |
91 // |-------------------------------------------------------|
92 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg)
93 // | rdi rsi rdx rcx r8 r9 | solaris/linux
94 // |-------------------------------------------------------|
95 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 |
96 // |-------------------------------------------------------|
98 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
99 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
100 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
101 // Windows runs out of register args here
102 #ifdef _WIN64
103 REGISTER_DECLARATION(Register, j_rarg3, rdi);
104 REGISTER_DECLARATION(Register, j_rarg4, rsi);
105 #else
106 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
107 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
108 #endif // _WIN64
109 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
111 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
112 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
113 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
114 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
115 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
116 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
117 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
118 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
120 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile
121 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile
123 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
124 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
126 #endif // _LP64
128 // Address is an abstraction used to represent a memory location
129 // using any of the amd64 addressing modes with one object.
130 //
131 // Note: A register location is represented via a Register, not
132 // via an address for efficiency & simplicity reasons.
134 class ArrayAddress;
136 class Address VALUE_OBJ_CLASS_SPEC {
137 public:
138 enum ScaleFactor {
139 no_scale = -1,
140 times_1 = 0,
141 times_2 = 1,
142 times_4 = 2,
143 times_8 = 3
144 };
146 private:
147 Register _base;
148 Register _index;
149 ScaleFactor _scale;
150 int _disp;
151 RelocationHolder _rspec;
153 // Easily misused constructors make them private
154 Address(int disp, address loc, relocInfo::relocType rtype);
155 Address(int disp, address loc, RelocationHolder spec);
157 public:
158 // creation
159 Address()
160 : _base(noreg),
161 _index(noreg),
162 _scale(no_scale),
163 _disp(0) {
164 }
166 // No default displacement otherwise Register can be implicitly
167 // converted to 0(Register) which is quite a different animal.
169 Address(Register base, int disp)
170 : _base(base),
171 _index(noreg),
172 _scale(no_scale),
173 _disp(disp) {
174 }
176 Address(Register base, Register index, ScaleFactor scale, int disp = 0)
177 : _base (base),
178 _index(index),
179 _scale(scale),
180 _disp (disp) {
181 assert(!index->is_valid() == (scale == Address::no_scale),
182 "inconsistent address");
183 }
185 // The following two overloads are used in connection with the
186 // ByteSize type (see sizes.hpp). They simplify the use of
187 // ByteSize'd arguments in assembly code. Note that their equivalent
188 // for the optimized build are the member functions with int disp
189 // argument since ByteSize is mapped to an int type in that case.
190 //
191 // Note: DO NOT introduce similar overloaded functions for WordSize
192 // arguments as in the optimized mode, both ByteSize and WordSize
193 // are mapped to the same type and thus the compiler cannot make a
194 // distinction anymore (=> compiler errors).
196 #ifdef ASSERT
197 Address(Register base, ByteSize disp)
198 : _base(base),
199 _index(noreg),
200 _scale(no_scale),
201 _disp(in_bytes(disp)) {
202 }
204 Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
205 : _base(base),
206 _index(index),
207 _scale(scale),
208 _disp(in_bytes(disp)) {
209 assert(!index->is_valid() == (scale == Address::no_scale),
210 "inconsistent address");
211 }
212 #endif // ASSERT
214 // accessors
215 bool uses(Register reg) const {
216 return _base == reg || _index == reg;
217 }
219 // Convert the raw encoding form into the form expected by the constructor for
220 // Address. An index of 4 (rsp) corresponds to having no index, so convert
221 // that to noreg for the Address constructor.
222 static Address make_raw(int base, int index, int scale, int disp);
224 static Address make_array(ArrayAddress);
225 Register base() const {
226 return _base;
227 }
229 Register index() const {
230 return _index;
231 }
233 int disp() const {
234 return _disp;
235 }
238 private:
239 bool base_needs_rex() const {
240 return _base != noreg && _base->encoding() >= 8;
241 }
243 bool index_needs_rex() const {
244 return _index != noreg &&_index->encoding() >= 8;
245 }
247 relocInfo::relocType reloc() const { return _rspec.type(); }
249 friend class Assembler;
250 friend class MacroAssembler;
251 friend class LIR_Assembler; // base/index/scale/disp
252 };
254 //
255 // AddressLiteral has been split out from Address because operands of this type
256 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
257 // the few instructions that need to deal with address literals are unique and the
258 // MacroAssembler does not have to implement every instruction in the Assembler
259 // in order to search for address literals that may need special handling depending
260 // on the instruction and the platform. As small step on the way to merging i486/amd64
261 // directories.
262 //
263 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
264 friend class ArrayAddress;
265 RelocationHolder _rspec;
266 // Typically we use AddressLiterals we want to use their rval
267 // However in some situations we want the lval (effect address) of the item.
268 // We provide a special factory for making those lvals.
269 bool _is_lval;
271 // If the target is far we'll need to load the ea of this to
272 // a register to reach it. Otherwise if near we can do rip
273 // relative addressing.
275 address _target;
277 protected:
278 // creation
279 AddressLiteral()
280 : _is_lval(false),
281 _target(NULL)
282 {}
284 public:
287 AddressLiteral(address target, relocInfo::relocType rtype);
289 AddressLiteral(address target, RelocationHolder const& rspec)
290 : _rspec(rspec),
291 _is_lval(false),
292 _target(target)
293 {}
295 AddressLiteral addr() {
296 AddressLiteral ret = *this;
297 ret._is_lval = true;
298 return ret;
299 }
302 private:
304 address target() { return _target; }
305 bool is_lval() { return _is_lval; }
307 relocInfo::relocType reloc() const { return _rspec.type(); }
308 const RelocationHolder& rspec() const { return _rspec; }
310 friend class Assembler;
311 friend class MacroAssembler;
312 friend class Address;
313 friend class LIR_Assembler;
314 };
316 // Convience classes
317 class RuntimeAddress: public AddressLiteral {
319 public:
321 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
323 };
325 class OopAddress: public AddressLiteral {
327 public:
329 OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){}
331 };
333 class ExternalAddress: public AddressLiteral {
335 public:
337 ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){}
339 };
341 class InternalAddress: public AddressLiteral {
343 public:
345 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
347 };
349 // x86 can do array addressing as a single operation since disp can be an absolute
350 // address but amd64 can't [e.g. array_base(rx, ry:width) ]. We create a class
351 // that expresses the concept but does extra magic on amd64 to get the final result
353 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
354 private:
356 AddressLiteral _base;
357 Address _index;
359 public:
361 ArrayAddress() {};
362 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
363 AddressLiteral base() { return _base; }
364 Address index() { return _index; }
366 };
368 // The amd64 Assembler: Pure assembler doing NO optimizations on
369 // the instruction level (e.g. mov rax, 0 is not translated into xor
370 // rax, rax!); i.e., what you write is what you get. The Assembler is
371 // generating code into a CodeBuffer.
373 const int FPUStateSizeInWords = 512 / wordSize;
375 class Assembler : public AbstractAssembler {
376 friend class AbstractAssembler; // for the non-virtual hack
377 friend class StubGenerator;
380 protected:
381 #ifdef ASSERT
382 void check_relocation(RelocationHolder const& rspec, int format);
383 #endif
385 inline void emit_long64(jlong x);
387 void emit_data(jint data, relocInfo::relocType rtype, int format /* = 1 */);
388 void emit_data(jint data, RelocationHolder const& rspec, int format /* = 1 */);
389 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
390 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
392 // Helper functions for groups of instructions
393 void emit_arith_b(int op1, int op2, Register dst, int imm8);
395 void emit_arith(int op1, int op2, Register dst, int imm32);
396 // only x86??
397 void emit_arith(int op1, int op2, Register dst, jobject obj);
398 void emit_arith(int op1, int op2, Register dst, Register src);
400 void emit_operand(Register reg,
401 Register base, Register index, Address::ScaleFactor scale,
402 int disp,
403 RelocationHolder const& rspec,
404 int rip_relative_correction = 0);
405 void emit_operand(Register reg, Address adr,
406 int rip_relative_correction = 0);
407 void emit_operand(XMMRegister reg,
408 Register base, Register index, Address::ScaleFactor scale,
409 int disp,
410 RelocationHolder const& rspec,
411 int rip_relative_correction = 0);
412 void emit_operand(XMMRegister reg, Address adr,
413 int rip_relative_correction = 0);
415 // Immediate-to-memory forms
416 void emit_arith_operand(int op1, Register rm, Address adr, int imm32);
418 void emit_farith(int b1, int b2, int i);
420 bool reachable(AddressLiteral adr);
422 // These are all easily abused and hence protected
424 // Make these disappear in 64bit mode since they would never be correct
425 #ifndef _LP64
426 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec);
427 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec);
429 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec);
430 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec);
432 void push_literal32(int32_t imm32, RelocationHolder const& rspec);
433 #endif // _LP64
436 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec);
438 // These are unique in that we are ensured by the caller that the 32bit
439 // relative in these instructions will always be able to reach the potentially
440 // 64bit address described by entry. Since they can take a 64bit address they
441 // don't have the 32 suffix like the other instructions in this class.
442 void jmp_literal(address entry, RelocationHolder const& rspec);
443 void call_literal(address entry, RelocationHolder const& rspec);
445 public:
446 enum Condition { // The amd64 condition codes used for conditional jumps/moves.
447 zero = 0x4,
448 notZero = 0x5,
449 equal = 0x4,
450 notEqual = 0x5,
451 less = 0xc,
452 lessEqual = 0xe,
453 greater = 0xf,
454 greaterEqual = 0xd,
455 below = 0x2,
456 belowEqual = 0x6,
457 above = 0x7,
458 aboveEqual = 0x3,
459 overflow = 0x0,
460 noOverflow = 0x1,
461 carrySet = 0x2,
462 carryClear = 0x3,
463 negative = 0x8,
464 positive = 0x9,
465 parity = 0xa,
466 noParity = 0xb
467 };
469 enum Prefix {
470 // segment overrides
471 // XXX remove segment prefixes
472 CS_segment = 0x2e,
473 SS_segment = 0x36,
474 DS_segment = 0x3e,
475 ES_segment = 0x26,
476 FS_segment = 0x64,
477 GS_segment = 0x65,
479 REX = 0x40,
481 REX_B = 0x41,
482 REX_X = 0x42,
483 REX_XB = 0x43,
484 REX_R = 0x44,
485 REX_RB = 0x45,
486 REX_RX = 0x46,
487 REX_RXB = 0x47,
489 REX_W = 0x48,
491 REX_WB = 0x49,
492 REX_WX = 0x4A,
493 REX_WXB = 0x4B,
494 REX_WR = 0x4C,
495 REX_WRB = 0x4D,
496 REX_WRX = 0x4E,
497 REX_WRXB = 0x4F
498 };
500 enum WhichOperand {
501 // input to locate_operand, and format code for relocations
502 imm64_operand = 0, // embedded 64-bit immediate operand
503 disp32_operand = 1, // embedded 32-bit displacement
504 call32_operand = 2, // embedded 32-bit self-relative displacement
505 _WhichOperand_limit = 3
506 };
508 public:
510 // Creation
511 Assembler(CodeBuffer* code)
512 : AbstractAssembler(code) {
513 }
515 // Decoding
516 static address locate_operand(address inst, WhichOperand which);
517 static address locate_next_instruction(address inst);
519 // Utilities
521 static bool is_simm(int64_t x, int nbits) { return -( CONST64(1) << (nbits-1) ) <= x && x < ( CONST64(1) << (nbits-1) ); }
522 static bool is_simm32 (int64_t x) { return x == (int64_t)(int32_t)x; }
525 // Stack
526 void pushaq();
527 void popaq();
529 void pushfq();
530 void popfq();
532 void pushq(int imm32);
534 void pushq(Register src);
535 void pushq(Address src);
537 void popq(Register dst);
538 void popq(Address dst);
540 // Instruction prefixes
541 void prefix(Prefix p);
543 int prefix_and_encode(int reg_enc, bool byteinst = false);
544 int prefixq_and_encode(int reg_enc);
546 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false);
547 int prefixq_and_encode(int dst_enc, int src_enc);
549 void prefix(Register reg);
550 void prefix(Address adr);
551 void prefixq(Address adr);
553 void prefix(Address adr, Register reg, bool byteinst = false);
554 void prefixq(Address adr, Register reg);
556 void prefix(Address adr, XMMRegister reg);
558 // Moves
559 void movb(Register dst, Address src);
560 void movb(Address dst, int imm8);
561 void movb(Address dst, Register src);
563 void movw(Address dst, int imm16);
564 void movw(Register dst, Address src);
565 void movw(Address dst, Register src);
567 void movl(Register dst, int imm32);
568 void movl(Register dst, Register src);
569 void movl(Register dst, Address src);
570 void movl(Address dst, int imm32);
571 void movl(Address dst, Register src);
573 void movq(Register dst, Register src);
574 void movq(Register dst, Address src);
575 void movq(Address dst, Register src);
576 // These prevent using movq from converting a zero (like NULL) into Register
577 // by giving the compiler two choices it can't resolve
578 void movq(Address dst, void* dummy);
579 void movq(Register dst, void* dummy);
581 void mov64(Register dst, intptr_t imm64);
582 void mov64(Address dst, intptr_t imm64);
584 void movsbl(Register dst, Address src);
585 void movsbl(Register dst, Register src);
586 void movswl(Register dst, Address src);
587 void movswl(Register dst, Register src);
588 void movslq(Register dst, Address src);
589 void movslq(Register dst, Register src);
591 void movzbl(Register dst, Address src);
592 void movzbl(Register dst, Register src);
593 void movzwl(Register dst, Address src);
594 void movzwl(Register dst, Register src);
596 protected: // Avoid using the next instructions directly.
597 // New cpus require use of movsd and movss to avoid partial register stall
598 // when loading from memory. But for old Opteron use movlpd instead of movsd.
599 // The selection is done in MacroAssembler::movdbl() and movflt().
600 void movss(XMMRegister dst, XMMRegister src);
601 void movss(XMMRegister dst, Address src);
602 void movss(Address dst, XMMRegister src);
603 void movsd(XMMRegister dst, XMMRegister src);
604 void movsd(Address dst, XMMRegister src);
605 void movsd(XMMRegister dst, Address src);
606 void movlpd(XMMRegister dst, Address src);
607 // New cpus require use of movaps and movapd to avoid partial register stall
608 // when moving between registers.
609 void movapd(XMMRegister dst, XMMRegister src);
610 void movaps(XMMRegister dst, XMMRegister src);
611 public:
613 void movdl(XMMRegister dst, Register src);
614 void movdl(Register dst, XMMRegister src);
615 void movdq(XMMRegister dst, Register src);
616 void movdq(Register dst, XMMRegister src);
618 void cmovl(Condition cc, Register dst, Register src);
619 void cmovl(Condition cc, Register dst, Address src);
620 void cmovq(Condition cc, Register dst, Register src);
621 void cmovq(Condition cc, Register dst, Address src);
623 // Prefetches
624 private:
625 void prefetch_prefix(Address src);
626 public:
627 void prefetcht0(Address src);
628 void prefetcht1(Address src);
629 void prefetcht2(Address src);
630 void prefetchnta(Address src);
631 void prefetchw(Address src);
633 // Arithmetics
634 void adcl(Register dst, int imm32);
635 void adcl(Register dst, Address src);
636 void adcl(Register dst, Register src);
637 void adcq(Register dst, int imm32);
638 void adcq(Register dst, Address src);
639 void adcq(Register dst, Register src);
641 void addl(Address dst, int imm32);
642 void addl(Address dst, Register src);
643 void addl(Register dst, int imm32);
644 void addl(Register dst, Address src);
645 void addl(Register dst, Register src);
646 void addq(Address dst, int imm32);
647 void addq(Address dst, Register src);
648 void addq(Register dst, int imm32);
649 void addq(Register dst, Address src);
650 void addq(Register dst, Register src);
652 void andl(Register dst, int imm32);
653 void andl(Register dst, Address src);
654 void andl(Register dst, Register src);
655 void andq(Register dst, int imm32);
656 void andq(Register dst, Address src);
657 void andq(Register dst, Register src);
659 void cmpb(Address dst, int imm8);
660 void cmpl(Address dst, int imm32);
661 void cmpl(Register dst, int imm32);
662 void cmpl(Register dst, Register src);
663 void cmpl(Register dst, Address src);
664 void cmpq(Address dst, int imm32);
665 void cmpq(Address dst, Register src);
666 void cmpq(Register dst, int imm32);
667 void cmpq(Register dst, Register src);
668 void cmpq(Register dst, Address src);
670 void ucomiss(XMMRegister dst, XMMRegister src);
671 void ucomisd(XMMRegister dst, XMMRegister src);
673 protected:
674 // Don't use next inc() and dec() methods directly. INC & DEC instructions
675 // could cause a partial flag stall since they don't set CF flag.
676 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
677 // which call inc() & dec() or add() & sub() in accordance with
678 // the product flag UseIncDec value.
680 void decl(Register dst);
681 void decl(Address dst);
682 void decq(Register dst);
683 void decq(Address dst);
685 void incl(Register dst);
686 void incl(Address dst);
687 void incq(Register dst);
688 void incq(Address dst);
690 public:
691 void idivl(Register src);
692 void idivq(Register src);
693 void cdql();
694 void cdqq();
696 void imull(Register dst, Register src);
697 void imull(Register dst, Register src, int value);
698 void imulq(Register dst, Register src);
699 void imulq(Register dst, Register src, int value);
701 void leal(Register dst, Address src);
702 void leaq(Register dst, Address src);
704 void mull(Address src);
705 void mull(Register src);
707 void negl(Register dst);
708 void negq(Register dst);
710 void notl(Register dst);
711 void notq(Register dst);
713 void orl(Address dst, int imm32);
714 void orl(Register dst, int imm32);
715 void orl(Register dst, Address src);
716 void orl(Register dst, Register src);
717 void orq(Address dst, int imm32);
718 void orq(Register dst, int imm32);
719 void orq(Register dst, Address src);
720 void orq(Register dst, Register src);
722 void rcll(Register dst, int imm8);
723 void rclq(Register dst, int imm8);
725 void sarl(Register dst, int imm8);
726 void sarl(Register dst);
727 void sarq(Register dst, int imm8);
728 void sarq(Register dst);
730 void sbbl(Address dst, int imm32);
731 void sbbl(Register dst, int imm32);
732 void sbbl(Register dst, Address src);
733 void sbbl(Register dst, Register src);
734 void sbbq(Address dst, int imm32);
735 void sbbq(Register dst, int imm32);
736 void sbbq(Register dst, Address src);
737 void sbbq(Register dst, Register src);
739 void shll(Register dst, int imm8);
740 void shll(Register dst);
741 void shlq(Register dst, int imm8);
742 void shlq(Register dst);
744 void shrl(Register dst, int imm8);
745 void shrl(Register dst);
746 void shrq(Register dst, int imm8);
747 void shrq(Register dst);
749 void subl(Address dst, int imm32);
750 void subl(Address dst, Register src);
751 void subl(Register dst, int imm32);
752 void subl(Register dst, Address src);
753 void subl(Register dst, Register src);
754 void subq(Address dst, int imm32);
755 void subq(Address dst, Register src);
756 void subq(Register dst, int imm32);
757 void subq(Register dst, Address src);
758 void subq(Register dst, Register src);
760 void testb(Register dst, int imm8);
761 void testl(Register dst, int imm32);
762 void testl(Register dst, Register src);
763 void testq(Register dst, int imm32);
764 void testq(Register dst, Register src);
766 void xaddl(Address dst, Register src);
767 void xaddq(Address dst, Register src);
769 void xorl(Register dst, int imm32);
770 void xorl(Register dst, Address src);
771 void xorl(Register dst, Register src);
772 void xorq(Register dst, int imm32);
773 void xorq(Register dst, Address src);
774 void xorq(Register dst, Register src);
776 // Miscellaneous
777 void bswapl(Register reg);
778 void bswapq(Register reg);
779 void lock();
781 void xchgl(Register reg, Address adr);
782 void xchgl(Register dst, Register src);
783 void xchgq(Register reg, Address adr);
784 void xchgq(Register dst, Register src);
786 void cmpxchgl(Register reg, Address adr);
787 void cmpxchgq(Register reg, Address adr);
789 void nop(int i = 1);
790 void addr_nop_4();
791 void addr_nop_5();
792 void addr_nop_7();
793 void addr_nop_8();
795 void hlt();
796 void ret(int imm16);
797 void smovl();
798 void rep_movl();
799 void rep_movq();
800 void rep_set();
801 void repne_scanl();
802 void repne_scanq();
803 void setb(Condition cc, Register dst);
805 void clflush(Address adr);
807 enum Membar_mask_bits {
808 StoreStore = 1 << 3,
809 LoadStore = 1 << 2,
810 StoreLoad = 1 << 1,
811 LoadLoad = 1 << 0
812 };
814 // Serializes memory.
815 void membar(Membar_mask_bits order_constraint) {
816 // We only have to handle StoreLoad and LoadLoad
817 if (order_constraint & StoreLoad) {
818 // MFENCE subsumes LFENCE
819 mfence();
820 } /* [jk] not needed currently: else if (order_constraint & LoadLoad) {
821 lfence();
822 } */
823 }
825 void lfence() {
826 emit_byte(0x0F);
827 emit_byte(0xAE);
828 emit_byte(0xE8);
829 }
831 void mfence() {
832 emit_byte(0x0F);
833 emit_byte(0xAE);
834 emit_byte(0xF0);
835 }
837 // Identify processor type and features
838 void cpuid() {
839 emit_byte(0x0F);
840 emit_byte(0xA2);
841 }
843 void cld() { emit_byte(0xfc);
844 }
846 void std() { emit_byte(0xfd);
847 }
850 // Calls
852 void call(Label& L, relocInfo::relocType rtype);
853 void call(Register reg);
854 void call(Address adr);
856 // Jumps
858 void jmp(Register reg);
859 void jmp(Address adr);
861 // Label operations & relative jumps (PPUM Appendix D)
862 // unconditional jump to L
863 void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none);
866 // Unconditional 8-bit offset jump to L.
867 // WARNING: be very careful using this for forward jumps. If the label is
868 // not bound within an 8-bit offset of this instruction, a run-time error
869 // will occur.
870 void jmpb(Label& L);
872 // jcc is the generic conditional branch generator to run- time
873 // routines, jcc is used for branches to labels. jcc takes a branch
874 // opcode (cc) and a label (L) and generates either a backward
875 // branch or a forward branch and links it to the label fixup
876 // chain. Usage:
877 //
878 // Label L; // unbound label
879 // jcc(cc, L); // forward branch to unbound label
880 // bind(L); // bind label to the current pc
881 // jcc(cc, L); // backward branch to bound label
882 // bind(L); // illegal: a label may be bound only once
883 //
884 // Note: The same Label can be used for forward and backward branches
885 // but it may be bound only once.
887 void jcc(Condition cc, Label& L,
888 relocInfo::relocType rtype = relocInfo::none);
890 // Conditional jump to a 8-bit offset to L.
891 // WARNING: be very careful using this for forward jumps. If the label is
892 // not bound within an 8-bit offset of this instruction, a run-time error
893 // will occur.
894 void jccb(Condition cc, Label& L);
896 // Floating-point operations
898 void fxsave(Address dst);
899 void fxrstor(Address src);
900 void ldmxcsr(Address src);
901 void stmxcsr(Address dst);
903 void addss(XMMRegister dst, XMMRegister src);
904 void addss(XMMRegister dst, Address src);
905 void subss(XMMRegister dst, XMMRegister src);
906 void subss(XMMRegister dst, Address src);
907 void mulss(XMMRegister dst, XMMRegister src);
908 void mulss(XMMRegister dst, Address src);
909 void divss(XMMRegister dst, XMMRegister src);
910 void divss(XMMRegister dst, Address src);
911 void addsd(XMMRegister dst, XMMRegister src);
912 void addsd(XMMRegister dst, Address src);
913 void subsd(XMMRegister dst, XMMRegister src);
914 void subsd(XMMRegister dst, Address src);
915 void mulsd(XMMRegister dst, XMMRegister src);
916 void mulsd(XMMRegister dst, Address src);
917 void divsd(XMMRegister dst, XMMRegister src);
918 void divsd(XMMRegister dst, Address src);
920 // We only need the double form
921 void sqrtsd(XMMRegister dst, XMMRegister src);
922 void sqrtsd(XMMRegister dst, Address src);
924 void xorps(XMMRegister dst, XMMRegister src);
925 void xorps(XMMRegister dst, Address src);
926 void xorpd(XMMRegister dst, XMMRegister src);
927 void xorpd(XMMRegister dst, Address src);
929 void cvtsi2ssl(XMMRegister dst, Register src);
930 void cvtsi2ssq(XMMRegister dst, Register src);
931 void cvtsi2sdl(XMMRegister dst, Register src);
932 void cvtsi2sdq(XMMRegister dst, Register src);
933 void cvttss2sil(Register dst, XMMRegister src); // truncates
934 void cvttss2siq(Register dst, XMMRegister src); // truncates
935 void cvttsd2sil(Register dst, XMMRegister src); // truncates
936 void cvttsd2siq(Register dst, XMMRegister src); // truncates
937 void cvtss2sd(XMMRegister dst, XMMRegister src);
938 void cvtsd2ss(XMMRegister dst, XMMRegister src);
939 void cvtdq2pd(XMMRegister dst, XMMRegister src);
940 void cvtdq2ps(XMMRegister dst, XMMRegister src);
942 void pxor(XMMRegister dst, Address src); // Xor Packed Byte Integer Values
943 void pxor(XMMRegister dst, XMMRegister src); // Xor Packed Byte Integer Values
945 void movdqa(XMMRegister dst, Address src); // Move Aligned Double Quadword
946 void movdqa(XMMRegister dst, XMMRegister src);
947 void movdqa(Address dst, XMMRegister src);
949 void movq(XMMRegister dst, Address src);
950 void movq(Address dst, XMMRegister src);
952 void pshufd(XMMRegister dst, XMMRegister src, int mode); // Shuffle Packed Doublewords
953 void pshufd(XMMRegister dst, Address src, int mode);
954 void pshuflw(XMMRegister dst, XMMRegister src, int mode); // Shuffle Packed Low Words
955 void pshuflw(XMMRegister dst, Address src, int mode);
957 void psrlq(XMMRegister dst, int shift); // Shift Right Logical Quadword Immediate
959 void punpcklbw(XMMRegister dst, XMMRegister src); // Interleave Low Bytes
960 void punpcklbw(XMMRegister dst, Address src);
961 };
964 // MacroAssembler extends Assembler by frequently used macros.
965 //
966 // Instructions for which a 'better' code sequence exists depending
967 // on arguments should also go in here.
969 class MacroAssembler : public Assembler {
970 friend class LIR_Assembler;
971 protected:
973 Address as_Address(AddressLiteral adr);
974 Address as_Address(ArrayAddress adr);
976 // Support for VM calls
977 //
978 // This is the base routine called by the different versions of
979 // call_VM_leaf. The interpreter may customize this version by
980 // overriding it for its purposes (e.g., to save/restore additional
981 // registers when doing a VM call).
983 virtual void call_VM_leaf_base(
984 address entry_point, // the entry point
985 int number_of_arguments // the number of arguments to
986 // pop after the call
987 );
989 // This is the base routine called by the different versions of
990 // call_VM. The interpreter may customize this version by overriding
991 // it for its purposes (e.g., to save/restore additional registers
992 // when doing a VM call).
993 //
994 // If no java_thread register is specified (noreg) than rdi will be
995 // used instead. call_VM_base returns the register which contains
996 // the thread upon return. If a thread register has been specified,
997 // the return value will correspond to that register. If no
998 // last_java_sp is specified (noreg) than rsp will be used instead.
999 virtual void call_VM_base( // returns the register
1000 // containing the thread upon
1001 // return
1002 Register oop_result, // where an oop-result ends up
1003 // if any; use noreg otherwise
1004 Register java_thread, // the thread if computed
1005 // before ; use noreg otherwise
1006 Register last_java_sp, // to set up last_Java_frame in
1007 // stubs; use noreg otherwise
1008 address entry_point, // the entry point
1009 int number_of_arguments, // the number of arguments (w/o
1010 // thread) to pop after the
1011 // call
1012 bool check_exceptions // whether to check for pending
1013 // exceptions after return
1014 );
1016 // This routines should emit JVMTI PopFrame handling and ForceEarlyReturn code.
1017 // The implementation is only non-empty for the InterpreterMacroAssembler,
1018 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
1019 virtual void check_and_handle_popframe(Register java_thread);
1020 virtual void check_and_handle_earlyret(Register java_thread);
1022 void call_VM_helper(Register oop_result,
1023 address entry_point,
1024 int number_of_arguments,
1025 bool check_exceptions = true);
1027 public:
1028 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
1030 // Support for NULL-checks
1031 //
1032 // Generates code that causes a NULL OS exception if the content of
1033 // reg is NULL. If the accessed location is M[reg + offset] and the
1034 // offset is known, provide the offset. No explicit code generation
1035 // is needed if the offset is within a certain range (0 <= offset <=
1036 // page_size).
1037 void null_check(Register reg, int offset = -1);
1038 static bool needs_explicit_null_check(int offset);
1040 // Required platform-specific helpers for Label::patch_instructions.
1041 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
1042 void pd_patch_instruction(address branch, address target);
1043 #ifndef PRODUCT
1044 static void pd_print_patched_instruction(address branch);
1045 #endif
1048 // The following 4 methods return the offset of the appropriate move
1049 // instruction. Note: these are 32 bit instructions
1051 // Support for fast byte/word loading with zero extension (depending
1052 // on particular CPU)
1053 int load_unsigned_byte(Register dst, Address src);
1054 int load_unsigned_word(Register dst, Address src);
1056 // Support for fast byte/word loading with sign extension (depending
1057 // on particular CPU)
1058 int load_signed_byte(Register dst, Address src);
1059 int load_signed_word(Register dst, Address src);
1061 // Support for inc/dec with optimal instruction selection depending
1062 // on value
1063 void incrementl(Register reg, int value = 1);
1064 void decrementl(Register reg, int value = 1);
1065 void incrementq(Register reg, int value = 1);
1066 void decrementq(Register reg, int value = 1);
1068 void incrementl(Address dst, int value = 1);
1069 void decrementl(Address dst, int value = 1);
1070 void incrementq(Address dst, int value = 1);
1071 void decrementq(Address dst, int value = 1);
1073 // Support optimal SSE move instructions.
1074 void movflt(XMMRegister dst, XMMRegister src) {
1075 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
1076 else { movss (dst, src); return; }
1077 }
1079 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
1081 void movflt(XMMRegister dst, AddressLiteral src);
1083 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
1085 void movdbl(XMMRegister dst, XMMRegister src) {
1086 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
1087 else { movsd (dst, src); return; }
1088 }
1090 void movdbl(XMMRegister dst, AddressLiteral src);
1092 void movdbl(XMMRegister dst, Address src) {
1093 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
1094 else { movlpd(dst, src); return; }
1095 }
1097 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
1099 void incrementl(AddressLiteral dst);
1100 void incrementl(ArrayAddress dst);
1102 // Alignment
1103 void align(int modulus);
1105 // Misc
1106 void fat_nop(); // 5 byte nop
1109 // C++ bool manipulation
1111 void movbool(Register dst, Address src);
1112 void movbool(Address dst, bool boolconst);
1113 void movbool(Address dst, Register src);
1114 void testbool(Register dst);
1116 // oop manipulations
1117 void load_klass(Register dst, Register src);
1118 void store_klass(Register dst, Register src);
1120 void load_heap_oop(Register dst, Address src);
1121 void store_heap_oop(Address dst, Register src);
1122 void encode_heap_oop(Register r);
1123 void decode_heap_oop(Register r);
1124 void encode_heap_oop_not_null(Register r);
1125 void decode_heap_oop_not_null(Register r);
1126 void encode_heap_oop_not_null(Register dst, Register src);
1127 void decode_heap_oop_not_null(Register dst, Register src);
1129 // Stack frame creation/removal
1130 void enter();
1131 void leave();
1133 // Support for getting the JavaThread pointer (i.e.; a reference to
1134 // thread-local information) The pointer will be loaded into the
1135 // thread register.
1136 void get_thread(Register thread);
1138 void int3();
1140 // Support for VM calls
1141 //
1142 // It is imperative that all calls into the VM are handled via the
1143 // call_VM macros. They make sure that the stack linkage is setup
1144 // correctly. call_VM's correspond to ENTRY/ENTRY_X entry points
1145 // while call_VM_leaf's correspond to LEAF entry points.
1146 void call_VM(Register oop_result,
1147 address entry_point,
1148 bool check_exceptions = true);
1149 void call_VM(Register oop_result,
1150 address entry_point,
1151 Register arg_1,
1152 bool check_exceptions = true);
1153 void call_VM(Register oop_result,
1154 address entry_point,
1155 Register arg_1, Register arg_2,
1156 bool check_exceptions = true);
1157 void call_VM(Register oop_result,
1158 address entry_point,
1159 Register arg_1, Register arg_2, Register arg_3,
1160 bool check_exceptions = true);
1162 // Overloadings with last_Java_sp
1163 void call_VM(Register oop_result,
1164 Register last_java_sp,
1165 address entry_point,
1166 int number_of_arguments = 0,
1167 bool check_exceptions = true);
1168 void call_VM(Register oop_result,
1169 Register last_java_sp,
1170 address entry_point,
1171 Register arg_1, bool
1172 check_exceptions = true);
1173 void call_VM(Register oop_result,
1174 Register last_java_sp,
1175 address entry_point,
1176 Register arg_1, Register arg_2,
1177 bool check_exceptions = true);
1178 void call_VM(Register oop_result,
1179 Register last_java_sp,
1180 address entry_point,
1181 Register arg_1, Register arg_2, Register arg_3,
1182 bool check_exceptions = true);
1184 void call_VM_leaf(address entry_point,
1185 int number_of_arguments = 0);
1186 void call_VM_leaf(address entry_point,
1187 Register arg_1);
1188 void call_VM_leaf(address entry_point,
1189 Register arg_1, Register arg_2);
1190 void call_VM_leaf(address entry_point,
1191 Register arg_1, Register arg_2, Register arg_3);
1193 // last Java Frame (fills frame anchor)
1194 void set_last_Java_frame(Register last_java_sp,
1195 Register last_java_fp,
1196 address last_java_pc);
1197 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
1199 // Stores
1200 void store_check(Register obj); // store check for
1201 // obj - register is
1202 // destroyed
1203 // afterwards
1204 void store_check(Register obj, Address dst); // same as above, dst
1205 // is exact store
1206 // location (reg. is
1207 // destroyed)
1209 void g1_write_barrier_pre(Register obj, Register tmp, Register tmp2, bool tosca_live );
1210 void g1_write_barrier_post(Register store_addr, Register new_val, Register tmp, Register tmp2);
1212 // split store_check(Register obj) to enhance instruction interleaving
1213 void store_check_part_1(Register obj);
1214 void store_check_part_2(Register obj);
1216 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
1217 void c2bool(Register x);
1219 // Int division/reminder for Java
1220 // (as idivl, but checks for special case as described in JVM spec.)
1221 // returns idivl instruction offset for implicit exception handling
1222 int corrected_idivl(Register reg);
1223 // Long division/reminder for Java
1224 // (as idivq, but checks for special case as described in JVM spec.)
1225 // returns idivq instruction offset for implicit exception handling
1226 int corrected_idivq(Register reg);
1228 // Push and pop integer/fpu/cpu state
1229 void push_IU_state();
1230 void pop_IU_state();
1232 void push_FPU_state();
1233 void pop_FPU_state();
1235 void push_CPU_state();
1236 void pop_CPU_state();
1238 // Sign extension
1239 void sign_extend_short(Register reg);
1240 void sign_extend_byte(Register reg);
1242 // Division by power of 2, rounding towards 0
1243 void division_with_shift(Register reg, int shift_value);
1245 // Round up to a power of two
1246 void round_to_l(Register reg, int modulus);
1247 void round_to_q(Register reg, int modulus);
1249 // allocation
1250 void eden_allocate(
1251 Register obj, // result: pointer to object after
1252 // successful allocation
1253 Register var_size_in_bytes, // object size in bytes if unknown at
1254 // compile time; invalid otherwise
1255 int con_size_in_bytes, // object size in bytes if known at
1256 // compile time
1257 Register t1, // temp register
1258 Label& slow_case // continuation point if fast
1259 // allocation fails
1260 );
1261 void tlab_allocate(
1262 Register obj, // result: pointer to object after
1263 // successful allocation
1264 Register var_size_in_bytes, // object size in bytes if unknown at
1265 // compile time; invalid otherwise
1266 int con_size_in_bytes, // object size in bytes if known at
1267 // compile time
1268 Register t1, // temp register
1269 Register t2, // temp register
1270 Label& slow_case // continuation point if fast
1271 // allocation fails
1272 );
1273 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
1275 //----
1277 // Debugging
1279 // only if +VerifyOops
1280 void verify_oop(Register reg, const char* s = "broken oop");
1281 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
1283 // if heap base register is used - reinit it with the correct value
1284 void reinit_heapbase();
1286 // only if +VerifyFPU
1287 void verify_FPU(int stack_depth, const char* s = "illegal FPU state") {}
1289 // prints msg, dumps registers and stops execution
1290 void stop(const char* msg);
1292 // prints message and continues
1293 void warn(const char* msg);
1295 static void debug(char* msg, int64_t pc, int64_t regs[]);
1297 void os_breakpoint();
1299 void untested()
1300 {
1301 stop("untested");
1302 }
1304 void unimplemented(const char* what = "")
1305 {
1306 char* b = new char[1024];
1307 sprintf(b, "unimplemented: %s", what);
1308 stop(b);
1309 }
1311 void should_not_reach_here()
1312 {
1313 stop("should not reach here");
1314 }
1316 // Stack overflow checking
1317 void bang_stack_with_offset(int offset)
1318 {
1319 // stack grows down, caller passes positive offset
1320 assert(offset > 0, "must bang with negative offset");
1321 movl(Address(rsp, (-offset)), rax);
1322 }
1324 // Writes to stack successive pages until offset reached to check for
1325 // stack overflow + shadow pages. Also, clobbers tmp
1326 void bang_stack_size(Register offset, Register tmp);
1328 // Support for serializing memory accesses between threads.
1329 void serialize_memory(Register thread, Register tmp);
1331 void verify_tlab();
1333 // Biased locking support
1334 // lock_reg and obj_reg must be loaded up with the appropriate values.
1335 // swap_reg must be rax and is killed.
1336 // tmp_reg must be supplied and is killed.
1337 // If swap_reg_contains_mark is true then the code assumes that the
1338 // mark word of the object has already been loaded into swap_reg.
1339 // Optional slow case is for implementations (interpreter and C1) which branch to
1340 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
1341 // Returns offset of first potentially-faulting instruction for null
1342 // check info (currently consumed only by C1). If
1343 // swap_reg_contains_mark is true then returns -1 as it is assumed
1344 // the calling code has already passed any potential faults.
1345 int biased_locking_enter(Register lock_reg, Register obj_reg, Register swap_reg, Register tmp_reg,
1346 bool swap_reg_contains_mark,
1347 Label& done, Label* slow_case = NULL,
1348 BiasedLockingCounters* counters = NULL);
1349 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
1351 Condition negate_condition(Condition cond);
1353 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
1354 // operands. In general the names are modified to avoid hiding the instruction in Assembler
1355 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
1356 // here in MacroAssembler. The major exception to this rule is call
1358 // Arithmetics
1360 void cmp8(AddressLiteral src1, int8_t imm32);
1362 void cmp32(AddressLiteral src1, int32_t src2);
1363 // compare reg - mem, or reg - &mem
1364 void cmp32(Register src1, AddressLiteral src2);
1366 void cmp32(Register src1, Address src2);
1368 #ifndef _LP64
1369 void cmpoop(Address dst, jobject obj);
1370 void cmpoop(Register dst, jobject obj);
1371 #endif // _LP64
1373 // NOTE src2 must be the lval. This is NOT an mem-mem compare
1374 void cmpptr(Address src1, AddressLiteral src2);
1376 void cmpptr(Register src1, AddressLiteral src);
1378 // will be cmpreg(?)
1379 void cmp64(Register src1, AddressLiteral src);
1381 void cmpxchgptr(Register reg, Address adr);
1382 void cmpxchgptr(Register reg, AddressLiteral adr);
1384 // Helper functions for statistics gathering.
1385 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
1386 void cond_inc32(Condition cond, AddressLiteral counter_addr);
1387 // Unconditional atomic increment.
1388 void atomic_incl(AddressLiteral counter_addr);
1391 void lea(Register dst, AddressLiteral src);
1392 void lea(Register dst, Address src);
1395 // Calls
1396 void call(Label& L, relocInfo::relocType rtype);
1397 void call(Register entry);
1398 void call(AddressLiteral entry);
1400 // Jumps
1402 // 32bit can do a case table jump in one instruction but we no longer allow the base
1403 // to be installed in the Address class
1404 void jump(ArrayAddress entry);
1406 void jump(AddressLiteral entry);
1407 void jump_cc(Condition cc, AddressLiteral dst);
1409 // Floating
1411 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
1412 void ldmxcsr(AddressLiteral src);
1414 private:
1415 // these are private because users should be doing movflt/movdbl
1417 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1418 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1419 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1420 void movss(XMMRegister dst, AddressLiteral src);
1422 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
1423 void movlpd(XMMRegister dst, AddressLiteral src);
1425 public:
1428 void xorpd(XMMRegister dst, XMMRegister src) {Assembler::xorpd(dst, src); }
1429 void xorpd(XMMRegister dst, Address src) {Assembler::xorpd(dst, src); }
1430 void xorpd(XMMRegister dst, AddressLiteral src);
1432 void xorps(XMMRegister dst, XMMRegister src) {Assembler::xorps(dst, src); }
1433 void xorps(XMMRegister dst, Address src) {Assembler::xorps(dst, src); }
1434 void xorps(XMMRegister dst, AddressLiteral src);
1437 // Data
1439 void movoop(Register dst, jobject obj);
1440 void movoop(Address dst, jobject obj);
1442 void movptr(ArrayAddress dst, Register src);
1443 void movptr(Register dst, AddressLiteral src);
1445 void movptr(Register dst, intptr_t src);
1446 void movptr(Address dst, intptr_t src);
1448 void movptr(Register dst, ArrayAddress src);
1450 // to avoid hiding movl
1451 void mov32(AddressLiteral dst, Register src);
1452 void mov32(Register dst, AddressLiteral src);
1454 void pushoop(jobject obj);
1456 // Can push value or effective address
1457 void pushptr(AddressLiteral src);
1459 };
1461 /**
1462 * class SkipIfEqual:
1463 *
1464 * Instantiating this class will result in assembly code being output that will
1465 * jump around any code emitted between the creation of the instance and it's
1466 * automatic destruction at the end of a scope block, depending on the value of
1467 * the flag passed to the constructor, which will be checked at run-time.
1468 */
1469 class SkipIfEqual {
1470 private:
1471 MacroAssembler* _masm;
1472 Label _label;
1474 public:
1475 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1476 ~SkipIfEqual();
1477 };
1480 #ifdef ASSERT
1481 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; }
1482 #endif