Mon, 09 Mar 2009 03:17:11 -0700
6797305: Add LoadUB and LoadUI opcode class
Summary: Add a LoadUB (unsigned byte) and LoadUI (unsigned int) opcode class so we have these load optimizations in the first place and do not need to handle them in the matcher.
Reviewed-by: never, kvn
1 //
2 // Copyright 1998-2009 Sun Microsystems, Inc. All Rights Reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 // CA 95054 USA or visit www.sun.com if you need additional information or
21 // have any questions.
22 //
23 //
25 // SPARC Architecture Description File
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg());
197 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()->next());
198 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg());
199 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()->next());
200 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg());
201 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()->next());
202 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg());
203 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()->next());
204 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg());
205 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()->next());
206 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg());
207 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()->next());
208 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg());
209 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()->next());
210 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg());
211 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()->next());
212 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg());
213 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()->next());
214 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg());
215 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()->next());
216 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg());
217 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()->next());
218 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg());
219 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()->next());
220 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg());
221 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()->next());
222 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg());
223 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()->next());
224 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg());
225 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()->next());
226 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg());
227 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()->next());
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 );
429 %}
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Must be visible to the DFA in dfa_sparc.cpp
461 extern bool can_branch_register( Node *bol, Node *cmp );
463 // Macros to extract hi & lo halves from a long pair.
464 // G0 is not part of any long pair, so assert on that.
465 // Prevents accidentally using G1 instead of G0.
466 #define LONG_HI_REG(x) (x)
467 #define LONG_LO_REG(x) (x)
469 %}
471 source %{
472 #define __ _masm.
474 // tertiary op of a LoadP or StoreP encoding
475 #define REGP_OP true
477 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
478 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
479 static Register reg_to_register_object(int register_encoding);
481 // Used by the DFA in dfa_sparc.cpp.
482 // Check for being able to use a V9 branch-on-register. Requires a
483 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
484 // extended. Doesn't work following an integer ADD, for example, because of
485 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
486 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
487 // replace them with zero, which could become sign-extension in a different OS
488 // release. There's no obvious reason why an interrupt will ever fill these
489 // bits with non-zero junk (the registers are reloaded with standard LD
490 // instructions which either zero-fill or sign-fill).
491 bool can_branch_register( Node *bol, Node *cmp ) {
492 if( !BranchOnRegister ) return false;
493 #ifdef _LP64
494 if( cmp->Opcode() == Op_CmpP )
495 return true; // No problems with pointer compares
496 #endif
497 if( cmp->Opcode() == Op_CmpL )
498 return true; // No problems with long compares
500 if( !SparcV9RegsHiBitsZero ) return false;
501 if( bol->as_Bool()->_test._test != BoolTest::ne &&
502 bol->as_Bool()->_test._test != BoolTest::eq )
503 return false;
505 // Check for comparing against a 'safe' value. Any operation which
506 // clears out the high word is safe. Thus, loads and certain shifts
507 // are safe, as are non-negative constants. Any operation which
508 // preserves zero bits in the high word is safe as long as each of its
509 // inputs are safe. Thus, phis and bitwise booleans are safe if their
510 // inputs are safe. At present, the only important case to recognize
511 // seems to be loads. Constants should fold away, and shifts &
512 // logicals can use the 'cc' forms.
513 Node *x = cmp->in(1);
514 if( x->is_Load() ) return true;
515 if( x->is_Phi() ) {
516 for( uint i = 1; i < x->req(); i++ )
517 if( !x->in(i)->is_Load() )
518 return false;
519 return true;
520 }
521 return false;
522 }
524 // ****************************************************************************
526 // REQUIRED FUNCTIONALITY
528 // !!!!! Special hack to get all type of calls to specify the byte offset
529 // from the start of the call to the point where the return address
530 // will point.
531 // The "return address" is the address of the call instruction, plus 8.
533 int MachCallStaticJavaNode::ret_addr_offset() {
534 return NativeCall::instruction_size; // call; delay slot
535 }
537 int MachCallDynamicJavaNode::ret_addr_offset() {
538 int vtable_index = this->_vtable_index;
539 if (vtable_index < 0) {
540 // must be invalid_vtable_index, not nonvirtual_vtable_index
541 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
542 return (NativeMovConstReg::instruction_size +
543 NativeCall::instruction_size); // sethi; setlo; call; delay slot
544 } else {
545 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
546 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
547 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
548 int klass_load_size;
549 if (UseCompressedOops) {
550 klass_load_size = 3*BytesPerInstWord; // see MacroAssembler::load_klass()
551 } else {
552 klass_load_size = 1*BytesPerInstWord;
553 }
554 if( Assembler::is_simm13(v_off) ) {
555 return klass_load_size +
556 (2*BytesPerInstWord + // ld_ptr, ld_ptr
557 NativeCall::instruction_size); // call; delay slot
558 } else {
559 return klass_load_size +
560 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
561 NativeCall::instruction_size); // call; delay slot
562 }
563 }
564 }
566 int MachCallRuntimeNode::ret_addr_offset() {
567 #ifdef _LP64
568 return NativeFarCall::instruction_size; // farcall; delay slot
569 #else
570 return NativeCall::instruction_size; // call; delay slot
571 #endif
572 }
574 // Indicate if the safepoint node needs the polling page as an input.
575 // Since Sparc does not have absolute addressing, it does.
576 bool SafePointNode::needs_polling_address_input() {
577 return true;
578 }
580 // emit an interrupt that is caught by the debugger (for debugging compiler)
581 void emit_break(CodeBuffer &cbuf) {
582 MacroAssembler _masm(&cbuf);
583 __ breakpoint_trap();
584 }
586 #ifndef PRODUCT
587 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
588 st->print("TA");
589 }
590 #endif
592 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
593 emit_break(cbuf);
594 }
596 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
597 return MachNode::size(ra_);
598 }
600 // Traceable jump
601 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
602 MacroAssembler _masm(&cbuf);
603 Register rdest = reg_to_register_object(jump_target);
604 __ JMP(rdest, 0);
605 __ delayed()->nop();
606 }
608 // Traceable jump and set exception pc
609 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
610 MacroAssembler _masm(&cbuf);
611 Register rdest = reg_to_register_object(jump_target);
612 __ JMP(rdest, 0);
613 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
614 }
616 void emit_nop(CodeBuffer &cbuf) {
617 MacroAssembler _masm(&cbuf);
618 __ nop();
619 }
621 void emit_illtrap(CodeBuffer &cbuf) {
622 MacroAssembler _masm(&cbuf);
623 __ illtrap(0);
624 }
627 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
628 assert(n->rule() != loadUB_rule, "");
630 intptr_t offset = 0;
631 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
632 const Node* addr = n->get_base_and_disp(offset, adr_type);
633 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
634 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
635 assert(addr->bottom_type()->isa_oopptr() == atype, "");
636 atype = atype->add_offset(offset);
637 assert(disp32 == offset, "wrong disp32");
638 return atype->_offset;
639 }
642 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
643 assert(n->rule() != loadUB_rule, "");
645 intptr_t offset = 0;
646 Node* addr = n->in(2);
647 assert(addr->bottom_type()->isa_oopptr() == atype, "");
648 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
649 Node* a = addr->in(2/*AddPNode::Address*/);
650 Node* o = addr->in(3/*AddPNode::Offset*/);
651 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
652 atype = a->bottom_type()->is_ptr()->add_offset(offset);
653 assert(atype->isa_oop_ptr(), "still an oop");
654 }
655 offset = atype->is_ptr()->_offset;
656 if (offset != Type::OffsetBot) offset += disp32;
657 return offset;
658 }
660 // Standard Sparc opcode form2 field breakdown
661 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
662 f0 &= (1<<19)-1; // Mask displacement to 19 bits
663 int op = (f30 << 30) |
664 (f29 << 29) |
665 (f25 << 25) |
666 (f22 << 22) |
667 (f20 << 20) |
668 (f19 << 19) |
669 (f0 << 0);
670 *((int*)(cbuf.code_end())) = op;
671 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
672 }
674 // Standard Sparc opcode form2 field breakdown
675 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
676 f0 >>= 10; // Drop 10 bits
677 f0 &= (1<<22)-1; // Mask displacement to 22 bits
678 int op = (f30 << 30) |
679 (f25 << 25) |
680 (f22 << 22) |
681 (f0 << 0);
682 *((int*)(cbuf.code_end())) = op;
683 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
684 }
686 // Standard Sparc opcode form3 field breakdown
687 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
688 int op = (f30 << 30) |
689 (f25 << 25) |
690 (f19 << 19) |
691 (f14 << 14) |
692 (f5 << 5) |
693 (f0 << 0);
694 *((int*)(cbuf.code_end())) = op;
695 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
696 }
698 // Standard Sparc opcode form3 field breakdown
699 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
700 simm13 &= (1<<13)-1; // Mask to 13 bits
701 int op = (f30 << 30) |
702 (f25 << 25) |
703 (f19 << 19) |
704 (f14 << 14) |
705 (1 << 13) | // bit to indicate immediate-mode
706 (simm13<<0);
707 *((int*)(cbuf.code_end())) = op;
708 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
709 }
711 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
712 simm10 &= (1<<10)-1; // Mask to 10 bits
713 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
714 }
716 #ifdef ASSERT
717 // Helper function for VerifyOops in emit_form3_mem_reg
718 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
719 warning("VerifyOops encountered unexpected instruction:");
720 n->dump(2);
721 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
722 }
723 #endif
726 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
727 int src1_enc, int disp32, int src2_enc, int dst_enc) {
729 #ifdef ASSERT
730 // The following code implements the +VerifyOops feature.
731 // It verifies oop values which are loaded into or stored out of
732 // the current method activation. +VerifyOops complements techniques
733 // like ScavengeALot, because it eagerly inspects oops in transit,
734 // as they enter or leave the stack, as opposed to ScavengeALot,
735 // which inspects oops "at rest", in the stack or heap, at safepoints.
736 // For this reason, +VerifyOops can sometimes detect bugs very close
737 // to their point of creation. It can also serve as a cross-check
738 // on the validity of oop maps, when used toegether with ScavengeALot.
740 // It would be good to verify oops at other points, especially
741 // when an oop is used as a base pointer for a load or store.
742 // This is presently difficult, because it is hard to know when
743 // a base address is biased or not. (If we had such information,
744 // it would be easy and useful to make a two-argument version of
745 // verify_oop which unbiases the base, and performs verification.)
747 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
748 bool is_verified_oop_base = false;
749 bool is_verified_oop_load = false;
750 bool is_verified_oop_store = false;
751 int tmp_enc = -1;
752 if (VerifyOops && src1_enc != R_SP_enc) {
753 // classify the op, mainly for an assert check
754 int st_op = 0, ld_op = 0;
755 switch (primary) {
756 case Assembler::stb_op3: st_op = Op_StoreB; break;
757 case Assembler::sth_op3: st_op = Op_StoreC; break;
758 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
759 case Assembler::stw_op3: st_op = Op_StoreI; break;
760 case Assembler::std_op3: st_op = Op_StoreL; break;
761 case Assembler::stf_op3: st_op = Op_StoreF; break;
762 case Assembler::stdf_op3: st_op = Op_StoreD; break;
764 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
765 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
766 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
767 case Assembler::ldx_op3: // may become LoadP or stay LoadI
768 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
769 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
770 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
771 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
772 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
773 case Assembler::ldub_op3: ld_op = Op_LoadB; break;
774 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
776 default: ShouldNotReachHere();
777 }
778 if (tertiary == REGP_OP) {
779 if (st_op == Op_StoreI) st_op = Op_StoreP;
780 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
781 else ShouldNotReachHere();
782 if (st_op) {
783 // a store
784 // inputs are (0:control, 1:memory, 2:address, 3:value)
785 Node* n2 = n->in(3);
786 if (n2 != NULL) {
787 const Type* t = n2->bottom_type();
788 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
789 }
790 } else {
791 // a load
792 const Type* t = n->bottom_type();
793 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
794 }
795 }
797 if (ld_op) {
798 // a Load
799 // inputs are (0:control, 1:memory, 2:address)
800 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
801 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) &&
802 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
803 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
804 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
805 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
806 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
807 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
808 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
809 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
810 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
811 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
812 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
813 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
814 !(n->rule() == loadUB_rule)) {
815 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
816 }
817 } else if (st_op) {
818 // a Store
819 // inputs are (0:control, 1:memory, 2:address, 3:value)
820 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
821 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
822 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
823 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
824 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
825 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
826 verify_oops_warning(n, n->ideal_Opcode(), st_op);
827 }
828 }
830 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
831 Node* addr = n->in(2);
832 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
833 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
834 if (atype != NULL) {
835 intptr_t offset = get_offset_from_base(n, atype, disp32);
836 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
837 if (offset != offset_2) {
838 get_offset_from_base(n, atype, disp32);
839 get_offset_from_base_2(n, atype, disp32);
840 }
841 assert(offset == offset_2, "different offsets");
842 if (offset == disp32) {
843 // we now know that src1 is a true oop pointer
844 is_verified_oop_base = true;
845 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
846 if( primary == Assembler::ldd_op3 ) {
847 is_verified_oop_base = false; // Cannot 'ldd' into O7
848 } else {
849 tmp_enc = dst_enc;
850 dst_enc = R_O7_enc; // Load into O7; preserve source oop
851 assert(src1_enc != dst_enc, "");
852 }
853 }
854 }
855 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
856 || offset == oopDesc::mark_offset_in_bytes())) {
857 // loading the mark should not be allowed either, but
858 // we don't check this since it conflicts with InlineObjectHash
859 // usage of LoadINode to get the mark. We could keep the
860 // check if we create a new LoadMarkNode
861 // but do not verify the object before its header is initialized
862 ShouldNotReachHere();
863 }
864 }
865 }
866 }
867 }
868 #endif
870 uint instr;
871 instr = (Assembler::ldst_op << 30)
872 | (dst_enc << 25)
873 | (primary << 19)
874 | (src1_enc << 14);
876 uint index = src2_enc;
877 int disp = disp32;
879 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
880 disp += STACK_BIAS;
882 // We should have a compiler bailout here rather than a guarantee.
883 // Better yet would be some mechanism to handle variable-size matches correctly.
884 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
886 if( disp == 0 ) {
887 // use reg-reg form
888 // bit 13 is already zero
889 instr |= index;
890 } else {
891 // use reg-imm form
892 instr |= 0x00002000; // set bit 13 to one
893 instr |= disp & 0x1FFF;
894 }
896 uint *code = (uint*)cbuf.code_end();
897 *code = instr;
898 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
900 #ifdef ASSERT
901 {
902 MacroAssembler _masm(&cbuf);
903 if (is_verified_oop_base) {
904 __ verify_oop(reg_to_register_object(src1_enc));
905 }
906 if (is_verified_oop_store) {
907 __ verify_oop(reg_to_register_object(dst_enc));
908 }
909 if (tmp_enc != -1) {
910 __ mov(O7, reg_to_register_object(tmp_enc));
911 }
912 if (is_verified_oop_load) {
913 __ verify_oop(reg_to_register_object(dst_enc));
914 }
915 }
916 #endif
917 }
919 void emit_form3_mem_reg_asi(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
920 int src1_enc, int disp32, int src2_enc, int dst_enc, int asi) {
922 uint instr;
923 instr = (Assembler::ldst_op << 30)
924 | (dst_enc << 25)
925 | (primary << 19)
926 | (src1_enc << 14);
928 int disp = disp32;
929 int index = src2_enc;
931 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
932 disp += STACK_BIAS;
934 // We should have a compiler bailout here rather than a guarantee.
935 // Better yet would be some mechanism to handle variable-size matches correctly.
936 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
938 if( disp != 0 ) {
939 // use reg-reg form
940 // set src2=R_O7 contains offset
941 index = R_O7_enc;
942 emit3_simm13( cbuf, Assembler::arith_op, index, Assembler::or_op3, 0, disp);
943 }
944 instr |= (asi << 5);
945 instr |= index;
946 uint *code = (uint*)cbuf.code_end();
947 *code = instr;
948 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
949 }
951 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false, bool force_far_call = false) {
952 // The method which records debug information at every safepoint
953 // expects the call to be the first instruction in the snippet as
954 // it creates a PcDesc structure which tracks the offset of a call
955 // from the start of the codeBlob. This offset is computed as
956 // code_end() - code_begin() of the code which has been emitted
957 // so far.
958 // In this particular case we have skirted around the problem by
959 // putting the "mov" instruction in the delay slot but the problem
960 // may bite us again at some other point and a cleaner/generic
961 // solution using relocations would be needed.
962 MacroAssembler _masm(&cbuf);
963 __ set_inst_mark();
965 // We flush the current window just so that there is a valid stack copy
966 // the fact that the current window becomes active again instantly is
967 // not a problem there is nothing live in it.
969 #ifdef ASSERT
970 int startpos = __ offset();
971 #endif /* ASSERT */
973 #ifdef _LP64
974 // Calls to the runtime or native may not be reachable from compiled code,
975 // so we generate the far call sequence on 64 bit sparc.
976 // This code sequence is relocatable to any address, even on LP64.
977 if ( force_far_call ) {
978 __ relocate(rtype);
979 Address dest(O7, (address)entry_point);
980 __ jumpl_to(dest, O7);
981 }
982 else
983 #endif
984 {
985 __ call((address)entry_point, rtype);
986 }
988 if (preserve_g2) __ delayed()->mov(G2, L7);
989 else __ delayed()->nop();
991 if (preserve_g2) __ mov(L7, G2);
993 #ifdef ASSERT
994 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
995 #ifdef _LP64
996 // Trash argument dump slots.
997 __ set(0xb0b8ac0db0b8ac0d, G1);
998 __ mov(G1, G5);
999 __ stx(G1, SP, STACK_BIAS + 0x80);
1000 __ stx(G1, SP, STACK_BIAS + 0x88);
1001 __ stx(G1, SP, STACK_BIAS + 0x90);
1002 __ stx(G1, SP, STACK_BIAS + 0x98);
1003 __ stx(G1, SP, STACK_BIAS + 0xA0);
1004 __ stx(G1, SP, STACK_BIAS + 0xA8);
1005 #else // _LP64
1006 // this is also a native call, so smash the first 7 stack locations,
1007 // and the various registers
1009 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1010 // while [SP+0x44..0x58] are the argument dump slots.
1011 __ set((intptr_t)0xbaadf00d, G1);
1012 __ mov(G1, G5);
1013 __ sllx(G1, 32, G1);
1014 __ or3(G1, G5, G1);
1015 __ mov(G1, G5);
1016 __ stx(G1, SP, 0x40);
1017 __ stx(G1, SP, 0x48);
1018 __ stx(G1, SP, 0x50);
1019 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1020 #endif // _LP64
1021 }
1022 #endif /*ASSERT*/
1023 }
1025 //=============================================================================
1026 // REQUIRED FUNCTIONALITY for encoding
1027 void emit_lo(CodeBuffer &cbuf, int val) { }
1028 void emit_hi(CodeBuffer &cbuf, int val) { }
1030 void emit_ptr(CodeBuffer &cbuf, intptr_t val, Register reg, bool ForceRelocatable) {
1031 MacroAssembler _masm(&cbuf);
1032 if (ForceRelocatable) {
1033 Address addr(reg, (address)val);
1034 __ sethi(addr, ForceRelocatable);
1035 __ add(addr, reg);
1036 } else {
1037 __ set(val, reg);
1038 }
1039 }
1042 //=============================================================================
1044 #ifndef PRODUCT
1045 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1046 Compile* C = ra_->C;
1048 for (int i = 0; i < OptoPrologueNops; i++) {
1049 st->print_cr("NOP"); st->print("\t");
1050 }
1052 if( VerifyThread ) {
1053 st->print_cr("Verify_Thread"); st->print("\t");
1054 }
1056 size_t framesize = C->frame_slots() << LogBytesPerInt;
1058 // Calls to C2R adapters often do not accept exceptional returns.
1059 // We require that their callers must bang for them. But be careful, because
1060 // some VM calls (such as call site linkage) can use several kilobytes of
1061 // stack. But the stack safety zone should account for that.
1062 // See bugs 4446381, 4468289, 4497237.
1063 if (C->need_stack_bang(framesize)) {
1064 st->print_cr("! stack bang"); st->print("\t");
1065 }
1067 if (Assembler::is_simm13(-framesize)) {
1068 st->print ("SAVE R_SP,-%d,R_SP",framesize);
1069 } else {
1070 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1071 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1072 st->print ("SAVE R_SP,R_G3,R_SP");
1073 }
1075 }
1076 #endif
1078 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1079 Compile* C = ra_->C;
1080 MacroAssembler _masm(&cbuf);
1082 for (int i = 0; i < OptoPrologueNops; i++) {
1083 __ nop();
1084 }
1086 __ verify_thread();
1088 size_t framesize = C->frame_slots() << LogBytesPerInt;
1089 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1090 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1092 // Calls to C2R adapters often do not accept exceptional returns.
1093 // We require that their callers must bang for them. But be careful, because
1094 // some VM calls (such as call site linkage) can use several kilobytes of
1095 // stack. But the stack safety zone should account for that.
1096 // See bugs 4446381, 4468289, 4497237.
1097 if (C->need_stack_bang(framesize)) {
1098 __ generate_stack_overflow_check(framesize);
1099 }
1101 if (Assembler::is_simm13(-framesize)) {
1102 __ save(SP, -framesize, SP);
1103 } else {
1104 __ sethi(-framesize & ~0x3ff, G3);
1105 __ add(G3, -framesize & 0x3ff, G3);
1106 __ save(SP, G3, SP);
1107 }
1108 C->set_frame_complete( __ offset() );
1109 }
1111 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1112 return MachNode::size(ra_);
1113 }
1115 int MachPrologNode::reloc() const {
1116 return 10; // a large enough number
1117 }
1119 //=============================================================================
1120 #ifndef PRODUCT
1121 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1122 Compile* C = ra_->C;
1124 if( do_polling() && ra_->C->is_method_compilation() ) {
1125 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1126 #ifdef _LP64
1127 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1128 #else
1129 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1130 #endif
1131 }
1133 if( do_polling() )
1134 st->print("RET\n\t");
1136 st->print("RESTORE");
1137 }
1138 #endif
1140 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1141 MacroAssembler _masm(&cbuf);
1142 Compile* C = ra_->C;
1144 __ verify_thread();
1146 // If this does safepoint polling, then do it here
1147 if( do_polling() && ra_->C->is_method_compilation() ) {
1148 Address polling_page(L0, (address)os::get_polling_page());
1149 __ sethi(polling_page, false);
1150 __ relocate(relocInfo::poll_return_type);
1151 __ ld_ptr( L0, 0, G0 );
1152 }
1154 // If this is a return, then stuff the restore in the delay slot
1155 if( do_polling() ) {
1156 __ ret();
1157 __ delayed()->restore();
1158 } else {
1159 __ restore();
1160 }
1161 }
1163 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1164 return MachNode::size(ra_);
1165 }
1167 int MachEpilogNode::reloc() const {
1168 return 16; // a large enough number
1169 }
1171 const Pipeline * MachEpilogNode::pipeline() const {
1172 return MachNode::pipeline_class();
1173 }
1175 int MachEpilogNode::safepoint_offset() const {
1176 assert( do_polling(), "no return for this epilog node");
1177 return MacroAssembler::size_of_sethi(os::get_polling_page());
1178 }
1180 //=============================================================================
1182 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1183 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1184 static enum RC rc_class( OptoReg::Name reg ) {
1185 if( !OptoReg::is_valid(reg) ) return rc_bad;
1186 if (OptoReg::is_stack(reg)) return rc_stack;
1187 VMReg r = OptoReg::as_VMReg(reg);
1188 if (r->is_Register()) return rc_int;
1189 assert(r->is_FloatRegister(), "must be");
1190 return rc_float;
1191 }
1193 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1194 if( cbuf ) {
1195 // Better yet would be some mechanism to handle variable-size matches correctly
1196 if (!Assembler::is_simm13(offset + STACK_BIAS)) {
1197 ra_->C->record_method_not_compilable("unable to handle large constant offsets");
1198 } else {
1199 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1200 }
1201 }
1202 #ifndef PRODUCT
1203 else if( !do_size ) {
1204 if( size != 0 ) st->print("\n\t");
1205 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1206 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1207 }
1208 #endif
1209 return size+4;
1210 }
1212 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1213 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1214 #ifndef PRODUCT
1215 else if( !do_size ) {
1216 if( size != 0 ) st->print("\n\t");
1217 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1218 }
1219 #endif
1220 return size+4;
1221 }
1223 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1224 PhaseRegAlloc *ra_,
1225 bool do_size,
1226 outputStream* st ) const {
1227 // Get registers to move
1228 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1229 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1230 OptoReg::Name dst_second = ra_->get_reg_second(this );
1231 OptoReg::Name dst_first = ra_->get_reg_first(this );
1233 enum RC src_second_rc = rc_class(src_second);
1234 enum RC src_first_rc = rc_class(src_first);
1235 enum RC dst_second_rc = rc_class(dst_second);
1236 enum RC dst_first_rc = rc_class(dst_first);
1238 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1240 // Generate spill code!
1241 int size = 0;
1243 if( src_first == dst_first && src_second == dst_second )
1244 return size; // Self copy, no move
1246 // --------------------------------------
1247 // Check for mem-mem move. Load into unused float registers and fall into
1248 // the float-store case.
1249 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1250 int offset = ra_->reg2offset(src_first);
1251 // Further check for aligned-adjacent pair, so we can use a double load
1252 if( (src_first&1)==0 && src_first+1 == src_second ) {
1253 src_second = OptoReg::Name(R_F31_num);
1254 src_second_rc = rc_float;
1255 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1256 } else {
1257 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1258 }
1259 src_first = OptoReg::Name(R_F30_num);
1260 src_first_rc = rc_float;
1261 }
1263 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1264 int offset = ra_->reg2offset(src_second);
1265 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1266 src_second = OptoReg::Name(R_F31_num);
1267 src_second_rc = rc_float;
1268 }
1270 // --------------------------------------
1271 // Check for float->int copy; requires a trip through memory
1272 if( src_first_rc == rc_float && dst_first_rc == rc_int ) {
1273 int offset = frame::register_save_words*wordSize;
1274 if( cbuf ) {
1275 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1276 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1277 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1278 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1279 }
1280 #ifndef PRODUCT
1281 else if( !do_size ) {
1282 if( size != 0 ) st->print("\n\t");
1283 st->print( "SUB R_SP,16,R_SP\n");
1284 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1285 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1286 st->print("\tADD R_SP,16,R_SP\n");
1287 }
1288 #endif
1289 size += 16;
1290 }
1292 // --------------------------------------
1293 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1294 // In such cases, I have to do the big-endian swap. For aligned targets, the
1295 // hardware does the flop for me. Doubles are always aligned, so no problem
1296 // there. Misaligned sources only come from native-long-returns (handled
1297 // special below).
1298 #ifndef _LP64
1299 if( src_first_rc == rc_int && // source is already big-endian
1300 src_second_rc != rc_bad && // 64-bit move
1301 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1302 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1303 // Do the big-endian flop.
1304 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1305 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1306 }
1307 #endif
1309 // --------------------------------------
1310 // Check for integer reg-reg copy
1311 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1312 #ifndef _LP64
1313 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1314 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1315 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1316 // operand contains the least significant word of the 64-bit value and vice versa.
1317 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1318 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1319 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1320 if( cbuf ) {
1321 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1322 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1323 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1324 #ifndef PRODUCT
1325 } else if( !do_size ) {
1326 if( size != 0 ) st->print("\n\t");
1327 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1328 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1329 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1330 #endif
1331 }
1332 return size+12;
1333 }
1334 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1335 // returning a long value in I0/I1
1336 // a SpillCopy must be able to target a return instruction's reg_class
1337 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1338 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1339 // operand contains the least significant word of the 64-bit value and vice versa.
1340 OptoReg::Name tdest = dst_first;
1342 if (src_first == dst_first) {
1343 tdest = OptoReg::Name(R_O7_num);
1344 size += 4;
1345 }
1347 if( cbuf ) {
1348 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1349 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1350 // ShrL_reg_imm6
1351 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1352 // ShrR_reg_imm6 src, 0, dst
1353 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1354 if (tdest != dst_first) {
1355 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1356 }
1357 }
1358 #ifndef PRODUCT
1359 else if( !do_size ) {
1360 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1361 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1362 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1363 if (tdest != dst_first) {
1364 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1365 }
1366 }
1367 #endif // PRODUCT
1368 return size+8;
1369 }
1370 #endif // !_LP64
1371 // Else normal reg-reg copy
1372 assert( src_second != dst_first, "smashed second before evacuating it" );
1373 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1374 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1375 // This moves an aligned adjacent pair.
1376 // See if we are done.
1377 if( src_first+1 == src_second && dst_first+1 == dst_second )
1378 return size;
1379 }
1381 // Check for integer store
1382 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1383 int offset = ra_->reg2offset(dst_first);
1384 // Further check for aligned-adjacent pair, so we can use a double store
1385 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1386 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1387 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1388 }
1390 // Check for integer load
1391 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1392 int offset = ra_->reg2offset(src_first);
1393 // Further check for aligned-adjacent pair, so we can use a double load
1394 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1395 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1396 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1397 }
1399 // Check for float reg-reg copy
1400 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1401 // Further check for aligned-adjacent pair, so we can use a double move
1402 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1403 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1404 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1405 }
1407 // Check for float store
1408 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1409 int offset = ra_->reg2offset(dst_first);
1410 // Further check for aligned-adjacent pair, so we can use a double store
1411 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1412 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1413 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1414 }
1416 // Check for float load
1417 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1418 int offset = ra_->reg2offset(src_first);
1419 // Further check for aligned-adjacent pair, so we can use a double load
1420 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1421 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1422 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1423 }
1425 // --------------------------------------------------------------------
1426 // Check for hi bits still needing moving. Only happens for misaligned
1427 // arguments to native calls.
1428 if( src_second == dst_second )
1429 return size; // Self copy; no move
1430 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1432 #ifndef _LP64
1433 // In the LP64 build, all registers can be moved as aligned/adjacent
1434 // pairs, so there's never any need to move the high bits separately.
1435 // The 32-bit builds have to deal with the 32-bit ABI which can force
1436 // all sorts of silly alignment problems.
1438 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1439 // 32-bits of a 64-bit register, but are needed in low bits of another
1440 // register (else it's a hi-bits-to-hi-bits copy which should have
1441 // happened already as part of a 64-bit move)
1442 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1443 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1444 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1445 // Shift src_second down to dst_second's low bits.
1446 if( cbuf ) {
1447 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1448 #ifndef PRODUCT
1449 } else if( !do_size ) {
1450 if( size != 0 ) st->print("\n\t");
1451 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1452 #endif
1453 }
1454 return size+4;
1455 }
1457 // Check for high word integer store. Must down-shift the hi bits
1458 // into a temp register, then fall into the case of storing int bits.
1459 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1460 // Shift src_second down to dst_second's low bits.
1461 if( cbuf ) {
1462 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1463 #ifndef PRODUCT
1464 } else if( !do_size ) {
1465 if( size != 0 ) st->print("\n\t");
1466 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1467 #endif
1468 }
1469 size+=4;
1470 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1471 }
1473 // Check for high word integer load
1474 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1475 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1477 // Check for high word integer store
1478 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1479 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1481 // Check for high word float store
1482 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1483 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1485 #endif // !_LP64
1487 Unimplemented();
1488 }
1490 #ifndef PRODUCT
1491 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1492 implementation( NULL, ra_, false, st );
1493 }
1494 #endif
1496 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1497 implementation( &cbuf, ra_, false, NULL );
1498 }
1500 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1501 return implementation( NULL, ra_, true, NULL );
1502 }
1504 //=============================================================================
1505 #ifndef PRODUCT
1506 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1507 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1508 }
1509 #endif
1511 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1512 MacroAssembler _masm(&cbuf);
1513 for(int i = 0; i < _count; i += 1) {
1514 __ nop();
1515 }
1516 }
1518 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1519 return 4 * _count;
1520 }
1523 //=============================================================================
1524 #ifndef PRODUCT
1525 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1526 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1527 int reg = ra_->get_reg_first(this);
1528 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1529 }
1530 #endif
1532 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1533 MacroAssembler _masm(&cbuf);
1534 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1535 int reg = ra_->get_encode(this);
1537 if (Assembler::is_simm13(offset)) {
1538 __ add(SP, offset, reg_to_register_object(reg));
1539 } else {
1540 __ set(offset, O7);
1541 __ add(SP, O7, reg_to_register_object(reg));
1542 }
1543 }
1545 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1546 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1547 assert(ra_ == ra_->C->regalloc(), "sanity");
1548 return ra_->C->scratch_emit_size(this);
1549 }
1551 //=============================================================================
1553 // emit call stub, compiled java to interpretor
1554 void emit_java_to_interp(CodeBuffer &cbuf ) {
1556 // Stub is fixed up when the corresponding call is converted from calling
1557 // compiled code to calling interpreted code.
1558 // set (empty), G5
1559 // jmp -1
1561 address mark = cbuf.inst_mark(); // get mark within main instrs section
1563 MacroAssembler _masm(&cbuf);
1565 address base =
1566 __ start_a_stub(Compile::MAX_stubs_size);
1567 if (base == NULL) return; // CodeBuffer::expand failed
1569 // static stub relocation stores the instruction address of the call
1570 __ relocate(static_stub_Relocation::spec(mark));
1572 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode()));
1574 __ set_inst_mark();
1575 Address a(G3, (address)-1);
1576 __ JUMP(a, 0);
1578 __ delayed()->nop();
1580 // Update current stubs pointer and restore code_end.
1581 __ end_a_stub();
1582 }
1584 // size of call stub, compiled java to interpretor
1585 uint size_java_to_interp() {
1586 // This doesn't need to be accurate but it must be larger or equal to
1587 // the real size of the stub.
1588 return (NativeMovConstReg::instruction_size + // sethi/setlo;
1589 NativeJump::instruction_size + // sethi; jmp; nop
1590 (TraceJumps ? 20 * BytesPerInstWord : 0) );
1591 }
1592 // relocation entries for call stub, compiled java to interpretor
1593 uint reloc_java_to_interp() {
1594 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call
1595 }
1598 //=============================================================================
1599 #ifndef PRODUCT
1600 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1601 st->print_cr("\nUEP:");
1602 #ifdef _LP64
1603 if (UseCompressedOops) {
1604 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1605 st->print_cr("\tSLL R_G5,3,R_G5");
1606 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1607 } else {
1608 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1609 }
1610 st->print_cr("\tCMP R_G5,R_G3" );
1611 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1612 #else // _LP64
1613 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1614 st->print_cr("\tCMP R_G5,R_G3" );
1615 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1616 #endif // _LP64
1617 }
1618 #endif
1620 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1621 MacroAssembler _masm(&cbuf);
1622 Label L;
1623 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1624 Register temp_reg = G3;
1625 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1627 // Load klass from receiver
1628 __ load_klass(O0, temp_reg);
1629 // Compare against expected klass
1630 __ cmp(temp_reg, G5_ic_reg);
1631 // Branch to miss code, checks xcc or icc depending
1632 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1633 }
1635 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1636 return MachNode::size(ra_);
1637 }
1640 //=============================================================================
1642 uint size_exception_handler() {
1643 if (TraceJumps) {
1644 return (400); // just a guess
1645 }
1646 return ( NativeJump::instruction_size ); // sethi;jmp;nop
1647 }
1649 uint size_deopt_handler() {
1650 if (TraceJumps) {
1651 return (400); // just a guess
1652 }
1653 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
1654 }
1656 // Emit exception handler code.
1657 int emit_exception_handler(CodeBuffer& cbuf) {
1658 Register temp_reg = G3;
1659 Address exception_blob(temp_reg, OptoRuntime::exception_blob()->instructions_begin());
1660 MacroAssembler _masm(&cbuf);
1662 address base =
1663 __ start_a_stub(size_exception_handler());
1664 if (base == NULL) return 0; // CodeBuffer::expand failed
1666 int offset = __ offset();
1668 __ JUMP(exception_blob, 0); // sethi;jmp
1669 __ delayed()->nop();
1671 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1673 __ end_a_stub();
1675 return offset;
1676 }
1678 int emit_deopt_handler(CodeBuffer& cbuf) {
1679 // Can't use any of the current frame's registers as we may have deopted
1680 // at a poll and everything (including G3) can be live.
1681 Register temp_reg = L0;
1682 Address deopt_blob(temp_reg, SharedRuntime::deopt_blob()->unpack());
1683 MacroAssembler _masm(&cbuf);
1685 address base =
1686 __ start_a_stub(size_deopt_handler());
1687 if (base == NULL) return 0; // CodeBuffer::expand failed
1689 int offset = __ offset();
1690 __ save_frame(0);
1691 __ JUMP(deopt_blob, 0); // sethi;jmp
1692 __ delayed()->restore();
1694 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1696 __ end_a_stub();
1697 return offset;
1699 }
1701 // Given a register encoding, produce a Integer Register object
1702 static Register reg_to_register_object(int register_encoding) {
1703 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1704 return as_Register(register_encoding);
1705 }
1707 // Given a register encoding, produce a single-precision Float Register object
1708 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1709 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1710 return as_SingleFloatRegister(register_encoding);
1711 }
1713 // Given a register encoding, produce a double-precision Float Register object
1714 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1715 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1716 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1717 return as_DoubleFloatRegister(register_encoding);
1718 }
1720 int Matcher::regnum_to_fpu_offset(int regnum) {
1721 return regnum - 32; // The FP registers are in the second chunk
1722 }
1724 #ifdef ASSERT
1725 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1726 #endif
1728 // Vector width in bytes
1729 const uint Matcher::vector_width_in_bytes(void) {
1730 return 8;
1731 }
1733 // Vector ideal reg
1734 const uint Matcher::vector_ideal_reg(void) {
1735 return Op_RegD;
1736 }
1738 // USII supports fxtof through the whole range of number, USIII doesn't
1739 const bool Matcher::convL2FSupported(void) {
1740 return VM_Version::has_fast_fxtof();
1741 }
1743 // Is this branch offset short enough that a short branch can be used?
1744 //
1745 // NOTE: If the platform does not provide any short branch variants, then
1746 // this method should return false for offset 0.
1747 bool Matcher::is_short_branch_offset(int rule, int offset) {
1748 return false;
1749 }
1751 const bool Matcher::isSimpleConstant64(jlong value) {
1752 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1753 // Depends on optimizations in MacroAssembler::setx.
1754 int hi = (int)(value >> 32);
1755 int lo = (int)(value & ~0);
1756 return (hi == 0) || (hi == -1) || (lo == 0);
1757 }
1759 // No scaling for the parameter the ClearArray node.
1760 const bool Matcher::init_array_count_is_in_bytes = true;
1762 // Threshold size for cleararray.
1763 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1765 // Should the Matcher clone shifts on addressing modes, expecting them to
1766 // be subsumed into complex addressing expressions or compute them into
1767 // registers? True for Intel but false for most RISCs
1768 const bool Matcher::clone_shift_expressions = false;
1770 // Is it better to copy float constants, or load them directly from memory?
1771 // Intel can load a float constant from a direct address, requiring no
1772 // extra registers. Most RISCs will have to materialize an address into a
1773 // register first, so they would do better to copy the constant from stack.
1774 const bool Matcher::rematerialize_float_constants = false;
1776 // If CPU can load and store mis-aligned doubles directly then no fixup is
1777 // needed. Else we split the double into 2 integer pieces and move it
1778 // piece-by-piece. Only happens when passing doubles into C code as the
1779 // Java calling convention forces doubles to be aligned.
1780 #ifdef _LP64
1781 const bool Matcher::misaligned_doubles_ok = true;
1782 #else
1783 const bool Matcher::misaligned_doubles_ok = false;
1784 #endif
1786 // No-op on SPARC.
1787 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1788 }
1790 // Advertise here if the CPU requires explicit rounding operations
1791 // to implement the UseStrictFP mode.
1792 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1794 // Do floats take an entire double register or just half?
1795 const bool Matcher::float_in_double = false;
1797 // Do ints take an entire long register or just half?
1798 // Note that we if-def off of _LP64.
1799 // The relevant question is how the int is callee-saved. In _LP64
1800 // the whole long is written but de-opt'ing will have to extract
1801 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1802 #ifdef _LP64
1803 const bool Matcher::int_in_long = true;
1804 #else
1805 const bool Matcher::int_in_long = false;
1806 #endif
1808 // Return whether or not this register is ever used as an argument. This
1809 // function is used on startup to build the trampoline stubs in generateOptoStub.
1810 // Registers not mentioned will be killed by the VM call in the trampoline, and
1811 // arguments in those registers not be available to the callee.
1812 bool Matcher::can_be_java_arg( int reg ) {
1813 // Standard sparc 6 args in registers
1814 if( reg == R_I0_num ||
1815 reg == R_I1_num ||
1816 reg == R_I2_num ||
1817 reg == R_I3_num ||
1818 reg == R_I4_num ||
1819 reg == R_I5_num ) return true;
1820 #ifdef _LP64
1821 // 64-bit builds can pass 64-bit pointers and longs in
1822 // the high I registers
1823 if( reg == R_I0H_num ||
1824 reg == R_I1H_num ||
1825 reg == R_I2H_num ||
1826 reg == R_I3H_num ||
1827 reg == R_I4H_num ||
1828 reg == R_I5H_num ) return true;
1830 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
1831 return true;
1832 }
1834 #else
1835 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
1836 // Longs cannot be passed in O regs, because O regs become I regs
1837 // after a 'save' and I regs get their high bits chopped off on
1838 // interrupt.
1839 if( reg == R_G1H_num || reg == R_G1_num ) return true;
1840 if( reg == R_G4H_num || reg == R_G4_num ) return true;
1841 #endif
1842 // A few float args in registers
1843 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
1845 return false;
1846 }
1848 bool Matcher::is_spillable_arg( int reg ) {
1849 return can_be_java_arg(reg);
1850 }
1852 // Register for DIVI projection of divmodI
1853 RegMask Matcher::divI_proj_mask() {
1854 ShouldNotReachHere();
1855 return RegMask();
1856 }
1858 // Register for MODI projection of divmodI
1859 RegMask Matcher::modI_proj_mask() {
1860 ShouldNotReachHere();
1861 return RegMask();
1862 }
1864 // Register for DIVL projection of divmodL
1865 RegMask Matcher::divL_proj_mask() {
1866 ShouldNotReachHere();
1867 return RegMask();
1868 }
1870 // Register for MODL projection of divmodL
1871 RegMask Matcher::modL_proj_mask() {
1872 ShouldNotReachHere();
1873 return RegMask();
1874 }
1876 %}
1879 // The intptr_t operand types, defined by textual substitution.
1880 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
1881 #ifdef _LP64
1882 #define immX immL
1883 #define immX13 immL13
1884 #define iRegX iRegL
1885 #define g1RegX g1RegL
1886 #else
1887 #define immX immI
1888 #define immX13 immI13
1889 #define iRegX iRegI
1890 #define g1RegX g1RegI
1891 #endif
1893 //----------ENCODING BLOCK-----------------------------------------------------
1894 // This block specifies the encoding classes used by the compiler to output
1895 // byte streams. Encoding classes are parameterized macros used by
1896 // Machine Instruction Nodes in order to generate the bit encoding of the
1897 // instruction. Operands specify their base encoding interface with the
1898 // interface keyword. There are currently supported four interfaces,
1899 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1900 // operand to generate a function which returns its register number when
1901 // queried. CONST_INTER causes an operand to generate a function which
1902 // returns the value of the constant when queried. MEMORY_INTER causes an
1903 // operand to generate four functions which return the Base Register, the
1904 // Index Register, the Scale Value, and the Offset Value of the operand when
1905 // queried. COND_INTER causes an operand to generate six functions which
1906 // return the encoding code (ie - encoding bits for the instruction)
1907 // associated with each basic boolean condition for a conditional instruction.
1908 //
1909 // Instructions specify two basic values for encoding. Again, a function
1910 // is available to check if the constant displacement is an oop. They use the
1911 // ins_encode keyword to specify their encoding classes (which must be
1912 // a sequence of enc_class names, and their parameters, specified in
1913 // the encoding block), and they use the
1914 // opcode keyword to specify, in order, their primary, secondary, and
1915 // tertiary opcode. Only the opcode sections which a particular instruction
1916 // needs for encoding need to be specified.
1917 encode %{
1918 enc_class enc_untested %{
1919 #ifdef ASSERT
1920 MacroAssembler _masm(&cbuf);
1921 __ untested("encoding");
1922 #endif
1923 %}
1925 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
1926 emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
1927 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
1928 %}
1930 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
1931 emit_form3_mem_reg(cbuf, this, $primary, -1,
1932 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
1933 %}
1935 enc_class form3_mem_reg_little( memory mem, iRegI dst) %{
1936 emit_form3_mem_reg_asi(cbuf, this, $primary, -1,
1937 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg, Assembler::ASI_PRIMARY_LITTLE);
1938 %}
1940 enc_class form3_mem_prefetch_read( memory mem ) %{
1941 emit_form3_mem_reg(cbuf, this, $primary, -1,
1942 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
1943 %}
1945 enc_class form3_mem_prefetch_write( memory mem ) %{
1946 emit_form3_mem_reg(cbuf, this, $primary, -1,
1947 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
1948 %}
1950 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
1951 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
1952 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
1953 guarantee($mem$$index == R_G0_enc, "double index?");
1954 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
1955 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
1956 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
1957 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
1958 %}
1960 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
1961 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
1962 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
1963 guarantee($mem$$index == R_G0_enc, "double index?");
1964 // Load long with 2 instructions
1965 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
1966 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
1967 %}
1969 //%%% form3_mem_plus_4_reg is a hack--get rid of it
1970 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
1971 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
1972 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
1973 %}
1975 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
1976 // Encode a reg-reg copy. If it is useless, then empty encoding.
1977 if( $rs2$$reg != $rd$$reg )
1978 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
1979 %}
1981 // Target lo half of long
1982 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
1983 // Encode a reg-reg copy. If it is useless, then empty encoding.
1984 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
1985 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
1986 %}
1988 // Source lo half of long
1989 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
1990 // Encode a reg-reg copy. If it is useless, then empty encoding.
1991 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
1992 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
1993 %}
1995 // Target hi half of long
1996 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
1997 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
1998 %}
2000 // Source lo half of long, and leave it sign extended.
2001 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2002 // Sign extend low half
2003 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2004 %}
2006 // Source hi half of long, and leave it sign extended.
2007 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2008 // Shift high half to low half
2009 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2010 %}
2012 // Source hi half of long
2013 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2014 // Encode a reg-reg copy. If it is useless, then empty encoding.
2015 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2016 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2017 %}
2019 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2020 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2021 %}
2023 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2024 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2025 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2026 %}
2028 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2029 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2030 // clear if nothing else is happening
2031 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2032 // blt,a,pn done
2033 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2034 // mov dst,-1 in delay slot
2035 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2036 %}
2038 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2039 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2040 %}
2042 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2043 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2044 %}
2046 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2047 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2048 %}
2050 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2051 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2052 %}
2054 enc_class move_return_pc_to_o1() %{
2055 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2056 %}
2058 #ifdef _LP64
2059 /* %%% merge with enc_to_bool */
2060 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2061 MacroAssembler _masm(&cbuf);
2063 Register src_reg = reg_to_register_object($src$$reg);
2064 Register dst_reg = reg_to_register_object($dst$$reg);
2065 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2066 %}
2067 #endif
2069 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2070 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2071 MacroAssembler _masm(&cbuf);
2073 Register p_reg = reg_to_register_object($p$$reg);
2074 Register q_reg = reg_to_register_object($q$$reg);
2075 Register y_reg = reg_to_register_object($y$$reg);
2076 Register tmp_reg = reg_to_register_object($tmp$$reg);
2078 __ subcc( p_reg, q_reg, p_reg );
2079 __ add ( p_reg, y_reg, tmp_reg );
2080 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2081 %}
2083 enc_class form_d2i_helper(regD src, regF dst) %{
2084 // fcmp %fcc0,$src,$src
2085 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2086 // branch %fcc0 not-nan, predict taken
2087 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2088 // fdtoi $src,$dst
2089 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2090 // fitos $dst,$dst (if nan)
2091 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2092 // clear $dst (if nan)
2093 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2094 // carry on here...
2095 %}
2097 enc_class form_d2l_helper(regD src, regD dst) %{
2098 // fcmp %fcc0,$src,$src check for NAN
2099 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2100 // branch %fcc0 not-nan, predict taken
2101 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2102 // fdtox $src,$dst convert in delay slot
2103 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2104 // fxtod $dst,$dst (if nan)
2105 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2106 // clear $dst (if nan)
2107 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2108 // carry on here...
2109 %}
2111 enc_class form_f2i_helper(regF src, regF dst) %{
2112 // fcmps %fcc0,$src,$src
2113 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2114 // branch %fcc0 not-nan, predict taken
2115 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2116 // fstoi $src,$dst
2117 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2118 // fitos $dst,$dst (if nan)
2119 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2120 // clear $dst (if nan)
2121 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2122 // carry on here...
2123 %}
2125 enc_class form_f2l_helper(regF src, regD dst) %{
2126 // fcmps %fcc0,$src,$src
2127 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2128 // branch %fcc0 not-nan, predict taken
2129 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2130 // fstox $src,$dst
2131 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2132 // fxtod $dst,$dst (if nan)
2133 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2134 // clear $dst (if nan)
2135 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2136 // carry on here...
2137 %}
2139 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2140 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2141 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2142 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2144 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2146 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2147 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2149 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2150 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2151 %}
2153 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2154 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2155 %}
2157 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2158 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2159 %}
2161 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2162 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2163 %}
2165 enc_class form3_convI2F(regF rs2, regF rd) %{
2166 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2167 %}
2169 // Encloding class for traceable jumps
2170 enc_class form_jmpl(g3RegP dest) %{
2171 emit_jmpl(cbuf, $dest$$reg);
2172 %}
2174 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2175 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2176 %}
2178 enc_class form2_nop() %{
2179 emit_nop(cbuf);
2180 %}
2182 enc_class form2_illtrap() %{
2183 emit_illtrap(cbuf);
2184 %}
2187 // Compare longs and convert into -1, 0, 1.
2188 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2189 // CMP $src1,$src2
2190 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2191 // blt,a,pn done
2192 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2193 // mov dst,-1 in delay slot
2194 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2195 // bgt,a,pn done
2196 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2197 // mov dst,1 in delay slot
2198 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2199 // CLR $dst
2200 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2201 %}
2203 enc_class enc_PartialSubtypeCheck() %{
2204 MacroAssembler _masm(&cbuf);
2205 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2206 __ delayed()->nop();
2207 %}
2209 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{
2210 MacroAssembler _masm(&cbuf);
2211 Label &L = *($labl$$label);
2212 Assembler::Predict predict_taken =
2213 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2215 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L);
2216 __ delayed()->nop();
2217 %}
2219 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{
2220 MacroAssembler _masm(&cbuf);
2221 Label &L = *($labl$$label);
2222 Assembler::Predict predict_taken =
2223 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2225 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L);
2226 __ delayed()->nop();
2227 %}
2229 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{
2230 MacroAssembler _masm(&cbuf);
2231 Label &L = *($labl$$label);
2232 Assembler::Predict predict_taken =
2233 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2235 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L);
2236 __ delayed()->nop();
2237 %}
2239 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{
2240 MacroAssembler _masm(&cbuf);
2241 Label &L = *($labl$$label);
2242 Assembler::Predict predict_taken =
2243 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2245 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L);
2246 __ delayed()->nop();
2247 %}
2249 enc_class jump_enc( iRegX switch_val, o7RegI table) %{
2250 MacroAssembler _masm(&cbuf);
2252 Register switch_reg = as_Register($switch_val$$reg);
2253 Register table_reg = O7;
2255 address table_base = __ address_table_constant(_index2label);
2256 RelocationHolder rspec = internal_word_Relocation::spec(table_base);
2258 // Load table address
2259 Address the_pc(table_reg, table_base, rspec);
2260 __ load_address(the_pc);
2262 // Jump to base address + switch value
2263 __ ld_ptr(table_reg, switch_reg, table_reg);
2264 __ jmp(table_reg, G0);
2265 __ delayed()->nop();
2267 %}
2269 enc_class enc_ba( Label labl ) %{
2270 MacroAssembler _masm(&cbuf);
2271 Label &L = *($labl$$label);
2272 __ ba(false, L);
2273 __ delayed()->nop();
2274 %}
2276 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{
2277 MacroAssembler _masm(&cbuf);
2278 Label &L = *$labl$$label;
2279 Assembler::Predict predict_taken =
2280 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2282 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L);
2283 __ delayed()->nop();
2284 %}
2286 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2287 int op = (Assembler::arith_op << 30) |
2288 ($dst$$reg << 25) |
2289 (Assembler::movcc_op3 << 19) |
2290 (1 << 18) | // cc2 bit for 'icc'
2291 ($cmp$$cmpcode << 14) |
2292 (0 << 13) | // select register move
2293 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2294 ($src$$reg << 0);
2295 *((int*)(cbuf.code_end())) = op;
2296 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2297 %}
2299 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2300 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2301 int op = (Assembler::arith_op << 30) |
2302 ($dst$$reg << 25) |
2303 (Assembler::movcc_op3 << 19) |
2304 (1 << 18) | // cc2 bit for 'icc'
2305 ($cmp$$cmpcode << 14) |
2306 (1 << 13) | // select immediate move
2307 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2308 (simm11 << 0);
2309 *((int*)(cbuf.code_end())) = op;
2310 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2311 %}
2313 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2314 int op = (Assembler::arith_op << 30) |
2315 ($dst$$reg << 25) |
2316 (Assembler::movcc_op3 << 19) |
2317 (0 << 18) | // cc2 bit for 'fccX'
2318 ($cmp$$cmpcode << 14) |
2319 (0 << 13) | // select register move
2320 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2321 ($src$$reg << 0);
2322 *((int*)(cbuf.code_end())) = op;
2323 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2324 %}
2326 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2327 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2328 int op = (Assembler::arith_op << 30) |
2329 ($dst$$reg << 25) |
2330 (Assembler::movcc_op3 << 19) |
2331 (0 << 18) | // cc2 bit for 'fccX'
2332 ($cmp$$cmpcode << 14) |
2333 (1 << 13) | // select immediate move
2334 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2335 (simm11 << 0);
2336 *((int*)(cbuf.code_end())) = op;
2337 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2338 %}
2340 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2341 int op = (Assembler::arith_op << 30) |
2342 ($dst$$reg << 25) |
2343 (Assembler::fpop2_op3 << 19) |
2344 (0 << 18) |
2345 ($cmp$$cmpcode << 14) |
2346 (1 << 13) | // select register move
2347 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2348 ($primary << 5) | // select single, double or quad
2349 ($src$$reg << 0);
2350 *((int*)(cbuf.code_end())) = op;
2351 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2352 %}
2354 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2355 int op = (Assembler::arith_op << 30) |
2356 ($dst$$reg << 25) |
2357 (Assembler::fpop2_op3 << 19) |
2358 (0 << 18) |
2359 ($cmp$$cmpcode << 14) |
2360 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2361 ($primary << 5) | // select single, double or quad
2362 ($src$$reg << 0);
2363 *((int*)(cbuf.code_end())) = op;
2364 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2365 %}
2367 // Used by the MIN/MAX encodings. Same as a CMOV, but
2368 // the condition comes from opcode-field instead of an argument.
2369 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2370 int op = (Assembler::arith_op << 30) |
2371 ($dst$$reg << 25) |
2372 (Assembler::movcc_op3 << 19) |
2373 (1 << 18) | // cc2 bit for 'icc'
2374 ($primary << 14) |
2375 (0 << 13) | // select register move
2376 (0 << 11) | // cc1, cc0 bits for 'icc'
2377 ($src$$reg << 0);
2378 *((int*)(cbuf.code_end())) = op;
2379 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2380 %}
2382 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2383 int op = (Assembler::arith_op << 30) |
2384 ($dst$$reg << 25) |
2385 (Assembler::movcc_op3 << 19) |
2386 (6 << 16) | // cc2 bit for 'xcc'
2387 ($primary << 14) |
2388 (0 << 13) | // select register move
2389 (0 << 11) | // cc1, cc0 bits for 'icc'
2390 ($src$$reg << 0);
2391 *((int*)(cbuf.code_end())) = op;
2392 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2393 %}
2395 // Utility encoding for loading a 64 bit Pointer into a register
2396 // The 64 bit pointer is stored in the generated code stream
2397 enc_class SetPtr( immP src, iRegP rd ) %{
2398 Register dest = reg_to_register_object($rd$$reg);
2399 // [RGV] This next line should be generated from ADLC
2400 if ( _opnds[1]->constant_is_oop() ) {
2401 intptr_t val = $src$$constant;
2402 MacroAssembler _masm(&cbuf);
2403 __ set_oop_constant((jobject)val, dest);
2404 } else { // non-oop pointers, e.g. card mark base, heap top
2405 emit_ptr(cbuf, $src$$constant, dest, /*ForceRelocatable=*/ false);
2406 }
2407 %}
2409 enc_class Set13( immI13 src, iRegI rd ) %{
2410 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2411 %}
2413 enc_class SetHi22( immI src, iRegI rd ) %{
2414 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2415 %}
2417 enc_class Set32( immI src, iRegI rd ) %{
2418 MacroAssembler _masm(&cbuf);
2419 __ set($src$$constant, reg_to_register_object($rd$$reg));
2420 %}
2422 enc_class SetNull( iRegI rd ) %{
2423 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0 );
2424 %}
2426 enc_class call_epilog %{
2427 if( VerifyStackAtCalls ) {
2428 MacroAssembler _masm(&cbuf);
2429 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2430 Register temp_reg = G3;
2431 __ add(SP, framesize, temp_reg);
2432 __ cmp(temp_reg, FP);
2433 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2434 }
2435 %}
2437 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2438 // to G1 so the register allocator will not have to deal with the misaligned register
2439 // pair.
2440 enc_class adjust_long_from_native_call %{
2441 #ifndef _LP64
2442 if (returns_long()) {
2443 // sllx O0,32,O0
2444 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2445 // srl O1,0,O1
2446 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2447 // or O0,O1,G1
2448 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2449 }
2450 #endif
2451 %}
2453 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2454 // CALL directly to the runtime
2455 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2456 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2457 /*preserve_g2=*/true, /*force far call*/true);
2458 %}
2460 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2461 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2462 // who we intended to call.
2463 if ( !_method ) {
2464 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2465 } else if (_optimized_virtual) {
2466 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2467 } else {
2468 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2469 }
2470 if( _method ) { // Emit stub for static call
2471 emit_java_to_interp(cbuf);
2472 }
2473 %}
2475 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2476 MacroAssembler _masm(&cbuf);
2477 __ set_inst_mark();
2478 int vtable_index = this->_vtable_index;
2479 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2480 if (vtable_index < 0) {
2481 // must be invalid_vtable_index, not nonvirtual_vtable_index
2482 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
2483 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2484 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2485 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2486 // !!!!!
2487 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info
2488 // emit_call_dynamic_prologue( cbuf );
2489 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg);
2491 address virtual_call_oop_addr = __ inst_mark();
2492 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2493 // who we intended to call.
2494 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
2495 emit_call_reloc(cbuf, $meth$$method, relocInfo::none);
2496 } else {
2497 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2498 // Just go thru the vtable
2499 // get receiver klass (receiver already checked for non-null)
2500 // If we end up going thru a c2i adapter interpreter expects method in G5
2501 int off = __ offset();
2502 __ load_klass(O0, G3_scratch);
2503 int klass_load_size;
2504 if (UseCompressedOops) {
2505 klass_load_size = 3*BytesPerInstWord;
2506 } else {
2507 klass_load_size = 1*BytesPerInstWord;
2508 }
2509 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2510 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2511 if( __ is_simm13(v_off) ) {
2512 __ ld_ptr(G3, v_off, G5_method);
2513 } else {
2514 // Generate 2 instructions
2515 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2516 __ or3(G5_method, v_off & 0x3ff, G5_method);
2517 // ld_ptr, set_hi, set
2518 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2519 "Unexpected instruction size(s)");
2520 __ ld_ptr(G3, G5_method, G5_method);
2521 }
2522 // NOTE: for vtable dispatches, the vtable entry will never be null.
2523 // However it may very well end up in handle_wrong_method if the
2524 // method is abstract for the particular class.
2525 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch);
2526 // jump to target (either compiled code or c2iadapter)
2527 __ jmpl(G3_scratch, G0, O7);
2528 __ delayed()->nop();
2529 }
2530 %}
2532 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2533 MacroAssembler _masm(&cbuf);
2535 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2536 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2537 // we might be calling a C2I adapter which needs it.
2539 assert(temp_reg != G5_ic_reg, "conflicting registers");
2540 // Load nmethod
2541 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg);
2543 // CALL to compiled java, indirect the contents of G3
2544 __ set_inst_mark();
2545 __ callr(temp_reg, G0);
2546 __ delayed()->nop();
2547 %}
2549 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2550 MacroAssembler _masm(&cbuf);
2551 Register Rdividend = reg_to_register_object($src1$$reg);
2552 Register Rdivisor = reg_to_register_object($src2$$reg);
2553 Register Rresult = reg_to_register_object($dst$$reg);
2555 __ sra(Rdivisor, 0, Rdivisor);
2556 __ sra(Rdividend, 0, Rdividend);
2557 __ sdivx(Rdividend, Rdivisor, Rresult);
2558 %}
2560 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2561 MacroAssembler _masm(&cbuf);
2563 Register Rdividend = reg_to_register_object($src1$$reg);
2564 int divisor = $imm$$constant;
2565 Register Rresult = reg_to_register_object($dst$$reg);
2567 __ sra(Rdividend, 0, Rdividend);
2568 __ sdivx(Rdividend, divisor, Rresult);
2569 %}
2571 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2572 MacroAssembler _masm(&cbuf);
2573 Register Rsrc1 = reg_to_register_object($src1$$reg);
2574 Register Rsrc2 = reg_to_register_object($src2$$reg);
2575 Register Rdst = reg_to_register_object($dst$$reg);
2577 __ sra( Rsrc1, 0, Rsrc1 );
2578 __ sra( Rsrc2, 0, Rsrc2 );
2579 __ mulx( Rsrc1, Rsrc2, Rdst );
2580 __ srlx( Rdst, 32, Rdst );
2581 %}
2583 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2584 MacroAssembler _masm(&cbuf);
2585 Register Rdividend = reg_to_register_object($src1$$reg);
2586 Register Rdivisor = reg_to_register_object($src2$$reg);
2587 Register Rresult = reg_to_register_object($dst$$reg);
2588 Register Rscratch = reg_to_register_object($scratch$$reg);
2590 assert(Rdividend != Rscratch, "");
2591 assert(Rdivisor != Rscratch, "");
2593 __ sra(Rdividend, 0, Rdividend);
2594 __ sra(Rdivisor, 0, Rdivisor);
2595 __ sdivx(Rdividend, Rdivisor, Rscratch);
2596 __ mulx(Rscratch, Rdivisor, Rscratch);
2597 __ sub(Rdividend, Rscratch, Rresult);
2598 %}
2600 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2601 MacroAssembler _masm(&cbuf);
2603 Register Rdividend = reg_to_register_object($src1$$reg);
2604 int divisor = $imm$$constant;
2605 Register Rresult = reg_to_register_object($dst$$reg);
2606 Register Rscratch = reg_to_register_object($scratch$$reg);
2608 assert(Rdividend != Rscratch, "");
2610 __ sra(Rdividend, 0, Rdividend);
2611 __ sdivx(Rdividend, divisor, Rscratch);
2612 __ mulx(Rscratch, divisor, Rscratch);
2613 __ sub(Rdividend, Rscratch, Rresult);
2614 %}
2616 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2617 MacroAssembler _masm(&cbuf);
2619 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2620 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2622 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2623 %}
2625 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2626 MacroAssembler _masm(&cbuf);
2628 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2629 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2631 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2632 %}
2634 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2635 MacroAssembler _masm(&cbuf);
2637 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2638 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2640 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2641 %}
2643 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2644 MacroAssembler _masm(&cbuf);
2646 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2647 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2649 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2650 %}
2652 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2653 MacroAssembler _masm(&cbuf);
2655 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2656 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2658 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2659 %}
2661 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2662 MacroAssembler _masm(&cbuf);
2664 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2665 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2667 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2668 %}
2670 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2671 MacroAssembler _masm(&cbuf);
2673 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2674 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2676 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2677 %}
2679 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2680 MacroAssembler _masm(&cbuf);
2682 Register Roop = reg_to_register_object($oop$$reg);
2683 Register Rbox = reg_to_register_object($box$$reg);
2684 Register Rscratch = reg_to_register_object($scratch$$reg);
2685 Register Rmark = reg_to_register_object($scratch2$$reg);
2687 assert(Roop != Rscratch, "");
2688 assert(Roop != Rmark, "");
2689 assert(Rbox != Rscratch, "");
2690 assert(Rbox != Rmark, "");
2692 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2693 %}
2695 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2696 MacroAssembler _masm(&cbuf);
2698 Register Roop = reg_to_register_object($oop$$reg);
2699 Register Rbox = reg_to_register_object($box$$reg);
2700 Register Rscratch = reg_to_register_object($scratch$$reg);
2701 Register Rmark = reg_to_register_object($scratch2$$reg);
2703 assert(Roop != Rscratch, "");
2704 assert(Roop != Rmark, "");
2705 assert(Rbox != Rscratch, "");
2706 assert(Rbox != Rmark, "");
2708 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2709 %}
2711 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2712 MacroAssembler _masm(&cbuf);
2713 Register Rmem = reg_to_register_object($mem$$reg);
2714 Register Rold = reg_to_register_object($old$$reg);
2715 Register Rnew = reg_to_register_object($new$$reg);
2717 // casx_under_lock picks 1 of 3 encodings:
2718 // For 32-bit pointers you get a 32-bit CAS
2719 // For 64-bit pointers you get a 64-bit CASX
2720 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2721 __ cmp( Rold, Rnew );
2722 %}
2724 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2725 Register Rmem = reg_to_register_object($mem$$reg);
2726 Register Rold = reg_to_register_object($old$$reg);
2727 Register Rnew = reg_to_register_object($new$$reg);
2729 MacroAssembler _masm(&cbuf);
2730 __ mov(Rnew, O7);
2731 __ casx(Rmem, Rold, O7);
2732 __ cmp( Rold, O7 );
2733 %}
2735 // raw int cas, used for compareAndSwap
2736 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2737 Register Rmem = reg_to_register_object($mem$$reg);
2738 Register Rold = reg_to_register_object($old$$reg);
2739 Register Rnew = reg_to_register_object($new$$reg);
2741 MacroAssembler _masm(&cbuf);
2742 __ mov(Rnew, O7);
2743 __ cas(Rmem, Rold, O7);
2744 __ cmp( Rold, O7 );
2745 %}
2747 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2748 Register Rres = reg_to_register_object($res$$reg);
2750 MacroAssembler _masm(&cbuf);
2751 __ mov(1, Rres);
2752 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2753 %}
2755 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2756 Register Rres = reg_to_register_object($res$$reg);
2758 MacroAssembler _masm(&cbuf);
2759 __ mov(1, Rres);
2760 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2761 %}
2763 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2764 MacroAssembler _masm(&cbuf);
2765 Register Rdst = reg_to_register_object($dst$$reg);
2766 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2767 : reg_to_DoubleFloatRegister_object($src1$$reg);
2768 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2769 : reg_to_DoubleFloatRegister_object($src2$$reg);
2771 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2772 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2773 %}
2775 enc_class LdImmL (immL src, iRegL dst, o7RegL tmp) %{ // Load Immediate
2776 MacroAssembler _masm(&cbuf);
2777 Register dest = reg_to_register_object($dst$$reg);
2778 Register temp = reg_to_register_object($tmp$$reg);
2779 __ set64( $src$$constant, dest, temp );
2780 %}
2782 enc_class LdImmF(immF src, regF dst, o7RegP tmp) %{ // Load Immediate
2783 address float_address = MacroAssembler(&cbuf).float_constant($src$$constant);
2784 RelocationHolder rspec = internal_word_Relocation::spec(float_address);
2785 #ifdef _LP64
2786 Register tmp_reg = reg_to_register_object($tmp$$reg);
2787 cbuf.relocate(cbuf.code_end(), rspec, 0);
2788 emit_ptr(cbuf, (intptr_t)float_address, tmp_reg, /*ForceRelocatable=*/ true);
2789 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::ldf_op3, $tmp$$reg, 0 );
2790 #else // _LP64
2791 uint *code;
2792 int tmp_reg = $tmp$$reg;
2794 cbuf.relocate(cbuf.code_end(), rspec, 0);
2795 emit2_22( cbuf, Assembler::branch_op, tmp_reg, Assembler::sethi_op2, (intptr_t) float_address );
2797 cbuf.relocate(cbuf.code_end(), rspec, 0);
2798 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::ldf_op3, tmp_reg, (intptr_t) float_address );
2799 #endif // _LP64
2800 %}
2802 enc_class LdImmD(immD src, regD dst, o7RegP tmp) %{ // Load Immediate
2803 address double_address = MacroAssembler(&cbuf).double_constant($src$$constant);
2804 RelocationHolder rspec = internal_word_Relocation::spec(double_address);
2805 #ifdef _LP64
2806 Register tmp_reg = reg_to_register_object($tmp$$reg);
2807 cbuf.relocate(cbuf.code_end(), rspec, 0);
2808 emit_ptr(cbuf, (intptr_t)double_address, tmp_reg, /*ForceRelocatable=*/ true);
2809 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, $tmp$$reg, 0 );
2810 #else // _LP64
2811 uint *code;
2812 int tmp_reg = $tmp$$reg;
2814 cbuf.relocate(cbuf.code_end(), rspec, 0);
2815 emit2_22( cbuf, Assembler::branch_op, tmp_reg, Assembler::sethi_op2, (intptr_t) double_address );
2817 cbuf.relocate(cbuf.code_end(), rspec, 0);
2818 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, tmp_reg, (intptr_t) double_address );
2819 #endif // _LP64
2820 %}
2822 enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{
2823 // Load a constant replicated "count" times with width "width"
2824 int bit_width = $width$$constant * 8;
2825 jlong elt_val = $src$$constant;
2826 elt_val &= (((jlong)1) << bit_width) - 1; // mask off sign bits
2827 jlong val = elt_val;
2828 for (int i = 0; i < $count$$constant - 1; i++) {
2829 val <<= bit_width;
2830 val |= elt_val;
2831 }
2832 jdouble dval = *(jdouble*)&val; // coerce to double type
2833 address double_address = MacroAssembler(&cbuf).double_constant(dval);
2834 RelocationHolder rspec = internal_word_Relocation::spec(double_address);
2835 #ifdef _LP64
2836 Register tmp_reg = reg_to_register_object($tmp$$reg);
2837 cbuf.relocate(cbuf.code_end(), rspec, 0);
2838 emit_ptr(cbuf, (intptr_t)double_address, tmp_reg, /*ForceRelocatable=*/ true);
2839 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, $tmp$$reg, 0 );
2840 #else // _LP64
2841 uint *code;
2842 int tmp_reg = $tmp$$reg;
2844 cbuf.relocate(cbuf.code_end(), rspec, 0);
2845 emit2_22( cbuf, Assembler::branch_op, tmp_reg, Assembler::sethi_op2, (intptr_t) double_address );
2847 cbuf.relocate(cbuf.code_end(), rspec, 0);
2848 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, tmp_reg, (intptr_t) double_address );
2849 #endif // _LP64
2850 %}
2853 enc_class ShouldNotEncodeThis ( ) %{
2854 ShouldNotCallThis();
2855 %}
2857 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
2858 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{
2859 MacroAssembler _masm(&cbuf);
2860 Register nof_bytes_arg = reg_to_register_object($cnt$$reg);
2861 Register nof_bytes_tmp = reg_to_register_object($temp$$reg);
2862 Register base_pointer_arg = reg_to_register_object($base$$reg);
2864 Label loop;
2865 __ mov(nof_bytes_arg, nof_bytes_tmp);
2867 // Loop and clear, walking backwards through the array.
2868 // nof_bytes_tmp (if >0) is always the number of bytes to zero
2869 __ bind(loop);
2870 __ deccc(nof_bytes_tmp, 8);
2871 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
2872 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
2873 // %%%% this mini-loop must not cross a cache boundary!
2874 %}
2877 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{
2878 Label Ldone, Lloop;
2879 MacroAssembler _masm(&cbuf);
2881 Register str1_reg = reg_to_register_object($str1$$reg);
2882 Register str2_reg = reg_to_register_object($str2$$reg);
2883 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
2884 Register tmp2_reg = reg_to_register_object($tmp2$$reg);
2885 Register result_reg = reg_to_register_object($result$$reg);
2887 // Get the first character position in both strings
2888 // [8] char array, [12] offset, [16] count
2889 int value_offset = java_lang_String:: value_offset_in_bytes();
2890 int offset_offset = java_lang_String::offset_offset_in_bytes();
2891 int count_offset = java_lang_String:: count_offset_in_bytes();
2893 // load str1 (jchar*) base address into tmp1_reg
2894 __ load_heap_oop(Address(str1_reg, 0, value_offset), tmp1_reg);
2895 __ ld(Address(str1_reg, 0, offset_offset), result_reg);
2896 __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg);
2897 __ ld(Address(str1_reg, 0, count_offset), str1_reg); // hoisted
2898 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
2899 __ load_heap_oop(Address(str2_reg, 0, value_offset), tmp2_reg); // hoisted
2900 __ add(result_reg, tmp1_reg, tmp1_reg);
2902 // load str2 (jchar*) base address into tmp2_reg
2903 // __ ld_ptr(Address(str2_reg, 0, value_offset), tmp2_reg); // hoisted
2904 __ ld(Address(str2_reg, 0, offset_offset), result_reg);
2905 __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg);
2906 __ ld(Address(str2_reg, 0, count_offset), str2_reg); // hoisted
2907 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
2908 __ subcc(str1_reg, str2_reg, O7); // hoisted
2909 __ add(result_reg, tmp2_reg, tmp2_reg);
2911 // Compute the minimum of the string lengths(str1_reg) and the
2912 // difference of the string lengths (stack)
2914 // discard string base pointers, after loading up the lengths
2915 // __ ld(Address(str1_reg, 0, count_offset), str1_reg); // hoisted
2916 // __ ld(Address(str2_reg, 0, count_offset), str2_reg); // hoisted
2918 // See if the lengths are different, and calculate min in str1_reg.
2919 // Stash diff in O7 in case we need it for a tie-breaker.
2920 Label Lskip;
2921 // __ subcc(str1_reg, str2_reg, O7); // hoisted
2922 __ sll(str1_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit
2923 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2924 // str2 is shorter, so use its count:
2925 __ delayed()->sll(str2_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit
2926 __ bind(Lskip);
2928 // reallocate str1_reg, str2_reg, result_reg
2929 // Note: limit_reg holds the string length pre-scaled by 2
2930 Register limit_reg = str1_reg;
2931 Register chr2_reg = str2_reg;
2932 Register chr1_reg = result_reg;
2933 // tmp{12} are the base pointers
2935 // Is the minimum length zero?
2936 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2937 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2938 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2940 // Load first characters
2941 __ lduh(tmp1_reg, 0, chr1_reg);
2942 __ lduh(tmp2_reg, 0, chr2_reg);
2944 // Compare first characters
2945 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2946 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2947 assert(chr1_reg == result_reg, "result must be pre-placed");
2948 __ delayed()->nop();
2950 {
2951 // Check after comparing first character to see if strings are equivalent
2952 Label LSkip2;
2953 // Check if the strings start at same location
2954 __ cmp(tmp1_reg, tmp2_reg);
2955 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2956 __ delayed()->nop();
2958 // Check if the length difference is zero (in O7)
2959 __ cmp(G0, O7);
2960 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2961 __ delayed()->mov(G0, result_reg); // result is zero
2963 // Strings might not be equal
2964 __ bind(LSkip2);
2965 }
2967 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2968 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2969 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2971 // Shift tmp1_reg and tmp2_reg to the end of the arrays, negate limit
2972 __ add(tmp1_reg, limit_reg, tmp1_reg);
2973 __ add(tmp2_reg, limit_reg, tmp2_reg);
2974 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2976 // Compare the rest of the characters
2977 __ lduh(tmp1_reg, limit_reg, chr1_reg);
2978 __ bind(Lloop);
2979 // __ lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted
2980 __ lduh(tmp2_reg, limit_reg, chr2_reg);
2981 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2982 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2983 assert(chr1_reg == result_reg, "result must be pre-placed");
2984 __ delayed()->inccc(limit_reg, sizeof(jchar));
2985 // annul LDUH if branch is not taken to prevent access past end of string
2986 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2987 __ delayed()->lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted
2989 // If strings are equal up to min length, return the length difference.
2990 __ mov(O7, result_reg);
2992 // Otherwise, return the difference between the first mismatched chars.
2993 __ bind(Ldone);
2994 %}
2996 enc_class enc_rethrow() %{
2997 cbuf.set_inst_mark();
2998 Register temp_reg = G3;
2999 Address rethrow_stub(temp_reg, OptoRuntime::rethrow_stub());
3000 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3001 MacroAssembler _masm(&cbuf);
3002 #ifdef ASSERT
3003 __ save_frame(0);
3004 Address last_rethrow_addr(L1, (address)&last_rethrow);
3005 __ sethi(last_rethrow_addr);
3006 __ get_pc(L2);
3007 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3008 __ st_ptr(L2, last_rethrow_addr);
3009 __ restore();
3010 #endif
3011 __ JUMP(rethrow_stub, 0); // sethi;jmp
3012 __ delayed()->nop();
3013 %}
3015 enc_class emit_mem_nop() %{
3016 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3017 unsigned int *code = (unsigned int*)cbuf.code_end();
3018 *code = (unsigned int)0xc0839040;
3019 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
3020 %}
3022 enc_class emit_fadd_nop() %{
3023 // Generates the instruction FMOVS f31,f31
3024 unsigned int *code = (unsigned int*)cbuf.code_end();
3025 *code = (unsigned int)0xbfa0003f;
3026 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
3027 %}
3029 enc_class emit_br_nop() %{
3030 // Generates the instruction BPN,PN .
3031 unsigned int *code = (unsigned int*)cbuf.code_end();
3032 *code = (unsigned int)0x00400000;
3033 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
3034 %}
3036 enc_class enc_membar_acquire %{
3037 MacroAssembler _masm(&cbuf);
3038 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3039 %}
3041 enc_class enc_membar_release %{
3042 MacroAssembler _masm(&cbuf);
3043 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3044 %}
3046 enc_class enc_membar_volatile %{
3047 MacroAssembler _masm(&cbuf);
3048 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3049 %}
3051 enc_class enc_repl8b( iRegI src, iRegL dst ) %{
3052 MacroAssembler _masm(&cbuf);
3053 Register src_reg = reg_to_register_object($src$$reg);
3054 Register dst_reg = reg_to_register_object($dst$$reg);
3055 __ sllx(src_reg, 56, dst_reg);
3056 __ srlx(dst_reg, 8, O7);
3057 __ or3 (dst_reg, O7, dst_reg);
3058 __ srlx(dst_reg, 16, O7);
3059 __ or3 (dst_reg, O7, dst_reg);
3060 __ srlx(dst_reg, 32, O7);
3061 __ or3 (dst_reg, O7, dst_reg);
3062 %}
3064 enc_class enc_repl4b( iRegI src, iRegL dst ) %{
3065 MacroAssembler _masm(&cbuf);
3066 Register src_reg = reg_to_register_object($src$$reg);
3067 Register dst_reg = reg_to_register_object($dst$$reg);
3068 __ sll(src_reg, 24, dst_reg);
3069 __ srl(dst_reg, 8, O7);
3070 __ or3(dst_reg, O7, dst_reg);
3071 __ srl(dst_reg, 16, O7);
3072 __ or3(dst_reg, O7, dst_reg);
3073 %}
3075 enc_class enc_repl4s( iRegI src, iRegL dst ) %{
3076 MacroAssembler _masm(&cbuf);
3077 Register src_reg = reg_to_register_object($src$$reg);
3078 Register dst_reg = reg_to_register_object($dst$$reg);
3079 __ sllx(src_reg, 48, dst_reg);
3080 __ srlx(dst_reg, 16, O7);
3081 __ or3 (dst_reg, O7, dst_reg);
3082 __ srlx(dst_reg, 32, O7);
3083 __ or3 (dst_reg, O7, dst_reg);
3084 %}
3086 enc_class enc_repl2i( iRegI src, iRegL dst ) %{
3087 MacroAssembler _masm(&cbuf);
3088 Register src_reg = reg_to_register_object($src$$reg);
3089 Register dst_reg = reg_to_register_object($dst$$reg);
3090 __ sllx(src_reg, 32, dst_reg);
3091 __ srlx(dst_reg, 32, O7);
3092 __ or3 (dst_reg, O7, dst_reg);
3093 %}
3095 %}
3097 //----------FRAME--------------------------------------------------------------
3098 // Definition of frame structure and management information.
3099 //
3100 // S T A C K L A Y O U T Allocators stack-slot number
3101 // | (to get allocators register number
3102 // G Owned by | | v add VMRegImpl::stack0)
3103 // r CALLER | |
3104 // o | +--------+ pad to even-align allocators stack-slot
3105 // w V | pad0 | numbers; owned by CALLER
3106 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3107 // h ^ | in | 5
3108 // | | args | 4 Holes in incoming args owned by SELF
3109 // | | | | 3
3110 // | | +--------+
3111 // V | | old out| Empty on Intel, window on Sparc
3112 // | old |preserve| Must be even aligned.
3113 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3114 // | | in | 3 area for Intel ret address
3115 // Owned by |preserve| Empty on Sparc.
3116 // SELF +--------+
3117 // | | pad2 | 2 pad to align old SP
3118 // | +--------+ 1
3119 // | | locks | 0
3120 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3121 // | | pad1 | 11 pad to align new SP
3122 // | +--------+
3123 // | | | 10
3124 // | | spills | 9 spills
3125 // V | | 8 (pad0 slot for callee)
3126 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3127 // ^ | out | 7
3128 // | | args | 6 Holes in outgoing args owned by CALLEE
3129 // Owned by +--------+
3130 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3131 // | new |preserve| Must be even-aligned.
3132 // | SP-+--------+----> Matcher::_new_SP, even aligned
3133 // | | |
3134 //
3135 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3136 // known from SELF's arguments and the Java calling convention.
3137 // Region 6-7 is determined per call site.
3138 // Note 2: If the calling convention leaves holes in the incoming argument
3139 // area, those holes are owned by SELF. Holes in the outgoing area
3140 // are owned by the CALLEE. Holes should not be nessecary in the
3141 // incoming area, as the Java calling convention is completely under
3142 // the control of the AD file. Doubles can be sorted and packed to
3143 // avoid holes. Holes in the outgoing arguments may be nessecary for
3144 // varargs C calling conventions.
3145 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3146 // even aligned with pad0 as needed.
3147 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3148 // region 6-11 is even aligned; it may be padded out more so that
3149 // the region from SP to FP meets the minimum stack alignment.
3151 frame %{
3152 // What direction does stack grow in (assumed to be same for native & Java)
3153 stack_direction(TOWARDS_LOW);
3155 // These two registers define part of the calling convention
3156 // between compiled code and the interpreter.
3157 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C
3158 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3160 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3161 cisc_spilling_operand_name(indOffset);
3163 // Number of stack slots consumed by a Monitor enter
3164 #ifdef _LP64
3165 sync_stack_slots(2);
3166 #else
3167 sync_stack_slots(1);
3168 #endif
3170 // Compiled code's Frame Pointer
3171 frame_pointer(R_SP);
3173 // Stack alignment requirement
3174 stack_alignment(StackAlignmentInBytes);
3175 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3176 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3178 // Number of stack slots between incoming argument block and the start of
3179 // a new frame. The PROLOG must add this many slots to the stack. The
3180 // EPILOG must remove this many slots.
3181 in_preserve_stack_slots(0);
3183 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3184 // for calls to C. Supports the var-args backing area for register parms.
3185 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3186 #ifdef _LP64
3187 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3188 varargs_C_out_slots_killed(12);
3189 #else
3190 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3191 varargs_C_out_slots_killed( 7);
3192 #endif
3194 // The after-PROLOG location of the return address. Location of
3195 // return address specifies a type (REG or STACK) and a number
3196 // representing the register number (i.e. - use a register name) or
3197 // stack slot.
3198 return_addr(REG R_I7); // Ret Addr is in register I7
3200 // Body of function which returns an OptoRegs array locating
3201 // arguments either in registers or in stack slots for calling
3202 // java
3203 calling_convention %{
3204 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3206 %}
3208 // Body of function which returns an OptoRegs array locating
3209 // arguments either in registers or in stack slots for callin
3210 // C.
3211 c_calling_convention %{
3212 // This is obviously always outgoing
3213 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3214 %}
3216 // Location of native (C/C++) and interpreter return values. This is specified to
3217 // be the same as Java. In the 32-bit VM, long values are actually returned from
3218 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3219 // to and from the register pairs is done by the appropriate call and epilog
3220 // opcodes. This simplifies the register allocator.
3221 c_return_value %{
3222 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3223 #ifdef _LP64
3224 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3225 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3226 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3227 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3228 #else // !_LP64
3229 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3230 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3231 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3232 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3233 #endif
3234 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3235 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3236 %}
3238 // Location of compiled Java return values. Same as C
3239 return_value %{
3240 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3241 #ifdef _LP64
3242 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3243 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3244 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3245 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3246 #else // !_LP64
3247 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3248 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3249 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3250 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3251 #endif
3252 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3253 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3254 %}
3256 %}
3259 //----------ATTRIBUTES---------------------------------------------------------
3260 //----------Operand Attributes-------------------------------------------------
3261 op_attrib op_cost(1); // Required cost attribute
3263 //----------Instruction Attributes---------------------------------------------
3264 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3265 ins_attrib ins_size(32); // Required size attribute (in bits)
3266 ins_attrib ins_pc_relative(0); // Required PC Relative flag
3267 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3268 // non-matching short branch variant of some
3269 // long branch?
3271 //----------OPERANDS-----------------------------------------------------------
3272 // Operand definitions must precede instruction definitions for correct parsing
3273 // in the ADLC because operands constitute user defined types which are used in
3274 // instruction definitions.
3276 //----------Simple Operands----------------------------------------------------
3277 // Immediate Operands
3278 // Integer Immediate: 32-bit
3279 operand immI() %{
3280 match(ConI);
3282 op_cost(0);
3283 // formats are generated automatically for constants and base registers
3284 format %{ %}
3285 interface(CONST_INTER);
3286 %}
3288 // Integer Immediate: 13-bit
3289 operand immI13() %{
3290 predicate(Assembler::is_simm13(n->get_int()));
3291 match(ConI);
3292 op_cost(0);
3294 format %{ %}
3295 interface(CONST_INTER);
3296 %}
3298 // Unsigned (positive) Integer Immediate: 13-bit
3299 operand immU13() %{
3300 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3301 match(ConI);
3302 op_cost(0);
3304 format %{ %}
3305 interface(CONST_INTER);
3306 %}
3308 // Integer Immediate: 6-bit
3309 operand immU6() %{
3310 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3311 match(ConI);
3312 op_cost(0);
3313 format %{ %}
3314 interface(CONST_INTER);
3315 %}
3317 // Integer Immediate: 11-bit
3318 operand immI11() %{
3319 predicate(Assembler::is_simm(n->get_int(),11));
3320 match(ConI);
3321 op_cost(0);
3322 format %{ %}
3323 interface(CONST_INTER);
3324 %}
3326 // Integer Immediate: 0-bit
3327 operand immI0() %{
3328 predicate(n->get_int() == 0);
3329 match(ConI);
3330 op_cost(0);
3332 format %{ %}
3333 interface(CONST_INTER);
3334 %}
3336 // Integer Immediate: the value 10
3337 operand immI10() %{
3338 predicate(n->get_int() == 10);
3339 match(ConI);
3340 op_cost(0);
3342 format %{ %}
3343 interface(CONST_INTER);
3344 %}
3346 // Integer Immediate: the values 0-31
3347 operand immU5() %{
3348 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3349 match(ConI);
3350 op_cost(0);
3352 format %{ %}
3353 interface(CONST_INTER);
3354 %}
3356 // Integer Immediate: the values 1-31
3357 operand immI_1_31() %{
3358 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3359 match(ConI);
3360 op_cost(0);
3362 format %{ %}
3363 interface(CONST_INTER);
3364 %}
3366 // Integer Immediate: the values 32-63
3367 operand immI_32_63() %{
3368 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3369 match(ConI);
3370 op_cost(0);
3372 format %{ %}
3373 interface(CONST_INTER);
3374 %}
3376 // Integer Immediate: the value 255
3377 operand immI_255() %{
3378 predicate( n->get_int() == 255 );
3379 match(ConI);
3380 op_cost(0);
3382 format %{ %}
3383 interface(CONST_INTER);
3384 %}
3386 // Long Immediate: the value FF
3387 operand immL_FF() %{
3388 predicate( n->get_long() == 0xFFL );
3389 match(ConL);
3390 op_cost(0);
3392 format %{ %}
3393 interface(CONST_INTER);
3394 %}
3396 // Long Immediate: the value FFFF
3397 operand immL_FFFF() %{
3398 predicate( n->get_long() == 0xFFFFL );
3399 match(ConL);
3400 op_cost(0);
3402 format %{ %}
3403 interface(CONST_INTER);
3404 %}
3406 // Pointer Immediate: 32 or 64-bit
3407 operand immP() %{
3408 match(ConP);
3410 op_cost(5);
3411 // formats are generated automatically for constants and base registers
3412 format %{ %}
3413 interface(CONST_INTER);
3414 %}
3416 operand immP13() %{
3417 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3418 match(ConP);
3419 op_cost(0);
3421 format %{ %}
3422 interface(CONST_INTER);
3423 %}
3425 operand immP0() %{
3426 predicate(n->get_ptr() == 0);
3427 match(ConP);
3428 op_cost(0);
3430 format %{ %}
3431 interface(CONST_INTER);
3432 %}
3434 operand immP_poll() %{
3435 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3436 match(ConP);
3438 // formats are generated automatically for constants and base registers
3439 format %{ %}
3440 interface(CONST_INTER);
3441 %}
3443 // Pointer Immediate
3444 operand immN()
3445 %{
3446 match(ConN);
3448 op_cost(10);
3449 format %{ %}
3450 interface(CONST_INTER);
3451 %}
3453 // NULL Pointer Immediate
3454 operand immN0()
3455 %{
3456 predicate(n->get_narrowcon() == 0);
3457 match(ConN);
3459 op_cost(0);
3460 format %{ %}
3461 interface(CONST_INTER);
3462 %}
3464 operand immL() %{
3465 match(ConL);
3466 op_cost(40);
3467 // formats are generated automatically for constants and base registers
3468 format %{ %}
3469 interface(CONST_INTER);
3470 %}
3472 operand immL0() %{
3473 predicate(n->get_long() == 0L);
3474 match(ConL);
3475 op_cost(0);
3476 // formats are generated automatically for constants and base registers
3477 format %{ %}
3478 interface(CONST_INTER);
3479 %}
3481 // Long Immediate: 13-bit
3482 operand immL13() %{
3483 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3484 match(ConL);
3485 op_cost(0);
3487 format %{ %}
3488 interface(CONST_INTER);
3489 %}
3491 // Long Immediate: low 32-bit mask
3492 operand immL_32bits() %{
3493 predicate(n->get_long() == 0xFFFFFFFFL);
3494 match(ConL);
3495 op_cost(0);
3497 format %{ %}
3498 interface(CONST_INTER);
3499 %}
3501 // Double Immediate
3502 operand immD() %{
3503 match(ConD);
3505 op_cost(40);
3506 format %{ %}
3507 interface(CONST_INTER);
3508 %}
3510 operand immD0() %{
3511 #ifdef _LP64
3512 // on 64-bit architectures this comparision is faster
3513 predicate(jlong_cast(n->getd()) == 0);
3514 #else
3515 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3516 #endif
3517 match(ConD);
3519 op_cost(0);
3520 format %{ %}
3521 interface(CONST_INTER);
3522 %}
3524 // Float Immediate
3525 operand immF() %{
3526 match(ConF);
3528 op_cost(20);
3529 format %{ %}
3530 interface(CONST_INTER);
3531 %}
3533 // Float Immediate: 0
3534 operand immF0() %{
3535 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3536 match(ConF);
3538 op_cost(0);
3539 format %{ %}
3540 interface(CONST_INTER);
3541 %}
3543 // Integer Register Operands
3544 // Integer Register
3545 operand iRegI() %{
3546 constraint(ALLOC_IN_RC(int_reg));
3547 match(RegI);
3549 match(notemp_iRegI);
3550 match(g1RegI);
3551 match(o0RegI);
3552 match(iRegIsafe);
3554 format %{ %}
3555 interface(REG_INTER);
3556 %}
3558 operand notemp_iRegI() %{
3559 constraint(ALLOC_IN_RC(notemp_int_reg));
3560 match(RegI);
3562 match(o0RegI);
3564 format %{ %}
3565 interface(REG_INTER);
3566 %}
3568 operand o0RegI() %{
3569 constraint(ALLOC_IN_RC(o0_regI));
3570 match(iRegI);
3572 format %{ %}
3573 interface(REG_INTER);
3574 %}
3576 // Pointer Register
3577 operand iRegP() %{
3578 constraint(ALLOC_IN_RC(ptr_reg));
3579 match(RegP);
3581 match(lock_ptr_RegP);
3582 match(g1RegP);
3583 match(g2RegP);
3584 match(g3RegP);
3585 match(g4RegP);
3586 match(i0RegP);
3587 match(o0RegP);
3588 match(o1RegP);
3589 match(l7RegP);
3591 format %{ %}
3592 interface(REG_INTER);
3593 %}
3595 operand sp_ptr_RegP() %{
3596 constraint(ALLOC_IN_RC(sp_ptr_reg));
3597 match(RegP);
3598 match(iRegP);
3600 format %{ %}
3601 interface(REG_INTER);
3602 %}
3604 operand lock_ptr_RegP() %{
3605 constraint(ALLOC_IN_RC(lock_ptr_reg));
3606 match(RegP);
3607 match(i0RegP);
3608 match(o0RegP);
3609 match(o1RegP);
3610 match(l7RegP);
3612 format %{ %}
3613 interface(REG_INTER);
3614 %}
3616 operand g1RegP() %{
3617 constraint(ALLOC_IN_RC(g1_regP));
3618 match(iRegP);
3620 format %{ %}
3621 interface(REG_INTER);
3622 %}
3624 operand g2RegP() %{
3625 constraint(ALLOC_IN_RC(g2_regP));
3626 match(iRegP);
3628 format %{ %}
3629 interface(REG_INTER);
3630 %}
3632 operand g3RegP() %{
3633 constraint(ALLOC_IN_RC(g3_regP));
3634 match(iRegP);
3636 format %{ %}
3637 interface(REG_INTER);
3638 %}
3640 operand g1RegI() %{
3641 constraint(ALLOC_IN_RC(g1_regI));
3642 match(iRegI);
3644 format %{ %}
3645 interface(REG_INTER);
3646 %}
3648 operand g3RegI() %{
3649 constraint(ALLOC_IN_RC(g3_regI));
3650 match(iRegI);
3652 format %{ %}
3653 interface(REG_INTER);
3654 %}
3656 operand g4RegI() %{
3657 constraint(ALLOC_IN_RC(g4_regI));
3658 match(iRegI);
3660 format %{ %}
3661 interface(REG_INTER);
3662 %}
3664 operand g4RegP() %{
3665 constraint(ALLOC_IN_RC(g4_regP));
3666 match(iRegP);
3668 format %{ %}
3669 interface(REG_INTER);
3670 %}
3672 operand i0RegP() %{
3673 constraint(ALLOC_IN_RC(i0_regP));
3674 match(iRegP);
3676 format %{ %}
3677 interface(REG_INTER);
3678 %}
3680 operand o0RegP() %{
3681 constraint(ALLOC_IN_RC(o0_regP));
3682 match(iRegP);
3684 format %{ %}
3685 interface(REG_INTER);
3686 %}
3688 operand o1RegP() %{
3689 constraint(ALLOC_IN_RC(o1_regP));
3690 match(iRegP);
3692 format %{ %}
3693 interface(REG_INTER);
3694 %}
3696 operand o2RegP() %{
3697 constraint(ALLOC_IN_RC(o2_regP));
3698 match(iRegP);
3700 format %{ %}
3701 interface(REG_INTER);
3702 %}
3704 operand o7RegP() %{
3705 constraint(ALLOC_IN_RC(o7_regP));
3706 match(iRegP);
3708 format %{ %}
3709 interface(REG_INTER);
3710 %}
3712 operand l7RegP() %{
3713 constraint(ALLOC_IN_RC(l7_regP));
3714 match(iRegP);
3716 format %{ %}
3717 interface(REG_INTER);
3718 %}
3720 operand o7RegI() %{
3721 constraint(ALLOC_IN_RC(o7_regI));
3722 match(iRegI);
3724 format %{ %}
3725 interface(REG_INTER);
3726 %}
3728 operand iRegN() %{
3729 constraint(ALLOC_IN_RC(int_reg));
3730 match(RegN);
3732 format %{ %}
3733 interface(REG_INTER);
3734 %}
3736 // Long Register
3737 operand iRegL() %{
3738 constraint(ALLOC_IN_RC(long_reg));
3739 match(RegL);
3741 format %{ %}
3742 interface(REG_INTER);
3743 %}
3745 operand o2RegL() %{
3746 constraint(ALLOC_IN_RC(o2_regL));
3747 match(iRegL);
3749 format %{ %}
3750 interface(REG_INTER);
3751 %}
3753 operand o7RegL() %{
3754 constraint(ALLOC_IN_RC(o7_regL));
3755 match(iRegL);
3757 format %{ %}
3758 interface(REG_INTER);
3759 %}
3761 operand g1RegL() %{
3762 constraint(ALLOC_IN_RC(g1_regL));
3763 match(iRegL);
3765 format %{ %}
3766 interface(REG_INTER);
3767 %}
3769 operand g3RegL() %{
3770 constraint(ALLOC_IN_RC(g3_regL));
3771 match(iRegL);
3773 format %{ %}
3774 interface(REG_INTER);
3775 %}
3777 // Int Register safe
3778 // This is 64bit safe
3779 operand iRegIsafe() %{
3780 constraint(ALLOC_IN_RC(long_reg));
3782 match(iRegI);
3784 format %{ %}
3785 interface(REG_INTER);
3786 %}
3788 // Condition Code Flag Register
3789 operand flagsReg() %{
3790 constraint(ALLOC_IN_RC(int_flags));
3791 match(RegFlags);
3793 format %{ "ccr" %} // both ICC and XCC
3794 interface(REG_INTER);
3795 %}
3797 // Condition Code Register, unsigned comparisons.
3798 operand flagsRegU() %{
3799 constraint(ALLOC_IN_RC(int_flags));
3800 match(RegFlags);
3802 format %{ "icc_U" %}
3803 interface(REG_INTER);
3804 %}
3806 // Condition Code Register, pointer comparisons.
3807 operand flagsRegP() %{
3808 constraint(ALLOC_IN_RC(int_flags));
3809 match(RegFlags);
3811 #ifdef _LP64
3812 format %{ "xcc_P" %}
3813 #else
3814 format %{ "icc_P" %}
3815 #endif
3816 interface(REG_INTER);
3817 %}
3819 // Condition Code Register, long comparisons.
3820 operand flagsRegL() %{
3821 constraint(ALLOC_IN_RC(int_flags));
3822 match(RegFlags);
3824 format %{ "xcc_L" %}
3825 interface(REG_INTER);
3826 %}
3828 // Condition Code Register, floating comparisons, unordered same as "less".
3829 operand flagsRegF() %{
3830 constraint(ALLOC_IN_RC(float_flags));
3831 match(RegFlags);
3832 match(flagsRegF0);
3834 format %{ %}
3835 interface(REG_INTER);
3836 %}
3838 operand flagsRegF0() %{
3839 constraint(ALLOC_IN_RC(float_flag0));
3840 match(RegFlags);
3842 format %{ %}
3843 interface(REG_INTER);
3844 %}
3847 // Condition Code Flag Register used by long compare
3848 operand flagsReg_long_LTGE() %{
3849 constraint(ALLOC_IN_RC(int_flags));
3850 match(RegFlags);
3851 format %{ "icc_LTGE" %}
3852 interface(REG_INTER);
3853 %}
3854 operand flagsReg_long_EQNE() %{
3855 constraint(ALLOC_IN_RC(int_flags));
3856 match(RegFlags);
3857 format %{ "icc_EQNE" %}
3858 interface(REG_INTER);
3859 %}
3860 operand flagsReg_long_LEGT() %{
3861 constraint(ALLOC_IN_RC(int_flags));
3862 match(RegFlags);
3863 format %{ "icc_LEGT" %}
3864 interface(REG_INTER);
3865 %}
3868 operand regD() %{
3869 constraint(ALLOC_IN_RC(dflt_reg));
3870 match(RegD);
3872 match(regD_low);
3874 format %{ %}
3875 interface(REG_INTER);
3876 %}
3878 operand regF() %{
3879 constraint(ALLOC_IN_RC(sflt_reg));
3880 match(RegF);
3882 format %{ %}
3883 interface(REG_INTER);
3884 %}
3886 operand regD_low() %{
3887 constraint(ALLOC_IN_RC(dflt_low_reg));
3888 match(regD);
3890 format %{ %}
3891 interface(REG_INTER);
3892 %}
3894 // Special Registers
3896 // Method Register
3897 operand inline_cache_regP(iRegP reg) %{
3898 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
3899 match(reg);
3900 format %{ %}
3901 interface(REG_INTER);
3902 %}
3904 operand interpreter_method_oop_regP(iRegP reg) %{
3905 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
3906 match(reg);
3907 format %{ %}
3908 interface(REG_INTER);
3909 %}
3912 //----------Complex Operands---------------------------------------------------
3913 // Indirect Memory Reference
3914 operand indirect(sp_ptr_RegP reg) %{
3915 constraint(ALLOC_IN_RC(sp_ptr_reg));
3916 match(reg);
3918 op_cost(100);
3919 format %{ "[$reg]" %}
3920 interface(MEMORY_INTER) %{
3921 base($reg);
3922 index(0x0);
3923 scale(0x0);
3924 disp(0x0);
3925 %}
3926 %}
3928 // Indirect with Offset
3929 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
3930 constraint(ALLOC_IN_RC(sp_ptr_reg));
3931 match(AddP reg offset);
3933 op_cost(100);
3934 format %{ "[$reg + $offset]" %}
3935 interface(MEMORY_INTER) %{
3936 base($reg);
3937 index(0x0);
3938 scale(0x0);
3939 disp($offset);
3940 %}
3941 %}
3943 // Note: Intel has a swapped version also, like this:
3944 //operand indOffsetX(iRegI reg, immP offset) %{
3945 // constraint(ALLOC_IN_RC(int_reg));
3946 // match(AddP offset reg);
3947 //
3948 // op_cost(100);
3949 // format %{ "[$reg + $offset]" %}
3950 // interface(MEMORY_INTER) %{
3951 // base($reg);
3952 // index(0x0);
3953 // scale(0x0);
3954 // disp($offset);
3955 // %}
3956 //%}
3957 //// However, it doesn't make sense for SPARC, since
3958 // we have no particularly good way to embed oops in
3959 // single instructions.
3961 // Indirect with Register Index
3962 operand indIndex(iRegP addr, iRegX index) %{
3963 constraint(ALLOC_IN_RC(ptr_reg));
3964 match(AddP addr index);
3966 op_cost(100);
3967 format %{ "[$addr + $index]" %}
3968 interface(MEMORY_INTER) %{
3969 base($addr);
3970 index($index);
3971 scale(0x0);
3972 disp(0x0);
3973 %}
3974 %}
3976 //----------Special Memory Operands--------------------------------------------
3977 // Stack Slot Operand - This operand is used for loading and storing temporary
3978 // values on the stack where a match requires a value to
3979 // flow through memory.
3980 operand stackSlotI(sRegI reg) %{
3981 constraint(ALLOC_IN_RC(stack_slots));
3982 op_cost(100);
3983 //match(RegI);
3984 format %{ "[$reg]" %}
3985 interface(MEMORY_INTER) %{
3986 base(0xE); // R_SP
3987 index(0x0);
3988 scale(0x0);
3989 disp($reg); // Stack Offset
3990 %}
3991 %}
3993 operand stackSlotP(sRegP reg) %{
3994 constraint(ALLOC_IN_RC(stack_slots));
3995 op_cost(100);
3996 //match(RegP);
3997 format %{ "[$reg]" %}
3998 interface(MEMORY_INTER) %{
3999 base(0xE); // R_SP
4000 index(0x0);
4001 scale(0x0);
4002 disp($reg); // Stack Offset
4003 %}
4004 %}
4006 operand stackSlotF(sRegF reg) %{
4007 constraint(ALLOC_IN_RC(stack_slots));
4008 op_cost(100);
4009 //match(RegF);
4010 format %{ "[$reg]" %}
4011 interface(MEMORY_INTER) %{
4012 base(0xE); // R_SP
4013 index(0x0);
4014 scale(0x0);
4015 disp($reg); // Stack Offset
4016 %}
4017 %}
4018 operand stackSlotD(sRegD reg) %{
4019 constraint(ALLOC_IN_RC(stack_slots));
4020 op_cost(100);
4021 //match(RegD);
4022 format %{ "[$reg]" %}
4023 interface(MEMORY_INTER) %{
4024 base(0xE); // R_SP
4025 index(0x0);
4026 scale(0x0);
4027 disp($reg); // Stack Offset
4028 %}
4029 %}
4030 operand stackSlotL(sRegL reg) %{
4031 constraint(ALLOC_IN_RC(stack_slots));
4032 op_cost(100);
4033 //match(RegL);
4034 format %{ "[$reg]" %}
4035 interface(MEMORY_INTER) %{
4036 base(0xE); // R_SP
4037 index(0x0);
4038 scale(0x0);
4039 disp($reg); // Stack Offset
4040 %}
4041 %}
4043 // Operands for expressing Control Flow
4044 // NOTE: Label is a predefined operand which should not be redefined in
4045 // the AD file. It is generically handled within the ADLC.
4047 //----------Conditional Branch Operands----------------------------------------
4048 // Comparison Op - This is the operation of the comparison, and is limited to
4049 // the following set of codes:
4050 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4051 //
4052 // Other attributes of the comparison, such as unsignedness, are specified
4053 // by the comparison instruction that sets a condition code flags register.
4054 // That result is represented by a flags operand whose subtype is appropriate
4055 // to the unsignedness (etc.) of the comparison.
4056 //
4057 // Later, the instruction which matches both the Comparison Op (a Bool) and
4058 // the flags (produced by the Cmp) specifies the coding of the comparison op
4059 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4061 operand cmpOp() %{
4062 match(Bool);
4064 format %{ "" %}
4065 interface(COND_INTER) %{
4066 equal(0x1);
4067 not_equal(0x9);
4068 less(0x3);
4069 greater_equal(0xB);
4070 less_equal(0x2);
4071 greater(0xA);
4072 %}
4073 %}
4075 // Comparison Op, unsigned
4076 operand cmpOpU() %{
4077 match(Bool);
4079 format %{ "u" %}
4080 interface(COND_INTER) %{
4081 equal(0x1);
4082 not_equal(0x9);
4083 less(0x5);
4084 greater_equal(0xD);
4085 less_equal(0x4);
4086 greater(0xC);
4087 %}
4088 %}
4090 // Comparison Op, pointer (same as unsigned)
4091 operand cmpOpP() %{
4092 match(Bool);
4094 format %{ "p" %}
4095 interface(COND_INTER) %{
4096 equal(0x1);
4097 not_equal(0x9);
4098 less(0x5);
4099 greater_equal(0xD);
4100 less_equal(0x4);
4101 greater(0xC);
4102 %}
4103 %}
4105 // Comparison Op, branch-register encoding
4106 operand cmpOp_reg() %{
4107 match(Bool);
4109 format %{ "" %}
4110 interface(COND_INTER) %{
4111 equal (0x1);
4112 not_equal (0x5);
4113 less (0x3);
4114 greater_equal(0x7);
4115 less_equal (0x2);
4116 greater (0x6);
4117 %}
4118 %}
4120 // Comparison Code, floating, unordered same as less
4121 operand cmpOpF() %{
4122 match(Bool);
4124 format %{ "fl" %}
4125 interface(COND_INTER) %{
4126 equal(0x9);
4127 not_equal(0x1);
4128 less(0x3);
4129 greater_equal(0xB);
4130 less_equal(0xE);
4131 greater(0x6);
4132 %}
4133 %}
4135 // Used by long compare
4136 operand cmpOp_commute() %{
4137 match(Bool);
4139 format %{ "" %}
4140 interface(COND_INTER) %{
4141 equal(0x1);
4142 not_equal(0x9);
4143 less(0xA);
4144 greater_equal(0x2);
4145 less_equal(0xB);
4146 greater(0x3);
4147 %}
4148 %}
4150 //----------OPERAND CLASSES----------------------------------------------------
4151 // Operand Classes are groups of operands that are used to simplify
4152 // instruction definitions by not requiring the AD writer to specify separate
4153 // instructions for every form of operand when the instruction accepts
4154 // multiple operand types with the same basic encoding and format. The classic
4155 // case of this is memory operands.
4156 // Indirect is not included since its use is limited to Compare & Swap
4157 opclass memory( indirect, indOffset13, indIndex );
4159 //----------PIPELINE-----------------------------------------------------------
4160 pipeline %{
4162 //----------ATTRIBUTES---------------------------------------------------------
4163 attributes %{
4164 fixed_size_instructions; // Fixed size instructions
4165 branch_has_delay_slot; // Branch has delay slot following
4166 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4167 instruction_unit_size = 4; // An instruction is 4 bytes long
4168 instruction_fetch_unit_size = 16; // The processor fetches one line
4169 instruction_fetch_units = 1; // of 16 bytes
4171 // List of nop instructions
4172 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4173 %}
4175 //----------RESOURCES----------------------------------------------------------
4176 // Resources are the functional units available to the machine
4177 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4179 //----------PIPELINE DESCRIPTION-----------------------------------------------
4180 // Pipeline Description specifies the stages in the machine's pipeline
4182 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4184 //----------PIPELINE CLASSES---------------------------------------------------
4185 // Pipeline Classes describe the stages in which input and output are
4186 // referenced by the hardware pipeline.
4188 // Integer ALU reg-reg operation
4189 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4190 single_instruction;
4191 dst : E(write);
4192 src1 : R(read);
4193 src2 : R(read);
4194 IALU : R;
4195 %}
4197 // Integer ALU reg-reg long operation
4198 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4199 instruction_count(2);
4200 dst : E(write);
4201 src1 : R(read);
4202 src2 : R(read);
4203 IALU : R;
4204 IALU : R;
4205 %}
4207 // Integer ALU reg-reg long dependent operation
4208 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4209 instruction_count(1); multiple_bundles;
4210 dst : E(write);
4211 src1 : R(read);
4212 src2 : R(read);
4213 cr : E(write);
4214 IALU : R(2);
4215 %}
4217 // Integer ALU reg-imm operaion
4218 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4219 single_instruction;
4220 dst : E(write);
4221 src1 : R(read);
4222 IALU : R;
4223 %}
4225 // Integer ALU reg-reg operation with condition code
4226 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4227 single_instruction;
4228 dst : E(write);
4229 cr : E(write);
4230 src1 : R(read);
4231 src2 : R(read);
4232 IALU : R;
4233 %}
4235 // Integer ALU reg-imm operation with condition code
4236 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4237 single_instruction;
4238 dst : E(write);
4239 cr : E(write);
4240 src1 : R(read);
4241 IALU : R;
4242 %}
4244 // Integer ALU zero-reg operation
4245 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4246 single_instruction;
4247 dst : E(write);
4248 src2 : R(read);
4249 IALU : R;
4250 %}
4252 // Integer ALU zero-reg operation with condition code only
4253 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4254 single_instruction;
4255 cr : E(write);
4256 src : R(read);
4257 IALU : R;
4258 %}
4260 // Integer ALU reg-reg operation with condition code only
4261 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4262 single_instruction;
4263 cr : E(write);
4264 src1 : R(read);
4265 src2 : R(read);
4266 IALU : R;
4267 %}
4269 // Integer ALU reg-imm operation with condition code only
4270 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4271 single_instruction;
4272 cr : E(write);
4273 src1 : R(read);
4274 IALU : R;
4275 %}
4277 // Integer ALU reg-reg-zero operation with condition code only
4278 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4279 single_instruction;
4280 cr : E(write);
4281 src1 : R(read);
4282 src2 : R(read);
4283 IALU : R;
4284 %}
4286 // Integer ALU reg-imm-zero operation with condition code only
4287 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4288 single_instruction;
4289 cr : E(write);
4290 src1 : R(read);
4291 IALU : R;
4292 %}
4294 // Integer ALU reg-reg operation with condition code, src1 modified
4295 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4296 single_instruction;
4297 cr : E(write);
4298 src1 : E(write);
4299 src1 : R(read);
4300 src2 : R(read);
4301 IALU : R;
4302 %}
4304 // Integer ALU reg-imm operation with condition code, src1 modified
4305 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4306 single_instruction;
4307 cr : E(write);
4308 src1 : E(write);
4309 src1 : R(read);
4310 IALU : R;
4311 %}
4313 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4314 multiple_bundles;
4315 dst : E(write)+4;
4316 cr : E(write);
4317 src1 : R(read);
4318 src2 : R(read);
4319 IALU : R(3);
4320 BR : R(2);
4321 %}
4323 // Integer ALU operation
4324 pipe_class ialu_none(iRegI dst) %{
4325 single_instruction;
4326 dst : E(write);
4327 IALU : R;
4328 %}
4330 // Integer ALU reg operation
4331 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4332 single_instruction; may_have_no_code;
4333 dst : E(write);
4334 src : R(read);
4335 IALU : R;
4336 %}
4338 // Integer ALU reg conditional operation
4339 // This instruction has a 1 cycle stall, and cannot execute
4340 // in the same cycle as the instruction setting the condition
4341 // code. We kludge this by pretending to read the condition code
4342 // 1 cycle earlier, and by marking the functional units as busy
4343 // for 2 cycles with the result available 1 cycle later than
4344 // is really the case.
4345 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4346 single_instruction;
4347 op2_out : C(write);
4348 op1 : R(read);
4349 cr : R(read); // This is really E, with a 1 cycle stall
4350 BR : R(2);
4351 MS : R(2);
4352 %}
4354 #ifdef _LP64
4355 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4356 instruction_count(1); multiple_bundles;
4357 dst : C(write)+1;
4358 src : R(read)+1;
4359 IALU : R(1);
4360 BR : E(2);
4361 MS : E(2);
4362 %}
4363 #endif
4365 // Integer ALU reg operation
4366 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4367 single_instruction; may_have_no_code;
4368 dst : E(write);
4369 src : R(read);
4370 IALU : R;
4371 %}
4372 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4373 single_instruction; may_have_no_code;
4374 dst : E(write);
4375 src : R(read);
4376 IALU : R;
4377 %}
4379 // Two integer ALU reg operations
4380 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4381 instruction_count(2);
4382 dst : E(write);
4383 src : R(read);
4384 A0 : R;
4385 A1 : R;
4386 %}
4388 // Two integer ALU reg operations
4389 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4390 instruction_count(2); may_have_no_code;
4391 dst : E(write);
4392 src : R(read);
4393 A0 : R;
4394 A1 : R;
4395 %}
4397 // Integer ALU imm operation
4398 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4399 single_instruction;
4400 dst : E(write);
4401 IALU : R;
4402 %}
4404 // Integer ALU reg-reg with carry operation
4405 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4406 single_instruction;
4407 dst : E(write);
4408 src1 : R(read);
4409 src2 : R(read);
4410 IALU : R;
4411 %}
4413 // Integer ALU cc operation
4414 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4415 single_instruction;
4416 dst : E(write);
4417 cc : R(read);
4418 IALU : R;
4419 %}
4421 // Integer ALU cc / second IALU operation
4422 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4423 instruction_count(1); multiple_bundles;
4424 dst : E(write)+1;
4425 src : R(read);
4426 IALU : R;
4427 %}
4429 // Integer ALU cc / second IALU operation
4430 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4431 instruction_count(1); multiple_bundles;
4432 dst : E(write)+1;
4433 p : R(read);
4434 q : R(read);
4435 IALU : R;
4436 %}
4438 // Integer ALU hi-lo-reg operation
4439 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4440 instruction_count(1); multiple_bundles;
4441 dst : E(write)+1;
4442 IALU : R(2);
4443 %}
4445 // Float ALU hi-lo-reg operation (with temp)
4446 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4447 instruction_count(1); multiple_bundles;
4448 dst : E(write)+1;
4449 IALU : R(2);
4450 %}
4452 // Long Constant
4453 pipe_class loadConL( iRegL dst, immL src ) %{
4454 instruction_count(2); multiple_bundles;
4455 dst : E(write)+1;
4456 IALU : R(2);
4457 IALU : R(2);
4458 %}
4460 // Pointer Constant
4461 pipe_class loadConP( iRegP dst, immP src ) %{
4462 instruction_count(0); multiple_bundles;
4463 fixed_latency(6);
4464 %}
4466 // Polling Address
4467 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4468 #ifdef _LP64
4469 instruction_count(0); multiple_bundles;
4470 fixed_latency(6);
4471 #else
4472 dst : E(write);
4473 IALU : R;
4474 #endif
4475 %}
4477 // Long Constant small
4478 pipe_class loadConLlo( iRegL dst, immL src ) %{
4479 instruction_count(2);
4480 dst : E(write);
4481 IALU : R;
4482 IALU : R;
4483 %}
4485 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4486 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4487 instruction_count(1); multiple_bundles;
4488 src : R(read);
4489 dst : M(write)+1;
4490 IALU : R;
4491 MS : E;
4492 %}
4494 // Integer ALU nop operation
4495 pipe_class ialu_nop() %{
4496 single_instruction;
4497 IALU : R;
4498 %}
4500 // Integer ALU nop operation
4501 pipe_class ialu_nop_A0() %{
4502 single_instruction;
4503 A0 : R;
4504 %}
4506 // Integer ALU nop operation
4507 pipe_class ialu_nop_A1() %{
4508 single_instruction;
4509 A1 : R;
4510 %}
4512 // Integer Multiply reg-reg operation
4513 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4514 single_instruction;
4515 dst : E(write);
4516 src1 : R(read);
4517 src2 : R(read);
4518 MS : R(5);
4519 %}
4521 // Integer Multiply reg-imm operation
4522 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4523 single_instruction;
4524 dst : E(write);
4525 src1 : R(read);
4526 MS : R(5);
4527 %}
4529 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4530 single_instruction;
4531 dst : E(write)+4;
4532 src1 : R(read);
4533 src2 : R(read);
4534 MS : R(6);
4535 %}
4537 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4538 single_instruction;
4539 dst : E(write)+4;
4540 src1 : R(read);
4541 MS : R(6);
4542 %}
4544 // Integer Divide reg-reg
4545 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4546 instruction_count(1); multiple_bundles;
4547 dst : E(write);
4548 temp : E(write);
4549 src1 : R(read);
4550 src2 : R(read);
4551 temp : R(read);
4552 MS : R(38);
4553 %}
4555 // Integer Divide reg-imm
4556 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4557 instruction_count(1); multiple_bundles;
4558 dst : E(write);
4559 temp : E(write);
4560 src1 : R(read);
4561 temp : R(read);
4562 MS : R(38);
4563 %}
4565 // Long Divide
4566 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4567 dst : E(write)+71;
4568 src1 : R(read);
4569 src2 : R(read)+1;
4570 MS : R(70);
4571 %}
4573 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4574 dst : E(write)+71;
4575 src1 : R(read);
4576 MS : R(70);
4577 %}
4579 // Floating Point Add Float
4580 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4581 single_instruction;
4582 dst : X(write);
4583 src1 : E(read);
4584 src2 : E(read);
4585 FA : R;
4586 %}
4588 // Floating Point Add Double
4589 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4590 single_instruction;
4591 dst : X(write);
4592 src1 : E(read);
4593 src2 : E(read);
4594 FA : R;
4595 %}
4597 // Floating Point Conditional Move based on integer flags
4598 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4599 single_instruction;
4600 dst : X(write);
4601 src : E(read);
4602 cr : R(read);
4603 FA : R(2);
4604 BR : R(2);
4605 %}
4607 // Floating Point Conditional Move based on integer flags
4608 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4609 single_instruction;
4610 dst : X(write);
4611 src : E(read);
4612 cr : R(read);
4613 FA : R(2);
4614 BR : R(2);
4615 %}
4617 // Floating Point Multiply Float
4618 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4619 single_instruction;
4620 dst : X(write);
4621 src1 : E(read);
4622 src2 : E(read);
4623 FM : R;
4624 %}
4626 // Floating Point Multiply Double
4627 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4628 single_instruction;
4629 dst : X(write);
4630 src1 : E(read);
4631 src2 : E(read);
4632 FM : R;
4633 %}
4635 // Floating Point Divide Float
4636 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4637 single_instruction;
4638 dst : X(write);
4639 src1 : E(read);
4640 src2 : E(read);
4641 FM : R;
4642 FDIV : C(14);
4643 %}
4645 // Floating Point Divide Double
4646 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4647 single_instruction;
4648 dst : X(write);
4649 src1 : E(read);
4650 src2 : E(read);
4651 FM : R;
4652 FDIV : C(17);
4653 %}
4655 // Floating Point Move/Negate/Abs Float
4656 pipe_class faddF_reg(regF dst, regF src) %{
4657 single_instruction;
4658 dst : W(write);
4659 src : E(read);
4660 FA : R(1);
4661 %}
4663 // Floating Point Move/Negate/Abs Double
4664 pipe_class faddD_reg(regD dst, regD src) %{
4665 single_instruction;
4666 dst : W(write);
4667 src : E(read);
4668 FA : R;
4669 %}
4671 // Floating Point Convert F->D
4672 pipe_class fcvtF2D(regD dst, regF src) %{
4673 single_instruction;
4674 dst : X(write);
4675 src : E(read);
4676 FA : R;
4677 %}
4679 // Floating Point Convert I->D
4680 pipe_class fcvtI2D(regD dst, regF src) %{
4681 single_instruction;
4682 dst : X(write);
4683 src : E(read);
4684 FA : R;
4685 %}
4687 // Floating Point Convert LHi->D
4688 pipe_class fcvtLHi2D(regD dst, regD src) %{
4689 single_instruction;
4690 dst : X(write);
4691 src : E(read);
4692 FA : R;
4693 %}
4695 // Floating Point Convert L->D
4696 pipe_class fcvtL2D(regD dst, regF src) %{
4697 single_instruction;
4698 dst : X(write);
4699 src : E(read);
4700 FA : R;
4701 %}
4703 // Floating Point Convert L->F
4704 pipe_class fcvtL2F(regD dst, regF src) %{
4705 single_instruction;
4706 dst : X(write);
4707 src : E(read);
4708 FA : R;
4709 %}
4711 // Floating Point Convert D->F
4712 pipe_class fcvtD2F(regD dst, regF src) %{
4713 single_instruction;
4714 dst : X(write);
4715 src : E(read);
4716 FA : R;
4717 %}
4719 // Floating Point Convert I->L
4720 pipe_class fcvtI2L(regD dst, regF src) %{
4721 single_instruction;
4722 dst : X(write);
4723 src : E(read);
4724 FA : R;
4725 %}
4727 // Floating Point Convert D->F
4728 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4729 instruction_count(1); multiple_bundles;
4730 dst : X(write)+6;
4731 src : E(read);
4732 FA : R;
4733 %}
4735 // Floating Point Convert D->L
4736 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4737 instruction_count(1); multiple_bundles;
4738 dst : X(write)+6;
4739 src : E(read);
4740 FA : R;
4741 %}
4743 // Floating Point Convert F->I
4744 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4745 instruction_count(1); multiple_bundles;
4746 dst : X(write)+6;
4747 src : E(read);
4748 FA : R;
4749 %}
4751 // Floating Point Convert F->L
4752 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4753 instruction_count(1); multiple_bundles;
4754 dst : X(write)+6;
4755 src : E(read);
4756 FA : R;
4757 %}
4759 // Floating Point Convert I->F
4760 pipe_class fcvtI2F(regF dst, regF src) %{
4761 single_instruction;
4762 dst : X(write);
4763 src : E(read);
4764 FA : R;
4765 %}
4767 // Floating Point Compare
4768 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4769 single_instruction;
4770 cr : X(write);
4771 src1 : E(read);
4772 src2 : E(read);
4773 FA : R;
4774 %}
4776 // Floating Point Compare
4777 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4778 single_instruction;
4779 cr : X(write);
4780 src1 : E(read);
4781 src2 : E(read);
4782 FA : R;
4783 %}
4785 // Floating Add Nop
4786 pipe_class fadd_nop() %{
4787 single_instruction;
4788 FA : R;
4789 %}
4791 // Integer Store to Memory
4792 pipe_class istore_mem_reg(memory mem, iRegI src) %{
4793 single_instruction;
4794 mem : R(read);
4795 src : C(read);
4796 MS : R;
4797 %}
4799 // Integer Store to Memory
4800 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
4801 single_instruction;
4802 mem : R(read);
4803 src : C(read);
4804 MS : R;
4805 %}
4807 // Integer Store Zero to Memory
4808 pipe_class istore_mem_zero(memory mem, immI0 src) %{
4809 single_instruction;
4810 mem : R(read);
4811 MS : R;
4812 %}
4814 // Special Stack Slot Store
4815 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
4816 single_instruction;
4817 stkSlot : R(read);
4818 src : C(read);
4819 MS : R;
4820 %}
4822 // Special Stack Slot Store
4823 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
4824 instruction_count(2); multiple_bundles;
4825 stkSlot : R(read);
4826 src : C(read);
4827 MS : R(2);
4828 %}
4830 // Float Store
4831 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
4832 single_instruction;
4833 mem : R(read);
4834 src : C(read);
4835 MS : R;
4836 %}
4838 // Float Store
4839 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
4840 single_instruction;
4841 mem : R(read);
4842 MS : R;
4843 %}
4845 // Double Store
4846 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
4847 instruction_count(1);
4848 mem : R(read);
4849 src : C(read);
4850 MS : R;
4851 %}
4853 // Double Store
4854 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
4855 single_instruction;
4856 mem : R(read);
4857 MS : R;
4858 %}
4860 // Special Stack Slot Float Store
4861 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
4862 single_instruction;
4863 stkSlot : R(read);
4864 src : C(read);
4865 MS : R;
4866 %}
4868 // Special Stack Slot Double Store
4869 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
4870 single_instruction;
4871 stkSlot : R(read);
4872 src : C(read);
4873 MS : R;
4874 %}
4876 // Integer Load (when sign bit propagation not needed)
4877 pipe_class iload_mem(iRegI dst, memory mem) %{
4878 single_instruction;
4879 mem : R(read);
4880 dst : C(write);
4881 MS : R;
4882 %}
4884 // Integer Load from stack operand
4885 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
4886 single_instruction;
4887 mem : R(read);
4888 dst : C(write);
4889 MS : R;
4890 %}
4892 // Integer Load (when sign bit propagation or masking is needed)
4893 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
4894 single_instruction;
4895 mem : R(read);
4896 dst : M(write);
4897 MS : R;
4898 %}
4900 // Float Load
4901 pipe_class floadF_mem(regF dst, memory mem) %{
4902 single_instruction;
4903 mem : R(read);
4904 dst : M(write);
4905 MS : R;
4906 %}
4908 // Float Load
4909 pipe_class floadD_mem(regD dst, memory mem) %{
4910 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
4911 mem : R(read);
4912 dst : M(write);
4913 MS : R;
4914 %}
4916 // Float Load
4917 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
4918 single_instruction;
4919 stkSlot : R(read);
4920 dst : M(write);
4921 MS : R;
4922 %}
4924 // Float Load
4925 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
4926 single_instruction;
4927 stkSlot : R(read);
4928 dst : M(write);
4929 MS : R;
4930 %}
4932 // Memory Nop
4933 pipe_class mem_nop() %{
4934 single_instruction;
4935 MS : R;
4936 %}
4938 pipe_class sethi(iRegP dst, immI src) %{
4939 single_instruction;
4940 dst : E(write);
4941 IALU : R;
4942 %}
4944 pipe_class loadPollP(iRegP poll) %{
4945 single_instruction;
4946 poll : R(read);
4947 MS : R;
4948 %}
4950 pipe_class br(Universe br, label labl) %{
4951 single_instruction_with_delay_slot;
4952 BR : R;
4953 %}
4955 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
4956 single_instruction_with_delay_slot;
4957 cr : E(read);
4958 BR : R;
4959 %}
4961 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
4962 single_instruction_with_delay_slot;
4963 op1 : E(read);
4964 BR : R;
4965 MS : R;
4966 %}
4968 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
4969 single_instruction_with_delay_slot;
4970 cr : E(read);
4971 BR : R;
4972 %}
4974 pipe_class br_nop() %{
4975 single_instruction;
4976 BR : R;
4977 %}
4979 pipe_class simple_call(method meth) %{
4980 instruction_count(2); multiple_bundles; force_serialization;
4981 fixed_latency(100);
4982 BR : R(1);
4983 MS : R(1);
4984 A0 : R(1);
4985 %}
4987 pipe_class compiled_call(method meth) %{
4988 instruction_count(1); multiple_bundles; force_serialization;
4989 fixed_latency(100);
4990 MS : R(1);
4991 %}
4993 pipe_class call(method meth) %{
4994 instruction_count(0); multiple_bundles; force_serialization;
4995 fixed_latency(100);
4996 %}
4998 pipe_class tail_call(Universe ignore, label labl) %{
4999 single_instruction; has_delay_slot;
5000 fixed_latency(100);
5001 BR : R(1);
5002 MS : R(1);
5003 %}
5005 pipe_class ret(Universe ignore) %{
5006 single_instruction; has_delay_slot;
5007 BR : R(1);
5008 MS : R(1);
5009 %}
5011 pipe_class ret_poll(g3RegP poll) %{
5012 instruction_count(3); has_delay_slot;
5013 poll : E(read);
5014 MS : R;
5015 %}
5017 // The real do-nothing guy
5018 pipe_class empty( ) %{
5019 instruction_count(0);
5020 %}
5022 pipe_class long_memory_op() %{
5023 instruction_count(0); multiple_bundles; force_serialization;
5024 fixed_latency(25);
5025 MS : R(1);
5026 %}
5028 // Check-cast
5029 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5030 array : R(read);
5031 match : R(read);
5032 IALU : R(2);
5033 BR : R(2);
5034 MS : R;
5035 %}
5037 // Convert FPU flags into +1,0,-1
5038 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5039 src1 : E(read);
5040 src2 : E(read);
5041 dst : E(write);
5042 FA : R;
5043 MS : R(2);
5044 BR : R(2);
5045 %}
5047 // Compare for p < q, and conditionally add y
5048 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5049 p : E(read);
5050 q : E(read);
5051 y : E(read);
5052 IALU : R(3)
5053 %}
5055 // Perform a compare, then move conditionally in a branch delay slot.
5056 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5057 src2 : E(read);
5058 srcdst : E(read);
5059 IALU : R;
5060 BR : R;
5061 %}
5063 // Define the class for the Nop node
5064 define %{
5065 MachNop = ialu_nop;
5066 %}
5068 %}
5070 //----------INSTRUCTIONS-------------------------------------------------------
5072 //------------Special Stack Slot instructions - no match rules-----------------
5073 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5074 // No match rule to avoid chain rule match.
5075 effect(DEF dst, USE src);
5076 ins_cost(MEMORY_REF_COST);
5077 size(4);
5078 format %{ "LDF $src,$dst\t! stkI to regF" %}
5079 opcode(Assembler::ldf_op3);
5080 ins_encode(simple_form3_mem_reg(src, dst));
5081 ins_pipe(floadF_stk);
5082 %}
5084 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5085 // No match rule to avoid chain rule match.
5086 effect(DEF dst, USE src);
5087 ins_cost(MEMORY_REF_COST);
5088 size(4);
5089 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5090 opcode(Assembler::lddf_op3);
5091 ins_encode(simple_form3_mem_reg(src, dst));
5092 ins_pipe(floadD_stk);
5093 %}
5095 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5096 // No match rule to avoid chain rule match.
5097 effect(DEF dst, USE src);
5098 ins_cost(MEMORY_REF_COST);
5099 size(4);
5100 format %{ "STF $src,$dst\t! regF to stkI" %}
5101 opcode(Assembler::stf_op3);
5102 ins_encode(simple_form3_mem_reg(dst, src));
5103 ins_pipe(fstoreF_stk_reg);
5104 %}
5106 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5107 // No match rule to avoid chain rule match.
5108 effect(DEF dst, USE src);
5109 ins_cost(MEMORY_REF_COST);
5110 size(4);
5111 format %{ "STDF $src,$dst\t! regD to stkL" %}
5112 opcode(Assembler::stdf_op3);
5113 ins_encode(simple_form3_mem_reg(dst, src));
5114 ins_pipe(fstoreD_stk_reg);
5115 %}
5117 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5118 effect(DEF dst, USE src);
5119 ins_cost(MEMORY_REF_COST*2);
5120 size(8);
5121 format %{ "STW $src,$dst.hi\t! long\n\t"
5122 "STW R_G0,$dst.lo" %}
5123 opcode(Assembler::stw_op3);
5124 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5125 ins_pipe(lstoreI_stk_reg);
5126 %}
5128 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5129 // No match rule to avoid chain rule match.
5130 effect(DEF dst, USE src);
5131 ins_cost(MEMORY_REF_COST);
5132 size(4);
5133 format %{ "STX $src,$dst\t! regL to stkD" %}
5134 opcode(Assembler::stx_op3);
5135 ins_encode(simple_form3_mem_reg( dst, src ) );
5136 ins_pipe(istore_stk_reg);
5137 %}
5139 //---------- Chain stack slots between similar types --------
5141 // Load integer from stack slot
5142 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5143 match(Set dst src);
5144 ins_cost(MEMORY_REF_COST);
5146 size(4);
5147 format %{ "LDUW $src,$dst\t!stk" %}
5148 opcode(Assembler::lduw_op3);
5149 ins_encode(simple_form3_mem_reg( src, dst ) );
5150 ins_pipe(iload_mem);
5151 %}
5153 // Store integer to stack slot
5154 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5155 match(Set dst src);
5156 ins_cost(MEMORY_REF_COST);
5158 size(4);
5159 format %{ "STW $src,$dst\t!stk" %}
5160 opcode(Assembler::stw_op3);
5161 ins_encode(simple_form3_mem_reg( dst, src ) );
5162 ins_pipe(istore_mem_reg);
5163 %}
5165 // Load long from stack slot
5166 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5167 match(Set dst src);
5169 ins_cost(MEMORY_REF_COST);
5170 size(4);
5171 format %{ "LDX $src,$dst\t! long" %}
5172 opcode(Assembler::ldx_op3);
5173 ins_encode(simple_form3_mem_reg( src, dst ) );
5174 ins_pipe(iload_mem);
5175 %}
5177 // Store long to stack slot
5178 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5179 match(Set dst src);
5181 ins_cost(MEMORY_REF_COST);
5182 size(4);
5183 format %{ "STX $src,$dst\t! long" %}
5184 opcode(Assembler::stx_op3);
5185 ins_encode(simple_form3_mem_reg( dst, src ) );
5186 ins_pipe(istore_mem_reg);
5187 %}
5189 #ifdef _LP64
5190 // Load pointer from stack slot, 64-bit encoding
5191 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5192 match(Set dst src);
5193 ins_cost(MEMORY_REF_COST);
5194 size(4);
5195 format %{ "LDX $src,$dst\t!ptr" %}
5196 opcode(Assembler::ldx_op3);
5197 ins_encode(simple_form3_mem_reg( src, dst ) );
5198 ins_pipe(iload_mem);
5199 %}
5201 // Store pointer to stack slot
5202 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5203 match(Set dst src);
5204 ins_cost(MEMORY_REF_COST);
5205 size(4);
5206 format %{ "STX $src,$dst\t!ptr" %}
5207 opcode(Assembler::stx_op3);
5208 ins_encode(simple_form3_mem_reg( dst, src ) );
5209 ins_pipe(istore_mem_reg);
5210 %}
5211 #else // _LP64
5212 // Load pointer from stack slot, 32-bit encoding
5213 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5214 match(Set dst src);
5215 ins_cost(MEMORY_REF_COST);
5216 format %{ "LDUW $src,$dst\t!ptr" %}
5217 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5218 ins_encode(simple_form3_mem_reg( src, dst ) );
5219 ins_pipe(iload_mem);
5220 %}
5222 // Store pointer to stack slot
5223 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5224 match(Set dst src);
5225 ins_cost(MEMORY_REF_COST);
5226 format %{ "STW $src,$dst\t!ptr" %}
5227 opcode(Assembler::stw_op3, Assembler::ldst_op);
5228 ins_encode(simple_form3_mem_reg( dst, src ) );
5229 ins_pipe(istore_mem_reg);
5230 %}
5231 #endif // _LP64
5233 //------------Special Nop instructions for bundling - no match rules-----------
5234 // Nop using the A0 functional unit
5235 instruct Nop_A0() %{
5236 ins_cost(0);
5238 format %{ "NOP ! Alu Pipeline" %}
5239 opcode(Assembler::or_op3, Assembler::arith_op);
5240 ins_encode( form2_nop() );
5241 ins_pipe(ialu_nop_A0);
5242 %}
5244 // Nop using the A1 functional unit
5245 instruct Nop_A1( ) %{
5246 ins_cost(0);
5248 format %{ "NOP ! Alu Pipeline" %}
5249 opcode(Assembler::or_op3, Assembler::arith_op);
5250 ins_encode( form2_nop() );
5251 ins_pipe(ialu_nop_A1);
5252 %}
5254 // Nop using the memory functional unit
5255 instruct Nop_MS( ) %{
5256 ins_cost(0);
5258 format %{ "NOP ! Memory Pipeline" %}
5259 ins_encode( emit_mem_nop );
5260 ins_pipe(mem_nop);
5261 %}
5263 // Nop using the floating add functional unit
5264 instruct Nop_FA( ) %{
5265 ins_cost(0);
5267 format %{ "NOP ! Floating Add Pipeline" %}
5268 ins_encode( emit_fadd_nop );
5269 ins_pipe(fadd_nop);
5270 %}
5272 // Nop using the branch functional unit
5273 instruct Nop_BR( ) %{
5274 ins_cost(0);
5276 format %{ "NOP ! Branch Pipeline" %}
5277 ins_encode( emit_br_nop );
5278 ins_pipe(br_nop);
5279 %}
5281 //----------Load/Store/Move Instructions---------------------------------------
5282 //----------Load Instructions--------------------------------------------------
5283 // Load Byte (8bit signed)
5284 instruct loadB(iRegI dst, memory mem) %{
5285 match(Set dst (LoadB mem));
5286 ins_cost(MEMORY_REF_COST);
5288 size(4);
5289 format %{ "LDSB $mem,$dst\t! byte" %}
5290 opcode(Assembler::ldsb_op3);
5291 ins_encode(simple_form3_mem_reg( mem, dst ) );
5292 ins_pipe(iload_mask_mem);
5293 %}
5295 // Load Byte (8bit signed) into a Long Register
5296 instruct loadB2L(iRegL dst, memory mem) %{
5297 match(Set dst (ConvI2L (LoadB mem)));
5298 ins_cost(MEMORY_REF_COST);
5300 size(4);
5301 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5302 opcode(Assembler::ldsb_op3);
5303 ins_encode(simple_form3_mem_reg( mem, dst ) );
5304 ins_pipe(iload_mask_mem);
5305 %}
5307 // Load Unsigned Byte (8bit UNsigned) into an int reg
5308 instruct loadUB(iRegI dst, memory mem) %{
5309 match(Set dst (LoadUB mem));
5310 ins_cost(MEMORY_REF_COST);
5312 size(4);
5313 format %{ "LDUB $mem,$dst\t! ubyte" %}
5314 opcode(Assembler::ldub_op3);
5315 ins_encode(simple_form3_mem_reg( mem, dst ) );
5316 ins_pipe(iload_mask_mem);
5317 %}
5319 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5320 instruct loadUB2L(iRegL dst, memory mem) %{
5321 match(Set dst (ConvI2L (LoadUB mem)));
5322 ins_cost(MEMORY_REF_COST);
5324 size(4);
5325 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5326 opcode(Assembler::ldub_op3);
5327 ins_encode(simple_form3_mem_reg( mem, dst ) );
5328 ins_pipe(iload_mask_mem);
5329 %}
5331 // Load Short (16bit signed)
5332 instruct loadS(iRegI dst, memory mem) %{
5333 match(Set dst (LoadS mem));
5334 ins_cost(MEMORY_REF_COST);
5336 size(4);
5337 format %{ "LDSH $mem,$dst\t! short" %}
5338 opcode(Assembler::ldsh_op3);
5339 ins_encode(simple_form3_mem_reg( mem, dst ) );
5340 ins_pipe(iload_mask_mem);
5341 %}
5343 // Load Short (16bit signed) into a Long Register
5344 instruct loadS2L(iRegL dst, memory mem) %{
5345 match(Set dst (ConvI2L (LoadS mem)));
5346 ins_cost(MEMORY_REF_COST);
5348 size(4);
5349 format %{ "LDSH $mem,$dst\t! short -> long" %}
5350 opcode(Assembler::ldsh_op3);
5351 ins_encode(simple_form3_mem_reg( mem, dst ) );
5352 ins_pipe(iload_mask_mem);
5353 %}
5355 // Load Unsigned Short/Char (16bit UNsigned)
5356 instruct loadUS(iRegI dst, memory mem) %{
5357 match(Set dst (LoadUS mem));
5358 ins_cost(MEMORY_REF_COST);
5360 size(4);
5361 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5362 opcode(Assembler::lduh_op3);
5363 ins_encode(simple_form3_mem_reg( mem, dst ) );
5364 ins_pipe(iload_mask_mem);
5365 %}
5367 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5368 instruct loadUS2L(iRegL dst, memory mem) %{
5369 match(Set dst (ConvI2L (LoadUS mem)));
5370 ins_cost(MEMORY_REF_COST);
5372 size(4);
5373 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5374 opcode(Assembler::lduh_op3);
5375 ins_encode(simple_form3_mem_reg( mem, dst ) );
5376 ins_pipe(iload_mask_mem);
5377 %}
5379 // Load Integer
5380 instruct loadI(iRegI dst, memory mem) %{
5381 match(Set dst (LoadI mem));
5382 ins_cost(MEMORY_REF_COST);
5384 size(4);
5385 format %{ "LDUW $mem,$dst\t! int" %}
5386 opcode(Assembler::lduw_op3);
5387 ins_encode(simple_form3_mem_reg( mem, dst ) );
5388 ins_pipe(iload_mem);
5389 %}
5391 // Load Integer into a Long Register
5392 instruct loadI2L(iRegL dst, memory mem) %{
5393 match(Set dst (ConvI2L (LoadI mem)));
5394 ins_cost(MEMORY_REF_COST);
5396 size(4);
5397 format %{ "LDSW $mem,$dst\t! int -> long" %}
5398 opcode(Assembler::ldsw_op3);
5399 ins_encode(simple_form3_mem_reg( mem, dst ) );
5400 ins_pipe(iload_mem);
5401 %}
5403 // Load Unsigned Integer into a Long Register
5404 instruct loadUI2L(iRegL dst, memory mem) %{
5405 match(Set dst (LoadUI2L mem));
5406 ins_cost(MEMORY_REF_COST);
5408 size(4);
5409 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5410 opcode(Assembler::lduw_op3);
5411 ins_encode(simple_form3_mem_reg( mem, dst ) );
5412 ins_pipe(iload_mem);
5413 %}
5415 // Load Long - aligned
5416 instruct loadL(iRegL dst, memory mem ) %{
5417 match(Set dst (LoadL mem));
5418 ins_cost(MEMORY_REF_COST);
5420 size(4);
5421 format %{ "LDX $mem,$dst\t! long" %}
5422 opcode(Assembler::ldx_op3);
5423 ins_encode(simple_form3_mem_reg( mem, dst ) );
5424 ins_pipe(iload_mem);
5425 %}
5427 // Load Long - UNaligned
5428 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5429 match(Set dst (LoadL_unaligned mem));
5430 effect(KILL tmp);
5431 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5432 size(16);
5433 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5434 "\tLDUW $mem ,$dst\n"
5435 "\tSLLX #32, $dst, $dst\n"
5436 "\tOR $dst, R_O7, $dst" %}
5437 opcode(Assembler::lduw_op3);
5438 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5439 ins_pipe(iload_mem);
5440 %}
5442 // Load Aligned Packed Byte into a Double Register
5443 instruct loadA8B(regD dst, memory mem) %{
5444 match(Set dst (Load8B mem));
5445 ins_cost(MEMORY_REF_COST);
5446 size(4);
5447 format %{ "LDDF $mem,$dst\t! packed8B" %}
5448 opcode(Assembler::lddf_op3);
5449 ins_encode(simple_form3_mem_reg( mem, dst ) );
5450 ins_pipe(floadD_mem);
5451 %}
5453 // Load Aligned Packed Char into a Double Register
5454 instruct loadA4C(regD dst, memory mem) %{
5455 match(Set dst (Load4C mem));
5456 ins_cost(MEMORY_REF_COST);
5457 size(4);
5458 format %{ "LDDF $mem,$dst\t! packed4C" %}
5459 opcode(Assembler::lddf_op3);
5460 ins_encode(simple_form3_mem_reg( mem, dst ) );
5461 ins_pipe(floadD_mem);
5462 %}
5464 // Load Aligned Packed Short into a Double Register
5465 instruct loadA4S(regD dst, memory mem) %{
5466 match(Set dst (Load4S mem));
5467 ins_cost(MEMORY_REF_COST);
5468 size(4);
5469 format %{ "LDDF $mem,$dst\t! packed4S" %}
5470 opcode(Assembler::lddf_op3);
5471 ins_encode(simple_form3_mem_reg( mem, dst ) );
5472 ins_pipe(floadD_mem);
5473 %}
5475 // Load Aligned Packed Int into a Double Register
5476 instruct loadA2I(regD dst, memory mem) %{
5477 match(Set dst (Load2I mem));
5478 ins_cost(MEMORY_REF_COST);
5479 size(4);
5480 format %{ "LDDF $mem,$dst\t! packed2I" %}
5481 opcode(Assembler::lddf_op3);
5482 ins_encode(simple_form3_mem_reg( mem, dst ) );
5483 ins_pipe(floadD_mem);
5484 %}
5486 // Load Range
5487 instruct loadRange(iRegI dst, memory mem) %{
5488 match(Set dst (LoadRange mem));
5489 ins_cost(MEMORY_REF_COST);
5491 size(4);
5492 format %{ "LDUW $mem,$dst\t! range" %}
5493 opcode(Assembler::lduw_op3);
5494 ins_encode(simple_form3_mem_reg( mem, dst ) );
5495 ins_pipe(iload_mem);
5496 %}
5498 // Load Integer into %f register (for fitos/fitod)
5499 instruct loadI_freg(regF dst, memory mem) %{
5500 match(Set dst (LoadI mem));
5501 ins_cost(MEMORY_REF_COST);
5502 size(4);
5504 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5505 opcode(Assembler::ldf_op3);
5506 ins_encode(simple_form3_mem_reg( mem, dst ) );
5507 ins_pipe(floadF_mem);
5508 %}
5510 // Load Pointer
5511 instruct loadP(iRegP dst, memory mem) %{
5512 match(Set dst (LoadP mem));
5513 ins_cost(MEMORY_REF_COST);
5514 size(4);
5516 #ifndef _LP64
5517 format %{ "LDUW $mem,$dst\t! ptr" %}
5518 opcode(Assembler::lduw_op3, 0, REGP_OP);
5519 #else
5520 format %{ "LDX $mem,$dst\t! ptr" %}
5521 opcode(Assembler::ldx_op3, 0, REGP_OP);
5522 #endif
5523 ins_encode( form3_mem_reg( mem, dst ) );
5524 ins_pipe(iload_mem);
5525 %}
5527 // Load Compressed Pointer
5528 instruct loadN(iRegN dst, memory mem) %{
5529 match(Set dst (LoadN mem));
5530 ins_cost(MEMORY_REF_COST);
5531 size(4);
5533 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5534 ins_encode %{
5535 Register index = $mem$$index$$Register;
5536 if (index != G0) {
5537 __ lduw($mem$$base$$Register, index, $dst$$Register);
5538 } else {
5539 __ lduw($mem$$base$$Register, $mem$$disp, $dst$$Register);
5540 }
5541 %}
5542 ins_pipe(iload_mem);
5543 %}
5545 // Load Klass Pointer
5546 instruct loadKlass(iRegP dst, memory mem) %{
5547 match(Set dst (LoadKlass mem));
5548 ins_cost(MEMORY_REF_COST);
5549 size(4);
5551 #ifndef _LP64
5552 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5553 opcode(Assembler::lduw_op3, 0, REGP_OP);
5554 #else
5555 format %{ "LDX $mem,$dst\t! klass ptr" %}
5556 opcode(Assembler::ldx_op3, 0, REGP_OP);
5557 #endif
5558 ins_encode( form3_mem_reg( mem, dst ) );
5559 ins_pipe(iload_mem);
5560 %}
5562 // Load narrow Klass Pointer
5563 instruct loadNKlass(iRegN dst, memory mem) %{
5564 match(Set dst (LoadNKlass mem));
5565 ins_cost(MEMORY_REF_COST);
5566 size(4);
5568 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5570 ins_encode %{
5571 Register base = as_Register($mem$$base);
5572 Register index = as_Register($mem$$index);
5573 Register dst = $dst$$Register;
5574 if (index != G0) {
5575 __ lduw(base, index, dst);
5576 } else {
5577 __ lduw(base, $mem$$disp, dst);
5578 }
5579 %}
5580 ins_pipe(iload_mem);
5581 %}
5583 // Load Double
5584 instruct loadD(regD dst, memory mem) %{
5585 match(Set dst (LoadD mem));
5586 ins_cost(MEMORY_REF_COST);
5588 size(4);
5589 format %{ "LDDF $mem,$dst" %}
5590 opcode(Assembler::lddf_op3);
5591 ins_encode(simple_form3_mem_reg( mem, dst ) );
5592 ins_pipe(floadD_mem);
5593 %}
5595 // Load Double - UNaligned
5596 instruct loadD_unaligned(regD_low dst, memory mem ) %{
5597 match(Set dst (LoadD_unaligned mem));
5598 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5599 size(8);
5600 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
5601 "\tLDF $mem+4,$dst.lo\t!" %}
5602 opcode(Assembler::ldf_op3);
5603 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
5604 ins_pipe(iload_mem);
5605 %}
5607 // Load Float
5608 instruct loadF(regF dst, memory mem) %{
5609 match(Set dst (LoadF mem));
5610 ins_cost(MEMORY_REF_COST);
5612 size(4);
5613 format %{ "LDF $mem,$dst" %}
5614 opcode(Assembler::ldf_op3);
5615 ins_encode(simple_form3_mem_reg( mem, dst ) );
5616 ins_pipe(floadF_mem);
5617 %}
5619 // Load Constant
5620 instruct loadConI( iRegI dst, immI src ) %{
5621 match(Set dst src);
5622 ins_cost(DEFAULT_COST * 3/2);
5623 format %{ "SET $src,$dst" %}
5624 ins_encode( Set32(src, dst) );
5625 ins_pipe(ialu_hi_lo_reg);
5626 %}
5628 instruct loadConI13( iRegI dst, immI13 src ) %{
5629 match(Set dst src);
5631 size(4);
5632 format %{ "MOV $src,$dst" %}
5633 ins_encode( Set13( src, dst ) );
5634 ins_pipe(ialu_imm);
5635 %}
5637 instruct loadConP(iRegP dst, immP src) %{
5638 match(Set dst src);
5639 ins_cost(DEFAULT_COST * 3/2);
5640 format %{ "SET $src,$dst\t!ptr" %}
5641 // This rule does not use "expand" unlike loadConI because then
5642 // the result type is not known to be an Oop. An ADLC
5643 // enhancement will be needed to make that work - not worth it!
5645 ins_encode( SetPtr( src, dst ) );
5646 ins_pipe(loadConP);
5648 %}
5650 instruct loadConP0(iRegP dst, immP0 src) %{
5651 match(Set dst src);
5653 size(4);
5654 format %{ "CLR $dst\t!ptr" %}
5655 ins_encode( SetNull( dst ) );
5656 ins_pipe(ialu_imm);
5657 %}
5659 instruct loadConP_poll(iRegP dst, immP_poll src) %{
5660 match(Set dst src);
5661 ins_cost(DEFAULT_COST);
5662 format %{ "SET $src,$dst\t!ptr" %}
5663 ins_encode %{
5664 Address polling_page(reg_to_register_object($dst$$reg), (address)os::get_polling_page());
5665 __ sethi(polling_page, false );
5666 %}
5667 ins_pipe(loadConP_poll);
5668 %}
5670 instruct loadConN0(iRegN dst, immN0 src) %{
5671 match(Set dst src);
5673 size(4);
5674 format %{ "CLR $dst\t! compressed NULL ptr" %}
5675 ins_encode( SetNull( dst ) );
5676 ins_pipe(ialu_imm);
5677 %}
5679 instruct loadConN(iRegN dst, immN src) %{
5680 match(Set dst src);
5681 ins_cost(DEFAULT_COST * 3/2);
5682 format %{ "SET $src,$dst\t! compressed ptr" %}
5683 ins_encode %{
5684 Register dst = $dst$$Register;
5685 __ set_narrow_oop((jobject)$src$$constant, dst);
5686 %}
5687 ins_pipe(ialu_hi_lo_reg);
5688 %}
5690 instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{
5691 // %%% maybe this should work like loadConD
5692 match(Set dst src);
5693 effect(KILL tmp);
5694 ins_cost(DEFAULT_COST * 4);
5695 format %{ "SET64 $src,$dst KILL $tmp\t! long" %}
5696 ins_encode( LdImmL(src, dst, tmp) );
5697 ins_pipe(loadConL);
5698 %}
5700 instruct loadConL0( iRegL dst, immL0 src ) %{
5701 match(Set dst src);
5702 ins_cost(DEFAULT_COST);
5703 size(4);
5704 format %{ "CLR $dst\t! long" %}
5705 ins_encode( Set13( src, dst ) );
5706 ins_pipe(ialu_imm);
5707 %}
5709 instruct loadConL13( iRegL dst, immL13 src ) %{
5710 match(Set dst src);
5711 ins_cost(DEFAULT_COST * 2);
5713 size(4);
5714 format %{ "MOV $src,$dst\t! long" %}
5715 ins_encode( Set13( src, dst ) );
5716 ins_pipe(ialu_imm);
5717 %}
5719 instruct loadConF(regF dst, immF src, o7RegP tmp) %{
5720 match(Set dst src);
5721 effect(KILL tmp);
5723 #ifdef _LP64
5724 size(36);
5725 #else
5726 size(8);
5727 #endif
5729 format %{ "SETHI hi(&$src),$tmp\t!get float $src from table\n\t"
5730 "LDF [$tmp+lo(&$src)],$dst" %}
5731 ins_encode( LdImmF(src, dst, tmp) );
5732 ins_pipe(loadConFD);
5733 %}
5735 instruct loadConD(regD dst, immD src, o7RegP tmp) %{
5736 match(Set dst src);
5737 effect(KILL tmp);
5739 #ifdef _LP64
5740 size(36);
5741 #else
5742 size(8);
5743 #endif
5745 format %{ "SETHI hi(&$src),$tmp\t!get double $src from table\n\t"
5746 "LDDF [$tmp+lo(&$src)],$dst" %}
5747 ins_encode( LdImmD(src, dst, tmp) );
5748 ins_pipe(loadConFD);
5749 %}
5751 // Prefetch instructions.
5752 // Must be safe to execute with invalid address (cannot fault).
5754 instruct prefetchr( memory mem ) %{
5755 match( PrefetchRead mem );
5756 ins_cost(MEMORY_REF_COST);
5758 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
5759 opcode(Assembler::prefetch_op3);
5760 ins_encode( form3_mem_prefetch_read( mem ) );
5761 ins_pipe(iload_mem);
5762 %}
5764 instruct prefetchw( memory mem ) %{
5765 match( PrefetchWrite mem );
5766 ins_cost(MEMORY_REF_COST);
5768 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
5769 opcode(Assembler::prefetch_op3);
5770 ins_encode( form3_mem_prefetch_write( mem ) );
5771 ins_pipe(iload_mem);
5772 %}
5775 //----------Store Instructions-------------------------------------------------
5776 // Store Byte
5777 instruct storeB(memory mem, iRegI src) %{
5778 match(Set mem (StoreB mem src));
5779 ins_cost(MEMORY_REF_COST);
5781 size(4);
5782 format %{ "STB $src,$mem\t! byte" %}
5783 opcode(Assembler::stb_op3);
5784 ins_encode(simple_form3_mem_reg( mem, src ) );
5785 ins_pipe(istore_mem_reg);
5786 %}
5788 instruct storeB0(memory mem, immI0 src) %{
5789 match(Set mem (StoreB mem src));
5790 ins_cost(MEMORY_REF_COST);
5792 size(4);
5793 format %{ "STB $src,$mem\t! byte" %}
5794 opcode(Assembler::stb_op3);
5795 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5796 ins_pipe(istore_mem_zero);
5797 %}
5799 instruct storeCM0(memory mem, immI0 src) %{
5800 match(Set mem (StoreCM mem src));
5801 ins_cost(MEMORY_REF_COST);
5803 size(4);
5804 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
5805 opcode(Assembler::stb_op3);
5806 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5807 ins_pipe(istore_mem_zero);
5808 %}
5810 // Store Char/Short
5811 instruct storeC(memory mem, iRegI src) %{
5812 match(Set mem (StoreC mem src));
5813 ins_cost(MEMORY_REF_COST);
5815 size(4);
5816 format %{ "STH $src,$mem\t! short" %}
5817 opcode(Assembler::sth_op3);
5818 ins_encode(simple_form3_mem_reg( mem, src ) );
5819 ins_pipe(istore_mem_reg);
5820 %}
5822 instruct storeC0(memory mem, immI0 src) %{
5823 match(Set mem (StoreC mem src));
5824 ins_cost(MEMORY_REF_COST);
5826 size(4);
5827 format %{ "STH $src,$mem\t! short" %}
5828 opcode(Assembler::sth_op3);
5829 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5830 ins_pipe(istore_mem_zero);
5831 %}
5833 // Store Integer
5834 instruct storeI(memory mem, iRegI src) %{
5835 match(Set mem (StoreI mem src));
5836 ins_cost(MEMORY_REF_COST);
5838 size(4);
5839 format %{ "STW $src,$mem" %}
5840 opcode(Assembler::stw_op3);
5841 ins_encode(simple_form3_mem_reg( mem, src ) );
5842 ins_pipe(istore_mem_reg);
5843 %}
5845 // Store Long
5846 instruct storeL(memory mem, iRegL src) %{
5847 match(Set mem (StoreL mem src));
5848 ins_cost(MEMORY_REF_COST);
5849 size(4);
5850 format %{ "STX $src,$mem\t! long" %}
5851 opcode(Assembler::stx_op3);
5852 ins_encode(simple_form3_mem_reg( mem, src ) );
5853 ins_pipe(istore_mem_reg);
5854 %}
5856 instruct storeI0(memory mem, immI0 src) %{
5857 match(Set mem (StoreI mem src));
5858 ins_cost(MEMORY_REF_COST);
5860 size(4);
5861 format %{ "STW $src,$mem" %}
5862 opcode(Assembler::stw_op3);
5863 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5864 ins_pipe(istore_mem_zero);
5865 %}
5867 instruct storeL0(memory mem, immL0 src) %{
5868 match(Set mem (StoreL mem src));
5869 ins_cost(MEMORY_REF_COST);
5871 size(4);
5872 format %{ "STX $src,$mem" %}
5873 opcode(Assembler::stx_op3);
5874 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5875 ins_pipe(istore_mem_zero);
5876 %}
5878 // Store Integer from float register (used after fstoi)
5879 instruct storeI_Freg(memory mem, regF src) %{
5880 match(Set mem (StoreI mem src));
5881 ins_cost(MEMORY_REF_COST);
5883 size(4);
5884 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
5885 opcode(Assembler::stf_op3);
5886 ins_encode(simple_form3_mem_reg( mem, src ) );
5887 ins_pipe(fstoreF_mem_reg);
5888 %}
5890 // Store Pointer
5891 instruct storeP(memory dst, sp_ptr_RegP src) %{
5892 match(Set dst (StoreP dst src));
5893 ins_cost(MEMORY_REF_COST);
5894 size(4);
5896 #ifndef _LP64
5897 format %{ "STW $src,$dst\t! ptr" %}
5898 opcode(Assembler::stw_op3, 0, REGP_OP);
5899 #else
5900 format %{ "STX $src,$dst\t! ptr" %}
5901 opcode(Assembler::stx_op3, 0, REGP_OP);
5902 #endif
5903 ins_encode( form3_mem_reg( dst, src ) );
5904 ins_pipe(istore_mem_spORreg);
5905 %}
5907 instruct storeP0(memory dst, immP0 src) %{
5908 match(Set dst (StoreP dst src));
5909 ins_cost(MEMORY_REF_COST);
5910 size(4);
5912 #ifndef _LP64
5913 format %{ "STW $src,$dst\t! ptr" %}
5914 opcode(Assembler::stw_op3, 0, REGP_OP);
5915 #else
5916 format %{ "STX $src,$dst\t! ptr" %}
5917 opcode(Assembler::stx_op3, 0, REGP_OP);
5918 #endif
5919 ins_encode( form3_mem_reg( dst, R_G0 ) );
5920 ins_pipe(istore_mem_zero);
5921 %}
5923 // Store Compressed Pointer
5924 instruct storeN(memory dst, iRegN src) %{
5925 match(Set dst (StoreN dst src));
5926 ins_cost(MEMORY_REF_COST);
5927 size(4);
5929 format %{ "STW $src,$dst\t! compressed ptr" %}
5930 ins_encode %{
5931 Register base = as_Register($dst$$base);
5932 Register index = as_Register($dst$$index);
5933 Register src = $src$$Register;
5934 if (index != G0) {
5935 __ stw(src, base, index);
5936 } else {
5937 __ stw(src, base, $dst$$disp);
5938 }
5939 %}
5940 ins_pipe(istore_mem_spORreg);
5941 %}
5943 instruct storeN0(memory dst, immN0 src) %{
5944 match(Set dst (StoreN dst src));
5945 ins_cost(MEMORY_REF_COST);
5946 size(4);
5948 format %{ "STW $src,$dst\t! compressed ptr" %}
5949 ins_encode %{
5950 Register base = as_Register($dst$$base);
5951 Register index = as_Register($dst$$index);
5952 if (index != G0) {
5953 __ stw(0, base, index);
5954 } else {
5955 __ stw(0, base, $dst$$disp);
5956 }
5957 %}
5958 ins_pipe(istore_mem_zero);
5959 %}
5961 // Store Double
5962 instruct storeD( memory mem, regD src) %{
5963 match(Set mem (StoreD mem src));
5964 ins_cost(MEMORY_REF_COST);
5966 size(4);
5967 format %{ "STDF $src,$mem" %}
5968 opcode(Assembler::stdf_op3);
5969 ins_encode(simple_form3_mem_reg( mem, src ) );
5970 ins_pipe(fstoreD_mem_reg);
5971 %}
5973 instruct storeD0( memory mem, immD0 src) %{
5974 match(Set mem (StoreD mem src));
5975 ins_cost(MEMORY_REF_COST);
5977 size(4);
5978 format %{ "STX $src,$mem" %}
5979 opcode(Assembler::stx_op3);
5980 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5981 ins_pipe(fstoreD_mem_zero);
5982 %}
5984 // Store Float
5985 instruct storeF( memory mem, regF src) %{
5986 match(Set mem (StoreF mem src));
5987 ins_cost(MEMORY_REF_COST);
5989 size(4);
5990 format %{ "STF $src,$mem" %}
5991 opcode(Assembler::stf_op3);
5992 ins_encode(simple_form3_mem_reg( mem, src ) );
5993 ins_pipe(fstoreF_mem_reg);
5994 %}
5996 instruct storeF0( memory mem, immF0 src) %{
5997 match(Set mem (StoreF mem src));
5998 ins_cost(MEMORY_REF_COST);
6000 size(4);
6001 format %{ "STW $src,$mem\t! storeF0" %}
6002 opcode(Assembler::stw_op3);
6003 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6004 ins_pipe(fstoreF_mem_zero);
6005 %}
6007 // Store Aligned Packed Bytes in Double register to memory
6008 instruct storeA8B(memory mem, regD src) %{
6009 match(Set mem (Store8B mem src));
6010 ins_cost(MEMORY_REF_COST);
6011 size(4);
6012 format %{ "STDF $src,$mem\t! packed8B" %}
6013 opcode(Assembler::stdf_op3);
6014 ins_encode(simple_form3_mem_reg( mem, src ) );
6015 ins_pipe(fstoreD_mem_reg);
6016 %}
6018 // Convert oop pointer into compressed form
6019 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6020 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6021 match(Set dst (EncodeP src));
6022 format %{ "encode_heap_oop $src, $dst" %}
6023 ins_encode %{
6024 __ encode_heap_oop($src$$Register, $dst$$Register);
6025 %}
6026 ins_pipe(ialu_reg);
6027 %}
6029 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6030 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6031 match(Set dst (EncodeP src));
6032 format %{ "encode_heap_oop_not_null $src, $dst" %}
6033 ins_encode %{
6034 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6035 %}
6036 ins_pipe(ialu_reg);
6037 %}
6039 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6040 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6041 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6042 match(Set dst (DecodeN src));
6043 format %{ "decode_heap_oop $src, $dst" %}
6044 ins_encode %{
6045 __ decode_heap_oop($src$$Register, $dst$$Register);
6046 %}
6047 ins_pipe(ialu_reg);
6048 %}
6050 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6051 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6052 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6053 match(Set dst (DecodeN src));
6054 format %{ "decode_heap_oop_not_null $src, $dst" %}
6055 ins_encode %{
6056 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6057 %}
6058 ins_pipe(ialu_reg);
6059 %}
6062 // Store Zero into Aligned Packed Bytes
6063 instruct storeA8B0(memory mem, immI0 zero) %{
6064 match(Set mem (Store8B mem zero));
6065 ins_cost(MEMORY_REF_COST);
6066 size(4);
6067 format %{ "STX $zero,$mem\t! packed8B" %}
6068 opcode(Assembler::stx_op3);
6069 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6070 ins_pipe(fstoreD_mem_zero);
6071 %}
6073 // Store Aligned Packed Chars/Shorts in Double register to memory
6074 instruct storeA4C(memory mem, regD src) %{
6075 match(Set mem (Store4C mem src));
6076 ins_cost(MEMORY_REF_COST);
6077 size(4);
6078 format %{ "STDF $src,$mem\t! packed4C" %}
6079 opcode(Assembler::stdf_op3);
6080 ins_encode(simple_form3_mem_reg( mem, src ) );
6081 ins_pipe(fstoreD_mem_reg);
6082 %}
6084 // Store Zero into Aligned Packed Chars/Shorts
6085 instruct storeA4C0(memory mem, immI0 zero) %{
6086 match(Set mem (Store4C mem (Replicate4C zero)));
6087 ins_cost(MEMORY_REF_COST);
6088 size(4);
6089 format %{ "STX $zero,$mem\t! packed4C" %}
6090 opcode(Assembler::stx_op3);
6091 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6092 ins_pipe(fstoreD_mem_zero);
6093 %}
6095 // Store Aligned Packed Ints in Double register to memory
6096 instruct storeA2I(memory mem, regD src) %{
6097 match(Set mem (Store2I mem src));
6098 ins_cost(MEMORY_REF_COST);
6099 size(4);
6100 format %{ "STDF $src,$mem\t! packed2I" %}
6101 opcode(Assembler::stdf_op3);
6102 ins_encode(simple_form3_mem_reg( mem, src ) );
6103 ins_pipe(fstoreD_mem_reg);
6104 %}
6106 // Store Zero into Aligned Packed Ints
6107 instruct storeA2I0(memory mem, immI0 zero) %{
6108 match(Set mem (Store2I mem zero));
6109 ins_cost(MEMORY_REF_COST);
6110 size(4);
6111 format %{ "STX $zero,$mem\t! packed2I" %}
6112 opcode(Assembler::stx_op3);
6113 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6114 ins_pipe(fstoreD_mem_zero);
6115 %}
6118 //----------MemBar Instructions-----------------------------------------------
6119 // Memory barrier flavors
6121 instruct membar_acquire() %{
6122 match(MemBarAcquire);
6123 ins_cost(4*MEMORY_REF_COST);
6125 size(0);
6126 format %{ "MEMBAR-acquire" %}
6127 ins_encode( enc_membar_acquire );
6128 ins_pipe(long_memory_op);
6129 %}
6131 instruct membar_acquire_lock() %{
6132 match(MemBarAcquire);
6133 predicate(Matcher::prior_fast_lock(n));
6134 ins_cost(0);
6136 size(0);
6137 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6138 ins_encode( );
6139 ins_pipe(empty);
6140 %}
6142 instruct membar_release() %{
6143 match(MemBarRelease);
6144 ins_cost(4*MEMORY_REF_COST);
6146 size(0);
6147 format %{ "MEMBAR-release" %}
6148 ins_encode( enc_membar_release );
6149 ins_pipe(long_memory_op);
6150 %}
6152 instruct membar_release_lock() %{
6153 match(MemBarRelease);
6154 predicate(Matcher::post_fast_unlock(n));
6155 ins_cost(0);
6157 size(0);
6158 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6159 ins_encode( );
6160 ins_pipe(empty);
6161 %}
6163 instruct membar_volatile() %{
6164 match(MemBarVolatile);
6165 ins_cost(4*MEMORY_REF_COST);
6167 size(4);
6168 format %{ "MEMBAR-volatile" %}
6169 ins_encode( enc_membar_volatile );
6170 ins_pipe(long_memory_op);
6171 %}
6173 instruct unnecessary_membar_volatile() %{
6174 match(MemBarVolatile);
6175 predicate(Matcher::post_store_load_barrier(n));
6176 ins_cost(0);
6178 size(0);
6179 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6180 ins_encode( );
6181 ins_pipe(empty);
6182 %}
6184 //----------Register Move Instructions-----------------------------------------
6185 instruct roundDouble_nop(regD dst) %{
6186 match(Set dst (RoundDouble dst));
6187 ins_cost(0);
6188 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6189 ins_encode( );
6190 ins_pipe(empty);
6191 %}
6194 instruct roundFloat_nop(regF dst) %{
6195 match(Set dst (RoundFloat dst));
6196 ins_cost(0);
6197 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6198 ins_encode( );
6199 ins_pipe(empty);
6200 %}
6203 // Cast Index to Pointer for unsafe natives
6204 instruct castX2P(iRegX src, iRegP dst) %{
6205 match(Set dst (CastX2P src));
6207 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6208 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6209 ins_pipe(ialu_reg);
6210 %}
6212 // Cast Pointer to Index for unsafe natives
6213 instruct castP2X(iRegP src, iRegX dst) %{
6214 match(Set dst (CastP2X src));
6216 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6217 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6218 ins_pipe(ialu_reg);
6219 %}
6221 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6222 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6223 match(Set stkSlot src); // chain rule
6224 ins_cost(MEMORY_REF_COST);
6225 format %{ "STDF $src,$stkSlot\t!stk" %}
6226 opcode(Assembler::stdf_op3);
6227 ins_encode(simple_form3_mem_reg(stkSlot, src));
6228 ins_pipe(fstoreD_stk_reg);
6229 %}
6231 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6232 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6233 match(Set dst stkSlot); // chain rule
6234 ins_cost(MEMORY_REF_COST);
6235 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6236 opcode(Assembler::lddf_op3);
6237 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6238 ins_pipe(floadD_stk);
6239 %}
6241 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6242 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6243 match(Set stkSlot src); // chain rule
6244 ins_cost(MEMORY_REF_COST);
6245 format %{ "STF $src,$stkSlot\t!stk" %}
6246 opcode(Assembler::stf_op3);
6247 ins_encode(simple_form3_mem_reg(stkSlot, src));
6248 ins_pipe(fstoreF_stk_reg);
6249 %}
6251 //----------Conditional Move---------------------------------------------------
6252 // Conditional move
6253 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6254 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6255 ins_cost(150);
6256 format %{ "MOV$cmp $pcc,$src,$dst" %}
6257 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6258 ins_pipe(ialu_reg);
6259 %}
6261 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6262 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6263 ins_cost(140);
6264 format %{ "MOV$cmp $pcc,$src,$dst" %}
6265 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6266 ins_pipe(ialu_imm);
6267 %}
6269 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6270 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6271 ins_cost(150);
6272 size(4);
6273 format %{ "MOV$cmp $icc,$src,$dst" %}
6274 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6275 ins_pipe(ialu_reg);
6276 %}
6278 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6279 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6280 ins_cost(140);
6281 size(4);
6282 format %{ "MOV$cmp $icc,$src,$dst" %}
6283 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6284 ins_pipe(ialu_imm);
6285 %}
6287 instruct cmovII_U_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6288 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6289 ins_cost(150);
6290 size(4);
6291 format %{ "MOV$cmp $icc,$src,$dst" %}
6292 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6293 ins_pipe(ialu_reg);
6294 %}
6296 instruct cmovII_U_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6297 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6298 ins_cost(140);
6299 size(4);
6300 format %{ "MOV$cmp $icc,$src,$dst" %}
6301 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6302 ins_pipe(ialu_imm);
6303 %}
6305 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6306 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6307 ins_cost(150);
6308 size(4);
6309 format %{ "MOV$cmp $fcc,$src,$dst" %}
6310 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6311 ins_pipe(ialu_reg);
6312 %}
6314 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6315 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6316 ins_cost(140);
6317 size(4);
6318 format %{ "MOV$cmp $fcc,$src,$dst" %}
6319 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6320 ins_pipe(ialu_imm);
6321 %}
6323 // Conditional move for RegN. Only cmov(reg,reg).
6324 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6325 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6326 ins_cost(150);
6327 format %{ "MOV$cmp $pcc,$src,$dst" %}
6328 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6329 ins_pipe(ialu_reg);
6330 %}
6332 // This instruction also works with CmpN so we don't need cmovNN_reg.
6333 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6334 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6335 ins_cost(150);
6336 size(4);
6337 format %{ "MOV$cmp $icc,$src,$dst" %}
6338 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6339 ins_pipe(ialu_reg);
6340 %}
6342 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6343 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6344 ins_cost(150);
6345 size(4);
6346 format %{ "MOV$cmp $fcc,$src,$dst" %}
6347 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6348 ins_pipe(ialu_reg);
6349 %}
6351 // Conditional move
6352 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6353 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6354 ins_cost(150);
6355 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6356 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6357 ins_pipe(ialu_reg);
6358 %}
6360 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6361 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6362 ins_cost(140);
6363 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6364 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6365 ins_pipe(ialu_imm);
6366 %}
6368 // This instruction also works with CmpN so we don't need cmovPN_reg.
6369 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6370 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6371 ins_cost(150);
6373 size(4);
6374 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6375 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6376 ins_pipe(ialu_reg);
6377 %}
6379 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6380 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6381 ins_cost(140);
6383 size(4);
6384 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6385 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6386 ins_pipe(ialu_imm);
6387 %}
6389 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6390 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6391 ins_cost(150);
6392 size(4);
6393 format %{ "MOV$cmp $fcc,$src,$dst" %}
6394 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6395 ins_pipe(ialu_imm);
6396 %}
6398 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6399 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6400 ins_cost(140);
6401 size(4);
6402 format %{ "MOV$cmp $fcc,$src,$dst" %}
6403 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6404 ins_pipe(ialu_imm);
6405 %}
6407 // Conditional move
6408 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6409 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6410 ins_cost(150);
6411 opcode(0x101);
6412 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6413 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6414 ins_pipe(int_conditional_float_move);
6415 %}
6417 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6418 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6419 ins_cost(150);
6421 size(4);
6422 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6423 opcode(0x101);
6424 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6425 ins_pipe(int_conditional_float_move);
6426 %}
6428 // Conditional move,
6429 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6430 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6431 ins_cost(150);
6432 size(4);
6433 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6434 opcode(0x1);
6435 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6436 ins_pipe(int_conditional_double_move);
6437 %}
6439 // Conditional move
6440 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6441 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6442 ins_cost(150);
6443 size(4);
6444 opcode(0x102);
6445 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6446 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6447 ins_pipe(int_conditional_double_move);
6448 %}
6450 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6451 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6452 ins_cost(150);
6454 size(4);
6455 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6456 opcode(0x102);
6457 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6458 ins_pipe(int_conditional_double_move);
6459 %}
6461 // Conditional move,
6462 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6463 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6464 ins_cost(150);
6465 size(4);
6466 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6467 opcode(0x2);
6468 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6469 ins_pipe(int_conditional_double_move);
6470 %}
6472 // Conditional move
6473 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
6474 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6475 ins_cost(150);
6476 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6477 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6478 ins_pipe(ialu_reg);
6479 %}
6481 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
6482 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6483 ins_cost(140);
6484 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6485 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6486 ins_pipe(ialu_imm);
6487 %}
6489 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
6490 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6491 ins_cost(150);
6493 size(4);
6494 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6495 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6496 ins_pipe(ialu_reg);
6497 %}
6500 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
6501 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
6502 ins_cost(150);
6504 size(4);
6505 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
6506 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6507 ins_pipe(ialu_reg);
6508 %}
6512 //----------OS and Locking Instructions----------------------------------------
6514 // This name is KNOWN by the ADLC and cannot be changed.
6515 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
6516 // for this guy.
6517 instruct tlsLoadP(g2RegP dst) %{
6518 match(Set dst (ThreadLocal));
6520 size(0);
6521 ins_cost(0);
6522 format %{ "# TLS is in G2" %}
6523 ins_encode( /*empty encoding*/ );
6524 ins_pipe(ialu_none);
6525 %}
6527 instruct checkCastPP( iRegP dst ) %{
6528 match(Set dst (CheckCastPP dst));
6530 size(0);
6531 format %{ "# checkcastPP of $dst" %}
6532 ins_encode( /*empty encoding*/ );
6533 ins_pipe(empty);
6534 %}
6537 instruct castPP( iRegP dst ) %{
6538 match(Set dst (CastPP dst));
6539 format %{ "# castPP of $dst" %}
6540 ins_encode( /*empty encoding*/ );
6541 ins_pipe(empty);
6542 %}
6544 instruct castII( iRegI dst ) %{
6545 match(Set dst (CastII dst));
6546 format %{ "# castII of $dst" %}
6547 ins_encode( /*empty encoding*/ );
6548 ins_cost(0);
6549 ins_pipe(empty);
6550 %}
6552 //----------Arithmetic Instructions--------------------------------------------
6553 // Addition Instructions
6554 // Register Addition
6555 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6556 match(Set dst (AddI src1 src2));
6558 size(4);
6559 format %{ "ADD $src1,$src2,$dst" %}
6560 ins_encode %{
6561 __ add($src1$$Register, $src2$$Register, $dst$$Register);
6562 %}
6563 ins_pipe(ialu_reg_reg);
6564 %}
6566 // Immediate Addition
6567 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
6568 match(Set dst (AddI src1 src2));
6570 size(4);
6571 format %{ "ADD $src1,$src2,$dst" %}
6572 opcode(Assembler::add_op3, Assembler::arith_op);
6573 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6574 ins_pipe(ialu_reg_imm);
6575 %}
6577 // Pointer Register Addition
6578 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
6579 match(Set dst (AddP src1 src2));
6581 size(4);
6582 format %{ "ADD $src1,$src2,$dst" %}
6583 opcode(Assembler::add_op3, Assembler::arith_op);
6584 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6585 ins_pipe(ialu_reg_reg);
6586 %}
6588 // Pointer Immediate Addition
6589 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
6590 match(Set dst (AddP src1 src2));
6592 size(4);
6593 format %{ "ADD $src1,$src2,$dst" %}
6594 opcode(Assembler::add_op3, Assembler::arith_op);
6595 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6596 ins_pipe(ialu_reg_imm);
6597 %}
6599 // Long Addition
6600 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
6601 match(Set dst (AddL src1 src2));
6603 size(4);
6604 format %{ "ADD $src1,$src2,$dst\t! long" %}
6605 opcode(Assembler::add_op3, Assembler::arith_op);
6606 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6607 ins_pipe(ialu_reg_reg);
6608 %}
6610 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
6611 match(Set dst (AddL src1 con));
6613 size(4);
6614 format %{ "ADD $src1,$con,$dst" %}
6615 opcode(Assembler::add_op3, Assembler::arith_op);
6616 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
6617 ins_pipe(ialu_reg_imm);
6618 %}
6620 //----------Conditional_store--------------------------------------------------
6621 // Conditional-store of the updated heap-top.
6622 // Used during allocation of the shared heap.
6623 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
6625 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
6626 instruct loadPLocked(iRegP dst, memory mem) %{
6627 match(Set dst (LoadPLocked mem));
6628 ins_cost(MEMORY_REF_COST);
6630 #ifndef _LP64
6631 size(4);
6632 format %{ "LDUW $mem,$dst\t! ptr" %}
6633 opcode(Assembler::lduw_op3, 0, REGP_OP);
6634 #else
6635 format %{ "LDX $mem,$dst\t! ptr" %}
6636 opcode(Assembler::ldx_op3, 0, REGP_OP);
6637 #endif
6638 ins_encode( form3_mem_reg( mem, dst ) );
6639 ins_pipe(iload_mem);
6640 %}
6642 // LoadL-locked. Same as a regular long load when used with a compare-swap
6643 instruct loadLLocked(iRegL dst, memory mem) %{
6644 match(Set dst (LoadLLocked mem));
6645 ins_cost(MEMORY_REF_COST);
6646 size(4);
6647 format %{ "LDX $mem,$dst\t! long" %}
6648 opcode(Assembler::ldx_op3);
6649 ins_encode(simple_form3_mem_reg( mem, dst ) );
6650 ins_pipe(iload_mem);
6651 %}
6653 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
6654 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
6655 effect( KILL newval );
6656 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
6657 "CMP R_G3,$oldval\t\t! See if we made progress" %}
6658 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
6659 ins_pipe( long_memory_op );
6660 %}
6662 // Conditional-store of an int value.
6663 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
6664 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
6665 effect( KILL newval );
6666 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
6667 "CMP $oldval,$newval\t\t! See if we made progress" %}
6668 ins_encode( enc_cas(mem_ptr,oldval,newval) );
6669 ins_pipe( long_memory_op );
6670 %}
6672 // Conditional-store of a long value.
6673 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
6674 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
6675 effect( KILL newval );
6676 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
6677 "CMP $oldval,$newval\t\t! See if we made progress" %}
6678 ins_encode( enc_cas(mem_ptr,oldval,newval) );
6679 ins_pipe( long_memory_op );
6680 %}
6682 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
6684 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6685 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
6686 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6687 format %{
6688 "MOV $newval,O7\n\t"
6689 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6690 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6691 "MOV 1,$res\n\t"
6692 "MOVne xcc,R_G0,$res"
6693 %}
6694 ins_encode( enc_casx(mem_ptr, oldval, newval),
6695 enc_lflags_ne_to_boolean(res) );
6696 ins_pipe( long_memory_op );
6697 %}
6700 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6701 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
6702 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6703 format %{
6704 "MOV $newval,O7\n\t"
6705 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6706 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6707 "MOV 1,$res\n\t"
6708 "MOVne icc,R_G0,$res"
6709 %}
6710 ins_encode( enc_casi(mem_ptr, oldval, newval),
6711 enc_iflags_ne_to_boolean(res) );
6712 ins_pipe( long_memory_op );
6713 %}
6715 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6716 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
6717 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6718 format %{
6719 "MOV $newval,O7\n\t"
6720 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6721 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6722 "MOV 1,$res\n\t"
6723 "MOVne xcc,R_G0,$res"
6724 %}
6725 #ifdef _LP64
6726 ins_encode( enc_casx(mem_ptr, oldval, newval),
6727 enc_lflags_ne_to_boolean(res) );
6728 #else
6729 ins_encode( enc_casi(mem_ptr, oldval, newval),
6730 enc_iflags_ne_to_boolean(res) );
6731 #endif
6732 ins_pipe( long_memory_op );
6733 %}
6735 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6736 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
6737 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6738 format %{
6739 "MOV $newval,O7\n\t"
6740 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6741 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6742 "MOV 1,$res\n\t"
6743 "MOVne icc,R_G0,$res"
6744 %}
6745 ins_encode( enc_casi(mem_ptr, oldval, newval),
6746 enc_iflags_ne_to_boolean(res) );
6747 ins_pipe( long_memory_op );
6748 %}
6750 //---------------------
6751 // Subtraction Instructions
6752 // Register Subtraction
6753 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6754 match(Set dst (SubI src1 src2));
6756 size(4);
6757 format %{ "SUB $src1,$src2,$dst" %}
6758 opcode(Assembler::sub_op3, Assembler::arith_op);
6759 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6760 ins_pipe(ialu_reg_reg);
6761 %}
6763 // Immediate Subtraction
6764 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
6765 match(Set dst (SubI src1 src2));
6767 size(4);
6768 format %{ "SUB $src1,$src2,$dst" %}
6769 opcode(Assembler::sub_op3, Assembler::arith_op);
6770 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6771 ins_pipe(ialu_reg_imm);
6772 %}
6774 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
6775 match(Set dst (SubI zero src2));
6777 size(4);
6778 format %{ "NEG $src2,$dst" %}
6779 opcode(Assembler::sub_op3, Assembler::arith_op);
6780 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
6781 ins_pipe(ialu_zero_reg);
6782 %}
6784 // Long subtraction
6785 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
6786 match(Set dst (SubL src1 src2));
6788 size(4);
6789 format %{ "SUB $src1,$src2,$dst\t! long" %}
6790 opcode(Assembler::sub_op3, Assembler::arith_op);
6791 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6792 ins_pipe(ialu_reg_reg);
6793 %}
6795 // Immediate Subtraction
6796 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
6797 match(Set dst (SubL src1 con));
6799 size(4);
6800 format %{ "SUB $src1,$con,$dst\t! long" %}
6801 opcode(Assembler::sub_op3, Assembler::arith_op);
6802 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
6803 ins_pipe(ialu_reg_imm);
6804 %}
6806 // Long negation
6807 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
6808 match(Set dst (SubL zero src2));
6810 size(4);
6811 format %{ "NEG $src2,$dst\t! long" %}
6812 opcode(Assembler::sub_op3, Assembler::arith_op);
6813 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
6814 ins_pipe(ialu_zero_reg);
6815 %}
6817 // Multiplication Instructions
6818 // Integer Multiplication
6819 // Register Multiplication
6820 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6821 match(Set dst (MulI src1 src2));
6823 size(4);
6824 format %{ "MULX $src1,$src2,$dst" %}
6825 opcode(Assembler::mulx_op3, Assembler::arith_op);
6826 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6827 ins_pipe(imul_reg_reg);
6828 %}
6830 // Immediate Multiplication
6831 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
6832 match(Set dst (MulI src1 src2));
6834 size(4);
6835 format %{ "MULX $src1,$src2,$dst" %}
6836 opcode(Assembler::mulx_op3, Assembler::arith_op);
6837 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6838 ins_pipe(imul_reg_imm);
6839 %}
6841 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
6842 match(Set dst (MulL src1 src2));
6843 ins_cost(DEFAULT_COST * 5);
6844 size(4);
6845 format %{ "MULX $src1,$src2,$dst\t! long" %}
6846 opcode(Assembler::mulx_op3, Assembler::arith_op);
6847 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6848 ins_pipe(mulL_reg_reg);
6849 %}
6851 // Immediate Multiplication
6852 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
6853 match(Set dst (MulL src1 src2));
6854 ins_cost(DEFAULT_COST * 5);
6855 size(4);
6856 format %{ "MULX $src1,$src2,$dst" %}
6857 opcode(Assembler::mulx_op3, Assembler::arith_op);
6858 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6859 ins_pipe(mulL_reg_imm);
6860 %}
6862 // Integer Division
6863 // Register Division
6864 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
6865 match(Set dst (DivI src1 src2));
6866 ins_cost((2+71)*DEFAULT_COST);
6868 format %{ "SRA $src2,0,$src2\n\t"
6869 "SRA $src1,0,$src1\n\t"
6870 "SDIVX $src1,$src2,$dst" %}
6871 ins_encode( idiv_reg( src1, src2, dst ) );
6872 ins_pipe(sdiv_reg_reg);
6873 %}
6875 // Immediate Division
6876 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
6877 match(Set dst (DivI src1 src2));
6878 ins_cost((2+71)*DEFAULT_COST);
6880 format %{ "SRA $src1,0,$src1\n\t"
6881 "SDIVX $src1,$src2,$dst" %}
6882 ins_encode( idiv_imm( src1, src2, dst ) );
6883 ins_pipe(sdiv_reg_imm);
6884 %}
6886 //----------Div-By-10-Expansion------------------------------------------------
6887 // Extract hi bits of a 32x32->64 bit multiply.
6888 // Expand rule only, not matched
6889 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
6890 effect( DEF dst, USE src1, USE src2 );
6891 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
6892 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
6893 ins_encode( enc_mul_hi(dst,src1,src2));
6894 ins_pipe(sdiv_reg_reg);
6895 %}
6897 // Magic constant, reciprocal of 10
6898 instruct loadConI_x66666667(iRegIsafe dst) %{
6899 effect( DEF dst );
6901 size(8);
6902 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
6903 ins_encode( Set32(0x66666667, dst) );
6904 ins_pipe(ialu_hi_lo_reg);
6905 %}
6907 // Register Shift Right Arithmetic Long by 32-63
6908 instruct sra_31( iRegI dst, iRegI src ) %{
6909 effect( DEF dst, USE src );
6910 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
6911 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
6912 ins_pipe(ialu_reg_reg);
6913 %}
6915 // Arithmetic Shift Right by 8-bit immediate
6916 instruct sra_reg_2( iRegI dst, iRegI src ) %{
6917 effect( DEF dst, USE src );
6918 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
6919 opcode(Assembler::sra_op3, Assembler::arith_op);
6920 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
6921 ins_pipe(ialu_reg_imm);
6922 %}
6924 // Integer DIV with 10
6925 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
6926 match(Set dst (DivI src div));
6927 ins_cost((6+6)*DEFAULT_COST);
6928 expand %{
6929 iRegIsafe tmp1; // Killed temps;
6930 iRegIsafe tmp2; // Killed temps;
6931 iRegI tmp3; // Killed temps;
6932 iRegI tmp4; // Killed temps;
6933 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
6934 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
6935 sra_31( tmp3, src ); // SRA src,31 -> tmp3
6936 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
6937 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
6938 %}
6939 %}
6941 // Register Long Division
6942 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
6943 match(Set dst (DivL src1 src2));
6944 ins_cost(DEFAULT_COST*71);
6945 size(4);
6946 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
6947 opcode(Assembler::sdivx_op3, Assembler::arith_op);
6948 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6949 ins_pipe(divL_reg_reg);
6950 %}
6952 // Register Long Division
6953 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
6954 match(Set dst (DivL src1 src2));
6955 ins_cost(DEFAULT_COST*71);
6956 size(4);
6957 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
6958 opcode(Assembler::sdivx_op3, Assembler::arith_op);
6959 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6960 ins_pipe(divL_reg_imm);
6961 %}
6963 // Integer Remainder
6964 // Register Remainder
6965 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
6966 match(Set dst (ModI src1 src2));
6967 effect( KILL ccr, KILL temp);
6969 format %{ "SREM $src1,$src2,$dst" %}
6970 ins_encode( irem_reg(src1, src2, dst, temp) );
6971 ins_pipe(sdiv_reg_reg);
6972 %}
6974 // Immediate Remainder
6975 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
6976 match(Set dst (ModI src1 src2));
6977 effect( KILL ccr, KILL temp);
6979 format %{ "SREM $src1,$src2,$dst" %}
6980 ins_encode( irem_imm(src1, src2, dst, temp) );
6981 ins_pipe(sdiv_reg_imm);
6982 %}
6984 // Register Long Remainder
6985 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
6986 effect(DEF dst, USE src1, USE src2);
6987 size(4);
6988 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
6989 opcode(Assembler::sdivx_op3, Assembler::arith_op);
6990 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6991 ins_pipe(divL_reg_reg);
6992 %}
6994 // Register Long Division
6995 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
6996 effect(DEF dst, USE src1, USE src2);
6997 size(4);
6998 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
6999 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7000 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7001 ins_pipe(divL_reg_imm);
7002 %}
7004 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7005 effect(DEF dst, USE src1, USE src2);
7006 size(4);
7007 format %{ "MULX $src1,$src2,$dst\t! long" %}
7008 opcode(Assembler::mulx_op3, Assembler::arith_op);
7009 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7010 ins_pipe(mulL_reg_reg);
7011 %}
7013 // Immediate Multiplication
7014 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7015 effect(DEF dst, USE src1, USE src2);
7016 size(4);
7017 format %{ "MULX $src1,$src2,$dst" %}
7018 opcode(Assembler::mulx_op3, Assembler::arith_op);
7019 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7020 ins_pipe(mulL_reg_imm);
7021 %}
7023 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7024 effect(DEF dst, USE src1, USE src2);
7025 size(4);
7026 format %{ "SUB $src1,$src2,$dst\t! long" %}
7027 opcode(Assembler::sub_op3, Assembler::arith_op);
7028 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7029 ins_pipe(ialu_reg_reg);
7030 %}
7032 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7033 effect(DEF dst, USE src1, USE src2);
7034 size(4);
7035 format %{ "SUB $src1,$src2,$dst\t! long" %}
7036 opcode(Assembler::sub_op3, Assembler::arith_op);
7037 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7038 ins_pipe(ialu_reg_reg);
7039 %}
7041 // Register Long Remainder
7042 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7043 match(Set dst (ModL src1 src2));
7044 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7045 expand %{
7046 iRegL tmp1;
7047 iRegL tmp2;
7048 divL_reg_reg_1(tmp1, src1, src2);
7049 mulL_reg_reg_1(tmp2, tmp1, src2);
7050 subL_reg_reg_1(dst, src1, tmp2);
7051 %}
7052 %}
7054 // Register Long Remainder
7055 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7056 match(Set dst (ModL src1 src2));
7057 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7058 expand %{
7059 iRegL tmp1;
7060 iRegL tmp2;
7061 divL_reg_imm13_1(tmp1, src1, src2);
7062 mulL_reg_imm13_1(tmp2, tmp1, src2);
7063 subL_reg_reg_2 (dst, src1, tmp2);
7064 %}
7065 %}
7067 // Integer Shift Instructions
7068 // Register Shift Left
7069 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7070 match(Set dst (LShiftI src1 src2));
7072 size(4);
7073 format %{ "SLL $src1,$src2,$dst" %}
7074 opcode(Assembler::sll_op3, Assembler::arith_op);
7075 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7076 ins_pipe(ialu_reg_reg);
7077 %}
7079 // Register Shift Left Immediate
7080 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7081 match(Set dst (LShiftI src1 src2));
7083 size(4);
7084 format %{ "SLL $src1,$src2,$dst" %}
7085 opcode(Assembler::sll_op3, Assembler::arith_op);
7086 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7087 ins_pipe(ialu_reg_imm);
7088 %}
7090 // Register Shift Left
7091 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7092 match(Set dst (LShiftL src1 src2));
7094 size(4);
7095 format %{ "SLLX $src1,$src2,$dst" %}
7096 opcode(Assembler::sllx_op3, Assembler::arith_op);
7097 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7098 ins_pipe(ialu_reg_reg);
7099 %}
7101 // Register Shift Left Immediate
7102 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7103 match(Set dst (LShiftL src1 src2));
7105 size(4);
7106 format %{ "SLLX $src1,$src2,$dst" %}
7107 opcode(Assembler::sllx_op3, Assembler::arith_op);
7108 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7109 ins_pipe(ialu_reg_imm);
7110 %}
7112 // Register Arithmetic Shift Right
7113 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7114 match(Set dst (RShiftI src1 src2));
7115 size(4);
7116 format %{ "SRA $src1,$src2,$dst" %}
7117 opcode(Assembler::sra_op3, Assembler::arith_op);
7118 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7119 ins_pipe(ialu_reg_reg);
7120 %}
7122 // Register Arithmetic Shift Right Immediate
7123 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7124 match(Set dst (RShiftI src1 src2));
7126 size(4);
7127 format %{ "SRA $src1,$src2,$dst" %}
7128 opcode(Assembler::sra_op3, Assembler::arith_op);
7129 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7130 ins_pipe(ialu_reg_imm);
7131 %}
7133 // Register Shift Right Arithmatic Long
7134 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7135 match(Set dst (RShiftL src1 src2));
7137 size(4);
7138 format %{ "SRAX $src1,$src2,$dst" %}
7139 opcode(Assembler::srax_op3, Assembler::arith_op);
7140 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7141 ins_pipe(ialu_reg_reg);
7142 %}
7144 // Register Shift Left Immediate
7145 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7146 match(Set dst (RShiftL src1 src2));
7148 size(4);
7149 format %{ "SRAX $src1,$src2,$dst" %}
7150 opcode(Assembler::srax_op3, Assembler::arith_op);
7151 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7152 ins_pipe(ialu_reg_imm);
7153 %}
7155 // Register Shift Right
7156 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7157 match(Set dst (URShiftI src1 src2));
7159 size(4);
7160 format %{ "SRL $src1,$src2,$dst" %}
7161 opcode(Assembler::srl_op3, Assembler::arith_op);
7162 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7163 ins_pipe(ialu_reg_reg);
7164 %}
7166 // Register Shift Right Immediate
7167 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7168 match(Set dst (URShiftI src1 src2));
7170 size(4);
7171 format %{ "SRL $src1,$src2,$dst" %}
7172 opcode(Assembler::srl_op3, Assembler::arith_op);
7173 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7174 ins_pipe(ialu_reg_imm);
7175 %}
7177 // Register Shift Right
7178 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7179 match(Set dst (URShiftL src1 src2));
7181 size(4);
7182 format %{ "SRLX $src1,$src2,$dst" %}
7183 opcode(Assembler::srlx_op3, Assembler::arith_op);
7184 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7185 ins_pipe(ialu_reg_reg);
7186 %}
7188 // Register Shift Right Immediate
7189 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7190 match(Set dst (URShiftL src1 src2));
7192 size(4);
7193 format %{ "SRLX $src1,$src2,$dst" %}
7194 opcode(Assembler::srlx_op3, Assembler::arith_op);
7195 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7196 ins_pipe(ialu_reg_imm);
7197 %}
7199 // Register Shift Right Immediate with a CastP2X
7200 #ifdef _LP64
7201 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7202 match(Set dst (URShiftL (CastP2X src1) src2));
7203 size(4);
7204 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7205 opcode(Assembler::srlx_op3, Assembler::arith_op);
7206 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7207 ins_pipe(ialu_reg_imm);
7208 %}
7209 #else
7210 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7211 match(Set dst (URShiftI (CastP2X src1) src2));
7212 size(4);
7213 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7214 opcode(Assembler::srl_op3, Assembler::arith_op);
7215 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7216 ins_pipe(ialu_reg_imm);
7217 %}
7218 #endif
7221 //----------Floating Point Arithmetic Instructions-----------------------------
7223 // Add float single precision
7224 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7225 match(Set dst (AddF src1 src2));
7227 size(4);
7228 format %{ "FADDS $src1,$src2,$dst" %}
7229 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7230 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7231 ins_pipe(faddF_reg_reg);
7232 %}
7234 // Add float double precision
7235 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7236 match(Set dst (AddD src1 src2));
7238 size(4);
7239 format %{ "FADDD $src1,$src2,$dst" %}
7240 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7241 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7242 ins_pipe(faddD_reg_reg);
7243 %}
7245 // Sub float single precision
7246 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7247 match(Set dst (SubF src1 src2));
7249 size(4);
7250 format %{ "FSUBS $src1,$src2,$dst" %}
7251 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7252 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7253 ins_pipe(faddF_reg_reg);
7254 %}
7256 // Sub float double precision
7257 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7258 match(Set dst (SubD src1 src2));
7260 size(4);
7261 format %{ "FSUBD $src1,$src2,$dst" %}
7262 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7263 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7264 ins_pipe(faddD_reg_reg);
7265 %}
7267 // Mul float single precision
7268 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7269 match(Set dst (MulF src1 src2));
7271 size(4);
7272 format %{ "FMULS $src1,$src2,$dst" %}
7273 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7274 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7275 ins_pipe(fmulF_reg_reg);
7276 %}
7278 // Mul float double precision
7279 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7280 match(Set dst (MulD src1 src2));
7282 size(4);
7283 format %{ "FMULD $src1,$src2,$dst" %}
7284 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7285 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7286 ins_pipe(fmulD_reg_reg);
7287 %}
7289 // Div float single precision
7290 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7291 match(Set dst (DivF src1 src2));
7293 size(4);
7294 format %{ "FDIVS $src1,$src2,$dst" %}
7295 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7296 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7297 ins_pipe(fdivF_reg_reg);
7298 %}
7300 // Div float double precision
7301 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7302 match(Set dst (DivD src1 src2));
7304 size(4);
7305 format %{ "FDIVD $src1,$src2,$dst" %}
7306 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7307 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7308 ins_pipe(fdivD_reg_reg);
7309 %}
7311 // Absolute float double precision
7312 instruct absD_reg(regD dst, regD src) %{
7313 match(Set dst (AbsD src));
7315 format %{ "FABSd $src,$dst" %}
7316 ins_encode(fabsd(dst, src));
7317 ins_pipe(faddD_reg);
7318 %}
7320 // Absolute float single precision
7321 instruct absF_reg(regF dst, regF src) %{
7322 match(Set dst (AbsF src));
7324 format %{ "FABSs $src,$dst" %}
7325 ins_encode(fabss(dst, src));
7326 ins_pipe(faddF_reg);
7327 %}
7329 instruct negF_reg(regF dst, regF src) %{
7330 match(Set dst (NegF src));
7332 size(4);
7333 format %{ "FNEGs $src,$dst" %}
7334 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7335 ins_encode(form3_opf_rs2F_rdF(src, dst));
7336 ins_pipe(faddF_reg);
7337 %}
7339 instruct negD_reg(regD dst, regD src) %{
7340 match(Set dst (NegD src));
7342 format %{ "FNEGd $src,$dst" %}
7343 ins_encode(fnegd(dst, src));
7344 ins_pipe(faddD_reg);
7345 %}
7347 // Sqrt float double precision
7348 instruct sqrtF_reg_reg(regF dst, regF src) %{
7349 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7351 size(4);
7352 format %{ "FSQRTS $src,$dst" %}
7353 ins_encode(fsqrts(dst, src));
7354 ins_pipe(fdivF_reg_reg);
7355 %}
7357 // Sqrt float double precision
7358 instruct sqrtD_reg_reg(regD dst, regD src) %{
7359 match(Set dst (SqrtD src));
7361 size(4);
7362 format %{ "FSQRTD $src,$dst" %}
7363 ins_encode(fsqrtd(dst, src));
7364 ins_pipe(fdivD_reg_reg);
7365 %}
7367 //----------Logical Instructions-----------------------------------------------
7368 // And Instructions
7369 // Register And
7370 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7371 match(Set dst (AndI src1 src2));
7373 size(4);
7374 format %{ "AND $src1,$src2,$dst" %}
7375 opcode(Assembler::and_op3, Assembler::arith_op);
7376 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7377 ins_pipe(ialu_reg_reg);
7378 %}
7380 // Immediate And
7381 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7382 match(Set dst (AndI src1 src2));
7384 size(4);
7385 format %{ "AND $src1,$src2,$dst" %}
7386 opcode(Assembler::and_op3, Assembler::arith_op);
7387 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7388 ins_pipe(ialu_reg_imm);
7389 %}
7391 // Register And Long
7392 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7393 match(Set dst (AndL src1 src2));
7395 ins_cost(DEFAULT_COST);
7396 size(4);
7397 format %{ "AND $src1,$src2,$dst\t! long" %}
7398 opcode(Assembler::and_op3, Assembler::arith_op);
7399 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7400 ins_pipe(ialu_reg_reg);
7401 %}
7403 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7404 match(Set dst (AndL src1 con));
7406 ins_cost(DEFAULT_COST);
7407 size(4);
7408 format %{ "AND $src1,$con,$dst\t! long" %}
7409 opcode(Assembler::and_op3, Assembler::arith_op);
7410 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7411 ins_pipe(ialu_reg_imm);
7412 %}
7414 // Or Instructions
7415 // Register Or
7416 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7417 match(Set dst (OrI src1 src2));
7419 size(4);
7420 format %{ "OR $src1,$src2,$dst" %}
7421 opcode(Assembler::or_op3, Assembler::arith_op);
7422 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7423 ins_pipe(ialu_reg_reg);
7424 %}
7426 // Immediate Or
7427 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7428 match(Set dst (OrI src1 src2));
7430 size(4);
7431 format %{ "OR $src1,$src2,$dst" %}
7432 opcode(Assembler::or_op3, Assembler::arith_op);
7433 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7434 ins_pipe(ialu_reg_imm);
7435 %}
7437 // Register Or Long
7438 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7439 match(Set dst (OrL src1 src2));
7441 ins_cost(DEFAULT_COST);
7442 size(4);
7443 format %{ "OR $src1,$src2,$dst\t! long" %}
7444 opcode(Assembler::or_op3, Assembler::arith_op);
7445 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7446 ins_pipe(ialu_reg_reg);
7447 %}
7449 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7450 match(Set dst (OrL src1 con));
7451 ins_cost(DEFAULT_COST*2);
7453 ins_cost(DEFAULT_COST);
7454 size(4);
7455 format %{ "OR $src1,$con,$dst\t! long" %}
7456 opcode(Assembler::or_op3, Assembler::arith_op);
7457 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7458 ins_pipe(ialu_reg_imm);
7459 %}
7461 #ifndef _LP64
7463 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
7464 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
7465 match(Set dst (OrI src1 (CastP2X src2)));
7467 size(4);
7468 format %{ "OR $src1,$src2,$dst" %}
7469 opcode(Assembler::or_op3, Assembler::arith_op);
7470 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7471 ins_pipe(ialu_reg_reg);
7472 %}
7474 #else
7476 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
7477 match(Set dst (OrL src1 (CastP2X src2)));
7479 ins_cost(DEFAULT_COST);
7480 size(4);
7481 format %{ "OR $src1,$src2,$dst\t! long" %}
7482 opcode(Assembler::or_op3, Assembler::arith_op);
7483 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7484 ins_pipe(ialu_reg_reg);
7485 %}
7487 #endif
7489 // Xor Instructions
7490 // Register Xor
7491 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7492 match(Set dst (XorI src1 src2));
7494 size(4);
7495 format %{ "XOR $src1,$src2,$dst" %}
7496 opcode(Assembler::xor_op3, Assembler::arith_op);
7497 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7498 ins_pipe(ialu_reg_reg);
7499 %}
7501 // Immediate Xor
7502 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7503 match(Set dst (XorI src1 src2));
7505 size(4);
7506 format %{ "XOR $src1,$src2,$dst" %}
7507 opcode(Assembler::xor_op3, Assembler::arith_op);
7508 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7509 ins_pipe(ialu_reg_imm);
7510 %}
7512 // Register Xor Long
7513 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7514 match(Set dst (XorL src1 src2));
7516 ins_cost(DEFAULT_COST);
7517 size(4);
7518 format %{ "XOR $src1,$src2,$dst\t! long" %}
7519 opcode(Assembler::xor_op3, Assembler::arith_op);
7520 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7521 ins_pipe(ialu_reg_reg);
7522 %}
7524 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7525 match(Set dst (XorL src1 con));
7527 ins_cost(DEFAULT_COST);
7528 size(4);
7529 format %{ "XOR $src1,$con,$dst\t! long" %}
7530 opcode(Assembler::xor_op3, Assembler::arith_op);
7531 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7532 ins_pipe(ialu_reg_imm);
7533 %}
7535 //----------Convert to Boolean-------------------------------------------------
7536 // Nice hack for 32-bit tests but doesn't work for
7537 // 64-bit pointers.
7538 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
7539 match(Set dst (Conv2B src));
7540 effect( KILL ccr );
7541 ins_cost(DEFAULT_COST*2);
7542 format %{ "CMP R_G0,$src\n\t"
7543 "ADDX R_G0,0,$dst" %}
7544 ins_encode( enc_to_bool( src, dst ) );
7545 ins_pipe(ialu_reg_ialu);
7546 %}
7548 #ifndef _LP64
7549 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
7550 match(Set dst (Conv2B src));
7551 effect( KILL ccr );
7552 ins_cost(DEFAULT_COST*2);
7553 format %{ "CMP R_G0,$src\n\t"
7554 "ADDX R_G0,0,$dst" %}
7555 ins_encode( enc_to_bool( src, dst ) );
7556 ins_pipe(ialu_reg_ialu);
7557 %}
7558 #else
7559 instruct convP2B( iRegI dst, iRegP src ) %{
7560 match(Set dst (Conv2B src));
7561 ins_cost(DEFAULT_COST*2);
7562 format %{ "MOV $src,$dst\n\t"
7563 "MOVRNZ $src,1,$dst" %}
7564 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
7565 ins_pipe(ialu_clr_and_mover);
7566 %}
7567 #endif
7569 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
7570 match(Set dst (CmpLTMask p q));
7571 effect( KILL ccr );
7572 ins_cost(DEFAULT_COST*4);
7573 format %{ "CMP $p,$q\n\t"
7574 "MOV #0,$dst\n\t"
7575 "BLT,a .+8\n\t"
7576 "MOV #-1,$dst" %}
7577 ins_encode( enc_ltmask(p,q,dst) );
7578 ins_pipe(ialu_reg_reg_ialu);
7579 %}
7581 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
7582 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
7583 effect(KILL ccr, TEMP tmp);
7584 ins_cost(DEFAULT_COST*3);
7586 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
7587 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
7588 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %}
7589 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
7590 ins_pipe( cadd_cmpltmask );
7591 %}
7593 instruct cadd_cmpLTMask2( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
7594 match(Set p (AddI (SubI p q) (AndI (CmpLTMask p q) y)));
7595 effect( KILL ccr, TEMP tmp);
7596 ins_cost(DEFAULT_COST*3);
7598 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
7599 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
7600 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %}
7601 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
7602 ins_pipe( cadd_cmpltmask );
7603 %}
7605 //----------Arithmetic Conversion Instructions---------------------------------
7606 // The conversions operations are all Alpha sorted. Please keep it that way!
7608 instruct convD2F_reg(regF dst, regD src) %{
7609 match(Set dst (ConvD2F src));
7610 size(4);
7611 format %{ "FDTOS $src,$dst" %}
7612 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
7613 ins_encode(form3_opf_rs2D_rdF(src, dst));
7614 ins_pipe(fcvtD2F);
7615 %}
7618 // Convert a double to an int in a float register.
7619 // If the double is a NAN, stuff a zero in instead.
7620 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
7621 effect(DEF dst, USE src, KILL fcc0);
7622 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
7623 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7624 "FDTOI $src,$dst\t! convert in delay slot\n\t"
7625 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
7626 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
7627 "skip:" %}
7628 ins_encode(form_d2i_helper(src,dst));
7629 ins_pipe(fcvtD2I);
7630 %}
7632 instruct convD2I_reg(stackSlotI dst, regD src) %{
7633 match(Set dst (ConvD2I src));
7634 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
7635 expand %{
7636 regF tmp;
7637 convD2I_helper(tmp, src);
7638 regF_to_stkI(dst, tmp);
7639 %}
7640 %}
7642 // Convert a double to a long in a double register.
7643 // If the double is a NAN, stuff a zero in instead.
7644 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
7645 effect(DEF dst, USE src, KILL fcc0);
7646 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
7647 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7648 "FDTOX $src,$dst\t! convert in delay slot\n\t"
7649 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
7650 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
7651 "skip:" %}
7652 ins_encode(form_d2l_helper(src,dst));
7653 ins_pipe(fcvtD2L);
7654 %}
7657 // Double to Long conversion
7658 instruct convD2L_reg(stackSlotL dst, regD src) %{
7659 match(Set dst (ConvD2L src));
7660 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
7661 expand %{
7662 regD tmp;
7663 convD2L_helper(tmp, src);
7664 regD_to_stkL(dst, tmp);
7665 %}
7666 %}
7669 instruct convF2D_reg(regD dst, regF src) %{
7670 match(Set dst (ConvF2D src));
7671 format %{ "FSTOD $src,$dst" %}
7672 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
7673 ins_encode(form3_opf_rs2F_rdD(src, dst));
7674 ins_pipe(fcvtF2D);
7675 %}
7678 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
7679 effect(DEF dst, USE src, KILL fcc0);
7680 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
7681 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7682 "FSTOI $src,$dst\t! convert in delay slot\n\t"
7683 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
7684 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
7685 "skip:" %}
7686 ins_encode(form_f2i_helper(src,dst));
7687 ins_pipe(fcvtF2I);
7688 %}
7690 instruct convF2I_reg(stackSlotI dst, regF src) %{
7691 match(Set dst (ConvF2I src));
7692 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
7693 expand %{
7694 regF tmp;
7695 convF2I_helper(tmp, src);
7696 regF_to_stkI(dst, tmp);
7697 %}
7698 %}
7701 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
7702 effect(DEF dst, USE src, KILL fcc0);
7703 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
7704 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7705 "FSTOX $src,$dst\t! convert in delay slot\n\t"
7706 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
7707 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
7708 "skip:" %}
7709 ins_encode(form_f2l_helper(src,dst));
7710 ins_pipe(fcvtF2L);
7711 %}
7713 // Float to Long conversion
7714 instruct convF2L_reg(stackSlotL dst, regF src) %{
7715 match(Set dst (ConvF2L src));
7716 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
7717 expand %{
7718 regD tmp;
7719 convF2L_helper(tmp, src);
7720 regD_to_stkL(dst, tmp);
7721 %}
7722 %}
7725 instruct convI2D_helper(regD dst, regF tmp) %{
7726 effect(USE tmp, DEF dst);
7727 format %{ "FITOD $tmp,$dst" %}
7728 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
7729 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
7730 ins_pipe(fcvtI2D);
7731 %}
7733 instruct convI2D_reg(stackSlotI src, regD dst) %{
7734 match(Set dst (ConvI2D src));
7735 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
7736 expand %{
7737 regF tmp;
7738 stkI_to_regF( tmp, src);
7739 convI2D_helper( dst, tmp);
7740 %}
7741 %}
7743 instruct convI2D_mem( regD_low dst, memory mem ) %{
7744 match(Set dst (ConvI2D (LoadI mem)));
7745 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
7746 size(8);
7747 format %{ "LDF $mem,$dst\n\t"
7748 "FITOD $dst,$dst" %}
7749 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
7750 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
7751 ins_pipe(floadF_mem);
7752 %}
7755 instruct convI2F_helper(regF dst, regF tmp) %{
7756 effect(DEF dst, USE tmp);
7757 format %{ "FITOS $tmp,$dst" %}
7758 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
7759 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
7760 ins_pipe(fcvtI2F);
7761 %}
7763 instruct convI2F_reg( regF dst, stackSlotI src ) %{
7764 match(Set dst (ConvI2F src));
7765 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
7766 expand %{
7767 regF tmp;
7768 stkI_to_regF(tmp,src);
7769 convI2F_helper(dst, tmp);
7770 %}
7771 %}
7773 instruct convI2F_mem( regF dst, memory mem ) %{
7774 match(Set dst (ConvI2F (LoadI mem)));
7775 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
7776 size(8);
7777 format %{ "LDF $mem,$dst\n\t"
7778 "FITOS $dst,$dst" %}
7779 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
7780 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
7781 ins_pipe(floadF_mem);
7782 %}
7785 instruct convI2L_reg(iRegL dst, iRegI src) %{
7786 match(Set dst (ConvI2L src));
7787 size(4);
7788 format %{ "SRA $src,0,$dst\t! int->long" %}
7789 opcode(Assembler::sra_op3, Assembler::arith_op);
7790 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
7791 ins_pipe(ialu_reg_reg);
7792 %}
7794 // Zero-extend convert int to long
7795 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
7796 match(Set dst (AndL (ConvI2L src) mask) );
7797 size(4);
7798 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
7799 opcode(Assembler::srl_op3, Assembler::arith_op);
7800 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
7801 ins_pipe(ialu_reg_reg);
7802 %}
7804 // Zero-extend long
7805 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
7806 match(Set dst (AndL src mask) );
7807 size(4);
7808 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
7809 opcode(Assembler::srl_op3, Assembler::arith_op);
7810 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
7811 ins_pipe(ialu_reg_reg);
7812 %}
7814 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
7815 match(Set dst (MoveF2I src));
7816 effect(DEF dst, USE src);
7817 ins_cost(MEMORY_REF_COST);
7819 size(4);
7820 format %{ "LDUW $src,$dst\t! MoveF2I" %}
7821 opcode(Assembler::lduw_op3);
7822 ins_encode(simple_form3_mem_reg( src, dst ) );
7823 ins_pipe(iload_mem);
7824 %}
7826 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
7827 match(Set dst (MoveI2F src));
7828 effect(DEF dst, USE src);
7829 ins_cost(MEMORY_REF_COST);
7831 size(4);
7832 format %{ "LDF $src,$dst\t! MoveI2F" %}
7833 opcode(Assembler::ldf_op3);
7834 ins_encode(simple_form3_mem_reg(src, dst));
7835 ins_pipe(floadF_stk);
7836 %}
7838 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
7839 match(Set dst (MoveD2L src));
7840 effect(DEF dst, USE src);
7841 ins_cost(MEMORY_REF_COST);
7843 size(4);
7844 format %{ "LDX $src,$dst\t! MoveD2L" %}
7845 opcode(Assembler::ldx_op3);
7846 ins_encode(simple_form3_mem_reg( src, dst ) );
7847 ins_pipe(iload_mem);
7848 %}
7850 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
7851 match(Set dst (MoveL2D src));
7852 effect(DEF dst, USE src);
7853 ins_cost(MEMORY_REF_COST);
7855 size(4);
7856 format %{ "LDDF $src,$dst\t! MoveL2D" %}
7857 opcode(Assembler::lddf_op3);
7858 ins_encode(simple_form3_mem_reg(src, dst));
7859 ins_pipe(floadD_stk);
7860 %}
7862 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
7863 match(Set dst (MoveF2I src));
7864 effect(DEF dst, USE src);
7865 ins_cost(MEMORY_REF_COST);
7867 size(4);
7868 format %{ "STF $src,$dst\t!MoveF2I" %}
7869 opcode(Assembler::stf_op3);
7870 ins_encode(simple_form3_mem_reg(dst, src));
7871 ins_pipe(fstoreF_stk_reg);
7872 %}
7874 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
7875 match(Set dst (MoveI2F src));
7876 effect(DEF dst, USE src);
7877 ins_cost(MEMORY_REF_COST);
7879 size(4);
7880 format %{ "STW $src,$dst\t!MoveI2F" %}
7881 opcode(Assembler::stw_op3);
7882 ins_encode(simple_form3_mem_reg( dst, src ) );
7883 ins_pipe(istore_mem_reg);
7884 %}
7886 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
7887 match(Set dst (MoveD2L src));
7888 effect(DEF dst, USE src);
7889 ins_cost(MEMORY_REF_COST);
7891 size(4);
7892 format %{ "STDF $src,$dst\t!MoveD2L" %}
7893 opcode(Assembler::stdf_op3);
7894 ins_encode(simple_form3_mem_reg(dst, src));
7895 ins_pipe(fstoreD_stk_reg);
7896 %}
7898 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
7899 match(Set dst (MoveL2D src));
7900 effect(DEF dst, USE src);
7901 ins_cost(MEMORY_REF_COST);
7903 size(4);
7904 format %{ "STX $src,$dst\t!MoveL2D" %}
7905 opcode(Assembler::stx_op3);
7906 ins_encode(simple_form3_mem_reg( dst, src ) );
7907 ins_pipe(istore_mem_reg);
7908 %}
7911 //-----------
7912 // Long to Double conversion using V8 opcodes.
7913 // Still useful because cheetah traps and becomes
7914 // amazingly slow for some common numbers.
7916 // Magic constant, 0x43300000
7917 instruct loadConI_x43300000(iRegI dst) %{
7918 effect(DEF dst);
7919 size(4);
7920 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
7921 ins_encode(SetHi22(0x43300000, dst));
7922 ins_pipe(ialu_none);
7923 %}
7925 // Magic constant, 0x41f00000
7926 instruct loadConI_x41f00000(iRegI dst) %{
7927 effect(DEF dst);
7928 size(4);
7929 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
7930 ins_encode(SetHi22(0x41f00000, dst));
7931 ins_pipe(ialu_none);
7932 %}
7934 // Construct a double from two float halves
7935 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
7936 effect(DEF dst, USE src1, USE src2);
7937 size(8);
7938 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
7939 "FMOVS $src2.lo,$dst.lo" %}
7940 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
7941 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
7942 ins_pipe(faddD_reg_reg);
7943 %}
7945 // Convert integer in high half of a double register (in the lower half of
7946 // the double register file) to double
7947 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
7948 effect(DEF dst, USE src);
7949 size(4);
7950 format %{ "FITOD $src,$dst" %}
7951 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
7952 ins_encode(form3_opf_rs2D_rdD(src, dst));
7953 ins_pipe(fcvtLHi2D);
7954 %}
7956 // Add float double precision
7957 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
7958 effect(DEF dst, USE src1, USE src2);
7959 size(4);
7960 format %{ "FADDD $src1,$src2,$dst" %}
7961 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7962 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7963 ins_pipe(faddD_reg_reg);
7964 %}
7966 // Sub float double precision
7967 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
7968 effect(DEF dst, USE src1, USE src2);
7969 size(4);
7970 format %{ "FSUBD $src1,$src2,$dst" %}
7971 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7972 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7973 ins_pipe(faddD_reg_reg);
7974 %}
7976 // Mul float double precision
7977 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
7978 effect(DEF dst, USE src1, USE src2);
7979 size(4);
7980 format %{ "FMULD $src1,$src2,$dst" %}
7981 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7982 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7983 ins_pipe(fmulD_reg_reg);
7984 %}
7986 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
7987 match(Set dst (ConvL2D src));
7988 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
7990 expand %{
7991 regD_low tmpsrc;
7992 iRegI ix43300000;
7993 iRegI ix41f00000;
7994 stackSlotL lx43300000;
7995 stackSlotL lx41f00000;
7996 regD_low dx43300000;
7997 regD dx41f00000;
7998 regD tmp1;
7999 regD_low tmp2;
8000 regD tmp3;
8001 regD tmp4;
8003 stkL_to_regD(tmpsrc, src);
8005 loadConI_x43300000(ix43300000);
8006 loadConI_x41f00000(ix41f00000);
8007 regI_to_stkLHi(lx43300000, ix43300000);
8008 regI_to_stkLHi(lx41f00000, ix41f00000);
8009 stkL_to_regD(dx43300000, lx43300000);
8010 stkL_to_regD(dx41f00000, lx41f00000);
8012 convI2D_regDHi_regD(tmp1, tmpsrc);
8013 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8014 subD_regD_regD(tmp3, tmp2, dx43300000);
8015 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8016 addD_regD_regD(dst, tmp3, tmp4);
8017 %}
8018 %}
8020 // Long to Double conversion using fast fxtof
8021 instruct convL2D_helper(regD dst, regD tmp) %{
8022 effect(DEF dst, USE tmp);
8023 size(4);
8024 format %{ "FXTOD $tmp,$dst" %}
8025 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8026 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8027 ins_pipe(fcvtL2D);
8028 %}
8030 instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{
8031 predicate(VM_Version::has_fast_fxtof());
8032 match(Set dst (ConvL2D src));
8033 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8034 expand %{
8035 regD tmp;
8036 stkL_to_regD(tmp, src);
8037 convL2D_helper(dst, tmp);
8038 %}
8039 %}
8041 //-----------
8042 // Long to Float conversion using V8 opcodes.
8043 // Still useful because cheetah traps and becomes
8044 // amazingly slow for some common numbers.
8046 // Long to Float conversion using fast fxtof
8047 instruct convL2F_helper(regF dst, regD tmp) %{
8048 effect(DEF dst, USE tmp);
8049 size(4);
8050 format %{ "FXTOS $tmp,$dst" %}
8051 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8052 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8053 ins_pipe(fcvtL2F);
8054 %}
8056 instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{
8057 match(Set dst (ConvL2F src));
8058 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8059 expand %{
8060 regD tmp;
8061 stkL_to_regD(tmp, src);
8062 convL2F_helper(dst, tmp);
8063 %}
8064 %}
8065 //-----------
8067 instruct convL2I_reg(iRegI dst, iRegL src) %{
8068 match(Set dst (ConvL2I src));
8069 #ifndef _LP64
8070 format %{ "MOV $src.lo,$dst\t! long->int" %}
8071 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8072 ins_pipe(ialu_move_reg_I_to_L);
8073 #else
8074 size(4);
8075 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8076 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8077 ins_pipe(ialu_reg);
8078 #endif
8079 %}
8081 // Register Shift Right Immediate
8082 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8083 match(Set dst (ConvL2I (RShiftL src cnt)));
8085 size(4);
8086 format %{ "SRAX $src,$cnt,$dst" %}
8087 opcode(Assembler::srax_op3, Assembler::arith_op);
8088 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8089 ins_pipe(ialu_reg_imm);
8090 %}
8092 // Replicate scalar to packed byte values in Double register
8093 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{
8094 effect(DEF dst, USE src);
8095 format %{ "SLLX $src,56,$dst\n\t"
8096 "SRLX $dst, 8,O7\n\t"
8097 "OR $dst,O7,$dst\n\t"
8098 "SRLX $dst,16,O7\n\t"
8099 "OR $dst,O7,$dst\n\t"
8100 "SRLX $dst,32,O7\n\t"
8101 "OR $dst,O7,$dst\t! replicate8B" %}
8102 ins_encode( enc_repl8b(src, dst));
8103 ins_pipe(ialu_reg);
8104 %}
8106 // Replicate scalar to packed byte values in Double register
8107 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{
8108 match(Set dst (Replicate8B src));
8109 expand %{
8110 iRegL tmp;
8111 Repl8B_reg_helper(tmp, src);
8112 regL_to_stkD(dst, tmp);
8113 %}
8114 %}
8116 // Replicate scalar constant to packed byte values in Double register
8117 instruct Repl8B_immI(regD dst, immI13 src, o7RegP tmp) %{
8118 match(Set dst (Replicate8B src));
8119 #ifdef _LP64
8120 size(36);
8121 #else
8122 size(8);
8123 #endif
8124 format %{ "SETHI hi(&Repl8($src)),$tmp\t!get Repl8B($src) from table\n\t"
8125 "LDDF [$tmp+lo(&Repl8($src))],$dst" %}
8126 ins_encode( LdReplImmI(src, dst, tmp, (8), (1)) );
8127 ins_pipe(loadConFD);
8128 %}
8130 // Replicate scalar to packed char values into stack slot
8131 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{
8132 effect(DEF dst, USE src);
8133 format %{ "SLLX $src,48,$dst\n\t"
8134 "SRLX $dst,16,O7\n\t"
8135 "OR $dst,O7,$dst\n\t"
8136 "SRLX $dst,32,O7\n\t"
8137 "OR $dst,O7,$dst\t! replicate4C" %}
8138 ins_encode( enc_repl4s(src, dst) );
8139 ins_pipe(ialu_reg);
8140 %}
8142 // Replicate scalar to packed char values into stack slot
8143 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{
8144 match(Set dst (Replicate4C src));
8145 expand %{
8146 iRegL tmp;
8147 Repl4C_reg_helper(tmp, src);
8148 regL_to_stkD(dst, tmp);
8149 %}
8150 %}
8152 // Replicate scalar constant to packed char values in Double register
8153 instruct Repl4C_immI(regD dst, immI src, o7RegP tmp) %{
8154 match(Set dst (Replicate4C src));
8155 #ifdef _LP64
8156 size(36);
8157 #else
8158 size(8);
8159 #endif
8160 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4C($src) from table\n\t"
8161 "LDDF [$tmp+lo(&Repl4($src))],$dst" %}
8162 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
8163 ins_pipe(loadConFD);
8164 %}
8166 // Replicate scalar to packed short values into stack slot
8167 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{
8168 effect(DEF dst, USE src);
8169 format %{ "SLLX $src,48,$dst\n\t"
8170 "SRLX $dst,16,O7\n\t"
8171 "OR $dst,O7,$dst\n\t"
8172 "SRLX $dst,32,O7\n\t"
8173 "OR $dst,O7,$dst\t! replicate4S" %}
8174 ins_encode( enc_repl4s(src, dst) );
8175 ins_pipe(ialu_reg);
8176 %}
8178 // Replicate scalar to packed short values into stack slot
8179 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{
8180 match(Set dst (Replicate4S src));
8181 expand %{
8182 iRegL tmp;
8183 Repl4S_reg_helper(tmp, src);
8184 regL_to_stkD(dst, tmp);
8185 %}
8186 %}
8188 // Replicate scalar constant to packed short values in Double register
8189 instruct Repl4S_immI(regD dst, immI src, o7RegP tmp) %{
8190 match(Set dst (Replicate4S src));
8191 #ifdef _LP64
8192 size(36);
8193 #else
8194 size(8);
8195 #endif
8196 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4S($src) from table\n\t"
8197 "LDDF [$tmp+lo(&Repl4($src))],$dst" %}
8198 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
8199 ins_pipe(loadConFD);
8200 %}
8202 // Replicate scalar to packed int values in Double register
8203 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{
8204 effect(DEF dst, USE src);
8205 format %{ "SLLX $src,32,$dst\n\t"
8206 "SRLX $dst,32,O7\n\t"
8207 "OR $dst,O7,$dst\t! replicate2I" %}
8208 ins_encode( enc_repl2i(src, dst));
8209 ins_pipe(ialu_reg);
8210 %}
8212 // Replicate scalar to packed int values in Double register
8213 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{
8214 match(Set dst (Replicate2I src));
8215 expand %{
8216 iRegL tmp;
8217 Repl2I_reg_helper(tmp, src);
8218 regL_to_stkD(dst, tmp);
8219 %}
8220 %}
8222 // Replicate scalar zero constant to packed int values in Double register
8223 instruct Repl2I_immI(regD dst, immI src, o7RegP tmp) %{
8224 match(Set dst (Replicate2I src));
8225 #ifdef _LP64
8226 size(36);
8227 #else
8228 size(8);
8229 #endif
8230 format %{ "SETHI hi(&Repl2($src)),$tmp\t!get Repl2I($src) from table\n\t"
8231 "LDDF [$tmp+lo(&Repl2($src))],$dst" %}
8232 ins_encode( LdReplImmI(src, dst, tmp, (2), (4)) );
8233 ins_pipe(loadConFD);
8234 %}
8236 //----------Control Flow Instructions------------------------------------------
8237 // Compare Instructions
8238 // Compare Integers
8239 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8240 match(Set icc (CmpI op1 op2));
8241 effect( DEF icc, USE op1, USE op2 );
8243 size(4);
8244 format %{ "CMP $op1,$op2" %}
8245 opcode(Assembler::subcc_op3, Assembler::arith_op);
8246 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8247 ins_pipe(ialu_cconly_reg_reg);
8248 %}
8250 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8251 match(Set icc (CmpU op1 op2));
8253 size(4);
8254 format %{ "CMP $op1,$op2\t! unsigned" %}
8255 opcode(Assembler::subcc_op3, Assembler::arith_op);
8256 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8257 ins_pipe(ialu_cconly_reg_reg);
8258 %}
8260 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8261 match(Set icc (CmpI op1 op2));
8262 effect( DEF icc, USE op1 );
8264 size(4);
8265 format %{ "CMP $op1,$op2" %}
8266 opcode(Assembler::subcc_op3, Assembler::arith_op);
8267 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8268 ins_pipe(ialu_cconly_reg_imm);
8269 %}
8271 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8272 match(Set icc (CmpI (AndI op1 op2) zero));
8274 size(4);
8275 format %{ "BTST $op2,$op1" %}
8276 opcode(Assembler::andcc_op3, Assembler::arith_op);
8277 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8278 ins_pipe(ialu_cconly_reg_reg_zero);
8279 %}
8281 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8282 match(Set icc (CmpI (AndI op1 op2) zero));
8284 size(4);
8285 format %{ "BTST $op2,$op1" %}
8286 opcode(Assembler::andcc_op3, Assembler::arith_op);
8287 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8288 ins_pipe(ialu_cconly_reg_imm_zero);
8289 %}
8291 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8292 match(Set xcc (CmpL op1 op2));
8293 effect( DEF xcc, USE op1, USE op2 );
8295 size(4);
8296 format %{ "CMP $op1,$op2\t\t! long" %}
8297 opcode(Assembler::subcc_op3, Assembler::arith_op);
8298 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8299 ins_pipe(ialu_cconly_reg_reg);
8300 %}
8302 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8303 match(Set xcc (CmpL op1 con));
8304 effect( DEF xcc, USE op1, USE con );
8306 size(4);
8307 format %{ "CMP $op1,$con\t\t! long" %}
8308 opcode(Assembler::subcc_op3, Assembler::arith_op);
8309 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8310 ins_pipe(ialu_cconly_reg_reg);
8311 %}
8313 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8314 match(Set xcc (CmpL (AndL op1 op2) zero));
8315 effect( DEF xcc, USE op1, USE op2 );
8317 size(4);
8318 format %{ "BTST $op1,$op2\t\t! long" %}
8319 opcode(Assembler::andcc_op3, Assembler::arith_op);
8320 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8321 ins_pipe(ialu_cconly_reg_reg);
8322 %}
8324 // useful for checking the alignment of a pointer:
8325 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8326 match(Set xcc (CmpL (AndL op1 con) zero));
8327 effect( DEF xcc, USE op1, USE con );
8329 size(4);
8330 format %{ "BTST $op1,$con\t\t! long" %}
8331 opcode(Assembler::andcc_op3, Assembler::arith_op);
8332 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8333 ins_pipe(ialu_cconly_reg_reg);
8334 %}
8336 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
8337 match(Set icc (CmpU op1 op2));
8339 size(4);
8340 format %{ "CMP $op1,$op2\t! unsigned" %}
8341 opcode(Assembler::subcc_op3, Assembler::arith_op);
8342 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8343 ins_pipe(ialu_cconly_reg_imm);
8344 %}
8346 // Compare Pointers
8347 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8348 match(Set pcc (CmpP op1 op2));
8350 size(4);
8351 format %{ "CMP $op1,$op2\t! ptr" %}
8352 opcode(Assembler::subcc_op3, Assembler::arith_op);
8353 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8354 ins_pipe(ialu_cconly_reg_reg);
8355 %}
8357 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8358 match(Set pcc (CmpP op1 op2));
8360 size(4);
8361 format %{ "CMP $op1,$op2\t! ptr" %}
8362 opcode(Assembler::subcc_op3, Assembler::arith_op);
8363 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8364 ins_pipe(ialu_cconly_reg_imm);
8365 %}
8367 // Compare Narrow oops
8368 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8369 match(Set icc (CmpN op1 op2));
8371 size(4);
8372 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8373 opcode(Assembler::subcc_op3, Assembler::arith_op);
8374 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8375 ins_pipe(ialu_cconly_reg_reg);
8376 %}
8378 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8379 match(Set icc (CmpN op1 op2));
8381 size(4);
8382 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8383 opcode(Assembler::subcc_op3, Assembler::arith_op);
8384 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8385 ins_pipe(ialu_cconly_reg_imm);
8386 %}
8388 //----------Max and Min--------------------------------------------------------
8389 // Min Instructions
8390 // Conditional move for min
8391 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8392 effect( USE_DEF op2, USE op1, USE icc );
8394 size(4);
8395 format %{ "MOVlt icc,$op1,$op2\t! min" %}
8396 opcode(Assembler::less);
8397 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8398 ins_pipe(ialu_reg_flags);
8399 %}
8401 // Min Register with Register.
8402 instruct minI_eReg(iRegI op1, iRegI op2) %{
8403 match(Set op2 (MinI op1 op2));
8404 ins_cost(DEFAULT_COST*2);
8405 expand %{
8406 flagsReg icc;
8407 compI_iReg(icc,op1,op2);
8408 cmovI_reg_lt(op2,op1,icc);
8409 %}
8410 %}
8412 // Max Instructions
8413 // Conditional move for max
8414 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
8415 effect( USE_DEF op2, USE op1, USE icc );
8416 format %{ "MOVgt icc,$op1,$op2\t! max" %}
8417 opcode(Assembler::greater);
8418 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8419 ins_pipe(ialu_reg_flags);
8420 %}
8422 // Max Register with Register
8423 instruct maxI_eReg(iRegI op1, iRegI op2) %{
8424 match(Set op2 (MaxI op1 op2));
8425 ins_cost(DEFAULT_COST*2);
8426 expand %{
8427 flagsReg icc;
8428 compI_iReg(icc,op1,op2);
8429 cmovI_reg_gt(op2,op1,icc);
8430 %}
8431 %}
8434 //----------Float Compares----------------------------------------------------
8435 // Compare floating, generate condition code
8436 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
8437 match(Set fcc (CmpF src1 src2));
8439 size(4);
8440 format %{ "FCMPs $fcc,$src1,$src2" %}
8441 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
8442 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
8443 ins_pipe(faddF_fcc_reg_reg_zero);
8444 %}
8446 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
8447 match(Set fcc (CmpD src1 src2));
8449 size(4);
8450 format %{ "FCMPd $fcc,$src1,$src2" %}
8451 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
8452 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
8453 ins_pipe(faddD_fcc_reg_reg_zero);
8454 %}
8457 // Compare floating, generate -1,0,1
8458 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
8459 match(Set dst (CmpF3 src1 src2));
8460 effect(KILL fcc0);
8461 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8462 format %{ "fcmpl $dst,$src1,$src2" %}
8463 // Primary = float
8464 opcode( true );
8465 ins_encode( floating_cmp( dst, src1, src2 ) );
8466 ins_pipe( floating_cmp );
8467 %}
8469 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
8470 match(Set dst (CmpD3 src1 src2));
8471 effect(KILL fcc0);
8472 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8473 format %{ "dcmpl $dst,$src1,$src2" %}
8474 // Primary = double (not float)
8475 opcode( false );
8476 ins_encode( floating_cmp( dst, src1, src2 ) );
8477 ins_pipe( floating_cmp );
8478 %}
8480 //----------Branches---------------------------------------------------------
8481 // Jump
8482 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
8483 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
8484 match(Jump switch_val);
8486 ins_cost(350);
8488 format %{ "SETHI [hi(table_base)],O7\n\t"
8489 "ADD O7, lo(table_base), O7\n\t"
8490 "LD [O7+$switch_val], O7\n\t"
8491 "JUMP O7"
8492 %}
8493 ins_encode( jump_enc( switch_val, table) );
8494 ins_pc_relative(1);
8495 ins_pipe(ialu_reg_reg);
8496 %}
8498 // Direct Branch. Use V8 version with longer range.
8499 instruct branch(label labl) %{
8500 match(Goto);
8501 effect(USE labl);
8503 size(8);
8504 ins_cost(BRANCH_COST);
8505 format %{ "BA $labl" %}
8506 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond
8507 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always);
8508 ins_encode( enc_ba( labl ) );
8509 ins_pc_relative(1);
8510 ins_pipe(br);
8511 %}
8513 // Conditional Direct Branch
8514 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
8515 match(If cmp icc);
8516 effect(USE labl);
8518 size(8);
8519 ins_cost(BRANCH_COST);
8520 format %{ "BP$cmp $icc,$labl" %}
8521 // Prim = bits 24-22, Secnd = bits 31-30
8522 ins_encode( enc_bp( labl, cmp, icc ) );
8523 ins_pc_relative(1);
8524 ins_pipe(br_cc);
8525 %}
8527 // Branch-on-register tests all 64 bits. We assume that values
8528 // in 64-bit registers always remains zero or sign extended
8529 // unless our code munges the high bits. Interrupts can chop
8530 // the high order bits to zero or sign at any time.
8531 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
8532 match(If cmp (CmpI op1 zero));
8533 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
8534 effect(USE labl);
8536 size(8);
8537 ins_cost(BRANCH_COST);
8538 format %{ "BR$cmp $op1,$labl" %}
8539 ins_encode( enc_bpr( labl, cmp, op1 ) );
8540 ins_pc_relative(1);
8541 ins_pipe(br_reg);
8542 %}
8544 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
8545 match(If cmp (CmpP op1 null));
8546 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
8547 effect(USE labl);
8549 size(8);
8550 ins_cost(BRANCH_COST);
8551 format %{ "BR$cmp $op1,$labl" %}
8552 ins_encode( enc_bpr( labl, cmp, op1 ) );
8553 ins_pc_relative(1);
8554 ins_pipe(br_reg);
8555 %}
8557 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
8558 match(If cmp (CmpL op1 zero));
8559 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
8560 effect(USE labl);
8562 size(8);
8563 ins_cost(BRANCH_COST);
8564 format %{ "BR$cmp $op1,$labl" %}
8565 ins_encode( enc_bpr( labl, cmp, op1 ) );
8566 ins_pc_relative(1);
8567 ins_pipe(br_reg);
8568 %}
8570 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
8571 match(If cmp icc);
8572 effect(USE labl);
8574 format %{ "BP$cmp $icc,$labl" %}
8575 // Prim = bits 24-22, Secnd = bits 31-30
8576 ins_encode( enc_bp( labl, cmp, icc ) );
8577 ins_pc_relative(1);
8578 ins_pipe(br_cc);
8579 %}
8581 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
8582 match(If cmp pcc);
8583 effect(USE labl);
8585 size(8);
8586 ins_cost(BRANCH_COST);
8587 format %{ "BP$cmp $pcc,$labl" %}
8588 // Prim = bits 24-22, Secnd = bits 31-30
8589 ins_encode( enc_bpx( labl, cmp, pcc ) );
8590 ins_pc_relative(1);
8591 ins_pipe(br_cc);
8592 %}
8594 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
8595 match(If cmp fcc);
8596 effect(USE labl);
8598 size(8);
8599 ins_cost(BRANCH_COST);
8600 format %{ "FBP$cmp $fcc,$labl" %}
8601 // Prim = bits 24-22, Secnd = bits 31-30
8602 ins_encode( enc_fbp( labl, cmp, fcc ) );
8603 ins_pc_relative(1);
8604 ins_pipe(br_fcc);
8605 %}
8607 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
8608 match(CountedLoopEnd cmp icc);
8609 effect(USE labl);
8611 size(8);
8612 ins_cost(BRANCH_COST);
8613 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
8614 // Prim = bits 24-22, Secnd = bits 31-30
8615 ins_encode( enc_bp( labl, cmp, icc ) );
8616 ins_pc_relative(1);
8617 ins_pipe(br_cc);
8618 %}
8620 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
8621 match(CountedLoopEnd cmp icc);
8622 effect(USE labl);
8624 size(8);
8625 ins_cost(BRANCH_COST);
8626 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
8627 // Prim = bits 24-22, Secnd = bits 31-30
8628 ins_encode( enc_bp( labl, cmp, icc ) );
8629 ins_pc_relative(1);
8630 ins_pipe(br_cc);
8631 %}
8633 // ============================================================================
8634 // Long Compare
8635 //
8636 // Currently we hold longs in 2 registers. Comparing such values efficiently
8637 // is tricky. The flavor of compare used depends on whether we are testing
8638 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
8639 // The GE test is the negated LT test. The LE test can be had by commuting
8640 // the operands (yielding a GE test) and then negating; negate again for the
8641 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
8642 // NE test is negated from that.
8644 // Due to a shortcoming in the ADLC, it mixes up expressions like:
8645 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
8646 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
8647 // are collapsed internally in the ADLC's dfa-gen code. The match for
8648 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
8649 // foo match ends up with the wrong leaf. One fix is to not match both
8650 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
8651 // both forms beat the trinary form of long-compare and both are very useful
8652 // on Intel which has so few registers.
8654 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
8655 match(If cmp xcc);
8656 effect(USE labl);
8658 size(8);
8659 ins_cost(BRANCH_COST);
8660 format %{ "BP$cmp $xcc,$labl" %}
8661 // Prim = bits 24-22, Secnd = bits 31-30
8662 ins_encode( enc_bpl( labl, cmp, xcc ) );
8663 ins_pc_relative(1);
8664 ins_pipe(br_cc);
8665 %}
8667 // Manifest a CmpL3 result in an integer register. Very painful.
8668 // This is the test to avoid.
8669 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
8670 match(Set dst (CmpL3 src1 src2) );
8671 effect( KILL ccr );
8672 ins_cost(6*DEFAULT_COST);
8673 size(24);
8674 format %{ "CMP $src1,$src2\t\t! long\n"
8675 "\tBLT,a,pn done\n"
8676 "\tMOV -1,$dst\t! delay slot\n"
8677 "\tBGT,a,pn done\n"
8678 "\tMOV 1,$dst\t! delay slot\n"
8679 "\tCLR $dst\n"
8680 "done:" %}
8681 ins_encode( cmpl_flag(src1,src2,dst) );
8682 ins_pipe(cmpL_reg);
8683 %}
8685 // Conditional move
8686 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
8687 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
8688 ins_cost(150);
8689 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
8690 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
8691 ins_pipe(ialu_reg);
8692 %}
8694 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
8695 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
8696 ins_cost(140);
8697 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
8698 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
8699 ins_pipe(ialu_imm);
8700 %}
8702 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
8703 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
8704 ins_cost(150);
8705 format %{ "MOV$cmp $xcc,$src,$dst" %}
8706 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
8707 ins_pipe(ialu_reg);
8708 %}
8710 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
8711 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
8712 ins_cost(140);
8713 format %{ "MOV$cmp $xcc,$src,$dst" %}
8714 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
8715 ins_pipe(ialu_imm);
8716 %}
8718 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
8719 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
8720 ins_cost(150);
8721 format %{ "MOV$cmp $xcc,$src,$dst" %}
8722 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
8723 ins_pipe(ialu_reg);
8724 %}
8726 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
8727 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
8728 ins_cost(150);
8729 format %{ "MOV$cmp $xcc,$src,$dst" %}
8730 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
8731 ins_pipe(ialu_reg);
8732 %}
8734 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
8735 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
8736 ins_cost(140);
8737 format %{ "MOV$cmp $xcc,$src,$dst" %}
8738 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
8739 ins_pipe(ialu_imm);
8740 %}
8742 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
8743 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
8744 ins_cost(150);
8745 opcode(0x101);
8746 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
8747 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
8748 ins_pipe(int_conditional_float_move);
8749 %}
8751 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
8752 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
8753 ins_cost(150);
8754 opcode(0x102);
8755 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
8756 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
8757 ins_pipe(int_conditional_float_move);
8758 %}
8760 // ============================================================================
8761 // Safepoint Instruction
8762 instruct safePoint_poll(iRegP poll) %{
8763 match(SafePoint poll);
8764 effect(USE poll);
8766 size(4);
8767 #ifdef _LP64
8768 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
8769 #else
8770 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
8771 #endif
8772 ins_encode %{
8773 __ relocate(relocInfo::poll_type);
8774 __ ld_ptr($poll$$Register, 0, G0);
8775 %}
8776 ins_pipe(loadPollP);
8777 %}
8779 // ============================================================================
8780 // Call Instructions
8781 // Call Java Static Instruction
8782 instruct CallStaticJavaDirect( method meth ) %{
8783 match(CallStaticJava);
8784 effect(USE meth);
8786 size(8);
8787 ins_cost(CALL_COST);
8788 format %{ "CALL,static ; NOP ==> " %}
8789 ins_encode( Java_Static_Call( meth ), call_epilog );
8790 ins_pc_relative(1);
8791 ins_pipe(simple_call);
8792 %}
8794 // Call Java Dynamic Instruction
8795 instruct CallDynamicJavaDirect( method meth ) %{
8796 match(CallDynamicJava);
8797 effect(USE meth);
8799 ins_cost(CALL_COST);
8800 format %{ "SET (empty),R_G5\n\t"
8801 "CALL,dynamic ; NOP ==> " %}
8802 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
8803 ins_pc_relative(1);
8804 ins_pipe(call);
8805 %}
8807 // Call Runtime Instruction
8808 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
8809 match(CallRuntime);
8810 effect(USE meth, KILL l7);
8811 ins_cost(CALL_COST);
8812 format %{ "CALL,runtime" %}
8813 ins_encode( Java_To_Runtime( meth ),
8814 call_epilog, adjust_long_from_native_call );
8815 ins_pc_relative(1);
8816 ins_pipe(simple_call);
8817 %}
8819 // Call runtime without safepoint - same as CallRuntime
8820 instruct CallLeafDirect(method meth, l7RegP l7) %{
8821 match(CallLeaf);
8822 effect(USE meth, KILL l7);
8823 ins_cost(CALL_COST);
8824 format %{ "CALL,runtime leaf" %}
8825 ins_encode( Java_To_Runtime( meth ),
8826 call_epilog,
8827 adjust_long_from_native_call );
8828 ins_pc_relative(1);
8829 ins_pipe(simple_call);
8830 %}
8832 // Call runtime without safepoint - same as CallLeaf
8833 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
8834 match(CallLeafNoFP);
8835 effect(USE meth, KILL l7);
8836 ins_cost(CALL_COST);
8837 format %{ "CALL,runtime leaf nofp" %}
8838 ins_encode( Java_To_Runtime( meth ),
8839 call_epilog,
8840 adjust_long_from_native_call );
8841 ins_pc_relative(1);
8842 ins_pipe(simple_call);
8843 %}
8845 // Tail Call; Jump from runtime stub to Java code.
8846 // Also known as an 'interprocedural jump'.
8847 // Target of jump will eventually return to caller.
8848 // TailJump below removes the return address.
8849 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
8850 match(TailCall jump_target method_oop );
8852 ins_cost(CALL_COST);
8853 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
8854 ins_encode(form_jmpl(jump_target));
8855 ins_pipe(tail_call);
8856 %}
8859 // Return Instruction
8860 instruct Ret() %{
8861 match(Return);
8863 // The epilogue node did the ret already.
8864 size(0);
8865 format %{ "! return" %}
8866 ins_encode();
8867 ins_pipe(empty);
8868 %}
8871 // Tail Jump; remove the return address; jump to target.
8872 // TailCall above leaves the return address around.
8873 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
8874 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
8875 // "restore" before this instruction (in Epilogue), we need to materialize it
8876 // in %i0.
8877 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
8878 match( TailJump jump_target ex_oop );
8879 ins_cost(CALL_COST);
8880 format %{ "! discard R_O7\n\t"
8881 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
8882 ins_encode(form_jmpl_set_exception_pc(jump_target));
8883 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
8884 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
8885 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
8886 ins_pipe(tail_call);
8887 %}
8889 // Create exception oop: created by stack-crawling runtime code.
8890 // Created exception is now available to this handler, and is setup
8891 // just prior to jumping to this handler. No code emitted.
8892 instruct CreateException( o0RegP ex_oop )
8893 %{
8894 match(Set ex_oop (CreateEx));
8895 ins_cost(0);
8897 size(0);
8898 // use the following format syntax
8899 format %{ "! exception oop is in R_O0; no code emitted" %}
8900 ins_encode();
8901 ins_pipe(empty);
8902 %}
8905 // Rethrow exception:
8906 // The exception oop will come in the first argument position.
8907 // Then JUMP (not call) to the rethrow stub code.
8908 instruct RethrowException()
8909 %{
8910 match(Rethrow);
8911 ins_cost(CALL_COST);
8913 // use the following format syntax
8914 format %{ "Jmp rethrow_stub" %}
8915 ins_encode(enc_rethrow);
8916 ins_pipe(tail_call);
8917 %}
8920 // Die now
8921 instruct ShouldNotReachHere( )
8922 %{
8923 match(Halt);
8924 ins_cost(CALL_COST);
8926 size(4);
8927 // Use the following format syntax
8928 format %{ "ILLTRAP ; ShouldNotReachHere" %}
8929 ins_encode( form2_illtrap() );
8930 ins_pipe(tail_call);
8931 %}
8933 // ============================================================================
8934 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
8935 // array for an instance of the superklass. Set a hidden internal cache on a
8936 // hit (cache is checked with exposed code in gen_subtype_check()). Return
8937 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
8938 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
8939 match(Set index (PartialSubtypeCheck sub super));
8940 effect( KILL pcc, KILL o7 );
8941 ins_cost(DEFAULT_COST*10);
8942 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
8943 ins_encode( enc_PartialSubtypeCheck() );
8944 ins_pipe(partial_subtype_check_pipe);
8945 %}
8947 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
8948 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
8949 effect( KILL idx, KILL o7 );
8950 ins_cost(DEFAULT_COST*10);
8951 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
8952 ins_encode( enc_PartialSubtypeCheck() );
8953 ins_pipe(partial_subtype_check_pipe);
8954 %}
8957 // ============================================================================
8958 // inlined locking and unlocking
8960 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
8961 match(Set pcc (FastLock object box));
8963 effect(KILL scratch, TEMP scratch2);
8964 ins_cost(100);
8966 size(4*112); // conservative overestimation ...
8967 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
8968 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
8969 ins_pipe(long_memory_op);
8970 %}
8973 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
8974 match(Set pcc (FastUnlock object box));
8975 effect(KILL scratch, TEMP scratch2);
8976 ins_cost(100);
8978 size(4*120); // conservative overestimation ...
8979 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
8980 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
8981 ins_pipe(long_memory_op);
8982 %}
8984 // Count and Base registers are fixed because the allocator cannot
8985 // kill unknown registers. The encodings are generic.
8986 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
8987 match(Set dummy (ClearArray cnt base));
8988 effect(TEMP temp, KILL ccr);
8989 ins_cost(300);
8990 format %{ "MOV $cnt,$temp\n"
8991 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
8992 " BRge loop\t\t! Clearing loop\n"
8993 " STX G0,[$base+$temp]\t! delay slot" %}
8994 ins_encode( enc_Clear_Array(cnt, base, temp) );
8995 ins_pipe(long_memory_op);
8996 %}
8998 instruct string_compare(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result,
8999 o7RegI tmp3, flagsReg ccr) %{
9000 match(Set result (StrComp str1 str2));
9001 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL ccr, KILL tmp3);
9002 ins_cost(300);
9003 format %{ "String Compare $str1,$str2 -> $result" %}
9004 ins_encode( enc_String_Compare(str1, str2, tmp1, tmp2, result) );
9005 ins_pipe(long_memory_op);
9006 %}
9008 // ============================================================================
9009 //------------Bytes reverse--------------------------------------------------
9011 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
9012 match(Set dst (ReverseBytesI src));
9013 effect(DEF dst, USE src);
9015 // Op cost is artificially doubled to make sure that load or store
9016 // instructions are preferred over this one which requires a spill
9017 // onto a stack slot.
9018 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9019 size(8);
9020 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
9021 opcode(Assembler::lduwa_op3);
9022 ins_encode( form3_mem_reg_little(src, dst) );
9023 ins_pipe( iload_mem );
9024 %}
9026 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
9027 match(Set dst (ReverseBytesL src));
9028 effect(DEF dst, USE src);
9030 // Op cost is artificially doubled to make sure that load or store
9031 // instructions are preferred over this one which requires a spill
9032 // onto a stack slot.
9033 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9034 size(8);
9035 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
9037 opcode(Assembler::ldxa_op3);
9038 ins_encode( form3_mem_reg_little(src, dst) );
9039 ins_pipe( iload_mem );
9040 %}
9042 // Load Integer reversed byte order
9043 instruct loadI_reversed(iRegI dst, memory src) %{
9044 match(Set dst (ReverseBytesI (LoadI src)));
9046 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
9047 size(8);
9048 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
9050 opcode(Assembler::lduwa_op3);
9051 ins_encode( form3_mem_reg_little( src, dst) );
9052 ins_pipe(iload_mem);
9053 %}
9055 // Load Long - aligned and reversed
9056 instruct loadL_reversed(iRegL dst, memory src) %{
9057 match(Set dst (ReverseBytesL (LoadL src)));
9059 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
9060 size(8);
9061 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
9063 opcode(Assembler::ldxa_op3);
9064 ins_encode( form3_mem_reg_little( src, dst ) );
9065 ins_pipe(iload_mem);
9066 %}
9068 // Store Integer reversed byte order
9069 instruct storeI_reversed(memory dst, iRegI src) %{
9070 match(Set dst (StoreI dst (ReverseBytesI src)));
9072 ins_cost(MEMORY_REF_COST);
9073 size(8);
9074 format %{ "STWA $src, $dst\t!asi=primary_little" %}
9076 opcode(Assembler::stwa_op3);
9077 ins_encode( form3_mem_reg_little( dst, src) );
9078 ins_pipe(istore_mem_reg);
9079 %}
9081 // Store Long reversed byte order
9082 instruct storeL_reversed(memory dst, iRegL src) %{
9083 match(Set dst (StoreL dst (ReverseBytesL src)));
9085 ins_cost(MEMORY_REF_COST);
9086 size(8);
9087 format %{ "STXA $src, $dst\t!asi=primary_little" %}
9089 opcode(Assembler::stxa_op3);
9090 ins_encode( form3_mem_reg_little( dst, src) );
9091 ins_pipe(istore_mem_reg);
9092 %}
9094 //----------PEEPHOLE RULES-----------------------------------------------------
9095 // These must follow all instruction definitions as they use the names
9096 // defined in the instructions definitions.
9097 //
9098 // peepmatch ( root_instr_name [preceding_instruction]* );
9099 //
9100 // peepconstraint %{
9101 // (instruction_number.operand_name relational_op instruction_number.operand_name
9102 // [, ...] );
9103 // // instruction numbers are zero-based using left to right order in peepmatch
9104 //
9105 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
9106 // // provide an instruction_number.operand_name for each operand that appears
9107 // // in the replacement instruction's match rule
9108 //
9109 // ---------VM FLAGS---------------------------------------------------------
9110 //
9111 // All peephole optimizations can be turned off using -XX:-OptoPeephole
9112 //
9113 // Each peephole rule is given an identifying number starting with zero and
9114 // increasing by one in the order seen by the parser. An individual peephole
9115 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
9116 // on the command-line.
9117 //
9118 // ---------CURRENT LIMITATIONS----------------------------------------------
9119 //
9120 // Only match adjacent instructions in same basic block
9121 // Only equality constraints
9122 // Only constraints between operands, not (0.dest_reg == EAX_enc)
9123 // Only one replacement instruction
9124 //
9125 // ---------EXAMPLE----------------------------------------------------------
9126 //
9127 // // pertinent parts of existing instructions in architecture description
9128 // instruct movI(eRegI dst, eRegI src) %{
9129 // match(Set dst (CopyI src));
9130 // %}
9131 //
9132 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
9133 // match(Set dst (AddI dst src));
9134 // effect(KILL cr);
9135 // %}
9136 //
9137 // // Change (inc mov) to lea
9138 // peephole %{
9139 // // increment preceeded by register-register move
9140 // peepmatch ( incI_eReg movI );
9141 // // require that the destination register of the increment
9142 // // match the destination register of the move
9143 // peepconstraint ( 0.dst == 1.dst );
9144 // // construct a replacement instruction that sets
9145 // // the destination to ( move's source register + one )
9146 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
9147 // %}
9148 //
9150 // // Change load of spilled value to only a spill
9151 // instruct storeI(memory mem, eRegI src) %{
9152 // match(Set mem (StoreI mem src));
9153 // %}
9154 //
9155 // instruct loadI(eRegI dst, memory mem) %{
9156 // match(Set dst (LoadI mem));
9157 // %}
9158 //
9159 // peephole %{
9160 // peepmatch ( loadI storeI );
9161 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
9162 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
9163 // %}
9165 //----------SMARTSPILL RULES---------------------------------------------------
9166 // These must follow all instruction definitions as they use the names
9167 // defined in the instructions definitions.
9168 //
9169 // SPARC will probably not have any of these rules due to RISC instruction set.
9171 //----------PIPELINE-----------------------------------------------------------
9172 // Rules which define the behavior of the target architectures pipeline.