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 //

 // Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved.

 // Copyright (c) 2012, 2017 SAP SE. All rights reserved.

 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 //

 // This code is free software; you can redistribute it and/or modify it

 // under the terms of the GNU General Public License version 2 only, as

 // published by the Free Software Foundation.

 //

 // This code is distributed in the hope that it will be useful, but WITHOUT

 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 // version 2 for more details (a copy is included in the LICENSE file that

 // accompanied this code).

 //

 // You should have received a copy of the GNU General Public License version

 // 2 along with this work; if not, write to the Free Software Foundation,

 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 //

 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 // or visit www.oracle.com if you need additional information or have any

 // questions.

 //

 //

 //

 // PPC64 Architecture Description File

 //

 //----------REGISTER DEFINITION BLOCK------------------------------------------

 // This information is used by the matcher and the register allocator to

 // describe individual registers and classes of registers within the target

 // architecture.

 register %{

 //----------Architecture Description Register Definitions----------------------

 // General Registers

 // "reg_def"  name (register save type, C convention save type,

 //                  ideal register type, encoding);

 //

 // Register Save Types:

 //

 //   NS  = No-Save:     The register allocator assumes that these registers

 //                      can be used without saving upon entry to the method, &

 //                      that they do not need to be saved at call sites.

 //

 //   SOC = Save-On-Call: The register allocator assumes that these registers

 //                      can be used without saving upon entry to the method,

 //                      but that they must be saved at call sites.

 //                      These are called "volatiles" on ppc.

 //

 //   SOE = Save-On-Entry: The register allocator assumes that these registers

 //                      must be saved before using them upon entry to the

 //                      method, but they do not need to be saved at call

 //                      sites.

 //                      These are called "nonvolatiles" on ppc.

 //

 //   AS  = Always-Save:   The register allocator assumes that these registers

 //                      must be saved before using them upon entry to the

 //                      method, & that they must be saved at call sites.

 //

 // Ideal Register Type is used to determine how to save & restore a

 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get

 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.

 //

 // The encoding number is the actual bit-pattern placed into the opcodes.

 //

 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI

 // Supplement Version 1.7 as of 2003-10-29.

 //

 // For each 64-bit register we must define two registers: the register

 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half',

 // e.g. R3_H, which is needed by the allocator, but is not used

 // for stores, loads, etc.

 // ----------------------------

 // Integer/Long Registers

 // ----------------------------

   // PPC64 has 32 64-bit integer registers.

   // types: v = volatile, nv = non-volatile, s = system

   reg_def R0   ( SOC, SOC, Op_RegI,  0, R0->as_VMReg()         );  // v   used in prologs

   reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() );

   reg_def R1   ( NS,  NS,  Op_RegI,  1, R1->as_VMReg()         );  // s   SP

   reg_def R1_H ( NS,  NS,  Op_RegI, 99, R1->as_VMReg()->next() );

   reg_def R2   ( SOC, SOC, Op_RegI,  2, R2->as_VMReg()         );  // v   TOC

   reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() );

   reg_def R3   ( SOC, SOC, Op_RegI,  3, R3->as_VMReg()         );  // v   iarg1 & iret

   reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() );

   reg_def R4   ( SOC, SOC, Op_RegI,  4, R4->as_VMReg()         );  //     iarg2

   reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() );

   reg_def R5   ( SOC, SOC, Op_RegI,  5, R5->as_VMReg()         );  // v   iarg3

   reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() );

   reg_def R6   ( SOC, SOC, Op_RegI,  6, R6->as_VMReg()         );  // v   iarg4

   reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() );

   reg_def R7   ( SOC, SOC, Op_RegI,  7, R7->as_VMReg()         );  // v   iarg5

   reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() );

   reg_def R8   ( SOC, SOC, Op_RegI,  8, R8->as_VMReg()         );  // v   iarg6

   reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() );

   reg_def R9   ( SOC, SOC, Op_RegI,  9, R9->as_VMReg()         );  // v   iarg7

   reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() );

   reg_def R10  ( SOC, SOC, Op_RegI, 10, R10->as_VMReg()        );  // v   iarg8

   reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next());

   reg_def R11  ( SOC, SOC, Op_RegI, 11, R11->as_VMReg()        );  // v   ENV / scratch

   reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next());

   reg_def R12  ( SOC, SOC, Op_RegI, 12, R12->as_VMReg()        );  // v   scratch

   reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next());

   reg_def R13  ( NS,  NS,  Op_RegI, 13, R13->as_VMReg()        );  // s   system thread id

   reg_def R13_H( NS,  NS,  Op_RegI, 99, R13->as_VMReg()->next());

   reg_def R14  ( SOC, SOE, Op_RegI, 14, R14->as_VMReg()        );  // nv

   reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next());

   reg_def R15  ( SOC, SOE, Op_RegI, 15, R15->as_VMReg()        );  // nv

   reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next());

   reg_def R16  ( SOC, SOE, Op_RegI, 16, R16->as_VMReg()        );  // nv

   reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next());

   reg_def R17  ( SOC, SOE, Op_RegI, 17, R17->as_VMReg()        );  // nv

   reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next());

   reg_def R18  ( SOC, SOE, Op_RegI, 18, R18->as_VMReg()        );  // nv

   reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next());

   reg_def R19  ( SOC, SOE, Op_RegI, 19, R19->as_VMReg()        );  // nv

   reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next());

   reg_def R20  ( SOC, SOE, Op_RegI, 20, R20->as_VMReg()        );  // nv

   reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next());

   reg_def R21  ( SOC, SOE, Op_RegI, 21, R21->as_VMReg()        );  // nv

   reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next());

   reg_def R22  ( SOC, SOE, Op_RegI, 22, R22->as_VMReg()        );  // nv

   reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next());

   reg_def R23  ( SOC, SOE, Op_RegI, 23, R23->as_VMReg()        );  // nv

   reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next());

   reg_def R24  ( SOC, SOE, Op_RegI, 24, R24->as_VMReg()        );  // nv

   reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next());

   reg_def R25  ( SOC, SOE, Op_RegI, 25, R25->as_VMReg()        );  // nv

   reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next());

   reg_def R26  ( SOC, SOE, Op_RegI, 26, R26->as_VMReg()        );  // nv

   reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next());

   reg_def R27  ( SOC, SOE, Op_RegI, 27, R27->as_VMReg()        );  // nv

   reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next());

   reg_def R28  ( SOC, SOE, Op_RegI, 28, R28->as_VMReg()        );  // nv

   reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next());

   reg_def R29  ( SOC, SOE, Op_RegI, 29, R29->as_VMReg()        );  // nv

   reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next());

   reg_def R30  ( SOC, SOE, Op_RegI, 30, R30->as_VMReg()        );  // nv

   reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next());

   reg_def R31  ( SOC, SOE, Op_RegI, 31, R31->as_VMReg()        );  // nv

   reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next());

 // ----------------------------

 // Float/Double Registers

 // ----------------------------

   // Double Registers

   // The rules of ADL require that double registers be defined in pairs.

   // Each pair must be two 32-bit values, but not necessarily a pair of

   // single float registers. In each pair, ADLC-assigned register numbers

   // must be adjacent, with the lower number even. Finally, when the

   // CPU stores such a register pair to memory, the word associated with

   // the lower ADLC-assigned number must be stored to the lower address.

   // PPC64 has 32 64-bit floating-point registers. Each can store a single

   // or double precision floating-point value.

   // types: v = volatile, nv = non-volatile, s = system

   reg_def F0   ( SOC, SOC, Op_RegF,  0, F0->as_VMReg()         );  // v   scratch

   reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() );

   reg_def F1   ( SOC, SOC, Op_RegF,  1, F1->as_VMReg()         );  // v   farg1 & fret

   reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() );

   reg_def F2   ( SOC, SOC, Op_RegF,  2, F2->as_VMReg()         );  // v   farg2

   reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() );

   reg_def F3   ( SOC, SOC, Op_RegF,  3, F3->as_VMReg()         );  // v   farg3

   reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() );

   reg_def F4   ( SOC, SOC, Op_RegF,  4, F4->as_VMReg()         );  // v   farg4

   reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() );

   reg_def F5   ( SOC, SOC, Op_RegF,  5, F5->as_VMReg()         );  // v   farg5

   reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() );

   reg_def F6   ( SOC, SOC, Op_RegF,  6, F6->as_VMReg()         );  // v   farg6

   reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() );

   reg_def F7   ( SOC, SOC, Op_RegF,  7, F7->as_VMReg()         );  // v   farg7

   reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() );

   reg_def F8   ( SOC, SOC, Op_RegF,  8, F8->as_VMReg()         );  // v   farg8

   reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() );

   reg_def F9   ( SOC, SOC, Op_RegF,  9, F9->as_VMReg()         );  // v   farg9

   reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() );

   reg_def F10  ( SOC, SOC, Op_RegF, 10, F10->as_VMReg()        );  // v   farg10

   reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next());

   reg_def F11  ( SOC, SOC, Op_RegF, 11, F11->as_VMReg()        );  // v   farg11

   reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next());

   reg_def F12  ( SOC, SOC, Op_RegF, 12, F12->as_VMReg()        );  // v   farg12

   reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next());

   reg_def F13  ( SOC, SOC, Op_RegF, 13, F13->as_VMReg()        );  // v   farg13

   reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next());

   reg_def F14  ( SOC, SOE, Op_RegF, 14, F14->as_VMReg()        );  // nv

   reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next());

   reg_def F15  ( SOC, SOE, Op_RegF, 15, F15->as_VMReg()        );  // nv

   reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next());

   reg_def F16  ( SOC, SOE, Op_RegF, 16, F16->as_VMReg()        );  // nv

   reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next());

   reg_def F17  ( SOC, SOE, Op_RegF, 17, F17->as_VMReg()        );  // nv

   reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next());

   reg_def F18  ( SOC, SOE, Op_RegF, 18, F18->as_VMReg()        );  // nv

   reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next());

   reg_def F19  ( SOC, SOE, Op_RegF, 19, F19->as_VMReg()        );  // nv

   reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next());

   reg_def F20  ( SOC, SOE, Op_RegF, 20, F20->as_VMReg()        );  // nv

   reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next());

   reg_def F21  ( SOC, SOE, Op_RegF, 21, F21->as_VMReg()        );  // nv

   reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next());

   reg_def F22  ( SOC, SOE, Op_RegF, 22, F22->as_VMReg()        );  // nv

   reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next());

   reg_def F23  ( SOC, SOE, Op_RegF, 23, F23->as_VMReg()        );  // nv

   reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next());

   reg_def F24  ( SOC, SOE, Op_RegF, 24, F24->as_VMReg()        );  // nv

   reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next());

   reg_def F25  ( SOC, SOE, Op_RegF, 25, F25->as_VMReg()        );  // nv

   reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next());

   reg_def F26  ( SOC, SOE, Op_RegF, 26, F26->as_VMReg()        );  // nv

   reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next());

   reg_def F27  ( SOC, SOE, Op_RegF, 27, F27->as_VMReg()        );  // nv

   reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next());

   reg_def F28  ( SOC, SOE, Op_RegF, 28, F28->as_VMReg()        );  // nv

   reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next());

   reg_def F29  ( SOC, SOE, Op_RegF, 29, F29->as_VMReg()        );  // nv

   reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next());

   reg_def F30  ( SOC, SOE, Op_RegF, 30, F30->as_VMReg()        );  // nv

   reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next());

   reg_def F31  ( SOC, SOE, Op_RegF, 31, F31->as_VMReg()        );  // nv

   reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next());

 // ----------------------------

 // Special Registers

 // ----------------------------

 // Condition Codes Flag Registers

   // PPC64 has 8 condition code "registers" which are all contained

   // in the CR register.

   // types: v = volatile, nv = non-volatile, s = system

   reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg());  // v

   reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg());  // v

   reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg());  // nv

   reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg());  // nv

   reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg());  // nv

   reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg());  // v

   reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg());  // v

   reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg());  // v

   // Special registers of PPC64

   reg_def SR_XER(    SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg());     // v

   reg_def SR_LR(     SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg());      // v

   reg_def SR_CTR(    SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg());     // v

   reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg());  // v

   reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v

   reg_def SR_PPR(    SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg());     // v

 // ----------------------------

 // Specify priority of register selection within phases of register

 // allocation. Highest priority is first. A useful heuristic is to

 // give registers a low priority when they are required by machine

 // instructions, like EAX and EDX on I486, and choose no-save registers

 // before save-on-call, & save-on-call before save-on-entry. Registers

 // which participate in fixed calling sequences should come last.

 // Registers which are used as pairs must fall on an even boundary.

 // It's worth about 1% on SPEC geomean to get this right.

 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration

 // in adGlobals_ppc64.hpp which defines the <register>_num values, e.g.

 // R3_num. Therefore, R3_num may not be (and in reality is not)

 // the same as R3->encoding()! Furthermore, we cannot make any

 // assumptions on ordering, e.g. R3_num may be less than R2_num.

 // Additionally, the function

 //   static enum RC rc_class(OptoReg::Name reg )

 // maps a given <register>_num value to its chunk type (except for flags)

 // and its current implementation relies on chunk0 and chunk1 having a

 // size of 64 each.

 // If you change this allocation class, please have a look at the

 // default values for the parameters RoundRobinIntegerRegIntervalStart

 // and RoundRobinFloatRegIntervalStart

 alloc_class chunk0 (

   // Chunk0 contains *all* 64 integer registers halves.

   // "non-volatile" registers

   R14, R14_H,

   R15, R15_H,

   R17, R17_H,

   R18, R18_H,

   R19, R19_H,

   R20, R20_H,

   R21, R21_H,

   R22, R22_H,

   R23, R23_H,

   R24, R24_H,

   R25, R25_H,

   R26, R26_H,

   R27, R27_H,

   R28, R28_H,

   R29, R29_H,

   R30, R30_H,

   R31, R31_H,

   // scratch/special registers

   R11, R11_H,

   R12, R12_H,

   // argument registers

   R10, R10_H,

   R9,  R9_H,

   R8,  R8_H,

   R7,  R7_H,

   R6,  R6_H,

   R5,  R5_H,

   R4,  R4_H,

   R3,  R3_H,

   // special registers, not available for allocation

   R16, R16_H,     // R16_thread

   R13, R13_H,     // system thread id

   R2,  R2_H,      // may be used for TOC

   R1,  R1_H,      // SP

   R0,  R0_H       // R0 (scratch)

 );

 // If you change this allocation class, please have a look at the

 // default values for the parameters RoundRobinIntegerRegIntervalStart

 // and RoundRobinFloatRegIntervalStart

 alloc_class chunk1 (

   // Chunk1 contains *all* 64 floating-point registers halves.

   // scratch register

   F0,  F0_H,

   // argument registers

   F13, F13_H,

   F12, F12_H,

   F11, F11_H,

   F10, F10_H,

   F9,  F9_H,

   F8,  F8_H,

   F7,  F7_H,

   F6,  F6_H,

   F5,  F5_H,

   F4,  F4_H,

   F3,  F3_H,

   F2,  F2_H,

   F1,  F1_H,

   // non-volatile registers

   F14, F14_H,

   F15, F15_H,

   F16, F16_H,

   F17, F17_H,

   F18, F18_H,

   F19, F19_H,

   F20, F20_H,

   F21, F21_H,

   F22, F22_H,

   F23, F23_H,

   F24, F24_H,

   F25, F25_H,

   F26, F26_H,

   F27, F27_H,

   F28, F28_H,

   F29, F29_H,

   F30, F30_H,

   F31, F31_H

 );

 alloc_class chunk2 (

   // Chunk2 contains *all* 8 condition code registers.

   CCR0,

   CCR1,

   CCR2,

   CCR3,

   CCR4,

   CCR5,

   CCR6,

   CCR7

 );

 alloc_class chunk3 (

   // special registers

   // These registers are not allocated, but used for nodes generated by postalloc expand.

   SR_XER,

   SR_LR,

   SR_CTR,

   SR_VRSAVE,

   SR_SPEFSCR,

   SR_PPR

 );

 //-------Architecture Description Register Classes-----------------------

 // Several register classes are automatically defined based upon

 // information in this architecture description.

 // 1) reg_class inline_cache_reg           ( as defined in frame section )

 // 2) reg_class compiler_method_oop_reg    ( as defined in frame section )

 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )

 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )

 //

 // ----------------------------

 // 32 Bit Register Classes

 // ----------------------------

 // We specify registers twice, once as read/write, and once read-only.

 // We use the read-only registers for source operands. With this, we

 // can include preset read only registers in this class, as a hard-coded

 // '0'-register. (We used to simulate this on ppc.)

 // 32 bit registers that can be read and written i.e. these registers

 // can be dest (or src) of normal instructions.

 reg_class bits32_reg_rw(

 /*R0*/              // R0

 /*R1*/              // SP

   R2,               // TOC

   R3,

   R4,

   R5,

   R6,

   R7,

   R8,

   R9,

   R10,

   R11,

   R12,

 /*R13*/             // system thread id

   R14,

   R15,

 /*R16*/             // R16_thread

   R17,

   R18,

   R19,

   R20,

   R21,

   R22,

   R23,

   R24,

   R25,

   R26,

   R27,

   R28,

 /*R29*/             // global TOC

 /*R30*/             // Narrow Oop Base

   R31

 );

 // 32 bit registers that can only be read i.e. these registers can

 // only be src of all instructions.

 reg_class bits32_reg_ro(

 /*R0*/              // R0

 /*R1*/              // SP

   R2                // TOC

   R3,

   R4,

   R5,

   R6,

   R7,

   R8,

   R9,

   R10,

   R11,

   R12,

 /*R13*/             // system thread id

   R14,

   R15,

 /*R16*/             // R16_thread

   R17,

   R18,

   R19,

   R20,

   R21,

   R22,

   R23,

   R24,

   R25,

   R26,

   R27,

   R28,

 /*R29*/

 /*R30*/             // Narrow Oop Base

   R31

 );

 // Complement-required-in-pipeline operands for narrow oops.

 reg_class bits32_reg_ro_not_complement (

 /*R0*/     // R0

   R1,      // SP

   R2,      // TOC

   R3,

   R4,

   R5,

   R6,

   R7,

   R8,

   R9,

   R10,

   R11,

   R12,

 /*R13,*/   // system thread id

   R14,

   R15,

   R16,    // R16_thread

   R17,

   R18,

   R19,

   R20,

   R21,

   R22,

 /*R23,

   R24,

   R25,

   R26,

   R27,

   R28,*/

 /*R29,*/ // TODO: let allocator handle TOC!!

 /*R30,*/

   R31

 );

 // Complement-required-in-pipeline operands for narrow oops.

 // See 64-bit declaration.

 reg_class bits32_reg_ro_complement (

   R23,

   R24,

   R25,

   R26,

   R27,

   R28

 );

 reg_class rscratch1_bits32_reg(R11);

 reg_class rscratch2_bits32_reg(R12);

 reg_class rarg1_bits32_reg(R3);

 reg_class rarg2_bits32_reg(R4);

 reg_class rarg3_bits32_reg(R5);

 reg_class rarg4_bits32_reg(R6);

 // ----------------------------

 // 64 Bit Register Classes

 // ----------------------------

 // 64-bit build means 64-bit pointers means hi/lo pairs

 reg_class rscratch1_bits64_reg(R11_H, R11);

 reg_class rscratch2_bits64_reg(R12_H, R12);

 reg_class rarg1_bits64_reg(R3_H, R3);

 reg_class rarg2_bits64_reg(R4_H, R4);

 reg_class rarg3_bits64_reg(R5_H, R5);

 reg_class rarg4_bits64_reg(R6_H, R6);

 // Thread register, 'written' by tlsLoadP, see there.

 reg_class thread_bits64_reg(R16_H, R16);

 reg_class r19_bits64_reg(R19_H, R19);

 // 64 bit registers that can be read and written i.e. these registers

 // can be dest (or src) of normal instructions.

 reg_class bits64_reg_rw(

 /*R0_H,  R0*/     // R0

 /*R1_H,  R1*/     // SP

   R2_H,  R2,      // TOC

   R3_H,  R3,

   R4_H,  R4,

   R5_H,  R5,

   R6_H,  R6,

   R7_H,  R7,

   R8_H,  R8,

   R9_H,  R9,

   R10_H, R10,

   R11_H, R11,

   R12_H, R12,

 /*R13_H, R13*/   // system thread id

   R14_H, R14,

   R15_H, R15,

 /*R16_H, R16*/   // R16_thread

   R17_H, R17,

   R18_H, R18,

   R19_H, R19,

   R20_H, R20,

   R21_H, R21,

   R22_H, R22,

   R23_H, R23,

   R24_H, R24,

   R25_H, R25,

   R26_H, R26,

   R27_H, R27,

   R28_H, R28,

 /*R29_H, R29*/

 /*R30_H, R30*/

   R31_H, R31

 );

 // 64 bit registers used excluding r2, r11 and r12

 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses

 // r2, r11 and r12 internally.

 reg_class bits64_reg_leaf_call(

 /*R0_H,  R0*/     // R0

 /*R1_H,  R1*/     // SP

 /*R2_H,  R2*/     // TOC

   R3_H,  R3,

   R4_H,  R4,

   R5_H,  R5,

   R6_H,  R6,

   R7_H,  R7,

   R8_H,  R8,

   R9_H,  R9,

   R10_H, R10,

 /*R11_H, R11*/

 /*R12_H, R12*/

 /*R13_H, R13*/   // system thread id

   R14_H, R14,

   R15_H, R15,

 /*R16_H, R16*/   // R16_thread

   R17_H, R17,

   R18_H, R18,

   R19_H, R19,

   R20_H, R20,

   R21_H, R21,

   R22_H, R22,

   R23_H, R23,

   R24_H, R24,

   R25_H, R25,

   R26_H, R26,

   R27_H, R27,

   R28_H, R28,

 /*R29_H, R29*/

 /*R30_H, R30*/

   R31_H, R31

 );

 // Used to hold the TOC to avoid collisions with expanded DynamicCall

 // which uses r19 as inline cache internally and expanded LeafCall which uses

 // r2, r11 and r12 internally.

 reg_class bits64_constant_table_base(

 /*R0_H,  R0*/     // R0

 /*R1_H,  R1*/     // SP

 /*R2_H,  R2*/     // TOC

   R3_H,  R3,

   R4_H,  R4,

   R5_H,  R5,

   R6_H,  R6,

   R7_H,  R7,

   R8_H,  R8,

   R9_H,  R9,

   R10_H, R10,

 /*R11_H, R11*/

 /*R12_H, R12*/

 /*R13_H, R13*/   // system thread id

   R14_H, R14,

   R15_H, R15,

 /*R16_H, R16*/   // R16_thread

   R17_H, R17,

   R18_H, R18,

 /*R19_H, R19*/

   R20_H, R20,

   R21_H, R21,

   R22_H, R22,

   R23_H, R23,

   R24_H, R24,

   R25_H, R25,

   R26_H, R26,

   R27_H, R27,

   R28_H, R28,

 /*R29_H, R29*/

 /*R30_H, R30*/

   R31_H, R31

 );

 // 64 bit registers that can only be read i.e. these registers can

 // only be src of all instructions.

 reg_class bits64_reg_ro(

 /*R0_H,  R0*/     // R0

   R1_H,  R1,

   R2_H,  R2,       // TOC

   R3_H,  R3,

   R4_H,  R4,

   R5_H,  R5,

   R6_H,  R6,

   R7_H,  R7,

   R8_H,  R8,

   R9_H,  R9,

   R10_H, R10,

   R11_H, R11,

   R12_H, R12,

 /*R13_H, R13*/   // system thread id

   R14_H, R14,

   R15_H, R15,

   R16_H, R16,    // R16_thread

   R17_H, R17,

   R18_H, R18,

   R19_H, R19,

   R20_H, R20,

   R21_H, R21,

   R22_H, R22,

   R23_H, R23,

   R24_H, R24,

   R25_H, R25,

   R26_H, R26,

   R27_H, R27,

   R28_H, R28,

 /*R29_H, R29*/ // TODO: let allocator handle TOC!!

 /*R30_H, R30,*/

   R31_H, R31

 );

 // Complement-required-in-pipeline operands.

 reg_class bits64_reg_ro_not_complement (

 /*R0_H,  R0*/     // R0

   R1_H,  R1,      // SP

   R2_H,  R2,      // TOC

   R3_H,  R3,

   R4_H,  R4,

   R5_H,  R5,

   R6_H,  R6,

   R7_H,  R7,

   R8_H,  R8,

   R9_H,  R9,

   R10_H, R10,

   R11_H, R11,

   R12_H, R12,

 /*R13_H, R13*/   // system thread id

   R14_H, R14,

   R15_H, R15,

   R16_H, R16,    // R16_thread

   R17_H, R17,

   R18_H, R18,

   R19_H, R19,

   R20_H, R20,

   R21_H, R21,

   R22_H, R22,

 /*R23_H, R23,

   R24_H, R24,

   R25_H, R25,

   R26_H, R26,

   R27_H, R27,

   R28_H, R28,*/

 /*R29_H, R29*/ // TODO: let allocator handle TOC!!

 /*R30_H, R30,*/

   R31_H, R31

 );

 // Complement-required-in-pipeline operands.

 // This register mask is used for the trap instructions that implement

 // the null checks on AIX. The trap instruction first computes the

 // complement of the value it shall trap on. Because of this, the

 // instruction can not be scheduled in the same cycle as an other

 // instruction reading the normal value of the same register. So we

 // force the value to check into 'bits64_reg_ro_not_complement'

 // and then copy it to 'bits64_reg_ro_complement' for the trap.

 reg_class bits64_reg_ro_complement (

   R23_H, R23,

   R24_H, R24,

   R25_H, R25,

   R26_H, R26,

   R27_H, R27,

   R28_H, R28

 );

 // ----------------------------

 // Special Class for Condition Code Flags Register

 reg_class int_flags(

 /*CCR0*/             // scratch

 /*CCR1*/             // scratch

 /*CCR2*/             // nv!

 /*CCR3*/             // nv!

 /*CCR4*/             // nv!

   CCR5,

   CCR6,

   CCR7

 );

 reg_class int_flags_CR0(CCR0);

 reg_class int_flags_CR1(CCR1);

 reg_class int_flags_CR6(CCR6);

 reg_class ctr_reg(SR_CTR);

 // ----------------------------

 // Float Register Classes

 // ----------------------------

 reg_class flt_reg(

 /*F0*/              // scratch

   F1,

   F2,

   F3,

   F4,

   F5,

   F6,

   F7,

   F8,

   F9,

   F10,

   F11,

   F12,

   F13,

   F14,              // nv!

   F15,              // nv!

   F16,              // nv!

   F17,              // nv!

   F18,              // nv!

   F19,              // nv!

   F20,              // nv!

   F21,              // nv!

   F22,              // nv!

   F23,              // nv!

   F24,              // nv!

   F25,              // nv!

   F26,              // nv!

   F27,              // nv!

   F28,              // nv!

   F29,              // nv!

   F30,              // nv!

   F31               // nv!

 );

 // Double precision float registers have virtual `high halves' that

 // are needed by the allocator.

 reg_class dbl_reg(

 /*F0,  F0_H*/     // scratch

   F1,  F1_H,

   F2,  F2_H,

   F3,  F3_H,

   F4,  F4_H,

   F5,  F5_H,

   F6,  F6_H,

   F7,  F7_H,

   F8,  F8_H,

   F9,  F9_H,

   F10, F10_H,

   F11, F11_H,

   F12, F12_H,

   F13, F13_H,

   F14, F14_H,    // nv!

   F15, F15_H,    // nv!

   F16, F16_H,    // nv!

   F17, F17_H,    // nv!

   F18, F18_H,    // nv!

   F19, F19_H,    // nv!

   F20, F20_H,    // nv!

   F21, F21_H,    // nv!

   F22, F22_H,    // nv!

   F23, F23_H,    // nv!

   F24, F24_H,    // nv!

   F25, F25_H,    // nv!

   F26, F26_H,    // nv!

   F27, F27_H,    // nv!

   F28, F28_H,    // nv!

   F29, F29_H,    // nv!

   F30, F30_H,    // nv!

   F31, F31_H     // nv!

 );

  %}

 //----------DEFINITION BLOCK---------------------------------------------------

 // Define name --> value mappings to inform the ADLC of an integer valued name

 // Current support includes integer values in the range [0, 0x7FFFFFFF]

 // Format:

 //        int_def  <name>         ( <int_value>, <expression>);

 // Generated Code in ad_<arch>.hpp

 //        #define  <name>   (<expression>)

 //        // value == <int_value>

 // Generated code in ad_<arch>.cpp adlc_verification()

 //        assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");

 //

 definitions %{

   // The default cost (of an ALU instruction).

   int_def DEFAULT_COST_LOW        (     30,      30);

   int_def DEFAULT_COST            (    100,     100);

   int_def HUGE_COST               (1000000, 1000000);

   // Memory refs

   int_def MEMORY_REF_COST_LOW     (    200, DEFAULT_COST * 2);

   int_def MEMORY_REF_COST         (    300, DEFAULT_COST * 3);

   // Branches are even more expensive.

   int_def BRANCH_COST             (    900, DEFAULT_COST * 9);

   int_def CALL_COST               (   1300, DEFAULT_COST * 13);

 %}

 //----------SOURCE BLOCK-------------------------------------------------------

 // This is a block of C++ code which provides values, functions, and

 // definitions necessary in the rest of the architecture description.

 source_hpp %{

   // Header information of the source block.

   // Method declarations/definitions which are used outside

   // the ad-scope can conveniently be defined here.

   //

   // To keep related declarations/definitions/uses close together,

   // we switch between source %{ }% and source_hpp %{ }% freely as needed.

   // Returns true if Node n is followed by a MemBar node that

   // will do an acquire. If so, this node must not do the acquire

   // operation.

   bool followed_by_acquire(const Node *n);

 %}

 source %{

 // Optimize load-acquire.

 //

 // Check if acquire is unnecessary due to following operation that does

 // acquire anyways.

 // Walk the pattern:

 //

 //      n: Load.acq

 //           |

 //      MemBarAcquire

 //       |         |

 //  Proj(ctrl)  Proj(mem)

 //       |         |

 //   MemBarRelease/Volatile

 //

 bool followed_by_acquire(const Node *load) {

   assert(load->is_Load(), "So far implemented only for loads.");

   // Find MemBarAcquire.

   const Node *mba = NULL;

   for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) {

     const Node *out = load->fast_out(i);

     if (out->Opcode() == Op_MemBarAcquire) {

       if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge.

       mba = out;

       break;

     }

   }

   if (!mba) return false;

   // Find following MemBar node.

   //

   // The following node must be reachable by control AND memory

   // edge to assure no other operations are in between the two nodes.

   //

   // So first get the Proj node, mem_proj, to use it to iterate forward.

   Node *mem_proj = NULL;

   for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) {

     mem_proj = mba->fast_out(i);      // Throw out-of-bounds if proj not found

     assert(mem_proj->is_Proj(), "only projections here");

     ProjNode *proj = mem_proj->as_Proj();

     if (proj->_con == TypeFunc::Memory &&

         !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only

       break;

   }

   assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken");

   // Search MemBar behind Proj. If there are other memory operations

   // behind the Proj we lost.

   for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) {

     Node *x = mem_proj->fast_out(j);

     // Proj might have an edge to a store or load node which precedes the membar.

     if (x->is_Mem()) return false;

     // On PPC64 release and volatile are implemented by an instruction

     // that also has acquire semantics. I.e. there is no need for an

     // acquire before these.

     int xop = x->Opcode();

     if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) {

       // Make sure we're not missing Call/Phi/MergeMem by checking

       // control edges. The control edge must directly lead back

       // to the MemBarAcquire

       Node *ctrl_proj = x->in(0);

       if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) {

         return true;

       }

     }

   }

   return false;

 }

 #define __ _masm.

 // Tertiary op of a LoadP or StoreP encoding.

 #define REGP_OP true

 // ****************************************************************************

 // REQUIRED FUNCTIONALITY

 // !!!!! Special hack to get all type of calls to specify the byte offset

 //       from the start of the call to the point where the return address

 //       will point.

 // PPC port: Removed use of lazy constant construct.

 int MachCallStaticJavaNode::ret_addr_offset() {

   // It's only a single branch-and-link instruction.

   return 4;

 }

 int MachCallDynamicJavaNode::ret_addr_offset() {

   // Offset is 4 with postalloc expanded calls (bl is one instruction). We use

   // postalloc expanded calls if we use inline caches and do not update method data.

   if (UseInlineCaches)

     return 4;

   int vtable_index = this->_vtable_index;

   if (vtable_index < 0) {

     // Must be invalid_vtable_index, not nonvirtual_vtable_index.

     assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");

     return 12;

   } else {

     assert(!UseInlineCaches, "expect vtable calls only if not using ICs");

     return 24;

   }

 }

 int MachCallRuntimeNode::ret_addr_offset() {

 #if defined(ABI_ELFv2)

   return 28;

 #else

   return 40;

 #endif

 }

 //=============================================================================

 // condition code conversions

 static int cc_to_boint(int cc) {

   return Assembler::bcondCRbiIs0 | (cc & 8);

 }

 static int cc_to_inverse_boint(int cc) {

   return Assembler::bcondCRbiIs0 | (8-(cc & 8));

 }

 static int cc_to_biint(int cc, int flags_reg) {

   return (flags_reg << 2) | (cc & 3);

 }

 //=============================================================================

 // Compute padding required for nodes which need alignment. The padding

 // is the number of bytes (not instructions) which will be inserted before

 // the instruction. The padding must match the size of a NOP instruction.

 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const {

   return (3*4-current_offset)&31;

 }

 int string_indexOf_imm1Node::compute_padding(int current_offset) const {

   return (2*4-current_offset)&31;

 }

 int string_indexOf_immNode::compute_padding(int current_offset) const {

   return (3*4-current_offset)&31;

 }

 int string_indexOfNode::compute_padding(int current_offset) const {

   return (1*4-current_offset)&31;

 }

 int string_compareNode::compute_padding(int current_offset) const {

   return (4*4-current_offset)&31;

 }

 int string_equals_immNode::compute_padding(int current_offset) const {

   if (opnd_array(3)->constant() < 16) return 0; // Don't insert nops for short version (loop completely unrolled).

   return (2*4-current_offset)&31;

 }

 int string_equalsNode::compute_padding(int current_offset) const {

   return (7*4-current_offset)&31;

 }

 int inlineCallClearArrayNode::compute_padding(int current_offset) const {

   return (2*4-current_offset)&31;

 }

 //=============================================================================

 // Indicate if the safepoint node needs the polling page as an input.

 bool SafePointNode::needs_polling_address_input() {

   // The address is loaded from thread by a seperate node.

   return true;

 }

 //=============================================================================

 // Emit an interrupt that is caught by the debugger (for debugging compiler).

 void emit_break(CodeBuffer &cbuf) {

   MacroAssembler _masm(&cbuf);

   __ illtrap();

 }

 #ifndef PRODUCT

 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {

   st->print("BREAKPOINT");

 }

 #endif

 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {

   emit_break(cbuf);

 }

 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {

   return MachNode::size(ra_);

 }

 //=============================================================================

 void emit_nop(CodeBuffer &cbuf) {

   MacroAssembler _masm(&cbuf);

   __ nop();

 }

 static inline void emit_long(CodeBuffer &cbuf, int value) {

   *((int*)(cbuf.insts_end())) = value;

   cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord);

 }

 //=============================================================================

 %} // interrupt source

 source_hpp %{ // Header information of the source block.

 //--------------------------------------------------------------

 //---<  Used for optimization in Compile::Shorten_branches  >---

 //--------------------------------------------------------------

 const uint trampoline_stub_size     =  6 * BytesPerInstWord;

 class CallStubImpl {

  public:

   // Emit call stub, compiled java to interpreter.

   static void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset);

   // Size of call trampoline stub.

   // This doesn't need to be accurate to the byte, but it

   // must be larger than or equal to the real size of the stub.

   static uint size_call_trampoline() {

     return trampoline_stub_size;

   }

   // number of relocations needed by a call trampoline stub

   static uint reloc_call_trampoline() {

     return 5;

   }

 };

 %} // end source_hpp

 source %{

 // Emit a trampoline stub for a call to a target which is too far away.

 //

 // code sequences:

 //

 // call-site:

 //   branch-and-link to <destination> or <trampoline stub>

 //

 // Related trampoline stub for this call-site in the stub section:

 //   load the call target from the constant pool

 //   branch via CTR (LR/link still points to the call-site above)

 void CallStubImpl::emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) {

   // Start the stub.

   address stub = __ start_a_stub(Compile::MAX_stubs_size/2);

   if (stub == NULL) {

     ciEnv::current()->record_failure("CodeCache is full");

     return;

   }

   // For java_to_interp stubs we use R11_scratch1 as scratch register

   // and in call trampoline stubs we use R12_scratch2. This way we

   // can distinguish them (see is_NativeCallTrampolineStub_at()).

   Register reg_scratch = R12_scratch2;

   // Create a trampoline stub relocation which relates this trampoline stub

   // with the call instruction at insts_call_instruction_offset in the

   // instructions code-section.

   __ relocate(trampoline_stub_Relocation::spec(__ code()->insts()->start() + insts_call_instruction_offset));

   const int stub_start_offset = __ offset();

   // Now, create the trampoline stub's code:

   // - load the TOC

   // - load the call target from the constant pool

   // - call

   __ calculate_address_from_global_toc(reg_scratch, __ method_toc());

   __ ld_largeoffset_unchecked(reg_scratch, destination_toc_offset, reg_scratch, false);

   __ mtctr(reg_scratch);

   __ bctr();

   const address stub_start_addr = __ addr_at(stub_start_offset);

   // FIXME: Assert that the trampoline stub can be identified and patched.

   // Assert that the encoded destination_toc_offset can be identified and that it is correct.

   assert(destination_toc_offset == NativeCallTrampolineStub_at(stub_start_addr)->destination_toc_offset(),

          "encoded offset into the constant pool must match");

   // Trampoline_stub_size should be good.

   assert((uint)(__ offset() - stub_start_offset) <= trampoline_stub_size, "should be good size");

   assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");

   // End the stub.

   __ end_a_stub();

 }

 //=============================================================================

 // Emit an inline branch-and-link call and a related trampoline stub.

 //

 // code sequences:

 //

 // call-site:

 //   branch-and-link to <destination> or <trampoline stub>

 //

 // Related trampoline stub for this call-site in the stub section:

 //   load the call target from the constant pool

 //   branch via CTR (LR/link still points to the call-site above)

 //

 typedef struct {

   int insts_call_instruction_offset;

   int ret_addr_offset;

 } EmitCallOffsets;

 // Emit a branch-and-link instruction that branches to a trampoline.

 // - Remember the offset of the branch-and-link instruction.

 // - Add a relocation at the branch-and-link instruction.

 // - Emit a branch-and-link.

 // - Remember the return pc offset.

 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) {

   EmitCallOffsets offsets = { -1, -1 };

   const int start_offset = __ offset();

   offsets.insts_call_instruction_offset = __ offset();

   // No entry point given, use the current pc.

   if (entry_point == NULL) entry_point = __ pc();

   if (!Compile::current()->in_scratch_emit_size()) {

     // Put the entry point as a constant into the constant pool.

     const address entry_point_toc_addr   = __ address_constant(entry_point, RelocationHolder::none);

     const int     entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);

     // Emit the trampoline stub which will be related to the branch-and-link below.

     CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset);

     if (ciEnv::current()->failing()) { return offsets; } // Code cache may be full.

     __ relocate(rtype);

   }

   // Note: At this point we do not have the address of the trampoline

   // stub, and the entry point might be too far away for bl, so __ pc()

   // serves as dummy and the bl will be patched later.

   __ bl((address) __ pc());

   offsets.ret_addr_offset = __ offset() - start_offset;

   return offsets;

 }

 //=============================================================================

 // Factory for creating loadConL* nodes for large/small constant pool.

 static inline jlong replicate_immF(float con) {

   // Replicate float con 2 times and pack into vector.

   int val = *((int*)&con);

   jlong lval = val;

   lval = (lval << 32) | (lval & 0xFFFFFFFFl);

   return lval;

 }

 //=============================================================================

 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask();

 int Compile::ConstantTable::calculate_table_base_offset() const {

   return 0;  // absolute addressing, no offset

 }

 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; }

 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {

   Compile *C = ra_->C;

   iRegPdstOper *op_dst = new (C) iRegPdstOper();

   MachNode *m1 = new (C) loadToc_hiNode();

   MachNode *m2 = new (C) loadToc_loNode();

   m1->add_req(NULL);

   m2->add_req(NULL, m1);

   m1->_opnds[0] = op_dst;

   m2->_opnds[0] = op_dst;

   m2->_opnds[1] = op_dst;

   ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));

   ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));

   nodes->push(m1);

   nodes->push(m2);

 }

 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {

   // Is postalloc expanded.

   ShouldNotReachHere();

 }

 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {

   return 0;

 }

 #ifndef PRODUCT

 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {

   st->print("-- \t// MachConstantBaseNode (empty encoding)");

 }

 #endif

 //=============================================================================

 #ifndef PRODUCT

 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {

   Compile* C = ra_->C;

   const long framesize = C->frame_slots() << LogBytesPerInt;

   st->print("PROLOG\n\t");

   if (C->need_stack_bang(framesize)) {

     st->print("stack_overflow_check\n\t");

   }

   if (!false /* TODO: PPC port C->is_frameless_method()*/) {

     st->print("save return pc\n\t");

     st->print("push frame %ld\n\t", -framesize);

   }

 }

 #endif

 // Macro used instead of the common __ to emulate the pipes of PPC.

 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the

 // micro scheduler to cope with "hand written" assembler like in the prolog. Though

 // still no scheduling of this code is possible, the micro scheduler is aware of the

 // code and can update its internal data. The following mechanism is used to achieve this:

 // The micro scheduler calls size() of each compound node during scheduling. size() does a

 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL.

 #if 0 // TODO: PPC port

 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling())                    \

                   C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \

                 _masm.

 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling())                    \

                   C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none)

 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling())                 \

                   C->hb_scheduling()->_pdScheduling->advance_offset

 #else

 #define ___(op) if (UsePower6SchedulerPPC64)                                          \

                   Unimplemented();                                                    \

                 _masm.

 #define ___stop if (UsePower6SchedulerPPC64)                                          \

                   Unimplemented()

 #define ___advance if (UsePower6SchedulerPPC64)                                       \

                   Unimplemented()

 #endif

 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {

   Compile* C = ra_->C;

   MacroAssembler _masm(&cbuf);

   const long framesize = C->frame_size_in_bytes();

   assert(framesize % (2 * wordSize) == 0, "must preserve 2*wordSize alignment");

   const bool method_is_frameless      = false /* TODO: PPC port C->is_frameless_method()*/;

   const Register return_pc            = R20; // Must match return_addr() in frame section.

   const Register callers_sp           = R21;

   const Register push_frame_temp      = R22;

   const Register toc_temp             = R23;

   assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp);

   if (method_is_frameless) {

     // Add nop at beginning of all frameless methods to prevent any

     // oop instructions from getting overwritten by make_not_entrant

     // (patching attempt would fail).

     ___(nop) nop();

   } else {

     // Get return pc.

     ___(mflr) mflr(return_pc);

   }

   // Calls to C2R adapters often do not accept exceptional returns.

   // We require that their callers must bang for them. But be

   // careful, because some VM calls (such as call site linkage) can

   // use several kilobytes of stack. But the stack safety zone should

   // account for that. See bugs 4446381, 4468289, 4497237.

   int bangsize = C->bang_size_in_bytes();

   assert(bangsize >= framesize || bangsize <= 0, "stack bang size incorrect");

   if (C->need_stack_bang(bangsize) && UseStackBanging) {

     // Unfortunately we cannot use the function provided in

     // assembler.cpp as we have to emulate the pipes. So I had to

     // insert the code of generate_stack_overflow_check(), see

     // assembler.cpp for some illuminative comments.

     const int page_size = os::vm_page_size();

     int bang_end = StackShadowPages * page_size;

     // This is how far the previous frame's stack banging extended.

     const int bang_end_safe = bang_end;

     if (bangsize > page_size) {

       bang_end += bangsize;

     }

     int bang_offset = bang_end_safe;

     while (bang_offset <= bang_end) {

       // Need at least one stack bang at end of shadow zone.

       // Again I had to copy code, this time from assembler_ppc.cpp,

       // bang_stack_with_offset - see there for comments.

       // Stack grows down, caller passes positive offset.

       assert(bang_offset > 0, "must bang with positive offset");

       long stdoffset = -bang_offset;

       if (Assembler::is_simm(stdoffset, 16)) {

         // Signed 16 bit offset, a simple std is ok.

         if (UseLoadInstructionsForStackBangingPPC64) {

           ___(ld) ld(R0,  (int)(signed short)stdoffset, R1_SP);

         } else {

           ___(std) std(R0, (int)(signed short)stdoffset, R1_SP);

         }

       } else if (Assembler::is_simm(stdoffset, 31)) {

         // Use largeoffset calculations for addis & ld/std.

         const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset);

         const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset);

         Register tmp = R11;

         ___(addis) addis(tmp, R1_SP, hi);

         if (UseLoadInstructionsForStackBangingPPC64) {

           ___(ld) ld(R0, lo, tmp);

         } else {

           ___(std) std(R0, lo, tmp);

         }

       } else {

         ShouldNotReachHere();

       }

       bang_offset += page_size;

     }

     // R11 trashed

   } // C->need_stack_bang(framesize) && UseStackBanging

   unsigned int bytes = (unsigned int)framesize;

   long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);

   ciMethod *currMethod = C->method();

   // Optimized version for most common case.

   if (UsePower6SchedulerPPC64 &&

       !method_is_frameless && Assembler::is_simm((int)(-offset), 16) &&

       !(false /* ConstantsALot TODO: PPC port*/)) {

     ___(or) mr(callers_sp, R1_SP);

     ___(std) std(return_pc, _abi(lr), R1_SP);

     ___(stdu) stdu(R1_SP, -offset, R1_SP);

     return;

   }

   if (!method_is_frameless) {

     // Get callers sp.

     ___(or) mr(callers_sp, R1_SP);

     // Push method's frame, modifies SP.

     assert(Assembler::is_uimm(framesize, 32U), "wrong type");

     // The ABI is already accounted for in 'framesize' via the

     // 'out_preserve' area.

     Register tmp = push_frame_temp;

     // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp).

     if (Assembler::is_simm(-offset, 16)) {

       ___(stdu) stdu(R1_SP, -offset, R1_SP);

     } else {

       long x = -offset;

       // Had to insert load_const(tmp, -offset).

       ___(addis)  lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16)));

       ___(ori)    ori( tmp, tmp, ((x >> 32) & 0x0000ffff));

       ___(rldicr) sldi(tmp, tmp, 32);

       ___(oris)   oris(tmp, tmp, (x & 0xffff0000) >> 16);

       ___(ori)    ori( tmp, tmp, (x & 0x0000ffff));

       ___(stdux) stdux(R1_SP, R1_SP, tmp);

     }

   }

 #if 0 // TODO: PPC port

   // For testing large constant pools, emit a lot of constants to constant pool.

   // "Randomize" const_size.

   if (ConstantsALot) {

     const int num_consts = const_size();

     for (int i = 0; i < num_consts; i++) {

       __ long_constant(0xB0B5B00BBABE);

     }

   }

 #endif

   if (!method_is_frameless) {

     // Save return pc.

     ___(std) std(return_pc, _abi(lr), callers_sp);

   }

 }

 #undef ___

 #undef ___stop

 #undef ___advance

 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {

   // Variable size. determine dynamically.

   return MachNode::size(ra_);

 }

 int MachPrologNode::reloc() const {

   // Return number of relocatable values contained in this instruction.

   return 1; // 1 reloc entry for load_const(toc).

 }

 //=============================================================================

 #ifndef PRODUCT

 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {

   Compile* C = ra_->C;

   st->print("EPILOG\n\t");

   st->print("restore return pc\n\t");

   st->print("pop frame\n\t");

   if (do_polling() && C->is_method_compilation()) {

     st->print("touch polling page\n\t");

   }

 }

 #endif

 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {

   Compile* C = ra_->C;

   MacroAssembler _masm(&cbuf);

   const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;

   assert(framesize >= 0, "negative frame-size?");

   const bool method_needs_polling = do_polling() && C->is_method_compilation();

   const bool method_is_frameless  = false /* TODO: PPC port C->is_frameless_method()*/;

   const Register return_pc        = R11;

   const Register polling_page     = R12;

   if (!method_is_frameless) {

     // Restore return pc relative to callers' sp.

     __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP);

   }

   if (method_needs_polling) {

     if (LoadPollAddressFromThread) {

       // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread);

       Unimplemented();

     } else {

       __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page()

     }

   }

   if (!method_is_frameless) {

     // Move return pc to LR.

     __ mtlr(return_pc);

     // Pop frame (fixed frame-size).

     __ addi(R1_SP, R1_SP, (int)framesize);

   }

   if (method_needs_polling) {

     // We need to mark the code position where the load from the safepoint

     // polling page was emitted as relocInfo::poll_return_type here.

     __ relocate(relocInfo::poll_return_type);

     __ load_from_polling_page(polling_page);

   }

 }

 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {

   // Variable size. Determine dynamically.

   return MachNode::size(ra_);

 }

 int MachEpilogNode::reloc() const {

   // Return number of relocatable values contained in this instruction.

   return 1; // 1 for load_from_polling_page.

 }

 const Pipeline * MachEpilogNode::pipeline() const {

   return MachNode::pipeline_class();

 }

 // This method seems to be obsolete. It is declared in machnode.hpp

 // and defined in all *.ad files, but it is never called. Should we

 // get rid of it?

 int MachEpilogNode::safepoint_offset() const {

   assert(do_polling(), "no return for this epilog node");

   return 0;

 }

 #if 0 // TODO: PPC port

 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {

   MacroAssembler _masm(&cbuf);

   if (LoadPollAddressFromThread) {

     _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread);

   } else {

     _masm.nop();

   }

 }

 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const {

   if (LoadPollAddressFromThread) {

     return 4;

   } else {

     return 4;

   }

 }

 #ifndef PRODUCT

 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const {

   st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread");

 }

 #endif

 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const {

   return RSCRATCH1_BITS64_REG_mask();

 }

 #endif // PPC port

 // =============================================================================

 // Figure out which register class each belongs in: rc_int, rc_float or

 // rc_stack.

 enum RC { rc_bad, rc_int, rc_float, rc_stack };

 static enum RC rc_class(OptoReg::Name reg) {

   // Return the register class for the given register. The given register

   // reg is a <register>_num value, which is an index into the MachRegisterNumbers

   // enumeration in adGlobals_ppc64.hpp.

   if (reg == OptoReg::Bad) return rc_bad;

   // We have 64 integer register halves, starting at index 0.

   if (reg < 64) return rc_int;

   // We have 64 floating-point register halves, starting at index 64.

   if (reg < 64+64) return rc_float;

   // Between float regs & stack are the flags regs.

   assert(OptoReg::is_stack(reg), "blow up if spilling flags");

   return rc_stack;

 }

 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset,

                         bool do_print, Compile* C, outputStream *st) {

   assert(opcode == Assembler::LD_OPCODE   ||

          opcode == Assembler::STD_OPCODE  ||

          opcode == Assembler::LWZ_OPCODE  ||

          opcode == Assembler::STW_OPCODE  ||

          opcode == Assembler::LFD_OPCODE  ||

          opcode == Assembler::STFD_OPCODE ||

          opcode == Assembler::LFS_OPCODE  ||

          opcode == Assembler::STFS_OPCODE,

          "opcode not supported");

   if (cbuf) {

     int d =

       (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ?

         Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/)

       : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build.

     emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP));

   }

 #ifndef PRODUCT

   else if (do_print) {

     st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy",

               op_str,

               Matcher::regName[reg],

               offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/);

   }

 #endif

   return 4; // size

 }

 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {

   Compile* C = ra_->C;

   // Get registers to move.

   OptoReg::Name src_hi = ra_->get_reg_second(in(1));

   OptoReg::Name src_lo = ra_->get_reg_first(in(1));

   OptoReg::Name dst_hi = ra_->get_reg_second(this);

   OptoReg::Name dst_lo = ra_->get_reg_first(this);

   enum RC src_hi_rc = rc_class(src_hi);

   enum RC src_lo_rc = rc_class(src_lo);

   enum RC dst_hi_rc = rc_class(dst_hi);

   enum RC dst_lo_rc = rc_class(dst_lo);

   assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");

   if (src_hi != OptoReg::Bad)

     assert((src_lo&1)==0 && src_lo+1==src_hi &&

            (dst_lo&1)==0 && dst_lo+1==dst_hi,

            "expected aligned-adjacent pairs");

   // Generate spill code!

   int size = 0;

   if (src_lo == dst_lo && src_hi == dst_hi)

     return size;            // Self copy, no move.

   // --------------------------------------

   // Memory->Memory Spill. Use R0 to hold the value.

   if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {

     int src_offset = ra_->reg2offset(src_lo);

     int dst_offset = ra_->reg2offset(dst_lo);

     if (src_hi != OptoReg::Bad) {

       assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack,

              "expected same type of move for high parts");

       size += ld_st_helper(cbuf, "LD  ", Assembler::LD_OPCODE,  R0_num, src_offset, !do_size, C, st);

       if (!cbuf && !do_size) st->print("\n\t");

       size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st);

     } else {

       size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st);

       if (!cbuf && !do_size) st->print("\n\t");

       size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st);

     }

     return size;

   }

   // --------------------------------------

   // Check for float->int copy; requires a trip through memory.

   if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {

     Unimplemented();

   }

   // --------------------------------------

   // Check for integer reg-reg copy.

   if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {

       Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);

       Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);

       size = (Rsrc != Rdst) ? 4 : 0;

       if (cbuf) {

         MacroAssembler _masm(cbuf);

         if (size) {

           __ mr(Rdst, Rsrc);

         }

       }

 #ifndef PRODUCT

       else if (!do_size) {

         if (size) {

           st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);

         } else {

           st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]);

         }

       }

 #endif

       return size;

   }

   // Check for integer store.

   if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {

     int dst_offset = ra_->reg2offset(dst_lo);

     if (src_hi != OptoReg::Bad) {

       assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack,

              "expected same type of move for high parts");

       size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st);

     } else {

       size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st);

     }

     return size;

   }

   // Check for integer load.

   if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {

     int src_offset = ra_->reg2offset(src_lo);

     if (src_hi != OptoReg::Bad) {

       assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack,

              "expected same type of move for high parts");

       size += ld_st_helper(cbuf, "LD  ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st);

     } else {

       size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st);

     }

     return size;

   }

   // Check for float reg-reg copy.

   if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {

     if (cbuf) {

       MacroAssembler _masm(cbuf);

       FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);

       FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);

       __ fmr(Rdst, Rsrc);

     }

 #ifndef PRODUCT

     else if (!do_size) {

       st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);

     }

 #endif

     return 4;

   }

   // Check for float store.

   if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {

     int dst_offset = ra_->reg2offset(dst_lo);

     if (src_hi != OptoReg::Bad) {

       assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack,

              "expected same type of move for high parts");

       size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st);

     } else {

       size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st);

     }

     return size;

   }

   // Check for float load.

   if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {

     int src_offset = ra_->reg2offset(src_lo);

     if (src_hi != OptoReg::Bad) {

       assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack,

              "expected same type of move for high parts");

       size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st);

     } else {

       size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st);

     }

     return size;

   }

   // --------------------------------------------------------------------

   // Check for hi bits still needing moving. Only happens for misaligned

   // arguments to native calls.

   if (src_hi == dst_hi)

     return size;               // Self copy; no move.

   assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");

   ShouldNotReachHere(); // Unimplemented

   return 0;

 }

 #ifndef PRODUCT

 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {

   if (!ra_)

     st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);

   else

     implementation(NULL, ra_, false, st);

 }

 #endif

 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {

   implementation(&cbuf, ra_, false, NULL);

 }

 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {

   return implementation(NULL, ra_, true, NULL);

 }

 #if 0 // TODO: PPC port

 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) {

 #ifndef PRODUCT

   if (ra_->node_regs_max_index() == 0) return archOpcode_undefined;

 #endif

   assert(ra_->node_regs_max_index() != 0, "");

   // Get registers to move.

   OptoReg::Name src_hi = ra_->get_reg_second(n->in(1));

   OptoReg::Name src_lo = ra_->get_reg_first(n->in(1));

   OptoReg::Name dst_hi = ra_->get_reg_second(n);

   OptoReg::Name dst_lo = ra_->get_reg_first(n);

   enum RC src_lo_rc = rc_class(src_lo);

   enum RC dst_lo_rc = rc_class(dst_lo);

   if (src_lo == dst_lo && src_hi == dst_hi)

     return ppc64Opcode_none;            // Self copy, no move.

   // --------------------------------------

   // Memory->Memory Spill. Use R0 to hold the value.

   if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {

     return ppc64Opcode_compound;

   }

   // --------------------------------------

   // Check for float->int copy; requires a trip through memory.

   if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {

     Unimplemented();

   }

   // --------------------------------------

   // Check for integer reg-reg copy.

   if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {

     Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);

     Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);

     if (Rsrc == Rdst) {

       return ppc64Opcode_none;

     } else {

       return ppc64Opcode_or;

     }

   }

   // Check for integer store.

   if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {

     if (src_hi != OptoReg::Bad) {

       return ppc64Opcode_std;

     } else {

       return ppc64Opcode_stw;

     }

   }

   // Check for integer load.

   if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {

     if (src_hi != OptoReg::Bad) {

       return ppc64Opcode_ld;

     } else {

       return ppc64Opcode_lwz;

     }

   }

   // Check for float reg-reg copy.

   if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {

     return ppc64Opcode_fmr;

   }

   // Check for float store.

   if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {

     if (src_hi != OptoReg::Bad) {

       return ppc64Opcode_stfd;

     } else {

       return ppc64Opcode_stfs;

     }

   }

   // Check for float load.

   if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {

     if (src_hi != OptoReg::Bad) {

       return ppc64Opcode_lfd;

     } else {

       return ppc64Opcode_lfs;

     }

   }

   // --------------------------------------------------------------------

   // Check for hi bits still needing moving. Only happens for misaligned

   // arguments to native calls.

   if (src_hi == dst_hi) {

     return ppc64Opcode_none;               // Self copy; no move.

   }

   ShouldNotReachHere();

   return ppc64Opcode_undefined;

 }

 #endif // PPC port

 #ifndef PRODUCT

 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const {

   st->print("NOP \t// %d nops to pad for loops.", _count);

 }

 #endif

 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {

   MacroAssembler _masm(&cbuf);

   // _count contains the number of nops needed for padding.

   for (int i = 0; i < _count; i++) {

     __ nop();

   }

 }

 uint MachNopNode::size(PhaseRegAlloc *ra_) const {

   return _count * 4;

 }

 #ifndef PRODUCT

 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {

   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());

   char reg_str[128];

   ra_->dump_register(this, reg_str);

   st->print("ADDI    %s, SP, %d \t// box node", reg_str, offset);

 }

 #endif

 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {

   MacroAssembler _masm(&cbuf);

   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());

   int reg    = ra_->get_encode(this);

   if (Assembler::is_simm(offset, 16)) {

     __ addi(as_Register(reg), R1, offset);

   } else {

     ShouldNotReachHere();

   }

 }

 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {

   // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).

   return 4;

 }

 #ifndef PRODUCT

 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const {

   st->print_cr("---- MachUEPNode ----");

   st->print_cr("...");

 }

 #endif

 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {

   // This is the unverified entry point.

   MacroAssembler _masm(&cbuf);

   // Inline_cache contains a klass.

   Register ic_klass       = as_Register(Matcher::inline_cache_reg_encode());

   Register receiver_klass = R12_scratch2;  // tmp

   assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1);

   assert(R11_scratch1 == R11, "need prologue scratch register");

   // Check for NULL argument if we don't have implicit null checks.

   if (!ImplicitNullChecks || !os::zero_page_read_protected()) {

     if (TrapBasedNullChecks) {

       __ trap_null_check(R3_ARG1);

     } else {

       Label valid;

       __ cmpdi(CCR0, R3_ARG1, 0);

       __ bne_predict_taken(CCR0, valid);

       // We have a null argument, branch to ic_miss_stub.

       __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),

                            relocInfo::runtime_call_type);

       __ bind(valid);

     }

   }

   // Assume argument is not NULL, load klass from receiver.

   __ load_klass(receiver_klass, R3_ARG1);

   if (TrapBasedICMissChecks) {

     __ trap_ic_miss_check(receiver_klass, ic_klass);

   } else {

     Label valid;

     __ cmpd(CCR0, receiver_klass, ic_klass);

     __ beq_predict_taken(CCR0, valid);

     // We have an unexpected klass, branch to ic_miss_stub.

     __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),

                          relocInfo::runtime_call_type);

     __ bind(valid);

   }

   // Argument is valid and klass is as expected, continue.

 }

 #if 0 // TODO: PPC port

 // Optimize UEP code on z (save a load_const() call in main path).

 int MachUEPNode::ep_offset() {

   return 0;

 }

 #endif

 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {

   // Variable size. Determine dynamically.

   return MachNode::size(ra_);

 }

 //=============================================================================

 %} // interrupt source

 source_hpp %{ // Header information of the source block.

 class HandlerImpl {

  public:

   static int emit_exception_handler(CodeBuffer &cbuf);

   static int emit_deopt_handler(CodeBuffer& cbuf);

   static uint size_exception_handler() {

     // The exception_handler is a b64_patchable.

     return MacroAssembler::b64_patchable_size;

   }

   static uint size_deopt_handler() {

     // The deopt_handler is a bl64_patchable.

     return MacroAssembler::bl64_patchable_size;

   }

 };

 %} // end source_hpp

 source %{

 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) {

   MacroAssembler _masm(&cbuf);

   address base = __ start_a_stub(size_exception_handler());

   if (base == NULL) return 0; // CodeBuffer::expand failed

   int offset = __ offset();

   __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(),

                        relocInfo::runtime_call_type);

   assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size");

   __ end_a_stub();

   return offset;

 }

 // The deopt_handler is like the exception handler, but it calls to

 // the deoptimization blob instead of jumping to the exception blob.

 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {

   MacroAssembler _masm(&cbuf);

   address base = __ start_a_stub(size_deopt_handler());

   if (base == NULL) return 0; // CodeBuffer::expand failed

   int offset = __ offset();

   __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(),

                         relocInfo::runtime_call_type);

   assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");

   __ end_a_stub();

   return offset;

 }

 //=============================================================================

 // Use a frame slots bias for frameless methods if accessing the stack.

 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {

   if (as_Register(reg_enc) == R1_SP) {

     return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes();

   }

   return 0;

 }

 const bool Matcher::match_rule_supported(int opcode) {

   if (!has_match_rule(opcode))

     return false;

   switch (opcode) {

   case Op_SqrtD:

     return VM_Version::has_fsqrt();

   case Op_CountLeadingZerosI:

   case Op_CountLeadingZerosL:

   case Op_CountTrailingZerosI:

   case Op_CountTrailingZerosL:

     if (!UseCountLeadingZerosInstructionsPPC64)

       return false;

     break;

   case Op_PopCountI:

   case Op_PopCountL:

     return (UsePopCountInstruction && VM_Version::has_popcntw());

   case Op_StrComp:

     return SpecialStringCompareTo;

   case Op_StrEquals:

     return SpecialStringEquals;

   case Op_StrIndexOf:

     return SpecialStringIndexOf;

   }

   return true;  // Per default match rules are supported.

 }

 int Matcher::regnum_to_fpu_offset(int regnum) {

   // No user for this method?

   Unimplemented();

   return 999;

 }

 const bool Matcher::convL2FSupported(void) {

   // fcfids can do the conversion (>= Power7).

   // fcfid + frsp showed rounding problem when result should be 0x3f800001.

   return VM_Version::has_fcfids(); // False means that conversion is done by runtime call.

 }

 // Vector width in bytes.

 const int Matcher::vector_width_in_bytes(BasicType bt) {

   assert(MaxVectorSize == 8, "");

   return 8;

 }

 // Vector ideal reg.

 const uint Matcher::vector_ideal_reg(int size) {

   assert(MaxVectorSize == 8 && size == 8, "");

   return Op_RegL;

 }

 const uint Matcher::vector_shift_count_ideal_reg(int size) {

   fatal("vector shift is not supported");

   return Node::NotAMachineReg;

 }

 // Limits on vector size (number of elements) loaded into vector.

 const int Matcher::max_vector_size(const BasicType bt) {

   assert(is_java_primitive(bt), "only primitive type vectors");

   return vector_width_in_bytes(bt)/type2aelembytes(bt);

 }

 const int Matcher::min_vector_size(const BasicType bt) {

   return max_vector_size(bt); // Same as max.

 }

 // PPC doesn't support misaligned vectors store/load.

 const bool Matcher::misaligned_vectors_ok() {

   return false;

 }

 // PPC AES support not yet implemented

 const bool Matcher::pass_original_key_for_aes() {

   return false;

 }

 // RETURNS: whether this branch offset is short enough that a short

 // branch can be used.

 //

 // If the platform does not provide any short branch variants, then

 // this method should return `false' for offset 0.

 //

 // `Compile::Fill_buffer' will decide on basis of this information

 // whether to do the pass `Compile::Shorten_branches' at all.

 //

 // And `Compile::Shorten_branches' will decide on basis of this

 // information whether to replace particular branch sites by short

 // ones.

 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {

   // Is the offset within the range of a ppc64 pc relative branch?

   bool b;

   const int safety_zone = 3 * BytesPerInstWord;

   b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone),

                          29 - 16 + 1 + 2);

   return b;

 }

 const bool Matcher::isSimpleConstant64(jlong value) {

   // Probably always true, even if a temp register is required.

   return true;

 }

 /* TODO: PPC port

 // Make a new machine dependent decode node (with its operands).

 MachTypeNode *Matcher::make_decode_node(Compile *C) {

   assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0,

          "This method is only implemented for unscaled cOops mode so far");

   MachTypeNode *decode = new (C) decodeN_unscaledNode();

   decode->set_opnd_array(0, new (C) iRegPdstOper());

   decode->set_opnd_array(1, new (C) iRegNsrcOper());

   return decode;

 }

 */

 // Threshold size for cleararray.

 const int Matcher::init_array_short_size = 8 * BytesPerLong;

 // false => size gets scaled to BytesPerLong, ok.

 const bool Matcher::init_array_count_is_in_bytes = false;

 // Use conditional move (CMOVL) on Power7.

 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves

 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet.

 // fsel doesn't accept a condition register as input, so this would be slightly different.

 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }

 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand).

 const bool Matcher::require_postalloc_expand = true;

 // Should the Matcher clone shifts on addressing modes, expecting them to

 // be subsumed into complex addressing expressions or compute them into

 // registers? True for Intel but false for most RISCs.

 const bool Matcher::clone_shift_expressions = false;

 // Do we need to mask the count passed to shift instructions or does

 // the cpu only look at the lower 5/6 bits anyway?

 // PowerPC requires masked shift counts.

 const bool Matcher::need_masked_shift_count = true;

 // This affects two different things:

 //  - how Decode nodes are matched

 //  - how ImplicitNullCheck opportunities are recognized

 // If true, the matcher will try to remove all Decodes and match them

 // (as operands) into nodes. NullChecks are not prepared to deal with

 // Decodes by final_graph_reshaping().

 // If false, final_graph_reshaping() forces the decode behind the Cmp

 // for a NullCheck. The matcher matches the Decode node into a register.

 // Implicit_null_check optimization moves the Decode along with the

 // memory operation back up before the NullCheck.

 bool Matcher::narrow_oop_use_complex_address() {

   // TODO: PPC port if (MatchDecodeNodes) return true;

   return false;

 }

 bool Matcher::narrow_klass_use_complex_address() {

   NOT_LP64(ShouldNotCallThis());

   assert(UseCompressedClassPointers, "only for compressed klass code");

   // TODO: PPC port if (MatchDecodeNodes) return true;

   return false;

 }

 // Is it better to copy float constants, or load them directly from memory?

 // Intel can load a float constant from a direct address, requiring no

 // extra registers. Most RISCs will have to materialize an address into a

 // register first, so they would do better to copy the constant from stack.

 const bool Matcher::rematerialize_float_constants = false;

 // If CPU can load and store mis-aligned doubles directly then no fixup is

 // needed. Else we split the double into 2 integer pieces and move it

 // piece-by-piece. Only happens when passing doubles into C code as the

 // Java calling convention forces doubles to be aligned.

 const bool Matcher::misaligned_doubles_ok = true;

 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {

  Unimplemented();

 }

 // Advertise here if the CPU requires explicit rounding operations

 // to implement the UseStrictFP mode.

 const bool Matcher::strict_fp_requires_explicit_rounding = false;

 // Do floats take an entire double register or just half?

 //

 // A float occupies a ppc64 double register. For the allocator, a

 // ppc64 double register appears as a pair of float registers.

 bool Matcher::float_in_double() { return true; }

 // Do ints take an entire long register or just half?

 // The relevant question is how the int is callee-saved:

 // the whole long is written but de-opt'ing will have to extract

 // the relevant 32 bits.

 const bool Matcher::int_in_long = true;

 // Constants for c2c and c calling conventions.

 const MachRegisterNumbers iarg_reg[8] = {

   R3_num, R4_num, R5_num, R6_num,

   R7_num, R8_num, R9_num, R10_num

 };

 const MachRegisterNumbers farg_reg[13] = {

   F1_num, F2_num, F3_num, F4_num,

   F5_num, F6_num, F7_num, F8_num,

   F9_num, F10_num, F11_num, F12_num,

   F13_num

 };

 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]);

 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]);

 // Return whether or not this register is ever used as an argument. This

 // function is used on startup to build the trampoline stubs in generateOptoStub.

 // Registers not mentioned will be killed by the VM call in the trampoline, and

 // arguments in those registers not be available to the callee.

 bool Matcher::can_be_java_arg(int reg) {

   // We return true for all registers contained in iarg_reg[] and

   // farg_reg[] and their virtual halves.

   // We must include the virtual halves in order to get STDs and LDs

   // instead of STWs and LWs in the trampoline stubs.

   if (   reg == R3_num  || reg == R3_H_num

       || reg == R4_num  || reg == R4_H_num

       || reg == R5_num  || reg == R5_H_num

       || reg == R6_num  || reg == R6_H_num

       || reg == R7_num  || reg == R7_H_num

       || reg == R8_num  || reg == R8_H_num

       || reg == R9_num  || reg == R9_H_num

       || reg == R10_num || reg == R10_H_num)

     return true;

   if (   reg == F1_num  || reg == F1_H_num

       || reg == F2_num  || reg == F2_H_num

       || reg == F3_num  || reg == F3_H_num

       || reg == F4_num  || reg == F4_H_num

       || reg == F5_num  || reg == F5_H_num

       || reg == F6_num  || reg == F6_H_num

       || reg == F7_num  || reg == F7_H_num

       || reg == F8_num  || reg == F8_H_num

       || reg == F9_num  || reg == F9_H_num

       || reg == F10_num || reg == F10_H_num

       || reg == F11_num || reg == F11_H_num

       || reg == F12_num || reg == F12_H_num

       || reg == F13_num || reg == F13_H_num)

     return true;

   return false;

 }

 bool Matcher::is_spillable_arg(int reg) {

   return can_be_java_arg(reg);

 }

 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {

   return false;

 }

 // Register for DIVI projection of divmodI.

 RegMask Matcher::divI_proj_mask() {

   ShouldNotReachHere();

   return RegMask();

 }

 // Register for MODI projection of divmodI.

 RegMask Matcher::modI_proj_mask() {

   ShouldNotReachHere();

   return RegMask();

 }

 // Register for DIVL projection of divmodL.

 RegMask Matcher::divL_proj_mask() {

   ShouldNotReachHere();

   return RegMask();

 }

 // Register for MODL projection of divmodL.

 RegMask Matcher::modL_proj_mask() {

   ShouldNotReachHere();

   return RegMask();

 }

 const RegMask Matcher::method_handle_invoke_SP_save_mask() {

   return RegMask();

 }

 %}

 //----------ENCODING BLOCK-----------------------------------------------------

 // This block specifies the encoding classes used by the compiler to output

 // byte streams. Encoding classes are parameterized macros used by

 // Machine Instruction Nodes in order to generate the bit encoding of the

 // instruction. Operands specify their base encoding interface with the

 // interface keyword. There are currently supported four interfaces,

 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an

 // operand to generate a function which returns its register number when

 // queried. CONST_INTER causes an operand to generate a function which

 // returns the value of the constant when queried. MEMORY_INTER causes an

 // operand to generate four functions which return the Base Register, the

 // Index Register, the Scale Value, and the Offset Value of the operand when

 // queried. COND_INTER causes an operand to generate six functions which

 // return the encoding code (ie - encoding bits for the instruction)

 // associated with each basic boolean condition for a conditional instruction.

 //

 // Instructions specify two basic values for encoding. Again, a function

 // is available to check if the constant displacement is an oop. They use the

 // ins_encode keyword to specify their encoding classes (which must be

 // a sequence of enc_class names, and their parameters, specified in

 // the encoding block), and they use the

 // opcode keyword to specify, in order, their primary, secondary, and

 // tertiary opcode. Only the opcode sections which a particular instruction

 // needs for encoding need to be specified.

 encode %{

   enc_class enc_unimplemented %{

     // TODO: PPC port $archOpcode(ppc64Opcode_compound);

     MacroAssembler _masm(&cbuf);

     __ unimplemented("Unimplemented mach node encoding in AD file.", 13);

   %}

   enc_class enc_untested %{

 #ifdef ASSERT

     // TODO: PPC port $archOpcode(ppc64Opcode_compound);

     MacroAssembler _masm(&cbuf);

     __ untested("Untested mach node encoding in AD file.");

 #else

     // TODO: PPC port $archOpcode(ppc64Opcode_none);

 #endif

   %}

   enc_class enc_lbz(iRegIdst dst, memory mem) %{

     // TODO: PPC port $archOpcode(ppc64Opcode_lbz);

     MacroAssembler _masm(&cbuf);

     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);

     __ lbz($dst$$Register, Idisp, $mem$$base$$Register);

   %}

   // Load acquire.

   enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{

     // TODO: PPC port $archOpcode(ppc64Opcode_compound);

     MacroAssembler _masm(&cbuf);

     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);

     __ lbz($dst$$Register, Idisp, $mem$$base$$Register);

     __ twi_0($dst$$Register);

     __ isync();

   %}

   enc_class enc_lhz(iRegIdst dst, memory mem) %{

     // TODO: PPC port $archOpcode(ppc64Opcode_lhz);

     MacroAssembler _masm(&cbuf);

     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);

     __ lhz($dst$$Register, Idisp, $mem$$base$$Register);

   %}

   // Load acquire.

   enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{

     // TODO: PPC port $archOpcode(ppc64Opcode_compound);

     MacroAssembler _masm(&cbuf);

     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);

     __ lhz($dst$$Register, Idisp, $mem$$base$$Register);

     __ twi_0($dst$$Register);

     __ isync();

   %}

   enc_class enc_lwz(iRegIdst dst, memory mem) %{

     // TODO: PPC port $archOpcode(ppc64Opcode_lwz);

     MacroAssembler _masm(&cbuf);

     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);

     __ lwz($dst$$Register, Idisp, $mem$$base$$Register);

   %}

   // Load acquire.

   enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{

     // TODO: PPC port $archOpcode(ppc64Opcode_compound);

     MacroAssembler _masm(&cbuf);

     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);

     __ lwz($dst$$Register, Idisp, $mem$$base$$Register);

     __ twi_0($dst$$Register);

     __ isync();

   %}

   enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{

     // TODO: PPC port $archOpcode(ppc64Opcode_ld);

     MacroAssembler _masm(&cbuf);

     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);

     // Operand 'ds' requires 4-alignment.

     assert((Idisp & 0x3) == 0, "unaligned offset");

     __ ld($dst$$Register, Idisp, $mem$$base$$Register);

   %}

   // Load acquire.

   enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{

     // TODO: PPC port $archOpcode(ppc64Opcode_compound);

     MacroAssembler _masm(&cbuf);

     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);

     // Operand 'ds' requires 4-alignment.

     assert((Idisp & 0x3) == 0, "unaligned offset");

     __ ld($dst$$Register, Idisp, $mem$$base$$Register);

     __ twi_0($dst$$Register);

     __ isync();

   %}

   enc_class enc_lfd(RegF dst, memory mem) %{

     // TODO: PPC port $archOpcode(ppc64Opcode_lfd);

     MacroAssembler _masm(&cbuf);

     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);

     __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);

   %}

   enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{

     // TODO: PPC port $archOpcode(ppc64Opcode_ld);

     MacroAssembler _masm(&cbuf);

     int toc_offset = 0;

     if (!ra_->C->in_scratch_emit_size()) {

       address const_toc_addr;

       // Create a non-oop constant, no relocation needed.

       // If it is an IC, it has a virtual_call_Relocation.

       const_toc_addr = __ long_constant((jlong)$src$$constant);

       // Get the constant's TOC offset.

       toc_offset = __ offset_to_method_toc(const_toc_addr);

       // Keep the current instruction offset in mind.

       ((loadConLNode*)this)->_cbuf_insts_offset = __ offset();

     }

     __ ld($dst$$Register, toc_offset, $toc$$Register);

   %}

   enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{

     // TODO: PPC port $archOpcode(ppc64Opcode_addis);

     MacroAssembler _masm(&cbuf);

     if (!ra_->C->in_scratch_emit_size()) {

       address const_toc_addr;

       // Create a non-oop constant, no relocation needed.

       // If it is an IC, it has a virtual_call_Relocation.

       const_toc_addr = __ long_constant((jlong)$src$$constant);

       // Get the constant's TOC offset.

       const int toc_offset = __ offset_to_method_toc(const_toc_addr);

       // Store the toc offset of the constant.

       ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset;

       // Also keep the current instruction offset in mind.

       ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset();

     }

     __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));

   %}

 %} // encode

 source %{

 typedef struct {

   loadConL_hiNode *_large_hi;

   loadConL_loNode *_large_lo;

   loadConLNode    *_small;

   MachNode        *_last;

 } loadConLNodesTuple;

 loadConLNodesTuple loadConLNodesTuple_create(Compile *C, PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc,

                                              OptoReg::Name reg_second, OptoReg::Name reg_first) {

   loadConLNodesTuple nodes;

   const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;

   if (large_constant_pool) {

     // Create new nodes.

     loadConL_hiNode *m1 = new (C) loadConL_hiNode();

     loadConL_loNode *m2 = new (C) loadConL_loNode();

     // inputs for new nodes

     m1->add_req(NULL, toc);

     m2->add_req(NULL, m1);

     // operands for new nodes

     m1->_opnds[0] = new (C) iRegLdstOper(); // dst

     m1->_opnds[1] = immSrc;                 // src

     m1->_opnds[2] = new (C) iRegPdstOper(); // toc

     m2->_opnds[0] = new (C) iRegLdstOper(); // dst

     m2->_opnds[1] = immSrc;                 // src

     m2->_opnds[2] = new (C) iRegLdstOper(); // base

     // Initialize ins_attrib TOC fields.

     m1->_const_toc_offset = -1;

     m2->_const_toc_offset_hi_node = m1;

     // Initialize ins_attrib instruction offset.

     m1->_cbuf_insts_offset = -1;

     // register allocation for new nodes

     ra_->set_pair(m1->_idx, reg_second, reg_first);

     ra_->set_pair(m2->_idx, reg_second, reg_first);

     // Create result.

     nodes._large_hi = m1;

     nodes._large_lo = m2;

     nodes._small = NULL;

     nodes._last = nodes._large_lo;

     assert(m2->bottom_type()->isa_long(), "must be long");

   } else {

     loadConLNode *m2 = new (C) loadConLNode();

     // inputs for new nodes

     m2->add_req(NULL, toc);

     // operands for new nodes

     m2->_opnds[0] = new (C) iRegLdstOper(); // dst