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src/share/vm/c1/c1_LIR.cpp@2d8a650513c2
src/share/vm/c1/c1_LIR.cpp
Fri, 29 Apr 2016 00:06:10 +0800
- author
- aoqi
- date
- Fri, 29 Apr 2016 00:06:10 +0800
- changeset 1
- 2d8a650513c2
- parent 0
- f90c822e73f8
- child 6876
- 710a3c8b516e
- permissions
- -rw-r--r--
Added MIPS 64-bit port.
1 /*
2 * Copyright (c) 2000, 2014, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 /*
26 * This file has been modified by Loongson Technology in 2015. These
27 * modifications are Copyright (c) 2015 Loongson Technology, and are made
28 * available on the same license terms set forth above.
29 */
31 #include "precompiled.hpp"
32 #include "c1/c1_InstructionPrinter.hpp"
33 #include "c1/c1_LIR.hpp"
34 #include "c1/c1_LIRAssembler.hpp"
35 #include "c1/c1_ValueStack.hpp"
36 #include "ci/ciInstance.hpp"
37 #include "runtime/sharedRuntime.hpp"
39 Register LIR_OprDesc::as_register() const {
40 return FrameMap::cpu_rnr2reg(cpu_regnr());
41 }
43 Register LIR_OprDesc::as_register_lo() const {
44 return FrameMap::cpu_rnr2reg(cpu_regnrLo());
45 }
47 Register LIR_OprDesc::as_register_hi() const {
48 return FrameMap::cpu_rnr2reg(cpu_regnrHi());
49 }
51 #if defined(X86)
53 XMMRegister LIR_OprDesc::as_xmm_float_reg() const {
54 return FrameMap::nr2xmmreg(xmm_regnr());
55 }
57 XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
58 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");
59 return FrameMap::nr2xmmreg(xmm_regnrLo());
60 }
62 #endif // X86
64 #if defined(SPARC) || defined(PPC)
66 FloatRegister LIR_OprDesc::as_float_reg() const {
67 return FrameMap::nr2floatreg(fpu_regnr());
68 }
70 FloatRegister LIR_OprDesc::as_double_reg() const {
71 return FrameMap::nr2floatreg(fpu_regnrHi());
72 }
74 #endif
75 #ifdef MIPS64
77 FloatRegister LIR_OprDesc::as_float_reg() const {
78 return FrameMap::nr2floatreg(fpu_regnr());
79 }
81 FloatRegister LIR_OprDesc::as_double_reg() const {
82 return FrameMap::nr2floatreg(fpu_regnrHi());
83 }
85 FloatRegister LIR_OprDesc::as_fpu_lo() const {
86 return FrameMap::nr2floatreg(fpu_regnrLo());
87 }
89 FloatRegister LIR_OprDesc::as_fpu_hi() const {
90 return FrameMap::nr2floatreg(fpu_regnrHi());
91 }
93 #endif
95 #ifdef ARM
97 FloatRegister LIR_OprDesc::as_float_reg() const {
98 return as_FloatRegister(fpu_regnr());
99 }
101 FloatRegister LIR_OprDesc::as_double_reg() const {
102 return as_FloatRegister(fpu_regnrLo());
103 }
105 #endif
108 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
110 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
111 ValueTag tag = type->tag();
112 switch (tag) {
113 case metaDataTag : {
114 ClassConstant* c = type->as_ClassConstant();
115 if (c != NULL && !c->value()->is_loaded()) {
116 return LIR_OprFact::metadataConst(NULL);
117 } else if (c != NULL) {
118 return LIR_OprFact::metadataConst(c->value()->constant_encoding());
119 } else {
120 MethodConstant* m = type->as_MethodConstant();
121 assert (m != NULL, "not a class or a method?");
122 return LIR_OprFact::metadataConst(m->value()->constant_encoding());
123 }
124 }
125 case objectTag : {
126 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding());
127 }
128 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value());
129 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value());
130 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value());
131 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value());
132 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value());
133 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
134 }
135 }
138 LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) {
139 switch (type->tag()) {
140 case objectTag: return LIR_OprFact::oopConst(NULL);
141 case addressTag:return LIR_OprFact::addressConst(0);
142 case intTag: return LIR_OprFact::intConst(0);
143 case floatTag: return LIR_OprFact::floatConst(0.0);
144 case longTag: return LIR_OprFact::longConst(0);
145 case doubleTag: return LIR_OprFact::doubleConst(0.0);
146 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
147 }
148 return illegalOpr;
149 }
153 //---------------------------------------------------
156 LIR_Address::Scale LIR_Address::scale(BasicType type) {
157 int elem_size = type2aelembytes(type);
158 switch (elem_size) {
159 case 1: return LIR_Address::times_1;
160 case 2: return LIR_Address::times_2;
161 case 4: return LIR_Address::times_4;
162 case 8: return LIR_Address::times_8;
163 }
164 ShouldNotReachHere();
165 return LIR_Address::times_1;
166 }
169 #ifndef PRODUCT
170 void LIR_Address::verify() const {
171 #if defined(SPARC) || defined(PPC)
172 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
173 assert(disp() == 0 || index()->is_illegal(), "can't have both");
174 #endif
175 #ifdef ARM
176 assert(disp() == 0 || index()->is_illegal(), "can't have both");
177 // Note: offsets higher than 4096 must not be rejected here. They can
178 // be handled by the back-end or will be rejected if not.
179 #endif
180 #ifdef _LP64
181 assert(base()->is_cpu_register(), "wrong base operand");
182 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
183 #ifndef MIPS64
184 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
185 "wrong type for addresses");
186 #endif
187 #else
188 assert(base()->is_single_cpu(), "wrong base operand");
189 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
190 assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
191 "wrong type for addresses");
192 #endif
193 }
194 #endif
197 //---------------------------------------------------
199 char LIR_OprDesc::type_char(BasicType t) {
200 switch (t) {
201 case T_ARRAY:
202 t = T_OBJECT;
203 case T_BOOLEAN:
204 case T_CHAR:
205 case T_FLOAT:
206 case T_DOUBLE:
207 case T_BYTE:
208 case T_SHORT:
209 case T_INT:
210 case T_LONG:
211 case T_OBJECT:
212 case T_ADDRESS:
213 case T_VOID:
214 return ::type2char(t);
215 case T_METADATA:
216 return 'M';
217 case T_ILLEGAL:
218 return '?';
220 default:
221 ShouldNotReachHere();
222 return '?';
223 }
224 }
226 #ifndef PRODUCT
227 void LIR_OprDesc::validate_type() const {
229 #ifdef ASSERT
230 if (!is_pointer() && !is_illegal()) {
231 OprKind kindfield = kind_field(); // Factored out because of compiler bug, see 8002160
232 switch (as_BasicType(type_field())) {
233 case T_LONG:
234 assert((kindfield == cpu_register || kindfield == stack_value) &&
235 size_field() == double_size, "must match");
236 break;
237 case T_FLOAT:
238 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
239 assert((kindfield == fpu_register || kindfield == stack_value
240 ARM_ONLY(|| kindfield == cpu_register)
241 PPC_ONLY(|| kindfield == cpu_register) ) &&
242 size_field() == single_size, "must match");
243 break;
244 case T_DOUBLE:
245 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
246 assert((kindfield == fpu_register || kindfield == stack_value
247 ARM_ONLY(|| kindfield == cpu_register)
248 PPC_ONLY(|| kindfield == cpu_register) ) &&
249 size_field() == double_size, "must match");
250 break;
251 case T_BOOLEAN:
252 case T_CHAR:
253 case T_BYTE:
254 case T_SHORT:
255 case T_INT:
256 case T_ADDRESS:
257 case T_OBJECT:
258 case T_METADATA:
259 case T_ARRAY:
260 assert((kindfield == cpu_register || kindfield == stack_value) &&
261 size_field() == single_size, "must match");
262 break;
264 case T_ILLEGAL:
265 // XXX TKR also means unknown right now
266 // assert(is_illegal(), "must match");
267 break;
269 default:
270 ShouldNotReachHere();
271 }
272 }
273 #endif
275 }
276 #endif // PRODUCT
279 bool LIR_OprDesc::is_oop() const {
280 if (is_pointer()) {
281 return pointer()->is_oop_pointer();
282 } else {
283 OprType t= type_field();
284 assert(t != unknown_type, "not set");
285 return t == object_type;
286 }
287 }
291 void LIR_Op2::verify() const {
292 #ifdef ASSERT
293 switch (code()) {
294 case lir_cmove:
295 case lir_xchg:
296 break;
298 default:
299 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(),
300 "can't produce oops from arith");
301 }
303 if (TwoOperandLIRForm) {
304 switch (code()) {
305 case lir_add:
306 case lir_sub:
307 case lir_mul:
308 case lir_mul_strictfp:
309 case lir_div:
310 case lir_div_strictfp:
311 case lir_rem:
312 case lir_logic_and:
313 case lir_logic_or:
314 case lir_logic_xor:
315 case lir_shl:
316 case lir_shr:
317 assert(in_opr1() == result_opr(), "opr1 and result must match");
318 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
319 break;
321 // special handling for lir_ushr because of write barriers
322 case lir_ushr:
323 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant");
324 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
325 break;
327 }
328 }
329 #endif
330 }
333 #ifndef MIPS64
334 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block)
335 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
336 , _cond(cond)
337 , _type(type)
338 , _label(block->label())
339 , _block(block)
340 , _ublock(NULL)
341 , _stub(NULL) {
342 }
344 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) :
345 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
346 , _cond(cond)
347 , _type(type)
348 , _label(stub->entry())
349 , _block(NULL)
350 , _ublock(NULL)
351 , _stub(stub) {
352 }
354 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock)
355 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
356 , _cond(cond)
357 , _type(type)
358 , _label(block->label())
359 , _block(block)
360 , _ublock(ublock)
361 , _stub(NULL)
362 {
363 }
365 #else
366 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
367 BlockBegin* block):
368 LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
369 _cond(cond),
370 _type(type),
371 _label(block->label()),
372 _block(block),
373 _ublock(NULL),
374 _stub(NULL) {
375 }
377 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
378 CodeStub* stub):
379 LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
380 _cond(cond),
381 _type(type),
382 _label(stub->entry()),
383 _block(NULL),
384 _ublock(NULL),
385 _stub(stub) {
386 }
389 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
390 BlockBegin *block, BlockBegin *ublock):
391 LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
392 _cond(cond),
393 _type(type),
394 _label(block->label()),
395 _block(block),
396 _ublock(ublock),
397 _stub(NULL) {
398 }
400 #endif
402 void LIR_OpBranch::change_block(BlockBegin* b) {
403 assert(_block != NULL, "must have old block");
404 assert(_block->label() == label(), "must be equal");
406 _block = b;
407 _label = b->label();
408 }
410 void LIR_OpBranch::change_ublock(BlockBegin* b) {
411 assert(_ublock != NULL, "must have old block");
412 _ublock = b;
413 }
415 void LIR_OpBranch::negate_cond() {
416 switch (_cond) {
417 case lir_cond_equal: _cond = lir_cond_notEqual; break;
418 case lir_cond_notEqual: _cond = lir_cond_equal; break;
419 case lir_cond_less: _cond = lir_cond_greaterEqual; break;
420 case lir_cond_lessEqual: _cond = lir_cond_greater; break;
421 case lir_cond_greaterEqual: _cond = lir_cond_less; break;
422 case lir_cond_greater: _cond = lir_cond_lessEqual; break;
423 default: ShouldNotReachHere();
424 }
425 }
428 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass,
429 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
430 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch,
431 CodeStub* stub)
433 : LIR_Op(code, result, NULL)
434 , _object(object)
435 , _array(LIR_OprFact::illegalOpr)
436 , _klass(klass)
437 , _tmp1(tmp1)
438 , _tmp2(tmp2)
439 , _tmp3(tmp3)
440 , _fast_check(fast_check)
441 , _stub(stub)
442 , _info_for_patch(info_for_patch)
443 , _info_for_exception(info_for_exception)
444 , _profiled_method(NULL)
445 , _profiled_bci(-1)
446 , _should_profile(false)
447 {
448 if (code == lir_checkcast) {
449 assert(info_for_exception != NULL, "checkcast throws exceptions");
450 } else if (code == lir_instanceof) {
451 assert(info_for_exception == NULL, "instanceof throws no exceptions");
452 } else {
453 ShouldNotReachHere();
454 }
455 }
459 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception)
460 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL)
461 , _object(object)
462 , _array(array)
463 , _klass(NULL)
464 , _tmp1(tmp1)
465 , _tmp2(tmp2)
466 , _tmp3(tmp3)
467 , _fast_check(false)
468 , _stub(NULL)
469 , _info_for_patch(NULL)
470 , _info_for_exception(info_for_exception)
471 , _profiled_method(NULL)
472 , _profiled_bci(-1)
473 , _should_profile(false)
474 {
475 if (code == lir_store_check) {
476 _stub = new ArrayStoreExceptionStub(object, info_for_exception);
477 assert(info_for_exception != NULL, "store_check throws exceptions");
478 } else {
479 ShouldNotReachHere();
480 }
481 }
484 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length,
485 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info)
486 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info)
487 , _tmp(tmp)
488 , _src(src)
489 , _src_pos(src_pos)
490 , _dst(dst)
491 , _dst_pos(dst_pos)
492 , _flags(flags)
493 , _expected_type(expected_type)
494 , _length(length) {
495 _stub = new ArrayCopyStub(this);
496 }
498 LIR_OpUpdateCRC32::LIR_OpUpdateCRC32(LIR_Opr crc, LIR_Opr val, LIR_Opr res)
499 : LIR_Op(lir_updatecrc32, res, NULL)
500 , _crc(crc)
501 , _val(val) {
502 }
504 //-------------------verify--------------------------
506 void LIR_Op1::verify() const {
507 switch(code()) {
508 case lir_move:
509 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be");
510 break;
511 case lir_null_check:
512 assert(in_opr()->is_register(), "must be");
513 break;
514 case lir_return:
515 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be");
516 break;
517 }
518 }
520 void LIR_OpRTCall::verify() const {
521 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function");
522 }
524 //-------------------visits--------------------------
526 // complete rework of LIR instruction visitor.
527 // The virtual calls for each instruction type is replaced by a big
528 // switch that adds the operands for each instruction
530 void LIR_OpVisitState::visit(LIR_Op* op) {
531 // copy information from the LIR_Op
532 reset();
533 set_op(op);
535 switch (op->code()) {
537 // LIR_Op0
538 case lir_word_align: // result and info always invalid
539 case lir_backwardbranch_target: // result and info always invalid
540 case lir_build_frame: // result and info always invalid
541 case lir_fpop_raw: // result and info always invalid
542 case lir_24bit_FPU: // result and info always invalid
543 case lir_reset_FPU: // result and info always invalid
544 case lir_breakpoint: // result and info always invalid
545 case lir_membar: // result and info always invalid
546 case lir_membar_acquire: // result and info always invalid
547 case lir_membar_release: // result and info always invalid
548 case lir_membar_loadload: // result and info always invalid
549 case lir_membar_storestore: // result and info always invalid
550 case lir_membar_loadstore: // result and info always invalid
551 case lir_membar_storeload: // result and info always invalid
552 {
553 assert(op->as_Op0() != NULL, "must be");
554 assert(op->_info == NULL, "info not used by this instruction");
555 assert(op->_result->is_illegal(), "not used");
556 break;
557 }
559 case lir_nop: // may have info, result always invalid
560 case lir_std_entry: // may have result, info always invalid
561 case lir_osr_entry: // may have result, info always invalid
562 case lir_get_thread: // may have result, info always invalid
563 {
564 assert(op->as_Op0() != NULL, "must be");
565 if (op->_info != NULL) do_info(op->_info);
566 if (op->_result->is_valid()) do_output(op->_result);
567 break;
568 }
571 // LIR_OpLabel
572 case lir_label: // result and info always invalid
573 {
574 assert(op->as_OpLabel() != NULL, "must be");
575 assert(op->_info == NULL, "info not used by this instruction");
576 assert(op->_result->is_illegal(), "not used");
577 break;
578 }
581 // LIR_Op1
582 case lir_fxch: // input always valid, result and info always invalid
583 case lir_fld: // input always valid, result and info always invalid
584 case lir_ffree: // input always valid, result and info always invalid
585 case lir_push: // input always valid, result and info always invalid
586 case lir_pop: // input always valid, result and info always invalid
587 case lir_return: // input always valid, result and info always invalid
588 case lir_leal: // input and result always valid, info always invalid
589 case lir_neg: // input and result always valid, info always invalid
590 case lir_monaddr: // input and result always valid, info always invalid
591 case lir_null_check: // input and info always valid, result always invalid
592 case lir_move: // input and result always valid, may have info
593 case lir_pack64: // input and result always valid
594 case lir_unpack64: // input and result always valid
595 case lir_prefetchr: // input always valid, result and info always invalid
596 case lir_prefetchw: // input always valid, result and info always invalid
597 {
598 assert(op->as_Op1() != NULL, "must be");
599 LIR_Op1* op1 = (LIR_Op1*)op;
601 if (op1->_info) do_info(op1->_info);
602 if (op1->_opr->is_valid()) do_input(op1->_opr);
603 if (op1->_result->is_valid()) do_output(op1->_result);
605 break;
606 }
608 case lir_safepoint:
609 {
610 assert(op->as_Op1() != NULL, "must be");
611 LIR_Op1* op1 = (LIR_Op1*)op;
613 assert(op1->_info != NULL, ""); do_info(op1->_info);
614 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register
615 assert(op1->_result->is_illegal(), "safepoint does not produce value");
617 break;
618 }
620 // LIR_OpConvert;
621 case lir_convert: // input and result always valid, info always invalid
622 {
623 assert(op->as_OpConvert() != NULL, "must be");
624 LIR_OpConvert* opConvert = (LIR_OpConvert*)op;
626 assert(opConvert->_info == NULL, "must be");
627 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr);
628 if (opConvert->_result->is_valid()) do_output(opConvert->_result);
629 #ifdef PPC
630 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1);
631 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2);
632 #endif
633 do_stub(opConvert->_stub);
635 break;
636 }
638 // LIR_OpBranch;
639 case lir_branch: // may have info, input and result register always invalid
640 case lir_cond_float_branch: // may have info, input and result register always invalid
641 {
642 assert(op->as_OpBranch() != NULL, "must be");
643 LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
645 #ifdef MIPS64
646 if (opBranch->_opr1->is_valid()) do_input(opBranch->_opr1);
647 if (opBranch->_opr2->is_valid()) do_input(opBranch->_opr2);
648 if (opBranch->_tmp1->is_valid()) do_temp(opBranch->_tmp1);
649 if (opBranch->_tmp2->is_valid()) do_temp(opBranch->_tmp2);
650 if (opBranch->_tmp3->is_valid()) do_temp(opBranch->_tmp3);
651 if (opBranch->_tmp4->is_valid()) do_temp(opBranch->_tmp4);
652 if (opBranch->_tmp5->is_valid()) do_temp(opBranch->_tmp5);
653 #endif
654 if (opBranch->_info != NULL) do_info(opBranch->_info);
655 assert(opBranch->_result->is_illegal(), "not used");
656 if (opBranch->_stub != NULL) opBranch->stub()->visit(this);
658 break;
659 }
662 // LIR_OpAllocObj
663 case lir_alloc_object:
664 {
665 assert(op->as_OpAllocObj() != NULL, "must be");
666 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op;
668 if (opAllocObj->_info) do_info(opAllocObj->_info);
669 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr);
670 do_temp(opAllocObj->_opr);
671 }
672 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1);
673 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
674 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3);
675 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4);
676 #ifdef MIPS64
677 if (opAllocObj->_tmp5->is_valid()) do_temp(opAllocObj->_tmp5);
678 if (opAllocObj->_tmp6->is_valid()) do_temp(opAllocObj->_tmp6);
679 #endif
680 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result);
681 do_stub(opAllocObj->_stub);
682 break;
683 }
686 // LIR_OpRoundFP;
687 case lir_roundfp: {
688 assert(op->as_OpRoundFP() != NULL, "must be");
689 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op;
691 assert(op->_info == NULL, "info not used by this instruction");
692 assert(opRoundFP->_tmp->is_illegal(), "not used");
693 do_input(opRoundFP->_opr);
694 do_output(opRoundFP->_result);
696 break;
697 }
700 // LIR_Op2
701 #ifdef MIPS64
702 case lir_null_check_for_branch:
703 #else
704 case lir_cmp:
705 #endif
706 case lir_cmp_l2i:
707 case lir_ucmp_fd2i:
708 case lir_cmp_fd2i:
709 case lir_add:
710 case lir_sub:
711 case lir_mul:
712 case lir_div:
713 case lir_rem:
714 case lir_sqrt:
715 case lir_abs:
716 case lir_logic_and:
717 case lir_logic_or:
718 case lir_logic_xor:
719 case lir_shl:
720 case lir_shr:
721 case lir_ushr:
722 case lir_xadd:
723 case lir_xchg:
724 case lir_assert:
725 {
726 assert(op->as_Op2() != NULL, "must be");
727 LIR_Op2* op2 = (LIR_Op2*)op;
728 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
729 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
731 if (op2->_info) do_info(op2->_info);
732 if (op2->_opr1->is_valid()) do_input(op2->_opr1);
733 if (op2->_opr2->is_valid()) do_input(op2->_opr2);
734 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
735 if (op2->_result->is_valid()) do_output(op2->_result);
736 if (op->code() == lir_xchg || op->code() == lir_xadd) {
737 // on ARM and PPC, return value is loaded first so could
738 // destroy inputs. On other platforms that implement those
739 // (x86, sparc), the extra constrainsts are harmless.
740 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
741 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
742 }
744 break;
745 }
747 // special handling for cmove: right input operand must not be equal
748 // to the result operand, otherwise the backend fails
749 case lir_cmove:
750 {
751 assert(op->as_Op2() != NULL, "must be");
752 LIR_Op2* op2 = (LIR_Op2*)op;
754 assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() &&
755 op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
756 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used");
758 do_input(op2->_opr1);
759 do_input(op2->_opr2);
760 do_temp(op2->_opr2);
761 do_output(op2->_result);
763 break;
764 }
766 // vspecial handling for strict operations: register input operands
767 // as temp to guarantee that they do not overlap with other
768 // registers
769 case lir_mul_strictfp:
770 case lir_div_strictfp:
771 {
772 assert(op->as_Op2() != NULL, "must be");
773 LIR_Op2* op2 = (LIR_Op2*)op;
775 assert(op2->_info == NULL, "not used");
776 assert(op2->_opr1->is_valid(), "used");
777 assert(op2->_opr2->is_valid(), "used");
778 assert(op2->_result->is_valid(), "used");
779 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
780 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
782 do_input(op2->_opr1); do_temp(op2->_opr1);
783 do_input(op2->_opr2); do_temp(op2->_opr2);
784 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
785 do_output(op2->_result);
787 break;
788 }
790 case lir_throw: {
791 assert(op->as_Op2() != NULL, "must be");
792 LIR_Op2* op2 = (LIR_Op2*)op;
794 if (op2->_info) do_info(op2->_info);
795 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
796 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter
797 assert(op2->_result->is_illegal(), "no result");
798 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
799 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
801 break;
802 }
804 case lir_unwind: {
805 assert(op->as_Op1() != NULL, "must be");
806 LIR_Op1* op1 = (LIR_Op1*)op;
808 assert(op1->_info == NULL, "no info");
809 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr);
810 assert(op1->_result->is_illegal(), "no result");
812 break;
813 }
816 case lir_tan:
817 case lir_sin:
818 case lir_cos:
819 case lir_log:
820 case lir_log10:
821 case lir_exp: {
822 assert(op->as_Op2() != NULL, "must be");
823 LIR_Op2* op2 = (LIR_Op2*)op;
825 // On x86 tan/sin/cos need two temporary fpu stack slots and
826 // log/log10 need one so handle opr2 and tmp as temp inputs.
827 // Register input operand as temp to guarantee that it doesn't
828 // overlap with the input.
829 assert(op2->_info == NULL, "not used");
830 assert(op2->_tmp5->is_illegal(), "not used");
831 assert(op2->_tmp2->is_valid() == (op->code() == lir_exp), "not used");
832 assert(op2->_tmp3->is_valid() == (op->code() == lir_exp), "not used");
833 assert(op2->_tmp4->is_valid() == (op->code() == lir_exp), "not used");
834 assert(op2->_opr1->is_valid(), "used");
835 do_input(op2->_opr1); do_temp(op2->_opr1);
837 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
838 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
839 if (op2->_tmp2->is_valid()) do_temp(op2->_tmp2);
840 if (op2->_tmp3->is_valid()) do_temp(op2->_tmp3);
841 if (op2->_tmp4->is_valid()) do_temp(op2->_tmp4);
842 if (op2->_result->is_valid()) do_output(op2->_result);
844 break;
845 }
847 case lir_pow: {
848 assert(op->as_Op2() != NULL, "must be");
849 LIR_Op2* op2 = (LIR_Op2*)op;
851 // On x86 pow needs two temporary fpu stack slots: tmp1 and
852 // tmp2. Register input operands as temps to guarantee that it
853 // doesn't overlap with the temporary slots.
854 assert(op2->_info == NULL, "not used");
855 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid(), "used");
856 assert(op2->_tmp1->is_valid() && op2->_tmp2->is_valid() && op2->_tmp3->is_valid()
857 && op2->_tmp4->is_valid() && op2->_tmp5->is_valid(), "used");
858 assert(op2->_result->is_valid(), "used");
860 do_input(op2->_opr1); do_temp(op2->_opr1);
861 do_input(op2->_opr2); do_temp(op2->_opr2);
862 do_temp(op2->_tmp1);
863 do_temp(op2->_tmp2);
864 do_temp(op2->_tmp3);
865 do_temp(op2->_tmp4);
866 do_temp(op2->_tmp5);
867 do_output(op2->_result);
869 break;
870 }
872 // LIR_Op3
873 #ifdef MIPS64
874 case lir_frem:
875 #endif
876 case lir_idiv:
877 case lir_irem: {
878 assert(op->as_Op3() != NULL, "must be");
879 LIR_Op3* op3= (LIR_Op3*)op;
881 if (op3->_info) do_info(op3->_info);
882 if (op3->_opr1->is_valid()) do_input(op3->_opr1);
884 // second operand is input and temp, so ensure that second operand
885 // and third operand get not the same register
886 if (op3->_opr2->is_valid()) do_input(op3->_opr2);
887 if (op3->_opr2->is_valid()) do_temp(op3->_opr2);
888 if (op3->_opr3->is_valid()) do_temp(op3->_opr3);
890 if (op3->_result->is_valid()) do_output(op3->_result);
892 break;
893 }
896 // LIR_OpJavaCall
897 case lir_static_call:
898 case lir_optvirtual_call:
899 case lir_icvirtual_call:
900 case lir_virtual_call:
901 case lir_dynamic_call: {
902 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall();
903 assert(opJavaCall != NULL, "must be");
905 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver);
907 // only visit register parameters
908 int n = opJavaCall->_arguments->length();
909 for (int i = opJavaCall->_receiver->is_valid() ? 1 : 0; i < n; i++) {
910 if (!opJavaCall->_arguments->at(i)->is_pointer()) {
911 do_input(*opJavaCall->_arguments->adr_at(i));
912 }
913 }
915 if (opJavaCall->_info) do_info(opJavaCall->_info);
916 if (opJavaCall->is_method_handle_invoke()) {
917 opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr();
918 do_temp(opJavaCall->_method_handle_invoke_SP_save_opr);
919 }
920 do_call();
921 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result);
923 break;
924 }
927 // LIR_OpRTCall
928 case lir_rtcall: {
929 assert(op->as_OpRTCall() != NULL, "must be");
930 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op;
932 // only visit register parameters
933 int n = opRTCall->_arguments->length();
934 for (int i = 0; i < n; i++) {
935 if (!opRTCall->_arguments->at(i)->is_pointer()) {
936 do_input(*opRTCall->_arguments->adr_at(i));
937 }
938 }
939 if (opRTCall->_info) do_info(opRTCall->_info);
940 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp);
941 do_call();
942 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result);
944 break;
945 }
948 // LIR_OpArrayCopy
949 case lir_arraycopy: {
950 assert(op->as_OpArrayCopy() != NULL, "must be");
951 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op;
953 assert(opArrayCopy->_result->is_illegal(), "unused");
954 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src);
955 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos);
956 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst);
957 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
958 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length);
959 #ifndef MIPS64
960 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp);
961 #endif
962 if (opArrayCopy->_info) do_info(opArrayCopy->_info);
964 // the implementation of arraycopy always has a call into the runtime
965 do_call();
967 break;
968 }
971 // LIR_OpUpdateCRC32
972 case lir_updatecrc32: {
973 assert(op->as_OpUpdateCRC32() != NULL, "must be");
974 LIR_OpUpdateCRC32* opUp = (LIR_OpUpdateCRC32*)op;
976 assert(opUp->_crc->is_valid(), "used"); do_input(opUp->_crc); do_temp(opUp->_crc);
977 assert(opUp->_val->is_valid(), "used"); do_input(opUp->_val); do_temp(opUp->_val);
978 assert(opUp->_result->is_valid(), "used"); do_output(opUp->_result);
979 assert(opUp->_info == NULL, "no info for LIR_OpUpdateCRC32");
981 break;
982 }
985 // LIR_OpLock
986 case lir_lock:
987 case lir_unlock: {
988 assert(op->as_OpLock() != NULL, "must be");
989 LIR_OpLock* opLock = (LIR_OpLock*)op;
991 if (opLock->_info) do_info(opLock->_info);
993 // TODO: check if these operands really have to be temp
994 // (or if input is sufficient). This may have influence on the oop map!
995 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock);
996 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr);
997 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj);
999 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch);
1000 assert(opLock->_result->is_illegal(), "unused");
1002 do_stub(opLock->_stub);
1004 break;
1005 }
1008 // LIR_OpDelay
1009 case lir_delay_slot: {
1010 assert(op->as_OpDelay() != NULL, "must be");
1011 LIR_OpDelay* opDelay = (LIR_OpDelay*)op;
1013 visit(opDelay->delay_op());
1014 break;
1015 }
1017 // LIR_OpTypeCheck
1018 case lir_instanceof:
1019 case lir_checkcast:
1020 case lir_store_check: {
1021 assert(op->as_OpTypeCheck() != NULL, "must be");
1022 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op;
1024 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception);
1025 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch);
1026 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object);
1027 if (op->code() == lir_store_check && opTypeCheck->_object->is_valid()) {
1028 do_temp(opTypeCheck->_object);
1029 }
1030 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array);
1031 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1);
1032 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2);
1033 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3);
1034 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result);
1035 do_stub(opTypeCheck->_stub);
1036 break;
1037 }
1039 // LIR_OpCompareAndSwap
1040 case lir_cas_long:
1041 case lir_cas_obj:
1042 case lir_cas_int: {
1043 assert(op->as_OpCompareAndSwap() != NULL, "must be");
1044 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op;
1046 assert(opCompareAndSwap->_addr->is_valid(), "used");
1047 assert(opCompareAndSwap->_cmp_value->is_valid(), "used");
1048 assert(opCompareAndSwap->_new_value->is_valid(), "used");
1049 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info);
1050 do_input(opCompareAndSwap->_addr);
1051 do_temp(opCompareAndSwap->_addr);
1052 do_input(opCompareAndSwap->_cmp_value);
1053 do_temp(opCompareAndSwap->_cmp_value);
1054 do_input(opCompareAndSwap->_new_value);
1055 do_temp(opCompareAndSwap->_new_value);
1056 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1);
1057 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2);
1058 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result);
1060 break;
1061 }
1064 // LIR_OpAllocArray;
1065 case lir_alloc_array: {
1066 assert(op->as_OpAllocArray() != NULL, "must be");
1067 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op;
1069 if (opAllocArray->_info) do_info(opAllocArray->_info);
1070 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass);
1071 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len);
1072 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1);
1073 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2);
1074 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3);
1075 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4);
1076 #ifdef MIPS64
1077 if (opAllocArray->_tmp5->is_valid()) do_temp(opAllocArray->_tmp5);
1078 #endif
1079 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result);
1080 do_stub(opAllocArray->_stub);
1081 break;
1082 }
1084 // LIR_OpProfileCall:
1085 case lir_profile_call: {
1086 assert(op->as_OpProfileCall() != NULL, "must be");
1087 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op;
1089 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv);
1090 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo);
1091 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1);
1092 break;
1093 }
1095 // LIR_OpProfileType:
1096 case lir_profile_type: {
1097 assert(op->as_OpProfileType() != NULL, "must be");
1098 LIR_OpProfileType* opProfileType = (LIR_OpProfileType*)op;
1100 do_input(opProfileType->_mdp); do_temp(opProfileType->_mdp);
1101 do_input(opProfileType->_obj);
1102 do_temp(opProfileType->_tmp);
1103 break;
1104 }
1105 default:
1106 ShouldNotReachHere();
1107 }
1108 }
1111 void LIR_OpVisitState::do_stub(CodeStub* stub) {
1112 if (stub != NULL) {
1113 stub->visit(this);
1114 }
1115 }
1117 XHandlers* LIR_OpVisitState::all_xhandler() {
1118 XHandlers* result = NULL;
1120 int i;
1121 for (i = 0; i < info_count(); i++) {
1122 if (info_at(i)->exception_handlers() != NULL) {
1123 result = info_at(i)->exception_handlers();
1124 break;
1125 }
1126 }
1128 #ifdef ASSERT
1129 for (i = 0; i < info_count(); i++) {
1130 assert(info_at(i)->exception_handlers() == NULL ||
1131 info_at(i)->exception_handlers() == result,
1132 "only one xhandler list allowed per LIR-operation");
1133 }
1134 #endif
1136 if (result != NULL) {
1137 return result;
1138 } else {
1139 return new XHandlers();
1140 }
1142 return result;
1143 }
1146 #ifdef ASSERT
1147 bool LIR_OpVisitState::no_operands(LIR_Op* op) {
1148 visit(op);
1150 return opr_count(inputMode) == 0 &&
1151 opr_count(outputMode) == 0 &&
1152 opr_count(tempMode) == 0 &&
1153 info_count() == 0 &&
1154 !has_call() &&
1155 !has_slow_case();
1156 }
1157 #endif
1159 //---------------------------------------------------
1162 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) {
1163 masm->emit_call(this);
1164 }
1166 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) {
1167 masm->emit_rtcall(this);
1168 }
1170 void LIR_OpLabel::emit_code(LIR_Assembler* masm) {
1171 masm->emit_opLabel(this);
1172 }
1174 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) {
1175 masm->emit_arraycopy(this);
1176 masm->append_code_stub(stub());
1177 }
1179 void LIR_OpUpdateCRC32::emit_code(LIR_Assembler* masm) {
1180 masm->emit_updatecrc32(this);
1181 }
1183 void LIR_Op0::emit_code(LIR_Assembler* masm) {
1184 masm->emit_op0(this);
1185 }
1187 void LIR_Op1::emit_code(LIR_Assembler* masm) {
1188 masm->emit_op1(this);
1189 }
1191 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) {
1192 masm->emit_alloc_obj(this);
1193 masm->append_code_stub(stub());
1194 }
1196 void LIR_OpBranch::emit_code(LIR_Assembler* masm) {
1197 masm->emit_opBranch(this);
1198 if (stub()) {
1199 masm->append_code_stub(stub());
1200 }
1201 }
1203 void LIR_OpConvert::emit_code(LIR_Assembler* masm) {
1204 masm->emit_opConvert(this);
1205 if (stub() != NULL) {
1206 masm->append_code_stub(stub());
1207 }
1208 }
1210 void LIR_Op2::emit_code(LIR_Assembler* masm) {
1211 masm->emit_op2(this);
1212 }
1214 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) {
1215 masm->emit_alloc_array(this);
1216 masm->append_code_stub(stub());
1217 }
1219 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) {
1220 masm->emit_opTypeCheck(this);
1221 if (stub()) {
1222 masm->append_code_stub(stub());
1223 }
1224 }
1226 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) {
1227 masm->emit_compare_and_swap(this);
1228 }
1230 void LIR_Op3::emit_code(LIR_Assembler* masm) {
1231 masm->emit_op3(this);
1232 }
1234 void LIR_OpLock::emit_code(LIR_Assembler* masm) {
1235 masm->emit_lock(this);
1236 if (stub()) {
1237 masm->append_code_stub(stub());
1238 }
1239 }
1241 #ifdef ASSERT
1242 void LIR_OpAssert::emit_code(LIR_Assembler* masm) {
1243 masm->emit_assert(this);
1244 }
1245 #endif
1247 void LIR_OpDelay::emit_code(LIR_Assembler* masm) {
1248 masm->emit_delay(this);
1249 }
1251 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) {
1252 masm->emit_profile_call(this);
1253 }
1255 void LIR_OpProfileType::emit_code(LIR_Assembler* masm) {
1256 masm->emit_profile_type(this);
1257 }
1259 // LIR_List
1260 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block)
1261 : _operations(8)
1262 , _compilation(compilation)
1263 #ifndef PRODUCT
1264 , _block(block)
1265 #endif
1266 #ifdef ASSERT
1267 , _file(NULL)
1268 , _line(0)
1269 #endif
1270 { }
1273 #ifdef ASSERT
1274 void LIR_List::set_file_and_line(const char * file, int line) {
1275 const char * f = strrchr(file, '/');
1276 if (f == NULL) f = strrchr(file, '\\');
1277 if (f == NULL) {
1278 f = file;
1279 } else {
1280 f++;
1281 }
1282 _file = f;
1283 _line = line;
1284 }
1285 #endif
1288 void LIR_List::append(LIR_InsertionBuffer* buffer) {
1289 assert(this == buffer->lir_list(), "wrong lir list");
1290 const int n = _operations.length();
1292 if (buffer->number_of_ops() > 0) {
1293 // increase size of instructions list
1294 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL);
1295 // insert ops from buffer into instructions list
1296 int op_index = buffer->number_of_ops() - 1;
1297 int ip_index = buffer->number_of_insertion_points() - 1;
1298 int from_index = n - 1;
1299 int to_index = _operations.length() - 1;
1300 for (; ip_index >= 0; ip_index --) {
1301 int index = buffer->index_at(ip_index);
1302 // make room after insertion point
1303 while (index < from_index) {
1304 _operations.at_put(to_index --, _operations.at(from_index --));
1305 }
1306 // insert ops from buffer
1307 for (int i = buffer->count_at(ip_index); i > 0; i --) {
1308 _operations.at_put(to_index --, buffer->op_at(op_index --));
1309 }
1310 }
1311 }
1313 buffer->finish();
1314 }
1317 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) {
1318 assert(reg->type() == T_OBJECT, "bad reg");
1319 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info));
1320 }
1322 void LIR_List::klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info) {
1323 assert(reg->type() == T_METADATA, "bad reg");
1324 append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg, T_METADATA, lir_patch_normal, info));
1325 }
1327 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1328 append(new LIR_Op1(
1329 lir_move,
1330 LIR_OprFact::address(addr),
1331 src,
1332 addr->type(),
1333 patch_code,
1334 info));
1335 }
1338 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1339 append(new LIR_Op1(
1340 lir_move,
1341 LIR_OprFact::address(address),
1342 dst,
1343 address->type(),
1344 patch_code,
1345 info, lir_move_volatile));
1346 }
1348 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1349 #ifndef MIPS64
1350 append(new LIR_Op1(
1351 lir_move,
1352 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1353 dst,
1354 type,
1355 patch_code,
1356 info, lir_move_volatile));
1357 #else
1358 add(base, offset, base);
1359 append(new LIR_Op1(
1360 lir_move,
1361 LIR_OprFact::address(new LIR_Address(base, 0, type)),
1362 dst,
1363 type,
1364 patch_code,
1365 info, lir_move_volatile));
1366 #endif
1367 }
1370 void LIR_List::prefetch(LIR_Address* addr, bool is_store) {
1371 append(new LIR_Op1(
1372 is_store ? lir_prefetchw : lir_prefetchr,
1373 LIR_OprFact::address(addr)));
1374 }
1377 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1378 append(new LIR_Op1(
1379 lir_move,
1380 LIR_OprFact::intConst(v),
1381 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1382 type,
1383 patch_code,
1384 info));
1385 }
1388 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1389 append(new LIR_Op1(
1390 lir_move,
1391 LIR_OprFact::oopConst(o),
1392 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1393 type,
1394 patch_code,
1395 info));
1396 }
1399 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1400 append(new LIR_Op1(
1401 lir_move,
1402 src,
1403 LIR_OprFact::address(addr),
1404 addr->type(),
1405 patch_code,
1406 info));
1407 }
1410 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1411 append(new LIR_Op1(
1412 lir_move,
1413 src,
1414 LIR_OprFact::address(addr),
1415 addr->type(),
1416 patch_code,
1417 info,
1418 lir_move_volatile));
1419 }
1421 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1422 #ifndef MIPS64
1423 append(new LIR_Op1(
1424 lir_move,
1425 src,
1426 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1427 type,
1428 patch_code,
1429 info, lir_move_volatile));
1430 #else
1431 add(base, offset, base);
1432 append(new LIR_Op1(
1433 lir_move,
1434 src,
1435 LIR_OprFact::address(new LIR_Address(base, 0, type)),
1436 type,
1437 patch_code,
1438 info, lir_move_volatile));
1440 #endif
1442 }
1444 #ifdef MIPS64
1445 void LIR_List::frem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1446 append(new LIR_Op3(
1447 lir_frem,
1448 left,
1449 right,
1450 tmp,
1451 res,
1452 info));
1453 }
1454 #endif
1456 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1457 append(new LIR_Op3(
1458 lir_idiv,
1459 left,
1460 right,
1461 tmp,
1462 res,
1463 info));
1464 }
1467 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1468 append(new LIR_Op3(
1469 lir_idiv,
1470 left,
1471 LIR_OprFact::intConst(right),
1472 tmp,
1473 res,
1474 info));
1475 }
1478 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1479 append(new LIR_Op3(
1480 lir_irem,
1481 left,
1482 right,
1483 tmp,
1484 res,
1485 info));
1486 }
1489 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1490 append(new LIR_Op3(
1491 lir_irem,
1492 left,
1493 LIR_OprFact::intConst(right),
1494 tmp,
1495 res,
1496 info));
1497 }
1500 #ifndef MIPS64
1501 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1502 append(new LIR_Op2(
1503 lir_cmp,
1504 condition,
1505 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)),
1506 LIR_OprFact::intConst(c),
1507 info));
1508 }
1511 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) {
1512 append(new LIR_Op2(
1513 lir_cmp,
1514 condition,
1515 reg,
1516 LIR_OprFact::address(addr),
1517 info));
1518 }
1520 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,
1521 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1522 append(new LIR_OpAllocObj(
1523 klass,
1524 dst,
1525 t1,
1526 t2,
1527 t3,
1528 t4,
1529 header_size,
1530 object_size,
1531 init_check,
1532 stub));
1533 }
1535 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) {
1536 append(new LIR_OpAllocArray(
1537 klass,
1538 len,
1539 dst,
1540 t1,
1541 t2,
1542 t3,
1543 t4,
1544 type,
1545 stub));
1546 }
1547 #else
1548 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, LIR_Opr t5, LIR_Opr t6,
1549 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1550 append(new LIR_OpAllocObj(
1551 klass,
1552 dst,
1553 t1,
1554 t2,
1555 t3,
1556 t4,
1557 t5,
1558 t6,
1559 header_size,
1560 object_size,
1561 init_check,
1562 stub));
1563 }
1564 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, LIR_Opr t5,
1565 BasicType type, LIR_Opr klass, CodeStub* stub) {
1566 append(new LIR_OpAllocArray(
1567 klass,
1568 len,
1569 dst,
1570 t1,
1571 t2,
1572 t3,
1573 t4,
1574 t5,
1575 type,
1576 stub));
1577 }
1579 #endif
1581 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1582 append(new LIR_Op2(
1583 lir_shl,
1584 value,
1585 count,
1586 dst,
1587 tmp));
1588 }
1590 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1591 append(new LIR_Op2(
1592 lir_shr,
1593 value,
1594 count,
1595 dst,
1596 tmp));
1597 }
1600 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1601 append(new LIR_Op2(
1602 lir_ushr,
1603 value,
1604 count,
1605 dst,
1606 tmp));
1607 }
1609 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) {
1610 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i,
1611 left,
1612 right,
1613 dst));
1614 }
1616 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) {
1617 append(new LIR_OpLock(
1618 lir_lock,
1619 hdr,
1620 obj,
1621 lock,
1622 scratch,
1623 stub,
1624 info));
1625 }
1627 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) {
1628 append(new LIR_OpLock(
1629 lir_unlock,
1630 hdr,
1631 obj,
1632 lock,
1633 scratch,
1634 stub,
1635 NULL));
1636 }
1639 void check_LIR() {
1640 // cannot do the proper checking as PRODUCT and other modes return different results
1641 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table");
1642 }
1646 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass,
1647 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check,
1648 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub,
1649 ciMethod* profiled_method, int profiled_bci) {
1650 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass,
1651 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub);
1652 if (profiled_method != NULL) {
1653 c->set_profiled_method(profiled_method);
1654 c->set_profiled_bci(profiled_bci);
1655 c->set_should_profile(true);
1656 }
1657 append(c);
1658 }
1660 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) {
1661 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL);
1662 if (profiled_method != NULL) {
1663 c->set_profiled_method(profiled_method);
1664 c->set_profiled_bci(profiled_bci);
1665 c->set_should_profile(true);
1666 }
1667 append(c);
1668 }
1670 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
1671 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) {
1672 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception);
1673 if (profiled_method != NULL) {
1674 c->set_profiled_method(profiled_method);
1675 c->set_profiled_bci(profiled_bci);
1676 c->set_should_profile(true);
1677 }
1678 append(c);
1679 }
1681 #ifndef MIPS64
1682 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1683 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1684 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
1685 }
1687 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1688 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1689 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result));
1690 }
1692 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1693 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1694 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result));
1695 }
1696 #else
1697 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1698 // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value,
1699 // // implying successful swap of new_value into addr
1700 append(new LIR_OpCompareAndSwap(lir_cas_long,
1701 addr,
1702 cmp_value,
1703 new_value,
1704 t1,
1705 t2,
1706 result));
1707 }
1709 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1710 // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value,
1711 // // implying successful swap of new_value into addr
1712 append(new LIR_OpCompareAndSwap(lir_cas_obj,
1713 addr,
1714 cmp_value,
1715 new_value,
1716 t1,
1717 t2,
1718 result));
1719 }
1721 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1722 // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value,
1723 // // implying successful swap of new_value into addr
1724 append(new LIR_OpCompareAndSwap(lir_cas_int,
1725 addr,
1726 cmp_value,
1727 new_value,
1728 t1,
1729 t2,
1730 result));
1731 }
1732 #endif
1735 #ifdef PRODUCT
1737 void print_LIR(BlockList* blocks) {
1738 }
1740 #else
1741 // LIR_OprDesc
1742 void LIR_OprDesc::print() const {
1743 print(tty);
1744 }
1746 void LIR_OprDesc::print(outputStream* out) const {
1747 if (is_illegal()) {
1748 return;
1749 }
1751 out->print("[");
1752 if (is_pointer()) {
1753 pointer()->print_value_on(out);
1754 } else if (is_single_stack()) {
1755 out->print("stack:%d", single_stack_ix());
1756 } else if (is_double_stack()) {
1757 out->print("dbl_stack:%d",double_stack_ix());
1758 } else if (is_virtual()) {
1759 out->print("R%d", vreg_number());
1760 } else if (is_single_cpu()) {
1761 out->print("%s", as_register()->name());
1762 } else if (is_double_cpu()) {
1763 out->print("%s", as_register_hi()->name());
1764 out->print("%s", as_register_lo()->name());
1765 #if defined(X86)
1766 } else if (is_single_xmm()) {
1767 out->print("%s", as_xmm_float_reg()->name());
1768 } else if (is_double_xmm()) {
1769 out->print("%s", as_xmm_double_reg()->name());
1770 } else if (is_single_fpu()) {
1771 out->print("fpu%d", fpu_regnr());
1772 } else if (is_double_fpu()) {
1773 out->print("fpu%d", fpu_regnrLo());
1774 #elif defined(ARM)
1775 } else if (is_single_fpu()) {
1776 out->print("s%d", fpu_regnr());
1777 } else if (is_double_fpu()) {
1778 out->print("d%d", fpu_regnrLo() >> 1);
1779 #else
1780 } else if (is_single_fpu()) {
1781 out->print("%s", as_float_reg()->name());
1782 } else if (is_double_fpu()) {
1783 out->print("%s", as_double_reg()->name());
1784 #endif
1786 } else if (is_illegal()) {
1787 out->print("-");
1788 } else {
1789 out->print("Unknown Operand");
1790 }
1791 if (!is_illegal()) {
1792 out->print("|%c", type_char());
1793 }
1794 if (is_register() && is_last_use()) {
1795 out->print("(last_use)");
1796 }
1797 out->print("]");
1798 }
1801 // LIR_Address
1802 void LIR_Const::print_value_on(outputStream* out) const {
1803 switch (type()) {
1804 case T_ADDRESS:out->print("address:%d",as_jint()); break;
1805 case T_INT: out->print("int:%d", as_jint()); break;
1806 case T_LONG: out->print("lng:" JLONG_FORMAT, as_jlong()); break;
1807 case T_FLOAT: out->print("flt:%f", as_jfloat()); break;
1808 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break;
1809 case T_OBJECT: out->print("obj:" INTPTR_FORMAT, p2i(as_jobject())); break;
1810 case T_METADATA: out->print("metadata:" INTPTR_FORMAT, p2i(as_metadata()));break;
1811 default: out->print("%3d:0x" UINT64_FORMAT_X, type(), (uint64_t)as_jlong()); break;
1812 }
1813 }
1815 // LIR_Address
1816 void LIR_Address::print_value_on(outputStream* out) const {
1817 out->print("Base:"); _base->print(out);
1818 #ifndef MIPS64
1819 if (!_index->is_illegal()) {
1820 out->print(" Index:"); _index->print(out);
1821 switch (scale()) {
1822 case times_1: break;
1823 case times_2: out->print(" * 2"); break;
1824 case times_4: out->print(" * 4"); break;
1825 case times_8: out->print(" * 8"); break;
1826 }
1827 }
1828 #endif
1829 out->print(" Disp: " INTX_FORMAT, _disp);
1830 }
1832 // debug output of block header without InstructionPrinter
1833 // (because phi functions are not necessary for LIR)
1834 static void print_block(BlockBegin* x) {
1835 // print block id
1836 BlockEnd* end = x->end();
1837 tty->print("B%d ", x->block_id());
1839 // print flags
1840 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std ");
1841 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr ");
1842 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex ");
1843 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr ");
1844 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb ");
1845 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh ");
1846 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le ");
1848 // print block bci range
1849 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci()));
1851 // print predecessors and successors
1852 if (x->number_of_preds() > 0) {
1853 tty->print("preds: ");
1854 for (int i = 0; i < x->number_of_preds(); i ++) {
1855 tty->print("B%d ", x->pred_at(i)->block_id());
1856 }
1857 }
1859 if (x->number_of_sux() > 0) {
1860 tty->print("sux: ");
1861 for (int i = 0; i < x->number_of_sux(); i ++) {
1862 tty->print("B%d ", x->sux_at(i)->block_id());
1863 }
1864 }
1866 // print exception handlers
1867 if (x->number_of_exception_handlers() > 0) {
1868 tty->print("xhandler: ");
1869 for (int i = 0; i < x->number_of_exception_handlers(); i++) {
1870 tty->print("B%d ", x->exception_handler_at(i)->block_id());
1871 }
1872 }
1874 tty->cr();
1875 }
1877 void print_LIR(BlockList* blocks) {
1878 tty->print_cr("LIR:");
1879 int i;
1880 for (i = 0; i < blocks->length(); i++) {
1881 BlockBegin* bb = blocks->at(i);
1882 print_block(bb);
1883 tty->print("__id_Instruction___________________________________________"); tty->cr();
1884 bb->lir()->print_instructions();
1885 }
1886 }
1888 void LIR_List::print_instructions() {
1889 for (int i = 0; i < _operations.length(); i++) {
1890 _operations.at(i)->print(); tty->cr();
1891 }
1892 tty->cr();
1893 }
1895 // LIR_Ops printing routines
1896 // LIR_Op
1897 void LIR_Op::print_on(outputStream* out) const {
1898 if (id() != -1 || PrintCFGToFile) {
1899 out->print("%4d ", id());
1900 } else {
1901 out->print(" ");
1902 }
1903 out->print("%s ", name());
1904 print_instr(out);
1905 if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci());
1906 #ifdef ASSERT
1907 if (Verbose && _file != NULL) {
1908 out->print(" (%s:%d)", _file, _line);
1909 }
1910 #endif
1911 }
1913 const char * LIR_Op::name() const {
1914 const char* s = NULL;
1915 switch(code()) {
1916 // LIR_Op0
1917 case lir_membar: s = "membar"; break;
1918 case lir_membar_acquire: s = "membar_acquire"; break;
1919 case lir_membar_release: s = "membar_release"; break;
1920 case lir_membar_loadload: s = "membar_loadload"; break;
1921 case lir_membar_storestore: s = "membar_storestore"; break;
1922 case lir_membar_loadstore: s = "membar_loadstore"; break;
1923 case lir_membar_storeload: s = "membar_storeload"; break;
1924 case lir_word_align: s = "word_align"; break;
1925 case lir_label: s = "label"; break;
1926 case lir_nop: s = "nop"; break;
1927 case lir_backwardbranch_target: s = "backbranch"; break;
1928 case lir_std_entry: s = "std_entry"; break;
1929 case lir_osr_entry: s = "osr_entry"; break;
1930 case lir_build_frame: s = "build_frm"; break;
1931 case lir_fpop_raw: s = "fpop_raw"; break;
1932 case lir_24bit_FPU: s = "24bit_FPU"; break;
1933 case lir_reset_FPU: s = "reset_FPU"; break;
1934 case lir_breakpoint: s = "breakpoint"; break;
1935 case lir_get_thread: s = "get_thread"; break;
1936 // LIR_Op1
1937 case lir_fxch: s = "fxch"; break;
1938 case lir_fld: s = "fld"; break;
1939 case lir_ffree: s = "ffree"; break;
1940 case lir_push: s = "push"; break;
1941 case lir_pop: s = "pop"; break;
1942 case lir_null_check: s = "null_check"; break;
1943 case lir_return: s = "return"; break;
1944 case lir_safepoint: s = "safepoint"; break;
1945 case lir_neg: s = "neg"; break;
1946 case lir_leal: s = "leal"; break;
1947 case lir_branch: s = "branch"; break;
1948 case lir_cond_float_branch: s = "flt_cond_br"; break;
1949 case lir_move: s = "move"; break;
1950 case lir_roundfp: s = "roundfp"; break;
1951 case lir_rtcall: s = "rtcall"; break;
1952 case lir_throw: s = "throw"; break;
1953 case lir_unwind: s = "unwind"; break;
1954 case lir_convert: s = "convert"; break;
1955 case lir_alloc_object: s = "alloc_obj"; break;
1956 case lir_monaddr: s = "mon_addr"; break;
1957 case lir_pack64: s = "pack64"; break;
1958 case lir_unpack64: s = "unpack64"; break;
1959 // LIR_Op2
1960 #ifdef MIPS64
1961 case lir_null_check_for_branch: s = "null_check_for_branch"; break;
1962 #else
1963 case lir_cmp: s = "cmp"; break;
1964 #endif
1965 case lir_cmp_l2i: s = "cmp_l2i"; break;
1966 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break;
1967 case lir_cmp_fd2i: s = "comp_fd2i"; break;
1968 case lir_cmove: s = "cmove"; break;
1969 case lir_add: s = "add"; break;
1970 case lir_sub: s = "sub"; break;
1971 case lir_mul: s = "mul"; break;
1972 case lir_mul_strictfp: s = "mul_strictfp"; break;
1973 case lir_div: s = "div"; break;
1974 case lir_div_strictfp: s = "div_strictfp"; break;
1975 case lir_rem: s = "rem"; break;
1976 case lir_abs: s = "abs"; break;
1977 case lir_sqrt: s = "sqrt"; break;
1978 case lir_sin: s = "sin"; break;
1979 case lir_cos: s = "cos"; break;
1980 case lir_tan: s = "tan"; break;
1981 case lir_log: s = "log"; break;
1982 case lir_log10: s = "log10"; break;
1983 case lir_exp: s = "exp"; break;
1984 case lir_pow: s = "pow"; break;
1985 case lir_logic_and: s = "logic_and"; break;
1986 case lir_logic_or: s = "logic_or"; break;
1987 case lir_logic_xor: s = "logic_xor"; break;
1988 case lir_shl: s = "shift_left"; break;
1989 case lir_shr: s = "shift_right"; break;
1990 case lir_ushr: s = "ushift_right"; break;
1991 case lir_alloc_array: s = "alloc_array"; break;
1992 case lir_xadd: s = "xadd"; break;
1993 case lir_xchg: s = "xchg"; break;
1994 // LIR_Op3
1995 #ifdef MIPS64
1996 case lir_frem: s = "frem"; break;
1997 #endif
1998 case lir_idiv: s = "idiv"; break;
1999 case lir_irem: s = "irem"; break;
2000 // LIR_OpJavaCall
2001 case lir_static_call: s = "static"; break;
2002 case lir_optvirtual_call: s = "optvirtual"; break;
2003 case lir_icvirtual_call: s = "icvirtual"; break;
2004 case lir_virtual_call: s = "virtual"; break;
2005 case lir_dynamic_call: s = "dynamic"; break;
2006 // LIR_OpArrayCopy
2007 case lir_arraycopy: s = "arraycopy"; break;
2008 // LIR_OpUpdateCRC32
2009 case lir_updatecrc32: s = "updatecrc32"; break;
2010 // LIR_OpLock
2011 case lir_lock: s = "lock"; break;
2012 case lir_unlock: s = "unlock"; break;
2013 // LIR_OpDelay
2014 case lir_delay_slot: s = "delay"; break;
2015 // LIR_OpTypeCheck
2016 case lir_instanceof: s = "instanceof"; break;
2017 case lir_checkcast: s = "checkcast"; break;
2018 case lir_store_check: s = "store_check"; break;
2019 // LIR_OpCompareAndSwap
2020 case lir_cas_long: s = "cas_long"; break;
2021 case lir_cas_obj: s = "cas_obj"; break;
2022 case lir_cas_int: s = "cas_int"; break;
2023 // LIR_OpProfileCall
2024 case lir_profile_call: s = "profile_call"; break;
2025 // LIR_OpProfileType
2026 case lir_profile_type: s = "profile_type"; break;
2027 // LIR_OpAssert
2028 #ifdef ASSERT
2029 case lir_assert: s = "assert"; break;
2030 #endif
2031 case lir_none: ShouldNotReachHere();break;
2032 default: s = "illegal_op"; break;
2033 }
2034 return s;
2035 }
2037 // LIR_OpJavaCall
2038 void LIR_OpJavaCall::print_instr(outputStream* out) const {
2039 out->print("call: ");
2040 out->print("[addr: " INTPTR_FORMAT "]", p2i(address()));
2041 if (receiver()->is_valid()) {
2042 out->print(" [recv: "); receiver()->print(out); out->print("]");
2043 }
2044 if (result_opr()->is_valid()) {
2045 out->print(" [result: "); result_opr()->print(out); out->print("]");
2046 }
2047 }
2049 // LIR_OpLabel
2050 void LIR_OpLabel::print_instr(outputStream* out) const {
2051 out->print("[label:" INTPTR_FORMAT "]", p2i(_label));
2052 }
2054 // LIR_OpArrayCopy
2055 void LIR_OpArrayCopy::print_instr(outputStream* out) const {
2056 src()->print(out); out->print(" ");
2057 src_pos()->print(out); out->print(" ");
2058 dst()->print(out); out->print(" ");
2059 dst_pos()->print(out); out->print(" ");
2060 length()->print(out); out->print(" ");
2061 tmp()->print(out); out->print(" ");
2062 }
2064 // LIR_OpUpdateCRC32
2065 void LIR_OpUpdateCRC32::print_instr(outputStream* out) const {
2066 crc()->print(out); out->print(" ");
2067 val()->print(out); out->print(" ");
2068 result_opr()->print(out); out->print(" ");
2069 }
2071 // LIR_OpCompareAndSwap
2072 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const {
2073 addr()->print(out); out->print(" ");
2074 cmp_value()->print(out); out->print(" ");
2075 new_value()->print(out); out->print(" ");
2076 tmp1()->print(out); out->print(" ");
2077 tmp2()->print(out); out->print(" ");
2079 }
2081 // LIR_Op0
2082 void LIR_Op0::print_instr(outputStream* out) const {
2083 result_opr()->print(out);
2084 }
2086 // LIR_Op1
2087 const char * LIR_Op1::name() const {
2088 if (code() == lir_move) {
2089 switch (move_kind()) {
2090 case lir_move_normal:
2091 return "move";
2092 case lir_move_unaligned:
2093 return "unaligned move";
2094 case lir_move_volatile:
2095 return "volatile_move";
2096 case lir_move_wide:
2097 return "wide_move";
2098 default:
2099 ShouldNotReachHere();
2100 return "illegal_op";
2101 }
2102 } else {
2103 return LIR_Op::name();
2104 }
2105 }
2108 void LIR_Op1::print_instr(outputStream* out) const {
2109 _opr->print(out); out->print(" ");
2110 result_opr()->print(out); out->print(" ");
2111 print_patch_code(out, patch_code());
2112 }
2115 // LIR_Op1
2116 void LIR_OpRTCall::print_instr(outputStream* out) const {
2117 intx a = (intx)addr();
2118 out->print("%s", Runtime1::name_for_address(addr()));
2119 out->print(" ");
2120 tmp()->print(out);
2121 }
2123 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) {
2124 switch(code) {
2125 case lir_patch_none: break;
2126 case lir_patch_low: out->print("[patch_low]"); break;
2127 case lir_patch_high: out->print("[patch_high]"); break;
2128 case lir_patch_normal: out->print("[patch_normal]"); break;
2129 default: ShouldNotReachHere();
2130 }
2131 }
2133 // LIR_OpBranch
2134 void LIR_OpBranch::print_instr(outputStream* out) const {
2135 print_condition(out, cond()); out->print(" ");
2136 #ifdef MIPS64
2137 in_opr1()->print(out); out->print(" ");
2138 in_opr2()->print(out); out->print(" ");
2139 #endif
2140 if (block() != NULL) {
2141 out->print("[B%d] ", block()->block_id());
2142 } else if (stub() != NULL) {
2143 out->print("[");
2144 stub()->print_name(out);
2145 out->print(": " INTPTR_FORMAT "]", p2i(stub()));
2146 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci());
2147 } else {
2148 out->print("[label:" INTPTR_FORMAT "] ", p2i(label()));
2149 }
2150 if (ublock() != NULL) {
2151 out->print("unordered: [B%d] ", ublock()->block_id());
2152 }
2153 }
2155 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
2156 switch(cond) {
2157 case lir_cond_equal: out->print("[EQ]"); break;
2158 case lir_cond_notEqual: out->print("[NE]"); break;
2159 case lir_cond_less: out->print("[LT]"); break;
2160 case lir_cond_lessEqual: out->print("[LE]"); break;
2161 case lir_cond_greaterEqual: out->print("[GE]"); break;
2162 case lir_cond_greater: out->print("[GT]"); break;
2163 case lir_cond_belowEqual: out->print("[BE]"); break;
2164 case lir_cond_aboveEqual: out->print("[AE]"); break;
2165 case lir_cond_always: out->print("[AL]"); break;
2166 default: out->print("[%d]",cond); break;
2167 }
2168 }
2170 // LIR_OpConvert
2171 void LIR_OpConvert::print_instr(outputStream* out) const {
2172 print_bytecode(out, bytecode());
2173 in_opr()->print(out); out->print(" ");
2174 result_opr()->print(out); out->print(" ");
2175 #ifdef PPC
2176 if(tmp1()->is_valid()) {
2177 tmp1()->print(out); out->print(" ");
2178 tmp2()->print(out); out->print(" ");
2179 }
2180 #endif
2181 }
2183 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) {
2184 switch(code) {
2185 case Bytecodes::_d2f: out->print("[d2f] "); break;
2186 case Bytecodes::_d2i: out->print("[d2i] "); break;
2187 case Bytecodes::_d2l: out->print("[d2l] "); break;
2188 case Bytecodes::_f2d: out->print("[f2d] "); break;
2189 case Bytecodes::_f2i: out->print("[f2i] "); break;
2190 case Bytecodes::_f2l: out->print("[f2l] "); break;
2191 case Bytecodes::_i2b: out->print("[i2b] "); break;
2192 case Bytecodes::_i2c: out->print("[i2c] "); break;
2193 case Bytecodes::_i2d: out->print("[i2d] "); break;
2194 case Bytecodes::_i2f: out->print("[i2f] "); break;
2195 case Bytecodes::_i2l: out->print("[i2l] "); break;
2196 case Bytecodes::_i2s: out->print("[i2s] "); break;
2197 case Bytecodes::_l2i: out->print("[l2i] "); break;
2198 case Bytecodes::_l2f: out->print("[l2f] "); break;
2199 case Bytecodes::_l2d: out->print("[l2d] "); break;
2200 default:
2201 out->print("[?%d]",code);
2202 break;
2203 }
2204 }
2206 void LIR_OpAllocObj::print_instr(outputStream* out) const {
2207 klass()->print(out); out->print(" ");
2208 obj()->print(out); out->print(" ");
2209 tmp1()->print(out); out->print(" ");
2210 tmp2()->print(out); out->print(" ");
2211 tmp3()->print(out); out->print(" ");
2212 tmp4()->print(out); out->print(" ");
2213 #ifdef MIPS64
2214 tmp5()->print(out); out->print(" ");
2215 tmp6()->print(out); out->print(" ");
2216 #endif
2217 out->print("[hdr:%d]", header_size()); out->print(" ");
2218 out->print("[obj:%d]", object_size()); out->print(" ");
2219 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2220 }
2222 void LIR_OpRoundFP::print_instr(outputStream* out) const {
2223 _opr->print(out); out->print(" ");
2224 tmp()->print(out); out->print(" ");
2225 result_opr()->print(out); out->print(" ");
2226 }
2228 // LIR_Op2
2229 void LIR_Op2::print_instr(outputStream* out) const {
2230 #ifndef MIPS64
2231 if (code() == lir_cmove) {
2232 print_condition(out, condition()); out->print(" ");
2233 }
2234 #endif
2235 in_opr1()->print(out); out->print(" ");
2236 in_opr2()->print(out); out->print(" ");
2237 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); }
2238 if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); }
2239 if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); }
2240 if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out); out->print(" "); }
2241 if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out); out->print(" "); }
2242 result_opr()->print(out);
2243 }
2245 void LIR_OpAllocArray::print_instr(outputStream* out) const {
2246 klass()->print(out); out->print(" ");
2247 len()->print(out); out->print(" ");
2248 obj()->print(out); out->print(" ");
2249 tmp1()->print(out); out->print(" ");
2250 tmp2()->print(out); out->print(" ");
2251 tmp3()->print(out); out->print(" ");
2252 tmp4()->print(out); out->print(" ");
2253 #ifdef MIPS64
2254 tmp5()->print(out); out->print(" ");
2255 #endif
2256 out->print("[type:0x%x]", type()); out->print(" ");
2257 out->print("[label:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2258 }
2261 void LIR_OpTypeCheck::print_instr(outputStream* out) const {
2262 object()->print(out); out->print(" ");
2263 if (code() == lir_store_check) {
2264 array()->print(out); out->print(" ");
2265 }
2266 if (code() != lir_store_check) {
2267 klass()->print_name_on(out); out->print(" ");
2268 if (fast_check()) out->print("fast_check ");
2269 }
2270 tmp1()->print(out); out->print(" ");
2271 tmp2()->print(out); out->print(" ");
2272 tmp3()->print(out); out->print(" ");
2273 result_opr()->print(out); out->print(" ");
2274 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci());
2275 }
2278 // LIR_Op3
2279 void LIR_Op3::print_instr(outputStream* out) const {
2280 in_opr1()->print(out); out->print(" ");
2281 in_opr2()->print(out); out->print(" ");
2282 in_opr3()->print(out); out->print(" ");
2283 result_opr()->print(out);
2284 }
2287 void LIR_OpLock::print_instr(outputStream* out) const {
2288 hdr_opr()->print(out); out->print(" ");
2289 obj_opr()->print(out); out->print(" ");
2290 lock_opr()->print(out); out->print(" ");
2291 if (_scratch->is_valid()) {
2292 _scratch->print(out); out->print(" ");
2293 }
2294 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2295 }
2297 #ifdef ASSERT
2298 void LIR_OpAssert::print_instr(outputStream* out) const {
2299 tty->print_cr("function LIR_OpAssert::print_instr unimplemented yet! ");
2300 Unimplemented();
2301 /*
2302 print_condition(out, condition()); out->print(" ");
2303 in_opr1()->print(out); out->print(" ");
2304 in_opr2()->print(out); out->print(", \"");
2305 out->print("%s", msg()); out->print("\"");
2306 */
2307 }
2308 #endif
2311 void LIR_OpDelay::print_instr(outputStream* out) const {
2312 _op->print_on(out);
2313 }
2316 // LIR_OpProfileCall
2317 void LIR_OpProfileCall::print_instr(outputStream* out) const {
2318 profiled_method()->name()->print_symbol_on(out);
2319 out->print(".");
2320 profiled_method()->holder()->name()->print_symbol_on(out);
2321 out->print(" @ %d ", profiled_bci());
2322 mdo()->print(out); out->print(" ");
2323 recv()->print(out); out->print(" ");
2324 tmp1()->print(out); out->print(" ");
2325 }
2327 // LIR_OpProfileType
2328 void LIR_OpProfileType::print_instr(outputStream* out) const {
2329 out->print("exact = "); exact_klass()->print_name_on(out);
2330 out->print("current = "); ciTypeEntries::print_ciklass(out, current_klass());
2331 mdp()->print(out); out->print(" ");
2332 obj()->print(out); out->print(" ");
2333 tmp()->print(out); out->print(" ");
2334 }
2336 #endif // PRODUCT
2338 // Implementation of LIR_InsertionBuffer
2340 void LIR_InsertionBuffer::append(int index, LIR_Op* op) {
2341 assert(_index_and_count.length() % 2 == 0, "must have a count for each index");
2343 int i = number_of_insertion_points() - 1;
2344 if (i < 0 || index_at(i) < index) {
2345 append_new(index, 1);
2346 } else {
2347 assert(index_at(i) == index, "can append LIR_Ops in ascending order only");
2348 assert(count_at(i) > 0, "check");
2349 set_count_at(i, count_at(i) + 1);
2350 }
2351 _ops.push(op);
2353 DEBUG_ONLY(verify());
2354 }
2356 #ifdef ASSERT
2357 void LIR_InsertionBuffer::verify() {
2358 int sum = 0;
2359 int prev_idx = -1;
2361 for (int i = 0; i < number_of_insertion_points(); i++) {
2362 assert(prev_idx < index_at(i), "index must be ordered ascending");
2363 sum += count_at(i);
2364 }
2365 assert(sum == number_of_ops(), "wrong total sum");
2366 }
2367 #endif
