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comparison: src/share/vm/c1/c1_LIR.cpp

src/share/vm/c1/c1_LIR.cpp

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20 * or visit www.oracle.com if you need additional information or have any 20 * or visit www.oracle.com if you need additional information or have any
21 * questions. 21 * questions.
22 * 22 *
23 */ 23 */
24 24
25 /*
26 * This file has been modified by Loongson Technology in 2015. These
27 * modifications are Copyright (c) 2015 Loongson Technology, and are made
28 * available on the same license terms set forth above.
29 */
30
25 #include "precompiled.hpp" 31 #include "precompiled.hpp"
26 #include "c1/c1_InstructionPrinter.hpp" 32 #include "c1/c1_InstructionPrinter.hpp"
27 #include "c1/c1_LIR.hpp" 33 #include "c1/c1_LIR.hpp"
28 #include "c1/c1_LIRAssembler.hpp" 34 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_ValueStack.hpp" 35 #include "c1/c1_ValueStack.hpp"
61 return FrameMap::nr2floatreg(fpu_regnr()); 67 return FrameMap::nr2floatreg(fpu_regnr());
62 } 68 }
63 69
64 FloatRegister LIR_OprDesc::as_double_reg() const { 70 FloatRegister LIR_OprDesc::as_double_reg() const {
65 return FrameMap::nr2floatreg(fpu_regnrHi()); 71 return FrameMap::nr2floatreg(fpu_regnrHi());
72 }
73
74 #endif
75 #ifdef MIPS64
76
77 FloatRegister LIR_OprDesc::as_float_reg() const {
78 return FrameMap::nr2floatreg(fpu_regnr());
79 }
80
81 FloatRegister LIR_OprDesc::as_double_reg() const {
82 return FrameMap::nr2floatreg(fpu_regnrHi());
83 }
84
85 FloatRegister LIR_OprDesc::as_fpu_lo() const {
86 return FrameMap::nr2floatreg(fpu_regnrLo());
87 }
88
89 FloatRegister LIR_OprDesc::as_fpu_hi() const {
90 return FrameMap::nr2floatreg(fpu_regnrHi());
66 } 91 }
67 92
68 #endif 93 #endif
69 94
70 #ifdef ARM 95 #ifdef ARM
153 // be handled by the back-end or will be rejected if not. 178 // be handled by the back-end or will be rejected if not.
154 #endif 179 #endif
155 #ifdef _LP64 180 #ifdef _LP64
156 assert(base()->is_cpu_register(), "wrong base operand"); 181 assert(base()->is_cpu_register(), "wrong base operand");
157 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand"); 182 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
183 #ifndef MIPS64
158 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA, 184 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
159 "wrong type for addresses"); 185 "wrong type for addresses");
186 #endif
160 #else 187 #else
161 assert(base()->is_single_cpu(), "wrong base operand"); 188 assert(base()->is_single_cpu(), "wrong base operand");
162 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand"); 189 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
163 assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA, 190 assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
164 "wrong type for addresses"); 191 "wrong type for addresses");
301 } 328 }
302 #endif 329 #endif
303 } 330 }
304 331
305 332
333 #ifndef MIPS64
306 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block) 334 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block)
307 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) 335 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
308 , _cond(cond) 336 , _cond(cond)
309 , _type(type) 337 , _type(type)
310 , _label(block->label()) 338 , _label(block->label())
331 , _block(block) 359 , _block(block)
332 , _ublock(ublock) 360 , _ublock(ublock)
333 , _stub(NULL) 361 , _stub(NULL)
334 { 362 {
335 } 363 }
364
365 #else
366 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
367 BlockBegin* block):
368 LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
369 _cond(cond),
370 _type(type),
371 _label(block->label()),
372 _block(block),
373 _ublock(NULL),
374 _stub(NULL) {
375 }
376
377 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
378 CodeStub* stub):
379 LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
380 _cond(cond),
381 _type(type),
382 _label(stub->entry()),
383 _block(NULL),
384 _ublock(NULL),
385 _stub(stub) {
386 }
387
388
389 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
390 BlockBegin *block, BlockBegin *ublock):
391 LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
392 _cond(cond),
393 _type(type),
394 _label(block->label()),
395 _block(block),
396 _ublock(ublock),
397 _stub(NULL) {
398 }
399
400 #endif
336 401
337 void LIR_OpBranch::change_block(BlockBegin* b) { 402 void LIR_OpBranch::change_block(BlockBegin* b) {
338 assert(_block != NULL, "must have old block"); 403 assert(_block != NULL, "must have old block");
339 assert(_block->label() == label(), "must be equal"); 404 assert(_block->label() == label(), "must be equal");
340 405
575 case lir_cond_float_branch: // may have info, input and result register always invalid 640 case lir_cond_float_branch: // may have info, input and result register always invalid
576 { 641 {
577 assert(op->as_OpBranch() != NULL, "must be"); 642 assert(op->as_OpBranch() != NULL, "must be");
578 LIR_OpBranch* opBranch = (LIR_OpBranch*)op; 643 LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
579 644
645 #ifdef MIPS64
646 if (opBranch->_opr1->is_valid()) do_input(opBranch->_opr1);
647 if (opBranch->_opr2->is_valid()) do_input(opBranch->_opr2);
648 if (opBranch->_tmp1->is_valid()) do_temp(opBranch->_tmp1);
649 if (opBranch->_tmp2->is_valid()) do_temp(opBranch->_tmp2);
650 if (opBranch->_tmp3->is_valid()) do_temp(opBranch->_tmp3);
651 if (opBranch->_tmp4->is_valid()) do_temp(opBranch->_tmp4);
652 if (opBranch->_tmp5->is_valid()) do_temp(opBranch->_tmp5);
653 #endif
580 if (opBranch->_info != NULL) do_info(opBranch->_info); 654 if (opBranch->_info != NULL) do_info(opBranch->_info);
581 assert(opBranch->_result->is_illegal(), "not used"); 655 assert(opBranch->_result->is_illegal(), "not used");
582 if (opBranch->_stub != NULL) opBranch->stub()->visit(this); 656 if (opBranch->_stub != NULL) opBranch->stub()->visit(this);
583 657
584 break; 658 break;
597 } 671 }
598 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1); 672 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1);
599 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2); 673 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
600 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3); 674 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3);
601 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4); 675 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4);
676 #ifdef MIPS64
677 if (opAllocObj->_tmp5->is_valid()) do_temp(opAllocObj->_tmp5);
678 if (opAllocObj->_tmp6->is_valid()) do_temp(opAllocObj->_tmp6);
679 #endif
602 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result); 680 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result);
603 do_stub(opAllocObj->_stub); 681 do_stub(opAllocObj->_stub);
604 break; 682 break;
605 } 683 }
606 684
618 break; 696 break;
619 } 697 }
620 698
621 699
622 // LIR_Op2 700 // LIR_Op2
701 #ifdef MIPS64
702 case lir_null_check_for_branch:
703 #else
623 case lir_cmp: 704 case lir_cmp:
705 #endif
624 case lir_cmp_l2i: 706 case lir_cmp_l2i:
625 case lir_ucmp_fd2i: 707 case lir_ucmp_fd2i:
626 case lir_cmp_fd2i: 708 case lir_cmp_fd2i:
627 case lir_add: 709 case lir_add:
628 case lir_sub: 710 case lir_sub:
786 868
787 break; 869 break;
788 } 870 }
789 871
790 // LIR_Op3 872 // LIR_Op3
873 #ifdef MIPS64
874 case lir_frem:
875 #endif
791 case lir_idiv: 876 case lir_idiv:
792 case lir_irem: { 877 case lir_irem: {
793 assert(op->as_Op3() != NULL, "must be"); 878 assert(op->as_Op3() != NULL, "must be");
794 LIR_Op3* op3= (LIR_Op3*)op; 879 LIR_Op3* op3= (LIR_Op3*)op;
795 880
869 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src); 954 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src);
870 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos); 955 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos);
871 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst); 956 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst);
872 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos); 957 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
873 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length); 958 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length);
959 #ifndef MIPS64
874 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp); 960 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp);
961 #endif
875 if (opArrayCopy->_info) do_info(opArrayCopy->_info); 962 if (opArrayCopy->_info) do_info(opArrayCopy->_info);
876 963
877 // the implementation of arraycopy always has a call into the runtime 964 // the implementation of arraycopy always has a call into the runtime
878 do_call(); 965 do_call();
879 966
984 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len); 1071 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len);
985 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1); 1072 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1);
986 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2); 1073 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2);
987 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3); 1074 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3);
988 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4); 1075 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4);
1076 #ifdef MIPS64
1077 if (opAllocArray->_tmp5->is_valid()) do_temp(opAllocArray->_tmp5);
1078 #endif
989 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result); 1079 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result);
990 do_stub(opAllocArray->_stub); 1080 do_stub(opAllocArray->_stub);
991 break; 1081 break;
992 } 1082 }
993 1083
1254 patch_code, 1344 patch_code,
1255 info, lir_move_volatile)); 1345 info, lir_move_volatile));
1256 } 1346 }
1257 1347
1258 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1348 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1349 #ifndef MIPS64
1259 append(new LIR_Op1( 1350 append(new LIR_Op1(
1260 lir_move, 1351 lir_move,
1261 LIR_OprFact::address(new LIR_Address(base, offset, type)), 1352 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1262 dst, 1353 dst,
1263 type, 1354 type,
1264 patch_code, 1355 patch_code,
1265 info, lir_move_volatile)); 1356 info, lir_move_volatile));
1357 #else
1358 add(base, offset, base);
1359 append(new LIR_Op1(
1360 lir_move,
1361 LIR_OprFact::address(new LIR_Address(base, 0, type)),
1362 dst,
1363 type,
1364 patch_code,
1365 info, lir_move_volatile));
1366 #endif
1266 } 1367 }
1267 1368
1268 1369
1269 void LIR_List::prefetch(LIR_Address* addr, bool is_store) { 1370 void LIR_List::prefetch(LIR_Address* addr, bool is_store) {
1270 append(new LIR_Op1( 1371 append(new LIR_Op1(
1316 info, 1417 info,
1317 lir_move_volatile)); 1418 lir_move_volatile));
1318 } 1419 }
1319 1420
1320 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1421 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1422 #ifndef MIPS64
1321 append(new LIR_Op1( 1423 append(new LIR_Op1(
1322 lir_move, 1424 lir_move,
1323 src, 1425 src,
1324 LIR_OprFact::address(new LIR_Address(base, offset, type)), 1426 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1325 type, 1427 type,
1326 patch_code, 1428 patch_code,
1327 info, lir_move_volatile)); 1429 info, lir_move_volatile));
1328 } 1430 #else
1329 1431 add(base, offset, base);
1432 append(new LIR_Op1(
1433 lir_move,
1434 src,
1435 LIR_OprFact::address(new LIR_Address(base, 0, type)),
1436 type,
1437 patch_code,
1438 info, lir_move_volatile));
1439
1440 #endif
1441
1442 }
1443
1444 #ifdef MIPS64
1445 void LIR_List::frem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1446 append(new LIR_Op3(
1447 lir_frem,
1448 left,
1449 right,
1450 tmp,
1451 res,
1452 info));
1453 }
1454 #endif
1330 1455
1331 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { 1456 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1332 append(new LIR_Op3( 1457 append(new LIR_Op3(
1333 lir_idiv, 1458 lir_idiv,
1334 left, 1459 left,
1370 res, 1495 res,
1371 info)); 1496 info));
1372 } 1497 }
1373 1498
1374 1499
1500 #ifndef MIPS64
1375 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) { 1501 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1376 append(new LIR_Op2( 1502 append(new LIR_Op2(
1377 lir_cmp, 1503 lir_cmp,
1378 condition, 1504 condition,
1379 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)), 1505 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)),
1416 t3, 1542 t3,
1417 t4, 1543 t4,
1418 type, 1544 type,
1419 stub)); 1545 stub));
1420 } 1546 }
1547 #else
1548 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, LIR_Opr t5, LIR_Opr t6,
1549 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1550 append(new LIR_OpAllocObj(
1551 klass,
1552 dst,
1553 t1,
1554 t2,
1555 t3,
1556 t4,
1557 t5,
1558 t6,
1559 header_size,
1560 object_size,
1561 init_check,
1562 stub));
1563 }
1564 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, LIR_Opr t5,
1565 BasicType type, LIR_Opr klass, CodeStub* stub) {
1566 append(new LIR_OpAllocArray(
1567 klass,
1568 len,
1569 dst,
1570 t1,
1571 t2,
1572 t3,
1573 t4,
1574 t5,
1575 type,
1576 stub));
1577 }
1578
1579 #endif
1421 1580
1422 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { 1581 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1423 append(new LIR_Op2( 1582 append(new LIR_Op2(
1424 lir_shl, 1583 lir_shl,
1425 value, 1584 value,
1506 c->set_should_profile(true); 1665 c->set_should_profile(true);
1507 } 1666 }
1508 append(c); 1667 append(c);
1509 } 1668 }
1510 1669
1511
1512 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, 1670 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
1513 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) { 1671 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) {
1514 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception); 1672 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception);
1515 if (profiled_method != NULL) { 1673 if (profiled_method != NULL) {
1516 c->set_profiled_method(profiled_method); 1674 c->set_profiled_method(profiled_method);
1518 c->set_should_profile(true); 1676 c->set_should_profile(true);
1519 } 1677 }
1520 append(c); 1678 append(c);
1521 } 1679 }
1522 1680
1523 1681 #ifndef MIPS64
1524 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, 1682 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1525 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { 1683 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1526 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result)); 1684 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
1527 } 1685 }
1528 1686
1533 1691
1534 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, 1692 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1535 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { 1693 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1536 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result)); 1694 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result));
1537 } 1695 }
1696 #else
1697 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1698 // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value,
1699 // // implying successful swap of new_value into addr
1700 append(new LIR_OpCompareAndSwap(lir_cas_long,
1701 addr,
1702 cmp_value,
1703 new_value,
1704 t1,
1705 t2,
1706 result));
1707 }
1708
1709 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1710 // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value,
1711 // // implying successful swap of new_value into addr
1712 append(new LIR_OpCompareAndSwap(lir_cas_obj,
1713 addr,
1714 cmp_value,
1715 new_value,
1716 t1,
1717 t2,
1718 result));
1719 }
1720
1721 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1722 // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value,
1723 // // implying successful swap of new_value into addr
1724 append(new LIR_OpCompareAndSwap(lir_cas_int,
1725 addr,
1726 cmp_value,
1727 new_value,
1728 t1,
1729 t2,
1730 result));
1731 }
1732 #endif
1538 1733
1539 1734
1540 #ifdef PRODUCT 1735 #ifdef PRODUCT
1541 1736
1542 void print_LIR(BlockList* blocks) { 1737 void print_LIR(BlockList* blocks) {
1618 } 1813 }
1619 1814
1620 // LIR_Address 1815 // LIR_Address
1621 void LIR_Address::print_value_on(outputStream* out) const { 1816 void LIR_Address::print_value_on(outputStream* out) const {
1622 out->print("Base:"); _base->print(out); 1817 out->print("Base:"); _base->print(out);
1818 #ifndef MIPS64
1623 if (!_index->is_illegal()) { 1819 if (!_index->is_illegal()) {
1624 out->print(" Index:"); _index->print(out); 1820 out->print(" Index:"); _index->print(out);
1625 switch (scale()) { 1821 switch (scale()) {
1626 case times_1: break; 1822 case times_1: break;
1627 case times_2: out->print(" * 2"); break; 1823 case times_2: out->print(" * 2"); break;
1628 case times_4: out->print(" * 4"); break; 1824 case times_4: out->print(" * 4"); break;
1629 case times_8: out->print(" * 8"); break; 1825 case times_8: out->print(" * 8"); break;
1630 } 1826 }
1631 } 1827 }
1828 #endif
1632 out->print(" Disp: " INTX_FORMAT, _disp); 1829 out->print(" Disp: " INTX_FORMAT, _disp);
1633 } 1830 }
1634 1831
1635 // debug output of block header without InstructionPrinter 1832 // debug output of block header without InstructionPrinter
1636 // (because phi functions are not necessary for LIR) 1833 // (because phi functions are not necessary for LIR)
1758 case lir_alloc_object: s = "alloc_obj"; break; 1955 case lir_alloc_object: s = "alloc_obj"; break;
1759 case lir_monaddr: s = "mon_addr"; break; 1956 case lir_monaddr: s = "mon_addr"; break;
1760 case lir_pack64: s = "pack64"; break; 1957 case lir_pack64: s = "pack64"; break;
1761 case lir_unpack64: s = "unpack64"; break; 1958 case lir_unpack64: s = "unpack64"; break;
1762 // LIR_Op2 1959 // LIR_Op2
1960 #ifdef MIPS64
1961 case lir_null_check_for_branch: s = "null_check_for_branch"; break;
1962 #else
1763 case lir_cmp: s = "cmp"; break; 1963 case lir_cmp: s = "cmp"; break;
1964 #endif
1764 case lir_cmp_l2i: s = "cmp_l2i"; break; 1965 case lir_cmp_l2i: s = "cmp_l2i"; break;
1765 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break; 1966 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break;
1766 case lir_cmp_fd2i: s = "comp_fd2i"; break; 1967 case lir_cmp_fd2i: s = "comp_fd2i"; break;
1767 case lir_cmove: s = "cmove"; break; 1968 case lir_cmove: s = "cmove"; break;
1768 case lir_add: s = "add"; break; 1969 case lir_add: s = "add"; break;
1789 case lir_ushr: s = "ushift_right"; break; 1990 case lir_ushr: s = "ushift_right"; break;
1790 case lir_alloc_array: s = "alloc_array"; break; 1991 case lir_alloc_array: s = "alloc_array"; break;
1791 case lir_xadd: s = "xadd"; break; 1992 case lir_xadd: s = "xadd"; break;
1792 case lir_xchg: s = "xchg"; break; 1993 case lir_xchg: s = "xchg"; break;
1793 // LIR_Op3 1994 // LIR_Op3
1995 #ifdef MIPS64
1996 case lir_frem: s = "frem"; break;
1997 #endif
1794 case lir_idiv: s = "idiv"; break; 1998 case lir_idiv: s = "idiv"; break;
1795 case lir_irem: s = "irem"; break; 1999 case lir_irem: s = "irem"; break;
1796 // LIR_OpJavaCall 2000 // LIR_OpJavaCall
1797 case lir_static_call: s = "static"; break; 2001 case lir_static_call: s = "static"; break;
1798 case lir_optvirtual_call: s = "optvirtual"; break; 2002 case lir_optvirtual_call: s = "optvirtual"; break;
1927 } 2131 }
1928 2132
1929 // LIR_OpBranch 2133 // LIR_OpBranch
1930 void LIR_OpBranch::print_instr(outputStream* out) const { 2134 void LIR_OpBranch::print_instr(outputStream* out) const {
1931 print_condition(out, cond()); out->print(" "); 2135 print_condition(out, cond()); out->print(" ");
2136 #ifdef MIPS64
2137 in_opr1()->print(out); out->print(" ");
2138 in_opr2()->print(out); out->print(" ");
2139 #endif
1932 if (block() != NULL) { 2140 if (block() != NULL) {
1933 out->print("[B%d] ", block()->block_id()); 2141 out->print("[B%d] ", block()->block_id());
1934 } else if (stub() != NULL) { 2142 } else if (stub() != NULL) {
1935 out->print("["); 2143 out->print("[");
1936 stub()->print_name(out); 2144 stub()->print_name(out);
2000 obj()->print(out); out->print(" "); 2208 obj()->print(out); out->print(" ");
2001 tmp1()->print(out); out->print(" "); 2209 tmp1()->print(out); out->print(" ");
2002 tmp2()->print(out); out->print(" "); 2210 tmp2()->print(out); out->print(" ");
2003 tmp3()->print(out); out->print(" "); 2211 tmp3()->print(out); out->print(" ");
2004 tmp4()->print(out); out->print(" "); 2212 tmp4()->print(out); out->print(" ");
2213 #ifdef MIPS64
2214 tmp5()->print(out); out->print(" ");
2215 tmp6()->print(out); out->print(" ");
2216 #endif
2005 out->print("[hdr:%d]", header_size()); out->print(" "); 2217 out->print("[hdr:%d]", header_size()); out->print(" ");
2006 out->print("[obj:%d]", object_size()); out->print(" "); 2218 out->print("[obj:%d]", object_size()); out->print(" ");
2007 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry())); 2219 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2008 } 2220 }
2009 2221
2013 result_opr()->print(out); out->print(" "); 2225 result_opr()->print(out); out->print(" ");
2014 } 2226 }
2015 2227
2016 // LIR_Op2 2228 // LIR_Op2
2017 void LIR_Op2::print_instr(outputStream* out) const { 2229 void LIR_Op2::print_instr(outputStream* out) const {
2230 #ifndef MIPS64
2018 if (code() == lir_cmove) { 2231 if (code() == lir_cmove) {
2019 print_condition(out, condition()); out->print(" "); 2232 print_condition(out, condition()); out->print(" ");
2020 } 2233 }
2234 #endif
2021 in_opr1()->print(out); out->print(" "); 2235 in_opr1()->print(out); out->print(" ");
2022 in_opr2()->print(out); out->print(" "); 2236 in_opr2()->print(out); out->print(" ");
2023 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); } 2237 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); }
2024 if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); } 2238 if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); }
2025 if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); } 2239 if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); }
2034 obj()->print(out); out->print(" "); 2248 obj()->print(out); out->print(" ");
2035 tmp1()->print(out); out->print(" "); 2249 tmp1()->print(out); out->print(" ");
2036 tmp2()->print(out); out->print(" "); 2250 tmp2()->print(out); out->print(" ");
2037 tmp3()->print(out); out->print(" "); 2251 tmp3()->print(out); out->print(" ");
2038 tmp4()->print(out); out->print(" "); 2252 tmp4()->print(out); out->print(" ");
2253 #ifdef MIPS64
2254 tmp5()->print(out); out->print(" ");
2255 #endif
2039 out->print("[type:0x%x]", type()); out->print(" "); 2256 out->print("[type:0x%x]", type()); out->print(" ");
2040 out->print("[label:" INTPTR_FORMAT "]", p2i(stub()->entry())); 2257 out->print("[label:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2041 } 2258 }
2042 2259
2043 2260
2077 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry())); 2294 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2078 } 2295 }
2079 2296
2080 #ifdef ASSERT 2297 #ifdef ASSERT
2081 void LIR_OpAssert::print_instr(outputStream* out) const { 2298 void LIR_OpAssert::print_instr(outputStream* out) const {
2299 tty->print_cr("function LIR_OpAssert::print_instr unimplemented yet! ");
2300 Unimplemented();
2301 /*
2082 print_condition(out, condition()); out->print(" "); 2302 print_condition(out, condition()); out->print(" ");
2083 in_opr1()->print(out); out->print(" "); 2303 in_opr1()->print(out); out->print(" ");
2084 in_opr2()->print(out); out->print(", \""); 2304 in_opr2()->print(out); out->print(", \"");
2085 out->print("%s", msg()); out->print("\""); 2305 out->print("%s", msg()); out->print("\"");
2306 */
2086 } 2307 }
2087 #endif 2308 #endif
2088 2309
2089 2310
2090 void LIR_OpDelay::print_instr(outputStream* out) const { 2311 void LIR_OpDelay::print_instr(outputStream* out) const {

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