Tue, 06 Oct 2009 10:15:38 -0700
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
Summary: Fix problem with the double register encodings in sparc.ad
Reviewed-by: never, jrose
Contributed-by: volker.simonis@gmail.com
1 /*
2 * Copyright 2003-2009 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
25 #include "incls/_precompiled.incl"
26 #include "incls/_sharedRuntime_sparc.cpp.incl"
28 #define __ masm->
30 #ifdef COMPILER2
31 UncommonTrapBlob* SharedRuntime::_uncommon_trap_blob;
32 #endif // COMPILER2
34 DeoptimizationBlob* SharedRuntime::_deopt_blob;
35 SafepointBlob* SharedRuntime::_polling_page_safepoint_handler_blob;
36 SafepointBlob* SharedRuntime::_polling_page_return_handler_blob;
37 RuntimeStub* SharedRuntime::_wrong_method_blob;
38 RuntimeStub* SharedRuntime::_ic_miss_blob;
39 RuntimeStub* SharedRuntime::_resolve_opt_virtual_call_blob;
40 RuntimeStub* SharedRuntime::_resolve_virtual_call_blob;
41 RuntimeStub* SharedRuntime::_resolve_static_call_blob;
43 class RegisterSaver {
45 // Used for saving volatile registers. This is Gregs, Fregs, I/L/O.
46 // The Oregs are problematic. In the 32bit build the compiler can
47 // have O registers live with 64 bit quantities. A window save will
48 // cut the heads off of the registers. We have to do a very extensive
49 // stack dance to save and restore these properly.
51 // Note that the Oregs problem only exists if we block at either a polling
52 // page exception a compiled code safepoint that was not originally a call
53 // or deoptimize following one of these kinds of safepoints.
55 // Lots of registers to save. For all builds, a window save will preserve
56 // the %i and %l registers. For the 32-bit longs-in-two entries and 64-bit
57 // builds a window-save will preserve the %o registers. In the LION build
58 // we need to save the 64-bit %o registers which requires we save them
59 // before the window-save (as then they become %i registers and get their
60 // heads chopped off on interrupt). We have to save some %g registers here
61 // as well.
62 enum {
63 // This frame's save area. Includes extra space for the native call:
64 // vararg's layout space and the like. Briefly holds the caller's
65 // register save area.
66 call_args_area = frame::register_save_words_sp_offset +
67 frame::memory_parameter_word_sp_offset*wordSize,
68 // Make sure save locations are always 8 byte aligned.
69 // can't use round_to because it doesn't produce compile time constant
70 start_of_extra_save_area = ((call_args_area + 7) & ~7),
71 g1_offset = start_of_extra_save_area, // g-regs needing saving
72 g3_offset = g1_offset+8,
73 g4_offset = g3_offset+8,
74 g5_offset = g4_offset+8,
75 o0_offset = g5_offset+8,
76 o1_offset = o0_offset+8,
77 o2_offset = o1_offset+8,
78 o3_offset = o2_offset+8,
79 o4_offset = o3_offset+8,
80 o5_offset = o4_offset+8,
81 start_of_flags_save_area = o5_offset+8,
82 ccr_offset = start_of_flags_save_area,
83 fsr_offset = ccr_offset + 8,
84 d00_offset = fsr_offset+8, // Start of float save area
85 register_save_size = d00_offset+8*32
86 };
89 public:
91 static int Oexception_offset() { return o0_offset; };
92 static int G3_offset() { return g3_offset; };
93 static int G5_offset() { return g5_offset; };
94 static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words);
95 static void restore_live_registers(MacroAssembler* masm);
97 // During deoptimization only the result register need to be restored
98 // all the other values have already been extracted.
100 static void restore_result_registers(MacroAssembler* masm);
101 };
103 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words) {
104 // Record volatile registers as callee-save values in an OopMap so their save locations will be
105 // propagated to the caller frame's RegisterMap during StackFrameStream construction (needed for
106 // deoptimization; see compiledVFrame::create_stack_value). The caller's I, L and O registers
107 // are saved in register windows - I's and L's in the caller's frame and O's in the stub frame
108 // (as the stub's I's) when the runtime routine called by the stub creates its frame.
109 int i;
110 // Always make the frame size 16 byte aligned.
111 int frame_size = round_to(additional_frame_words + register_save_size, 16);
112 // OopMap frame size is in c2 stack slots (sizeof(jint)) not bytes or words
113 int frame_size_in_slots = frame_size / sizeof(jint);
114 // CodeBlob frame size is in words.
115 *total_frame_words = frame_size / wordSize;
116 // OopMap* map = new OopMap(*total_frame_words, 0);
117 OopMap* map = new OopMap(frame_size_in_slots, 0);
119 #if !defined(_LP64)
121 // Save 64-bit O registers; they will get their heads chopped off on a 'save'.
122 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
123 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
124 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8);
125 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8);
126 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8);
127 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8);
128 #endif /* _LP64 */
130 __ save(SP, -frame_size, SP);
132 #ifndef _LP64
133 // Reload the 64 bit Oregs. Although they are now Iregs we load them
134 // to Oregs here to avoid interrupts cutting off their heads
136 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
137 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
138 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2);
139 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3);
140 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4);
141 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5);
143 __ stx(O0, SP, o0_offset+STACK_BIAS);
144 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset + 4)>>2), O0->as_VMReg());
146 __ stx(O1, SP, o1_offset+STACK_BIAS);
148 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset + 4)>>2), O1->as_VMReg());
150 __ stx(O2, SP, o2_offset+STACK_BIAS);
151 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset + 4)>>2), O2->as_VMReg());
153 __ stx(O3, SP, o3_offset+STACK_BIAS);
154 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset + 4)>>2), O3->as_VMReg());
156 __ stx(O4, SP, o4_offset+STACK_BIAS);
157 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset + 4)>>2), O4->as_VMReg());
159 __ stx(O5, SP, o5_offset+STACK_BIAS);
160 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset + 4)>>2), O5->as_VMReg());
161 #endif /* _LP64 */
164 #ifdef _LP64
165 int debug_offset = 0;
166 #else
167 int debug_offset = 4;
168 #endif
169 // Save the G's
170 __ stx(G1, SP, g1_offset+STACK_BIAS);
171 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset + debug_offset)>>2), G1->as_VMReg());
173 __ stx(G3, SP, g3_offset+STACK_BIAS);
174 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset + debug_offset)>>2), G3->as_VMReg());
176 __ stx(G4, SP, g4_offset+STACK_BIAS);
177 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset + debug_offset)>>2), G4->as_VMReg());
179 __ stx(G5, SP, g5_offset+STACK_BIAS);
180 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset + debug_offset)>>2), G5->as_VMReg());
182 // This is really a waste but we'll keep things as they were for now
183 if (true) {
184 #ifndef _LP64
185 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset)>>2), O0->as_VMReg()->next());
186 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset)>>2), O1->as_VMReg()->next());
187 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset)>>2), O2->as_VMReg()->next());
188 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset)>>2), O3->as_VMReg()->next());
189 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset)>>2), O4->as_VMReg()->next());
190 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset)>>2), O5->as_VMReg()->next());
191 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset)>>2), G1->as_VMReg()->next());
192 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset)>>2), G3->as_VMReg()->next());
193 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset)>>2), G4->as_VMReg()->next());
194 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset)>>2), G5->as_VMReg()->next());
195 #endif /* _LP64 */
196 }
199 // Save the flags
200 __ rdccr( G5 );
201 __ stx(G5, SP, ccr_offset+STACK_BIAS);
202 __ stxfsr(SP, fsr_offset+STACK_BIAS);
204 // Save all the FP registers: 32 doubles (32 floats correspond to the 2 halves of the first 16 doubles)
205 int offset = d00_offset;
206 for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) {
207 FloatRegister f = as_FloatRegister(i);
208 __ stf(FloatRegisterImpl::D, f, SP, offset+STACK_BIAS);
209 // Record as callee saved both halves of double registers (2 float registers).
210 map->set_callee_saved(VMRegImpl::stack2reg(offset>>2), f->as_VMReg());
211 map->set_callee_saved(VMRegImpl::stack2reg((offset + sizeof(float))>>2), f->as_VMReg()->next());
212 offset += sizeof(double);
213 }
215 // And we're done.
217 return map;
218 }
221 // Pop the current frame and restore all the registers that we
222 // saved.
223 void RegisterSaver::restore_live_registers(MacroAssembler* masm) {
225 // Restore all the FP registers
226 for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) {
227 __ ldf(FloatRegisterImpl::D, SP, d00_offset+i*sizeof(float)+STACK_BIAS, as_FloatRegister(i));
228 }
230 __ ldx(SP, ccr_offset+STACK_BIAS, G1);
231 __ wrccr (G1) ;
233 // Restore the G's
234 // Note that G2 (AKA GThread) must be saved and restored separately.
235 // TODO-FIXME: save and restore some of the other ASRs, viz., %asi and %gsr.
237 __ ldx(SP, g1_offset+STACK_BIAS, G1);
238 __ ldx(SP, g3_offset+STACK_BIAS, G3);
239 __ ldx(SP, g4_offset+STACK_BIAS, G4);
240 __ ldx(SP, g5_offset+STACK_BIAS, G5);
243 #if !defined(_LP64)
244 // Restore the 64-bit O's.
245 __ ldx(SP, o0_offset+STACK_BIAS, O0);
246 __ ldx(SP, o1_offset+STACK_BIAS, O1);
247 __ ldx(SP, o2_offset+STACK_BIAS, O2);
248 __ ldx(SP, o3_offset+STACK_BIAS, O3);
249 __ ldx(SP, o4_offset+STACK_BIAS, O4);
250 __ ldx(SP, o5_offset+STACK_BIAS, O5);
252 // And temporarily place them in TLS
254 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
255 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
256 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8);
257 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8);
258 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8);
259 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8);
260 #endif /* _LP64 */
262 // Restore flags
264 __ ldxfsr(SP, fsr_offset+STACK_BIAS);
266 __ restore();
268 #if !defined(_LP64)
269 // Now reload the 64bit Oregs after we've restore the window.
270 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
271 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
272 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2);
273 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3);
274 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4);
275 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5);
276 #endif /* _LP64 */
278 }
280 // Pop the current frame and restore the registers that might be holding
281 // a result.
282 void RegisterSaver::restore_result_registers(MacroAssembler* masm) {
284 #if !defined(_LP64)
285 // 32bit build returns longs in G1
286 __ ldx(SP, g1_offset+STACK_BIAS, G1);
288 // Retrieve the 64-bit O's.
289 __ ldx(SP, o0_offset+STACK_BIAS, O0);
290 __ ldx(SP, o1_offset+STACK_BIAS, O1);
291 // and save to TLS
292 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
293 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
294 #endif /* _LP64 */
296 __ ldf(FloatRegisterImpl::D, SP, d00_offset+STACK_BIAS, as_FloatRegister(0));
298 __ restore();
300 #if !defined(_LP64)
301 // Now reload the 64bit Oregs after we've restore the window.
302 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
303 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
304 #endif /* _LP64 */
306 }
308 // The java_calling_convention describes stack locations as ideal slots on
309 // a frame with no abi restrictions. Since we must observe abi restrictions
310 // (like the placement of the register window) the slots must be biased by
311 // the following value.
312 static int reg2offset(VMReg r) {
313 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
314 }
316 // ---------------------------------------------------------------------------
317 // Read the array of BasicTypes from a signature, and compute where the
318 // arguments should go. Values in the VMRegPair regs array refer to 4-byte (VMRegImpl::stack_slot_size)
319 // quantities. Values less than VMRegImpl::stack0 are registers, those above
320 // refer to 4-byte stack slots. All stack slots are based off of the window
321 // top. VMRegImpl::stack0 refers to the first slot past the 16-word window,
322 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register
323 // values 0-63 (up to RegisterImpl::number_of_registers) are the 64-bit
324 // integer registers. Values 64-95 are the (32-bit only) float registers.
325 // Each 32-bit quantity is given its own number, so the integer registers
326 // (in either 32- or 64-bit builds) use 2 numbers. For example, there is
327 // an O0-low and an O0-high. Essentially, all int register numbers are doubled.
329 // Register results are passed in O0-O5, for outgoing call arguments. To
330 // convert to incoming arguments, convert all O's to I's. The regs array
331 // refer to the low and hi 32-bit words of 64-bit registers or stack slots.
332 // If the regs[].second() field is set to VMRegImpl::Bad(), it means it's unused (a
333 // 32-bit value was passed). If both are VMRegImpl::Bad(), it means no value was
334 // passed (used as a placeholder for the other half of longs and doubles in
335 // the 64-bit build). regs[].second() is either VMRegImpl::Bad() or regs[].second() is
336 // regs[].first()+1 (regs[].first() may be misaligned in the C calling convention).
337 // Sparc never passes a value in regs[].second() but not regs[].first() (regs[].first()
338 // == VMRegImpl::Bad() && regs[].second() != VMRegImpl::Bad()) nor unrelated values in the
339 // same VMRegPair.
341 // Note: the INPUTS in sig_bt are in units of Java argument words, which are
342 // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit
343 // units regardless of build.
346 // ---------------------------------------------------------------------------
347 // The compiled Java calling convention. The Java convention always passes
348 // 64-bit values in adjacent aligned locations (either registers or stack),
349 // floats in float registers and doubles in aligned float pairs. Values are
350 // packed in the registers. There is no backing varargs store for values in
351 // registers. In the 32-bit build, longs are passed in G1 and G4 (cannot be
352 // passed in I's, because longs in I's get their heads chopped off at
353 // interrupt).
354 int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
355 VMRegPair *regs,
356 int total_args_passed,
357 int is_outgoing) {
358 assert(F31->as_VMReg()->is_reg(), "overlapping stack/register numbers");
360 // Convention is to pack the first 6 int/oop args into the first 6 registers
361 // (I0-I5), extras spill to the stack. Then pack the first 8 float args
362 // into F0-F7, extras spill to the stack. Then pad all register sets to
363 // align. Then put longs and doubles into the same registers as they fit,
364 // else spill to the stack.
365 const int int_reg_max = SPARC_ARGS_IN_REGS_NUM;
366 const int flt_reg_max = 8;
367 //
368 // Where 32-bit 1-reg longs start being passed
369 // In tiered we must pass on stack because c1 can't use a "pair" in a single reg.
370 // So make it look like we've filled all the G regs that c2 wants to use.
371 Register g_reg = TieredCompilation ? noreg : G1;
373 // Count int/oop and float args. See how many stack slots we'll need and
374 // where the longs & doubles will go.
375 int int_reg_cnt = 0;
376 int flt_reg_cnt = 0;
377 // int stk_reg_pairs = frame::register_save_words*(wordSize>>2);
378 // int stk_reg_pairs = SharedRuntime::out_preserve_stack_slots();
379 int stk_reg_pairs = 0;
380 for (int i = 0; i < total_args_passed; i++) {
381 switch (sig_bt[i]) {
382 case T_LONG: // LP64, longs compete with int args
383 assert(sig_bt[i+1] == T_VOID, "");
384 #ifdef _LP64
385 if (int_reg_cnt < int_reg_max) int_reg_cnt++;
386 #endif
387 break;
388 case T_OBJECT:
389 case T_ARRAY:
390 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
391 if (int_reg_cnt < int_reg_max) int_reg_cnt++;
392 #ifndef _LP64
393 else stk_reg_pairs++;
394 #endif
395 break;
396 case T_INT:
397 case T_SHORT:
398 case T_CHAR:
399 case T_BYTE:
400 case T_BOOLEAN:
401 if (int_reg_cnt < int_reg_max) int_reg_cnt++;
402 else stk_reg_pairs++;
403 break;
404 case T_FLOAT:
405 if (flt_reg_cnt < flt_reg_max) flt_reg_cnt++;
406 else stk_reg_pairs++;
407 break;
408 case T_DOUBLE:
409 assert(sig_bt[i+1] == T_VOID, "");
410 break;
411 case T_VOID:
412 break;
413 default:
414 ShouldNotReachHere();
415 }
416 }
418 // This is where the longs/doubles start on the stack.
419 stk_reg_pairs = (stk_reg_pairs+1) & ~1; // Round
421 int int_reg_pairs = (int_reg_cnt+1) & ~1; // 32-bit 2-reg longs only
422 int flt_reg_pairs = (flt_reg_cnt+1) & ~1;
424 // int stk_reg = frame::register_save_words*(wordSize>>2);
425 // int stk_reg = SharedRuntime::out_preserve_stack_slots();
426 int stk_reg = 0;
427 int int_reg = 0;
428 int flt_reg = 0;
430 // Now do the signature layout
431 for (int i = 0; i < total_args_passed; i++) {
432 switch (sig_bt[i]) {
433 case T_INT:
434 case T_SHORT:
435 case T_CHAR:
436 case T_BYTE:
437 case T_BOOLEAN:
438 #ifndef _LP64
439 case T_OBJECT:
440 case T_ARRAY:
441 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
442 #endif // _LP64
443 if (int_reg < int_reg_max) {
444 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
445 regs[i].set1(r->as_VMReg());
446 } else {
447 regs[i].set1(VMRegImpl::stack2reg(stk_reg++));
448 }
449 break;
451 #ifdef _LP64
452 case T_OBJECT:
453 case T_ARRAY:
454 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
455 if (int_reg < int_reg_max) {
456 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
457 regs[i].set2(r->as_VMReg());
458 } else {
459 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
460 stk_reg_pairs += 2;
461 }
462 break;
463 #endif // _LP64
465 case T_LONG:
466 assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half");
467 #ifdef _LP64
468 if (int_reg < int_reg_max) {
469 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
470 regs[i].set2(r->as_VMReg());
471 } else {
472 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
473 stk_reg_pairs += 2;
474 }
475 #else
476 #ifdef COMPILER2
477 // For 32-bit build, can't pass longs in O-regs because they become
478 // I-regs and get trashed. Use G-regs instead. G1 and G4 are almost
479 // spare and available. This convention isn't used by the Sparc ABI or
480 // anywhere else. If we're tiered then we don't use G-regs because c1
481 // can't deal with them as a "pair". (Tiered makes this code think g's are filled)
482 // G0: zero
483 // G1: 1st Long arg
484 // G2: global allocated to TLS
485 // G3: used in inline cache check
486 // G4: 2nd Long arg
487 // G5: used in inline cache check
488 // G6: used by OS
489 // G7: used by OS
491 if (g_reg == G1) {
492 regs[i].set2(G1->as_VMReg()); // This long arg in G1
493 g_reg = G4; // Where the next arg goes
494 } else if (g_reg == G4) {
495 regs[i].set2(G4->as_VMReg()); // The 2nd long arg in G4
496 g_reg = noreg; // No more longs in registers
497 } else {
498 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
499 stk_reg_pairs += 2;
500 }
501 #else // COMPILER2
502 if (int_reg_pairs + 1 < int_reg_max) {
503 if (is_outgoing) {
504 regs[i].set_pair(as_oRegister(int_reg_pairs + 1)->as_VMReg(), as_oRegister(int_reg_pairs)->as_VMReg());
505 } else {
506 regs[i].set_pair(as_iRegister(int_reg_pairs + 1)->as_VMReg(), as_iRegister(int_reg_pairs)->as_VMReg());
507 }
508 int_reg_pairs += 2;
509 } else {
510 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
511 stk_reg_pairs += 2;
512 }
513 #endif // COMPILER2
514 #endif // _LP64
515 break;
517 case T_FLOAT:
518 if (flt_reg < flt_reg_max) regs[i].set1(as_FloatRegister(flt_reg++)->as_VMReg());
519 else regs[i].set1( VMRegImpl::stack2reg(stk_reg++));
520 break;
521 case T_DOUBLE:
522 assert(sig_bt[i+1] == T_VOID, "expecting half");
523 if (flt_reg_pairs + 1 < flt_reg_max) {
524 regs[i].set2(as_FloatRegister(flt_reg_pairs)->as_VMReg());
525 flt_reg_pairs += 2;
526 } else {
527 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
528 stk_reg_pairs += 2;
529 }
530 break;
531 case T_VOID: regs[i].set_bad(); break; // Halves of longs & doubles
532 default:
533 ShouldNotReachHere();
534 }
535 }
537 // retun the amount of stack space these arguments will need.
538 return stk_reg_pairs;
540 }
542 // Helper class mostly to avoid passing masm everywhere, and handle
543 // store displacement overflow logic.
544 class AdapterGenerator {
545 MacroAssembler *masm;
546 Register Rdisp;
547 void set_Rdisp(Register r) { Rdisp = r; }
549 void patch_callers_callsite();
550 void tag_c2i_arg(frame::Tag t, Register base, int st_off, Register scratch);
552 // base+st_off points to top of argument
553 int arg_offset(const int st_off) { return st_off + Interpreter::value_offset_in_bytes(); }
554 int next_arg_offset(const int st_off) {
555 return st_off - Interpreter::stackElementSize() + Interpreter::value_offset_in_bytes();
556 }
558 int tag_offset(const int st_off) { return st_off + Interpreter::tag_offset_in_bytes(); }
559 int next_tag_offset(const int st_off) {
560 return st_off - Interpreter::stackElementSize() + Interpreter::tag_offset_in_bytes();
561 }
563 // Argument slot values may be loaded first into a register because
564 // they might not fit into displacement.
565 RegisterOrConstant arg_slot(const int st_off);
566 RegisterOrConstant next_arg_slot(const int st_off);
568 RegisterOrConstant tag_slot(const int st_off);
569 RegisterOrConstant next_tag_slot(const int st_off);
571 // Stores long into offset pointed to by base
572 void store_c2i_long(Register r, Register base,
573 const int st_off, bool is_stack);
574 void store_c2i_object(Register r, Register base,
575 const int st_off);
576 void store_c2i_int(Register r, Register base,
577 const int st_off);
578 void store_c2i_double(VMReg r_2,
579 VMReg r_1, Register base, const int st_off);
580 void store_c2i_float(FloatRegister f, Register base,
581 const int st_off);
583 public:
584 void gen_c2i_adapter(int total_args_passed,
585 // VMReg max_arg,
586 int comp_args_on_stack, // VMRegStackSlots
587 const BasicType *sig_bt,
588 const VMRegPair *regs,
589 Label& skip_fixup);
590 void gen_i2c_adapter(int total_args_passed,
591 // VMReg max_arg,
592 int comp_args_on_stack, // VMRegStackSlots
593 const BasicType *sig_bt,
594 const VMRegPair *regs);
596 AdapterGenerator(MacroAssembler *_masm) : masm(_masm) {}
597 };
600 // Patch the callers callsite with entry to compiled code if it exists.
601 void AdapterGenerator::patch_callers_callsite() {
602 Label L;
603 __ ld_ptr(G5_method, in_bytes(methodOopDesc::code_offset()), G3_scratch);
604 __ br_null(G3_scratch, false, __ pt, L);
605 // Schedule the branch target address early.
606 __ delayed()->ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
607 // Call into the VM to patch the caller, then jump to compiled callee
608 __ save_frame(4); // Args in compiled layout; do not blow them
610 // Must save all the live Gregs the list is:
611 // G1: 1st Long arg (32bit build)
612 // G2: global allocated to TLS
613 // G3: used in inline cache check (scratch)
614 // G4: 2nd Long arg (32bit build);
615 // G5: used in inline cache check (methodOop)
617 // The longs must go to the stack by hand since in the 32 bit build they can be trashed by window ops.
619 #ifdef _LP64
620 // mov(s,d)
621 __ mov(G1, L1);
622 __ mov(G4, L4);
623 __ mov(G5_method, L5);
624 __ mov(G5_method, O0); // VM needs target method
625 __ mov(I7, O1); // VM needs caller's callsite
626 // Must be a leaf call...
627 // can be very far once the blob has been relocated
628 AddressLiteral dest(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite));
629 __ relocate(relocInfo::runtime_call_type);
630 __ jumpl_to(dest, O7, O7);
631 __ delayed()->mov(G2_thread, L7_thread_cache);
632 __ mov(L7_thread_cache, G2_thread);
633 __ mov(L1, G1);
634 __ mov(L4, G4);
635 __ mov(L5, G5_method);
636 #else
637 __ stx(G1, FP, -8 + STACK_BIAS);
638 __ stx(G4, FP, -16 + STACK_BIAS);
639 __ mov(G5_method, L5);
640 __ mov(G5_method, O0); // VM needs target method
641 __ mov(I7, O1); // VM needs caller's callsite
642 // Must be a leaf call...
643 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite), relocInfo::runtime_call_type);
644 __ delayed()->mov(G2_thread, L7_thread_cache);
645 __ mov(L7_thread_cache, G2_thread);
646 __ ldx(FP, -8 + STACK_BIAS, G1);
647 __ ldx(FP, -16 + STACK_BIAS, G4);
648 __ mov(L5, G5_method);
649 __ ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
650 #endif /* _LP64 */
652 __ restore(); // Restore args
653 __ bind(L);
654 }
656 void AdapterGenerator::tag_c2i_arg(frame::Tag t, Register base, int st_off,
657 Register scratch) {
658 if (TaggedStackInterpreter) {
659 RegisterOrConstant slot = tag_slot(st_off);
660 // have to store zero because local slots can be reused (rats!)
661 if (t == frame::TagValue) {
662 __ st_ptr(G0, base, slot);
663 } else if (t == frame::TagCategory2) {
664 __ st_ptr(G0, base, slot);
665 __ st_ptr(G0, base, next_tag_slot(st_off));
666 } else {
667 __ mov(t, scratch);
668 __ st_ptr(scratch, base, slot);
669 }
670 }
671 }
674 RegisterOrConstant AdapterGenerator::arg_slot(const int st_off) {
675 RegisterOrConstant roc(arg_offset(st_off));
676 return __ ensure_simm13_or_reg(roc, Rdisp);
677 }
679 RegisterOrConstant AdapterGenerator::next_arg_slot(const int st_off) {
680 RegisterOrConstant roc(next_arg_offset(st_off));
681 return __ ensure_simm13_or_reg(roc, Rdisp);
682 }
685 RegisterOrConstant AdapterGenerator::tag_slot(const int st_off) {
686 RegisterOrConstant roc(tag_offset(st_off));
687 return __ ensure_simm13_or_reg(roc, Rdisp);
688 }
690 RegisterOrConstant AdapterGenerator::next_tag_slot(const int st_off) {
691 RegisterOrConstant roc(next_tag_offset(st_off));
692 return __ ensure_simm13_or_reg(roc, Rdisp);
693 }
696 // Stores long into offset pointed to by base
697 void AdapterGenerator::store_c2i_long(Register r, Register base,
698 const int st_off, bool is_stack) {
699 #ifdef _LP64
700 // In V9, longs are given 2 64-bit slots in the interpreter, but the
701 // data is passed in only 1 slot.
702 __ stx(r, base, next_arg_slot(st_off));
703 #else
704 #ifdef COMPILER2
705 // Misaligned store of 64-bit data
706 __ stw(r, base, arg_slot(st_off)); // lo bits
707 __ srlx(r, 32, r);
708 __ stw(r, base, next_arg_slot(st_off)); // hi bits
709 #else
710 if (is_stack) {
711 // Misaligned store of 64-bit data
712 __ stw(r, base, arg_slot(st_off)); // lo bits
713 __ srlx(r, 32, r);
714 __ stw(r, base, next_arg_slot(st_off)); // hi bits
715 } else {
716 __ stw(r->successor(), base, arg_slot(st_off) ); // lo bits
717 __ stw(r , base, next_arg_slot(st_off)); // hi bits
718 }
719 #endif // COMPILER2
720 #endif // _LP64
721 tag_c2i_arg(frame::TagCategory2, base, st_off, r);
722 }
724 void AdapterGenerator::store_c2i_object(Register r, Register base,
725 const int st_off) {
726 __ st_ptr (r, base, arg_slot(st_off));
727 tag_c2i_arg(frame::TagReference, base, st_off, r);
728 }
730 void AdapterGenerator::store_c2i_int(Register r, Register base,
731 const int st_off) {
732 __ st (r, base, arg_slot(st_off));
733 tag_c2i_arg(frame::TagValue, base, st_off, r);
734 }
736 // Stores into offset pointed to by base
737 void AdapterGenerator::store_c2i_double(VMReg r_2,
738 VMReg r_1, Register base, const int st_off) {
739 #ifdef _LP64
740 // In V9, doubles are given 2 64-bit slots in the interpreter, but the
741 // data is passed in only 1 slot.
742 __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), base, next_arg_slot(st_off));
743 #else
744 // Need to marshal 64-bit value from misaligned Lesp loads
745 __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), base, next_arg_slot(st_off));
746 __ stf(FloatRegisterImpl::S, r_2->as_FloatRegister(), base, arg_slot(st_off) );
747 #endif
748 tag_c2i_arg(frame::TagCategory2, base, st_off, G1_scratch);
749 }
751 void AdapterGenerator::store_c2i_float(FloatRegister f, Register base,
752 const int st_off) {
753 __ stf(FloatRegisterImpl::S, f, base, arg_slot(st_off));
754 tag_c2i_arg(frame::TagValue, base, st_off, G1_scratch);
755 }
757 void AdapterGenerator::gen_c2i_adapter(
758 int total_args_passed,
759 // VMReg max_arg,
760 int comp_args_on_stack, // VMRegStackSlots
761 const BasicType *sig_bt,
762 const VMRegPair *regs,
763 Label& skip_fixup) {
765 // Before we get into the guts of the C2I adapter, see if we should be here
766 // at all. We've come from compiled code and are attempting to jump to the
767 // interpreter, which means the caller made a static call to get here
768 // (vcalls always get a compiled target if there is one). Check for a
769 // compiled target. If there is one, we need to patch the caller's call.
770 // However we will run interpreted if we come thru here. The next pass
771 // thru the call site will run compiled. If we ran compiled here then
772 // we can (theorectically) do endless i2c->c2i->i2c transitions during
773 // deopt/uncommon trap cycles. If we always go interpreted here then
774 // we can have at most one and don't need to play any tricks to keep
775 // from endlessly growing the stack.
776 //
777 // Actually if we detected that we had an i2c->c2i transition here we
778 // ought to be able to reset the world back to the state of the interpreted
779 // call and not bother building another interpreter arg area. We don't
780 // do that at this point.
782 patch_callers_callsite();
784 __ bind(skip_fixup);
786 // Since all args are passed on the stack, total_args_passed*wordSize is the
787 // space we need. Add in varargs area needed by the interpreter. Round up
788 // to stack alignment.
789 const int arg_size = total_args_passed * Interpreter::stackElementSize();
790 const int varargs_area =
791 (frame::varargs_offset - frame::register_save_words)*wordSize;
792 const int extraspace = round_to(arg_size + varargs_area, 2*wordSize);
794 int bias = STACK_BIAS;
795 const int interp_arg_offset = frame::varargs_offset*wordSize +
796 (total_args_passed-1)*Interpreter::stackElementSize();
798 Register base = SP;
800 #ifdef _LP64
801 // In the 64bit build because of wider slots and STACKBIAS we can run
802 // out of bits in the displacement to do loads and stores. Use g3 as
803 // temporary displacement.
804 if (! __ is_simm13(extraspace)) {
805 __ set(extraspace, G3_scratch);
806 __ sub(SP, G3_scratch, SP);
807 } else {
808 __ sub(SP, extraspace, SP);
809 }
810 set_Rdisp(G3_scratch);
811 #else
812 __ sub(SP, extraspace, SP);
813 #endif // _LP64
815 // First write G1 (if used) to where ever it must go
816 for (int i=0; i<total_args_passed; i++) {
817 const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize()) + bias;
818 VMReg r_1 = regs[i].first();
819 VMReg r_2 = regs[i].second();
820 if (r_1 == G1_scratch->as_VMReg()) {
821 if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) {
822 store_c2i_object(G1_scratch, base, st_off);
823 } else if (sig_bt[i] == T_LONG) {
824 assert(!TieredCompilation, "should not use register args for longs");
825 store_c2i_long(G1_scratch, base, st_off, false);
826 } else {
827 store_c2i_int(G1_scratch, base, st_off);
828 }
829 }
830 }
832 // Now write the args into the outgoing interpreter space
833 for (int i=0; i<total_args_passed; i++) {
834 const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize()) + bias;
835 VMReg r_1 = regs[i].first();
836 VMReg r_2 = regs[i].second();
837 if (!r_1->is_valid()) {
838 assert(!r_2->is_valid(), "");
839 continue;
840 }
841 // Skip G1 if found as we did it first in order to free it up
842 if (r_1 == G1_scratch->as_VMReg()) {
843 continue;
844 }
845 #ifdef ASSERT
846 bool G1_forced = false;
847 #endif // ASSERT
848 if (r_1->is_stack()) { // Pretend stack targets are loaded into G1
849 #ifdef _LP64
850 Register ld_off = Rdisp;
851 __ set(reg2offset(r_1) + extraspace + bias, ld_off);
852 #else
853 int ld_off = reg2offset(r_1) + extraspace + bias;
854 #ifdef ASSERT
855 G1_forced = true;
856 #endif // ASSERT
857 #endif // _LP64
858 r_1 = G1_scratch->as_VMReg();// as part of the load/store shuffle
859 if (!r_2->is_valid()) __ ld (base, ld_off, G1_scratch);
860 else __ ldx(base, ld_off, G1_scratch);
861 }
863 if (r_1->is_Register()) {
864 Register r = r_1->as_Register()->after_restore();
865 if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) {
866 store_c2i_object(r, base, st_off);
867 } else if (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
868 if (TieredCompilation) {
869 assert(G1_forced || sig_bt[i] != T_LONG, "should not use register args for longs");
870 }
871 store_c2i_long(r, base, st_off, r_2->is_stack());
872 } else {
873 store_c2i_int(r, base, st_off);
874 }
875 } else {
876 assert(r_1->is_FloatRegister(), "");
877 if (sig_bt[i] == T_FLOAT) {
878 store_c2i_float(r_1->as_FloatRegister(), base, st_off);
879 } else {
880 assert(sig_bt[i] == T_DOUBLE, "wrong type");
881 store_c2i_double(r_2, r_1, base, st_off);
882 }
883 }
884 }
886 #ifdef _LP64
887 // Need to reload G3_scratch, used for temporary displacements.
888 __ ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
890 // Pass O5_savedSP as an argument to the interpreter.
891 // The interpreter will restore SP to this value before returning.
892 __ set(extraspace, G1);
893 __ add(SP, G1, O5_savedSP);
894 #else
895 // Pass O5_savedSP as an argument to the interpreter.
896 // The interpreter will restore SP to this value before returning.
897 __ add(SP, extraspace, O5_savedSP);
898 #endif // _LP64
900 __ mov((frame::varargs_offset)*wordSize -
901 1*Interpreter::stackElementSize()+bias+BytesPerWord, G1);
902 // Jump to the interpreter just as if interpreter was doing it.
903 __ jmpl(G3_scratch, 0, G0);
904 // Setup Lesp for the call. Cannot actually set Lesp as the current Lesp
905 // (really L0) is in use by the compiled frame as a generic temp. However,
906 // the interpreter does not know where its args are without some kind of
907 // arg pointer being passed in. Pass it in Gargs.
908 __ delayed()->add(SP, G1, Gargs);
909 }
911 void AdapterGenerator::gen_i2c_adapter(
912 int total_args_passed,
913 // VMReg max_arg,
914 int comp_args_on_stack, // VMRegStackSlots
915 const BasicType *sig_bt,
916 const VMRegPair *regs) {
918 // Generate an I2C adapter: adjust the I-frame to make space for the C-frame
919 // layout. Lesp was saved by the calling I-frame and will be restored on
920 // return. Meanwhile, outgoing arg space is all owned by the callee
921 // C-frame, so we can mangle it at will. After adjusting the frame size,
922 // hoist register arguments and repack other args according to the compiled
923 // code convention. Finally, end in a jump to the compiled code. The entry
924 // point address is the start of the buffer.
926 // We will only enter here from an interpreted frame and never from after
927 // passing thru a c2i. Azul allowed this but we do not. If we lose the
928 // race and use a c2i we will remain interpreted for the race loser(s).
929 // This removes all sorts of headaches on the x86 side and also eliminates
930 // the possibility of having c2i -> i2c -> c2i -> ... endless transitions.
932 // As you can see from the list of inputs & outputs there are not a lot
933 // of temp registers to work with: mostly G1, G3 & G4.
935 // Inputs:
936 // G2_thread - TLS
937 // G5_method - Method oop
938 // G4 (Gargs) - Pointer to interpreter's args
939 // O0..O4 - free for scratch
940 // O5_savedSP - Caller's saved SP, to be restored if needed
941 // O6 - Current SP!
942 // O7 - Valid return address
943 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet)
945 // Outputs:
946 // G2_thread - TLS
947 // G1, G4 - Outgoing long args in 32-bit build
948 // O0-O5 - Outgoing args in compiled layout
949 // O6 - Adjusted or restored SP
950 // O7 - Valid return address
951 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet)
952 // F0-F7 - more outgoing args
955 // Gargs is the incoming argument base, and also an outgoing argument.
956 __ sub(Gargs, BytesPerWord, Gargs);
958 #ifdef ASSERT
959 {
960 // on entry OsavedSP and SP should be equal
961 Label ok;
962 __ cmp(O5_savedSP, SP);
963 __ br(Assembler::equal, false, Assembler::pt, ok);
964 __ delayed()->nop();
965 __ stop("I5_savedSP not set");
966 __ should_not_reach_here();
967 __ bind(ok);
968 }
969 #endif
971 // ON ENTRY TO THE CODE WE ARE MAKING, WE HAVE AN INTERPRETED FRAME
972 // WITH O7 HOLDING A VALID RETURN PC
973 //
974 // | |
975 // : java stack :
976 // | |
977 // +--------------+ <--- start of outgoing args
978 // | receiver | |
979 // : rest of args : |---size is java-arg-words
980 // | | |
981 // +--------------+ <--- O4_args (misaligned) and Lesp if prior is not C2I
982 // | | |
983 // : unused : |---Space for max Java stack, plus stack alignment
984 // | | |
985 // +--------------+ <--- SP + 16*wordsize
986 // | |
987 // : window :
988 // | |
989 // +--------------+ <--- SP
991 // WE REPACK THE STACK. We use the common calling convention layout as
992 // discovered by calling SharedRuntime::calling_convention. We assume it
993 // causes an arbitrary shuffle of memory, which may require some register
994 // temps to do the shuffle. We hope for (and optimize for) the case where
995 // temps are not needed. We may have to resize the stack slightly, in case
996 // we need alignment padding (32-bit interpreter can pass longs & doubles
997 // misaligned, but the compilers expect them aligned).
998 //
999 // | |
1000 // : java stack :
1001 // | |
1002 // +--------------+ <--- start of outgoing args
1003 // | pad, align | |
1004 // +--------------+ |
1005 // | ints, floats | |---Outgoing stack args, packed low.
1006 // +--------------+ | First few args in registers.
1007 // : doubles : |
1008 // | longs | |
1009 // +--------------+ <--- SP' + 16*wordsize
1010 // | |
1011 // : window :
1012 // | |
1013 // +--------------+ <--- SP'
1015 // ON EXIT FROM THE CODE WE ARE MAKING, WE STILL HAVE AN INTERPRETED FRAME
1016 // WITH O7 HOLDING A VALID RETURN PC - ITS JUST THAT THE ARGS ARE NOW SETUP
1017 // FOR COMPILED CODE AND THE FRAME SLIGHTLY GROWN.
1019 // Cut-out for having no stack args. Since up to 6 args are passed
1020 // in registers, we will commonly have no stack args.
1021 if (comp_args_on_stack > 0) {
1023 // Convert VMReg stack slots to words.
1024 int comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
1025 // Round up to miminum stack alignment, in wordSize
1026 comp_words_on_stack = round_to(comp_words_on_stack, 2);
1027 // Now compute the distance from Lesp to SP. This calculation does not
1028 // include the space for total_args_passed because Lesp has not yet popped
1029 // the arguments.
1030 __ sub(SP, (comp_words_on_stack)*wordSize, SP);
1031 }
1033 // Will jump to the compiled code just as if compiled code was doing it.
1034 // Pre-load the register-jump target early, to schedule it better.
1035 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3);
1037 // Now generate the shuffle code. Pick up all register args and move the
1038 // rest through G1_scratch.
1039 for (int i=0; i<total_args_passed; i++) {
1040 if (sig_bt[i] == T_VOID) {
1041 // Longs and doubles are passed in native word order, but misaligned
1042 // in the 32-bit build.
1043 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
1044 continue;
1045 }
1047 // Pick up 0, 1 or 2 words from Lesp+offset. Assume mis-aligned in the
1048 // 32-bit build and aligned in the 64-bit build. Look for the obvious
1049 // ldx/lddf optimizations.
1051 // Load in argument order going down.
1052 const int ld_off = (total_args_passed-i)*Interpreter::stackElementSize();
1053 set_Rdisp(G1_scratch);
1055 VMReg r_1 = regs[i].first();
1056 VMReg r_2 = regs[i].second();
1057 if (!r_1->is_valid()) {
1058 assert(!r_2->is_valid(), "");
1059 continue;
1060 }
1061 if (r_1->is_stack()) { // Pretend stack targets are loaded into F8/F9
1062 r_1 = F8->as_VMReg(); // as part of the load/store shuffle
1063 if (r_2->is_valid()) r_2 = r_1->next();
1064 }
1065 if (r_1->is_Register()) { // Register argument
1066 Register r = r_1->as_Register()->after_restore();
1067 if (!r_2->is_valid()) {
1068 __ ld(Gargs, arg_slot(ld_off), r);
1069 } else {
1070 #ifdef _LP64
1071 // In V9, longs are given 2 64-bit slots in the interpreter, but the
1072 // data is passed in only 1 slot.
1073 RegisterOrConstant slot = (sig_bt[i] == T_LONG) ?
1074 next_arg_slot(ld_off) : arg_slot(ld_off);
1075 __ ldx(Gargs, slot, r);
1076 #else
1077 // Need to load a 64-bit value into G1/G4, but G1/G4 is being used in the
1078 // stack shuffle. Load the first 2 longs into G1/G4 later.
1079 #endif
1080 }
1081 } else {
1082 assert(r_1->is_FloatRegister(), "");
1083 if (!r_2->is_valid()) {
1084 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_1->as_FloatRegister());
1085 } else {
1086 #ifdef _LP64
1087 // In V9, doubles are given 2 64-bit slots in the interpreter, but the
1088 // data is passed in only 1 slot. This code also handles longs that
1089 // are passed on the stack, but need a stack-to-stack move through a
1090 // spare float register.
1091 RegisterOrConstant slot = (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) ?
1092 next_arg_slot(ld_off) : arg_slot(ld_off);
1093 __ ldf(FloatRegisterImpl::D, Gargs, slot, r_1->as_FloatRegister());
1094 #else
1095 // Need to marshal 64-bit value from misaligned Lesp loads
1096 __ ldf(FloatRegisterImpl::S, Gargs, next_arg_slot(ld_off), r_1->as_FloatRegister());
1097 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_2->as_FloatRegister());
1098 #endif
1099 }
1100 }
1101 // Was the argument really intended to be on the stack, but was loaded
1102 // into F8/F9?
1103 if (regs[i].first()->is_stack()) {
1104 assert(r_1->as_FloatRegister() == F8, "fix this code");
1105 // Convert stack slot to an SP offset
1106 int st_off = reg2offset(regs[i].first()) + STACK_BIAS;
1107 // Store down the shuffled stack word. Target address _is_ aligned.
1108 RegisterOrConstant slot = __ ensure_simm13_or_reg(st_off, Rdisp);
1109 if (!r_2->is_valid()) __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), SP, slot);
1110 else __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), SP, slot);
1111 }
1112 }
1113 bool made_space = false;
1114 #ifndef _LP64
1115 // May need to pick up a few long args in G1/G4
1116 bool g4_crushed = false;
1117 bool g3_crushed = false;
1118 for (int i=0; i<total_args_passed; i++) {
1119 if (regs[i].first()->is_Register() && regs[i].second()->is_valid()) {
1120 // Load in argument order going down
1121 int ld_off = (total_args_passed-i)*Interpreter::stackElementSize();
1122 // Need to marshal 64-bit value from misaligned Lesp loads
1123 Register r = regs[i].first()->as_Register()->after_restore();
1124 if (r == G1 || r == G4) {
1125 assert(!g4_crushed, "ordering problem");
1126 if (r == G4){
1127 g4_crushed = true;
1128 __ lduw(Gargs, arg_slot(ld_off) , G3_scratch); // Load lo bits
1129 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits
1130 } else {
1131 // better schedule this way
1132 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits
1133 __ lduw(Gargs, arg_slot(ld_off) , G3_scratch); // Load lo bits
1134 }
1135 g3_crushed = true;
1136 __ sllx(r, 32, r);
1137 __ or3(G3_scratch, r, r);
1138 } else {
1139 assert(r->is_out(), "longs passed in two O registers");
1140 __ ld (Gargs, arg_slot(ld_off) , r->successor()); // Load lo bits
1141 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits
1142 }
1143 }
1144 }
1145 #endif
1147 // Jump to the compiled code just as if compiled code was doing it.
1148 //
1149 #ifndef _LP64
1150 if (g3_crushed) {
1151 // Rats load was wasted, at least it is in cache...
1152 __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3);
1153 }
1154 #endif /* _LP64 */
1156 // 6243940 We might end up in handle_wrong_method if
1157 // the callee is deoptimized as we race thru here. If that
1158 // happens we don't want to take a safepoint because the
1159 // caller frame will look interpreted and arguments are now
1160 // "compiled" so it is much better to make this transition
1161 // invisible to the stack walking code. Unfortunately if
1162 // we try and find the callee by normal means a safepoint
1163 // is possible. So we stash the desired callee in the thread
1164 // and the vm will find there should this case occur.
1165 Address callee_target_addr(G2_thread, JavaThread::callee_target_offset());
1166 __ st_ptr(G5_method, callee_target_addr);
1168 if (StressNonEntrant) {
1169 // Open a big window for deopt failure
1170 __ save_frame(0);
1171 __ mov(G0, L0);
1172 Label loop;
1173 __ bind(loop);
1174 __ sub(L0, 1, L0);
1175 __ br_null(L0, false, Assembler::pt, loop);
1176 __ delayed()->nop();
1178 __ restore();
1179 }
1182 __ jmpl(G3, 0, G0);
1183 __ delayed()->nop();
1184 }
1186 // ---------------------------------------------------------------
1187 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
1188 int total_args_passed,
1189 // VMReg max_arg,
1190 int comp_args_on_stack, // VMRegStackSlots
1191 const BasicType *sig_bt,
1192 const VMRegPair *regs) {
1193 address i2c_entry = __ pc();
1195 AdapterGenerator agen(masm);
1197 agen.gen_i2c_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs);
1200 // -------------------------------------------------------------------------
1201 // Generate a C2I adapter. On entry we know G5 holds the methodOop. The
1202 // args start out packed in the compiled layout. They need to be unpacked
1203 // into the interpreter layout. This will almost always require some stack
1204 // space. We grow the current (compiled) stack, then repack the args. We
1205 // finally end in a jump to the generic interpreter entry point. On exit
1206 // from the interpreter, the interpreter will restore our SP (lest the
1207 // compiled code, which relys solely on SP and not FP, get sick).
1209 address c2i_unverified_entry = __ pc();
1210 Label skip_fixup;
1211 {
1212 #if !defined(_LP64) && defined(COMPILER2)
1213 Register R_temp = L0; // another scratch register
1214 #else
1215 Register R_temp = G1; // another scratch register
1216 #endif
1218 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
1220 __ verify_oop(O0);
1221 __ verify_oop(G5_method);
1222 __ load_klass(O0, G3_scratch);
1223 __ verify_oop(G3_scratch);
1225 #if !defined(_LP64) && defined(COMPILER2)
1226 __ save(SP, -frame::register_save_words*wordSize, SP);
1227 __ ld_ptr(G5_method, compiledICHolderOopDesc::holder_klass_offset(), R_temp);
1228 __ verify_oop(R_temp);
1229 __ cmp(G3_scratch, R_temp);
1230 __ restore();
1231 #else
1232 __ ld_ptr(G5_method, compiledICHolderOopDesc::holder_klass_offset(), R_temp);
1233 __ verify_oop(R_temp);
1234 __ cmp(G3_scratch, R_temp);
1235 #endif
1237 Label ok, ok2;
1238 __ brx(Assembler::equal, false, Assembler::pt, ok);
1239 __ delayed()->ld_ptr(G5_method, compiledICHolderOopDesc::holder_method_offset(), G5_method);
1240 __ jump_to(ic_miss, G3_scratch);
1241 __ delayed()->nop();
1243 __ bind(ok);
1244 // Method might have been compiled since the call site was patched to
1245 // interpreted if that is the case treat it as a miss so we can get
1246 // the call site corrected.
1247 __ ld_ptr(G5_method, in_bytes(methodOopDesc::code_offset()), G3_scratch);
1248 __ bind(ok2);
1249 __ br_null(G3_scratch, false, __ pt, skip_fixup);
1250 __ delayed()->ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
1251 __ jump_to(ic_miss, G3_scratch);
1252 __ delayed()->nop();
1254 }
1256 address c2i_entry = __ pc();
1258 agen.gen_c2i_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
1260 __ flush();
1261 return new AdapterHandlerEntry(i2c_entry, c2i_entry, c2i_unverified_entry);
1263 }
1265 // Helper function for native calling conventions
1266 static VMReg int_stk_helper( int i ) {
1267 // Bias any stack based VMReg we get by ignoring the window area
1268 // but not the register parameter save area.
1269 //
1270 // This is strange for the following reasons. We'd normally expect
1271 // the calling convention to return an VMReg for a stack slot
1272 // completely ignoring any abi reserved area. C2 thinks of that
1273 // abi area as only out_preserve_stack_slots. This does not include
1274 // the area allocated by the C abi to store down integer arguments
1275 // because the java calling convention does not use it. So
1276 // since c2 assumes that there are only out_preserve_stack_slots
1277 // to bias the optoregs (which impacts VMRegs) when actually referencing any actual stack
1278 // location the c calling convention must add in this bias amount
1279 // to make up for the fact that the out_preserve_stack_slots is
1280 // insufficient for C calls. What a mess. I sure hope those 6
1281 // stack words were worth it on every java call!
1283 // Another way of cleaning this up would be for out_preserve_stack_slots
1284 // to take a parameter to say whether it was C or java calling conventions.
1285 // Then things might look a little better (but not much).
1287 int mem_parm_offset = i - SPARC_ARGS_IN_REGS_NUM;
1288 if( mem_parm_offset < 0 ) {
1289 return as_oRegister(i)->as_VMReg();
1290 } else {
1291 int actual_offset = (mem_parm_offset + frame::memory_parameter_word_sp_offset) * VMRegImpl::slots_per_word;
1292 // Now return a biased offset that will be correct when out_preserve_slots is added back in
1293 return VMRegImpl::stack2reg(actual_offset - SharedRuntime::out_preserve_stack_slots());
1294 }
1295 }
1298 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
1299 VMRegPair *regs,
1300 int total_args_passed) {
1302 // Return the number of VMReg stack_slots needed for the args.
1303 // This value does not include an abi space (like register window
1304 // save area).
1306 // The native convention is V8 if !LP64
1307 // The LP64 convention is the V9 convention which is slightly more sane.
1309 // We return the amount of VMReg stack slots we need to reserve for all
1310 // the arguments NOT counting out_preserve_stack_slots. Since we always
1311 // have space for storing at least 6 registers to memory we start with that.
1312 // See int_stk_helper for a further discussion.
1313 int max_stack_slots = (frame::varargs_offset * VMRegImpl::slots_per_word) - SharedRuntime::out_preserve_stack_slots();
1315 #ifdef _LP64
1316 // V9 convention: All things "as-if" on double-wide stack slots.
1317 // Hoist any int/ptr/long's in the first 6 to int regs.
1318 // Hoist any flt/dbl's in the first 16 dbl regs.
1319 int j = 0; // Count of actual args, not HALVES
1320 for( int i=0; i<total_args_passed; i++, j++ ) {
1321 switch( sig_bt[i] ) {
1322 case T_BOOLEAN:
1323 case T_BYTE:
1324 case T_CHAR:
1325 case T_INT:
1326 case T_SHORT:
1327 regs[i].set1( int_stk_helper( j ) ); break;
1328 case T_LONG:
1329 assert( sig_bt[i+1] == T_VOID, "expecting half" );
1330 case T_ADDRESS: // raw pointers, like current thread, for VM calls
1331 case T_ARRAY:
1332 case T_OBJECT:
1333 regs[i].set2( int_stk_helper( j ) );
1334 break;
1335 case T_FLOAT:
1336 if ( j < 16 ) {
1337 // V9ism: floats go in ODD registers
1338 regs[i].set1(as_FloatRegister(1 + (j<<1))->as_VMReg());
1339 } else {
1340 // V9ism: floats go in ODD stack slot
1341 regs[i].set1(VMRegImpl::stack2reg(1 + (j<<1)));
1342 }
1343 break;
1344 case T_DOUBLE:
1345 assert( sig_bt[i+1] == T_VOID, "expecting half" );
1346 if ( j < 16 ) {
1347 // V9ism: doubles go in EVEN/ODD regs
1348 regs[i].set2(as_FloatRegister(j<<1)->as_VMReg());
1349 } else {
1350 // V9ism: doubles go in EVEN/ODD stack slots
1351 regs[i].set2(VMRegImpl::stack2reg(j<<1));
1352 }
1353 break;
1354 case T_VOID: regs[i].set_bad(); j--; break; // Do not count HALVES
1355 default:
1356 ShouldNotReachHere();
1357 }
1358 if (regs[i].first()->is_stack()) {
1359 int off = regs[i].first()->reg2stack();
1360 if (off > max_stack_slots) max_stack_slots = off;
1361 }
1362 if (regs[i].second()->is_stack()) {
1363 int off = regs[i].second()->reg2stack();
1364 if (off > max_stack_slots) max_stack_slots = off;
1365 }
1366 }
1368 #else // _LP64
1369 // V8 convention: first 6 things in O-regs, rest on stack.
1370 // Alignment is willy-nilly.
1371 for( int i=0; i<total_args_passed; i++ ) {
1372 switch( sig_bt[i] ) {
1373 case T_ADDRESS: // raw pointers, like current thread, for VM calls
1374 case T_ARRAY:
1375 case T_BOOLEAN:
1376 case T_BYTE:
1377 case T_CHAR:
1378 case T_FLOAT:
1379 case T_INT:
1380 case T_OBJECT:
1381 case T_SHORT:
1382 regs[i].set1( int_stk_helper( i ) );
1383 break;
1384 case T_DOUBLE:
1385 case T_LONG:
1386 assert( sig_bt[i+1] == T_VOID, "expecting half" );
1387 regs[i].set_pair( int_stk_helper( i+1 ), int_stk_helper( i ) );
1388 break;
1389 case T_VOID: regs[i].set_bad(); break;
1390 default:
1391 ShouldNotReachHere();
1392 }
1393 if (regs[i].first()->is_stack()) {
1394 int off = regs[i].first()->reg2stack();
1395 if (off > max_stack_slots) max_stack_slots = off;
1396 }
1397 if (regs[i].second()->is_stack()) {
1398 int off = regs[i].second()->reg2stack();
1399 if (off > max_stack_slots) max_stack_slots = off;
1400 }
1401 }
1402 #endif // _LP64
1404 return round_to(max_stack_slots + 1, 2);
1406 }
1409 // ---------------------------------------------------------------------------
1410 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1411 switch (ret_type) {
1412 case T_FLOAT:
1413 __ stf(FloatRegisterImpl::S, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS);
1414 break;
1415 case T_DOUBLE:
1416 __ stf(FloatRegisterImpl::D, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS);
1417 break;
1418 }
1419 }
1421 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1422 switch (ret_type) {
1423 case T_FLOAT:
1424 __ ldf(FloatRegisterImpl::S, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS, F0);
1425 break;
1426 case T_DOUBLE:
1427 __ ldf(FloatRegisterImpl::D, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS, F0);
1428 break;
1429 }
1430 }
1432 // Check and forward and pending exception. Thread is stored in
1433 // L7_thread_cache and possibly NOT in G2_thread. Since this is a native call, there
1434 // is no exception handler. We merely pop this frame off and throw the
1435 // exception in the caller's frame.
1436 static void check_forward_pending_exception(MacroAssembler *masm, Register Rex_oop) {
1437 Label L;
1438 __ br_null(Rex_oop, false, Assembler::pt, L);
1439 __ delayed()->mov(L7_thread_cache, G2_thread); // restore in case we have exception
1440 // Since this is a native call, we *know* the proper exception handler
1441 // without calling into the VM: it's the empty function. Just pop this
1442 // frame and then jump to forward_exception_entry; O7 will contain the
1443 // native caller's return PC.
1444 AddressLiteral exception_entry(StubRoutines::forward_exception_entry());
1445 __ jump_to(exception_entry, G3_scratch);
1446 __ delayed()->restore(); // Pop this frame off.
1447 __ bind(L);
1448 }
1450 // A simple move of integer like type
1451 static void simple_move32(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1452 if (src.first()->is_stack()) {
1453 if (dst.first()->is_stack()) {
1454 // stack to stack
1455 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
1456 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
1457 } else {
1458 // stack to reg
1459 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1460 }
1461 } else if (dst.first()->is_stack()) {
1462 // reg to stack
1463 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
1464 } else {
1465 __ mov(src.first()->as_Register(), dst.first()->as_Register());
1466 }
1467 }
1469 // On 64 bit we will store integer like items to the stack as
1470 // 64 bits items (sparc abi) even though java would only store
1471 // 32bits for a parameter. On 32bit it will simply be 32 bits
1472 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
1473 static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1474 if (src.first()->is_stack()) {
1475 if (dst.first()->is_stack()) {
1476 // stack to stack
1477 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
1478 __ st_ptr(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
1479 } else {
1480 // stack to reg
1481 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1482 }
1483 } else if (dst.first()->is_stack()) {
1484 // reg to stack
1485 __ st_ptr(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
1486 } else {
1487 __ mov(src.first()->as_Register(), dst.first()->as_Register());
1488 }
1489 }
1492 // An oop arg. Must pass a handle not the oop itself
1493 static void object_move(MacroAssembler* masm,
1494 OopMap* map,
1495 int oop_handle_offset,
1496 int framesize_in_slots,
1497 VMRegPair src,
1498 VMRegPair dst,
1499 bool is_receiver,
1500 int* receiver_offset) {
1502 // must pass a handle. First figure out the location we use as a handle
1504 if (src.first()->is_stack()) {
1505 // Oop is already on the stack
1506 Register rHandle = dst.first()->is_stack() ? L5 : dst.first()->as_Register();
1507 __ add(FP, reg2offset(src.first()) + STACK_BIAS, rHandle);
1508 __ ld_ptr(rHandle, 0, L4);
1509 #ifdef _LP64
1510 __ movr( Assembler::rc_z, L4, G0, rHandle );
1511 #else
1512 __ tst( L4 );
1513 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle );
1514 #endif
1515 if (dst.first()->is_stack()) {
1516 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS);
1517 }
1518 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1519 if (is_receiver) {
1520 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
1521 }
1522 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
1523 } else {
1524 // Oop is in an input register pass we must flush it to the stack
1525 const Register rOop = src.first()->as_Register();
1526 const Register rHandle = L5;
1527 int oop_slot = rOop->input_number() * VMRegImpl::slots_per_word + oop_handle_offset;
1528 int offset = oop_slot*VMRegImpl::stack_slot_size;
1529 Label skip;
1530 __ st_ptr(rOop, SP, offset + STACK_BIAS);
1531 if (is_receiver) {
1532 *receiver_offset = oop_slot * VMRegImpl::stack_slot_size;
1533 }
1534 map->set_oop(VMRegImpl::stack2reg(oop_slot));
1535 __ add(SP, offset + STACK_BIAS, rHandle);
1536 #ifdef _LP64
1537 __ movr( Assembler::rc_z, rOop, G0, rHandle );
1538 #else
1539 __ tst( rOop );
1540 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle );
1541 #endif
1543 if (dst.first()->is_stack()) {
1544 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS);
1545 } else {
1546 __ mov(rHandle, dst.first()->as_Register());
1547 }
1548 }
1549 }
1551 // A float arg may have to do float reg int reg conversion
1552 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1553 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
1555 if (src.first()->is_stack()) {
1556 if (dst.first()->is_stack()) {
1557 // stack to stack the easiest of the bunch
1558 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
1559 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
1560 } else {
1561 // stack to reg
1562 if (dst.first()->is_Register()) {
1563 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1564 } else {
1565 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
1566 }
1567 }
1568 } else if (dst.first()->is_stack()) {
1569 // reg to stack
1570 if (src.first()->is_Register()) {
1571 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
1572 } else {
1573 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
1574 }
1575 } else {
1576 // reg to reg
1577 if (src.first()->is_Register()) {
1578 if (dst.first()->is_Register()) {
1579 // gpr -> gpr
1580 __ mov(src.first()->as_Register(), dst.first()->as_Register());
1581 } else {
1582 // gpr -> fpr
1583 __ st(src.first()->as_Register(), FP, -4 + STACK_BIAS);
1584 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.first()->as_FloatRegister());
1585 }
1586 } else if (dst.first()->is_Register()) {
1587 // fpr -> gpr
1588 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), FP, -4 + STACK_BIAS);
1589 __ ld(FP, -4 + STACK_BIAS, dst.first()->as_Register());
1590 } else {
1591 // fpr -> fpr
1592 // In theory these overlap but the ordering is such that this is likely a nop
1593 if ( src.first() != dst.first()) {
1594 __ fmov(FloatRegisterImpl::S, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister());
1595 }
1596 }
1597 }
1598 }
1600 static void split_long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1601 VMRegPair src_lo(src.first());
1602 VMRegPair src_hi(src.second());
1603 VMRegPair dst_lo(dst.first());
1604 VMRegPair dst_hi(dst.second());
1605 simple_move32(masm, src_lo, dst_lo);
1606 simple_move32(masm, src_hi, dst_hi);
1607 }
1609 // A long move
1610 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1612 // Do the simple ones here else do two int moves
1613 if (src.is_single_phys_reg() ) {
1614 if (dst.is_single_phys_reg()) {
1615 __ mov(src.first()->as_Register(), dst.first()->as_Register());
1616 } else {
1617 // split src into two separate registers
1618 // Remember hi means hi address or lsw on sparc
1619 // Move msw to lsw
1620 if (dst.second()->is_reg()) {
1621 // MSW -> MSW
1622 __ srax(src.first()->as_Register(), 32, dst.first()->as_Register());
1623 // Now LSW -> LSW
1624 // this will only move lo -> lo and ignore hi
1625 VMRegPair split(dst.second());
1626 simple_move32(masm, src, split);
1627 } else {
1628 VMRegPair split(src.first(), L4->as_VMReg());
1629 // MSW -> MSW (lo ie. first word)
1630 __ srax(src.first()->as_Register(), 32, L4);
1631 split_long_move(masm, split, dst);
1632 }
1633 }
1634 } else if (dst.is_single_phys_reg()) {
1635 if (src.is_adjacent_aligned_on_stack(2)) {
1636 __ ldx(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1637 } else {
1638 // dst is a single reg.
1639 // Remember lo is low address not msb for stack slots
1640 // and lo is the "real" register for registers
1641 // src is
1643 VMRegPair split;
1645 if (src.first()->is_reg()) {
1646 // src.lo (msw) is a reg, src.hi is stk/reg
1647 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> src.lo [the MSW is in the LSW of the reg]
1648 split.set_pair(dst.first(), src.first());
1649 } else {
1650 // msw is stack move to L5
1651 // lsw is stack move to dst.lo (real reg)
1652 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> L5
1653 split.set_pair(dst.first(), L5->as_VMReg());
1654 }
1656 // src.lo -> src.lo/L5, src.hi -> dst.lo (the real reg)
1657 // msw -> src.lo/L5, lsw -> dst.lo
1658 split_long_move(masm, src, split);
1660 // So dst now has the low order correct position the
1661 // msw half
1662 __ sllx(split.first()->as_Register(), 32, L5);
1664 const Register d = dst.first()->as_Register();
1665 __ or3(L5, d, d);
1666 }
1667 } else {
1668 // For LP64 we can probably do better.
1669 split_long_move(masm, src, dst);
1670 }
1671 }
1673 // A double move
1674 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1676 // The painful thing here is that like long_move a VMRegPair might be
1677 // 1: a single physical register
1678 // 2: two physical registers (v8)
1679 // 3: a physical reg [lo] and a stack slot [hi] (v8)
1680 // 4: two stack slots
1682 // Since src is always a java calling convention we know that the src pair
1683 // is always either all registers or all stack (and aligned?)
1685 // in a register [lo] and a stack slot [hi]
1686 if (src.first()->is_stack()) {
1687 if (dst.first()->is_stack()) {
1688 // stack to stack the easiest of the bunch
1689 // ought to be a way to do this where if alignment is ok we use ldd/std when possible
1690 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
1691 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
1692 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
1693 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
1694 } else {
1695 // stack to reg
1696 if (dst.second()->is_stack()) {
1697 // stack -> reg, stack -> stack
1698 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
1699 if (dst.first()->is_Register()) {
1700 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1701 } else {
1702 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
1703 }
1704 // This was missing. (very rare case)
1705 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
1706 } else {
1707 // stack -> reg
1708 // Eventually optimize for alignment QQQ
1709 if (dst.first()->is_Register()) {
1710 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1711 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_Register());
1712 } else {
1713 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
1714 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_FloatRegister());
1715 }
1716 }
1717 }
1718 } else if (dst.first()->is_stack()) {
1719 // reg to stack
1720 if (src.first()->is_Register()) {
1721 // Eventually optimize for alignment QQQ
1722 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
1723 if (src.second()->is_stack()) {
1724 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
1725 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
1726 } else {
1727 __ st(src.second()->as_Register(), SP, reg2offset(dst.second()) + STACK_BIAS);
1728 }
1729 } else {
1730 // fpr to stack
1731 if (src.second()->is_stack()) {
1732 ShouldNotReachHere();
1733 } else {
1734 // Is the stack aligned?
1735 if (reg2offset(dst.first()) & 0x7) {
1736 // No do as pairs
1737 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
1738 __ stf(FloatRegisterImpl::S, src.second()->as_FloatRegister(), SP, reg2offset(dst.second()) + STACK_BIAS);
1739 } else {
1740 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
1741 }
1742 }
1743 }
1744 } else {
1745 // reg to reg
1746 if (src.first()->is_Register()) {
1747 if (dst.first()->is_Register()) {
1748 // gpr -> gpr
1749 __ mov(src.first()->as_Register(), dst.first()->as_Register());
1750 __ mov(src.second()->as_Register(), dst.second()->as_Register());
1751 } else {
1752 // gpr -> fpr
1753 // ought to be able to do a single store
1754 __ stx(src.first()->as_Register(), FP, -8 + STACK_BIAS);
1755 __ stx(src.second()->as_Register(), FP, -4 + STACK_BIAS);
1756 // ought to be able to do a single load
1757 __ ldf(FloatRegisterImpl::S, FP, -8 + STACK_BIAS, dst.first()->as_FloatRegister());
1758 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.second()->as_FloatRegister());
1759 }
1760 } else if (dst.first()->is_Register()) {
1761 // fpr -> gpr
1762 // ought to be able to do a single store
1763 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), FP, -8 + STACK_BIAS);
1764 // ought to be able to do a single load
1765 // REMEMBER first() is low address not LSB
1766 __ ld(FP, -8 + STACK_BIAS, dst.first()->as_Register());
1767 if (dst.second()->is_Register()) {
1768 __ ld(FP, -4 + STACK_BIAS, dst.second()->as_Register());
1769 } else {
1770 __ ld(FP, -4 + STACK_BIAS, L4);
1771 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
1772 }
1773 } else {
1774 // fpr -> fpr
1775 // In theory these overlap but the ordering is such that this is likely a nop
1776 if ( src.first() != dst.first()) {
1777 __ fmov(FloatRegisterImpl::D, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister());
1778 }
1779 }
1780 }
1781 }
1783 // Creates an inner frame if one hasn't already been created, and
1784 // saves a copy of the thread in L7_thread_cache
1785 static void create_inner_frame(MacroAssembler* masm, bool* already_created) {
1786 if (!*already_created) {
1787 __ save_frame(0);
1788 // Save thread in L7 (INNER FRAME); it crosses a bunch of VM calls below
1789 // Don't use save_thread because it smashes G2 and we merely want to save a
1790 // copy
1791 __ mov(G2_thread, L7_thread_cache);
1792 *already_created = true;
1793 }
1794 }
1796 // ---------------------------------------------------------------------------
1797 // Generate a native wrapper for a given method. The method takes arguments
1798 // in the Java compiled code convention, marshals them to the native
1799 // convention (handlizes oops, etc), transitions to native, makes the call,
1800 // returns to java state (possibly blocking), unhandlizes any result and
1801 // returns.
1802 nmethod *SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
1803 methodHandle method,
1804 int total_in_args,
1805 int comp_args_on_stack, // in VMRegStackSlots
1806 BasicType *in_sig_bt,
1807 VMRegPair *in_regs,
1808 BasicType ret_type) {
1810 // Native nmethod wrappers never take possesion of the oop arguments.
1811 // So the caller will gc the arguments. The only thing we need an
1812 // oopMap for is if the call is static
1813 //
1814 // An OopMap for lock (and class if static), and one for the VM call itself
1815 OopMapSet *oop_maps = new OopMapSet();
1816 intptr_t start = (intptr_t)__ pc();
1818 // First thing make an ic check to see if we should even be here
1819 {
1820 Label L;
1821 const Register temp_reg = G3_scratch;
1822 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
1823 __ verify_oop(O0);
1824 __ load_klass(O0, temp_reg);
1825 __ cmp(temp_reg, G5_inline_cache_reg);
1826 __ brx(Assembler::equal, true, Assembler::pt, L);
1827 __ delayed()->nop();
1829 __ jump_to(ic_miss, temp_reg);
1830 __ delayed()->nop();
1831 __ align(CodeEntryAlignment);
1832 __ bind(L);
1833 }
1835 int vep_offset = ((intptr_t)__ pc()) - start;
1837 #ifdef COMPILER1
1838 if (InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) {
1839 // Object.hashCode can pull the hashCode from the header word
1840 // instead of doing a full VM transition once it's been computed.
1841 // Since hashCode is usually polymorphic at call sites we can't do
1842 // this optimization at the call site without a lot of work.
1843 Label slowCase;
1844 Register receiver = O0;
1845 Register result = O0;
1846 Register header = G3_scratch;
1847 Register hash = G3_scratch; // overwrite header value with hash value
1848 Register mask = G1; // to get hash field from header
1850 // Read the header and build a mask to get its hash field. Give up if the object is not unlocked.
1851 // We depend on hash_mask being at most 32 bits and avoid the use of
1852 // hash_mask_in_place because it could be larger than 32 bits in a 64-bit
1853 // vm: see markOop.hpp.
1854 __ ld_ptr(receiver, oopDesc::mark_offset_in_bytes(), header);
1855 __ sethi(markOopDesc::hash_mask, mask);
1856 __ btst(markOopDesc::unlocked_value, header);
1857 __ br(Assembler::zero, false, Assembler::pn, slowCase);
1858 if (UseBiasedLocking) {
1859 // Check if biased and fall through to runtime if so
1860 __ delayed()->nop();
1861 __ btst(markOopDesc::biased_lock_bit_in_place, header);
1862 __ br(Assembler::notZero, false, Assembler::pn, slowCase);
1863 }
1864 __ delayed()->or3(mask, markOopDesc::hash_mask & 0x3ff, mask);
1866 // Check for a valid (non-zero) hash code and get its value.
1867 #ifdef _LP64
1868 __ srlx(header, markOopDesc::hash_shift, hash);
1869 #else
1870 __ srl(header, markOopDesc::hash_shift, hash);
1871 #endif
1872 __ andcc(hash, mask, hash);
1873 __ br(Assembler::equal, false, Assembler::pn, slowCase);
1874 __ delayed()->nop();
1876 // leaf return.
1877 __ retl();
1878 __ delayed()->mov(hash, result);
1879 __ bind(slowCase);
1880 }
1881 #endif // COMPILER1
1884 // We have received a description of where all the java arg are located
1885 // on entry to the wrapper. We need to convert these args to where
1886 // the jni function will expect them. To figure out where they go
1887 // we convert the java signature to a C signature by inserting
1888 // the hidden arguments as arg[0] and possibly arg[1] (static method)
1890 int total_c_args = total_in_args + 1;
1891 if (method->is_static()) {
1892 total_c_args++;
1893 }
1895 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args);
1896 VMRegPair * out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args);
1898 int argc = 0;
1899 out_sig_bt[argc++] = T_ADDRESS;
1900 if (method->is_static()) {
1901 out_sig_bt[argc++] = T_OBJECT;
1902 }
1904 for (int i = 0; i < total_in_args ; i++ ) {
1905 out_sig_bt[argc++] = in_sig_bt[i];
1906 }
1908 // Now figure out where the args must be stored and how much stack space
1909 // they require (neglecting out_preserve_stack_slots but space for storing
1910 // the 1st six register arguments). It's weird see int_stk_helper.
1911 //
1912 int out_arg_slots;
1913 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
1915 // Compute framesize for the wrapper. We need to handlize all oops in
1916 // registers. We must create space for them here that is disjoint from
1917 // the windowed save area because we have no control over when we might
1918 // flush the window again and overwrite values that gc has since modified.
1919 // (The live window race)
1920 //
1921 // We always just allocate 6 word for storing down these object. This allow
1922 // us to simply record the base and use the Ireg number to decide which
1923 // slot to use. (Note that the reg number is the inbound number not the
1924 // outbound number).
1925 // We must shuffle args to match the native convention, and include var-args space.
1927 // Calculate the total number of stack slots we will need.
1929 // First count the abi requirement plus all of the outgoing args
1930 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
1932 // Now the space for the inbound oop handle area
1934 int oop_handle_offset = stack_slots;
1935 stack_slots += 6*VMRegImpl::slots_per_word;
1937 // Now any space we need for handlizing a klass if static method
1939 int oop_temp_slot_offset = 0;
1940 int klass_slot_offset = 0;
1941 int klass_offset = -1;
1942 int lock_slot_offset = 0;
1943 bool is_static = false;
1945 if (method->is_static()) {
1946 klass_slot_offset = stack_slots;
1947 stack_slots += VMRegImpl::slots_per_word;
1948 klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size;
1949 is_static = true;
1950 }
1952 // Plus a lock if needed
1954 if (method->is_synchronized()) {
1955 lock_slot_offset = stack_slots;
1956 stack_slots += VMRegImpl::slots_per_word;
1957 }
1959 // Now a place to save return value or as a temporary for any gpr -> fpr moves
1960 stack_slots += 2;
1962 // Ok The space we have allocated will look like:
1963 //
1964 //
1965 // FP-> | |
1966 // |---------------------|
1967 // | 2 slots for moves |
1968 // |---------------------|
1969 // | lock box (if sync) |
1970 // |---------------------| <- lock_slot_offset
1971 // | klass (if static) |
1972 // |---------------------| <- klass_slot_offset
1973 // | oopHandle area |
1974 // |---------------------| <- oop_handle_offset
1975 // | outbound memory |
1976 // | based arguments |
1977 // | |
1978 // |---------------------|
1979 // | vararg area |
1980 // |---------------------|
1981 // | |
1982 // SP-> | out_preserved_slots |
1983 //
1984 //
1987 // Now compute actual number of stack words we need rounding to make
1988 // stack properly aligned.
1989 stack_slots = round_to(stack_slots, 2 * VMRegImpl::slots_per_word);
1991 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
1993 // Generate stack overflow check before creating frame
1994 __ generate_stack_overflow_check(stack_size);
1996 // Generate a new frame for the wrapper.
1997 __ save(SP, -stack_size, SP);
1999 int frame_complete = ((intptr_t)__ pc()) - start;
2001 __ verify_thread();
2004 //
2005 // We immediately shuffle the arguments so that any vm call we have to
2006 // make from here on out (sync slow path, jvmti, etc.) we will have
2007 // captured the oops from our caller and have a valid oopMap for
2008 // them.
2010 // -----------------
2011 // The Grand Shuffle
2012 //
2013 // Natives require 1 or 2 extra arguments over the normal ones: the JNIEnv*
2014 // (derived from JavaThread* which is in L7_thread_cache) and, if static,
2015 // the class mirror instead of a receiver. This pretty much guarantees that
2016 // register layout will not match. We ignore these extra arguments during
2017 // the shuffle. The shuffle is described by the two calling convention
2018 // vectors we have in our possession. We simply walk the java vector to
2019 // get the source locations and the c vector to get the destinations.
2020 // Because we have a new window and the argument registers are completely
2021 // disjoint ( I0 -> O1, I1 -> O2, ...) we have nothing to worry about
2022 // here.
2024 // This is a trick. We double the stack slots so we can claim
2025 // the oops in the caller's frame. Since we are sure to have
2026 // more args than the caller doubling is enough to make
2027 // sure we can capture all the incoming oop args from the
2028 // caller.
2029 //
2030 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
2031 int c_arg = total_c_args - 1;
2032 // Record sp-based slot for receiver on stack for non-static methods
2033 int receiver_offset = -1;
2035 // We move the arguments backward because the floating point registers
2036 // destination will always be to a register with a greater or equal register
2037 // number or the stack.
2039 #ifdef ASSERT
2040 bool reg_destroyed[RegisterImpl::number_of_registers];
2041 bool freg_destroyed[FloatRegisterImpl::number_of_registers];
2042 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
2043 reg_destroyed[r] = false;
2044 }
2045 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) {
2046 freg_destroyed[f] = false;
2047 }
2049 #endif /* ASSERT */
2051 for ( int i = total_in_args - 1; i >= 0 ; i--, c_arg-- ) {
2053 #ifdef ASSERT
2054 if (in_regs[i].first()->is_Register()) {
2055 assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "ack!");
2056 } else if (in_regs[i].first()->is_FloatRegister()) {
2057 assert(!freg_destroyed[in_regs[i].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)], "ack!");
2058 }
2059 if (out_regs[c_arg].first()->is_Register()) {
2060 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true;
2061 } else if (out_regs[c_arg].first()->is_FloatRegister()) {
2062 freg_destroyed[out_regs[c_arg].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)] = true;
2063 }
2064 #endif /* ASSERT */
2066 switch (in_sig_bt[i]) {
2067 case T_ARRAY:
2068 case T_OBJECT:
2069 object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
2070 ((i == 0) && (!is_static)),
2071 &receiver_offset);
2072 break;
2073 case T_VOID:
2074 break;
2076 case T_FLOAT:
2077 float_move(masm, in_regs[i], out_regs[c_arg]);
2078 break;
2080 case T_DOUBLE:
2081 assert( i + 1 < total_in_args &&
2082 in_sig_bt[i + 1] == T_VOID &&
2083 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
2084 double_move(masm, in_regs[i], out_regs[c_arg]);
2085 break;
2087 case T_LONG :
2088 long_move(masm, in_regs[i], out_regs[c_arg]);
2089 break;
2091 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
2093 default:
2094 move32_64(masm, in_regs[i], out_regs[c_arg]);
2095 }
2096 }
2098 // Pre-load a static method's oop into O1. Used both by locking code and
2099 // the normal JNI call code.
2100 if (method->is_static()) {
2101 __ set_oop_constant(JNIHandles::make_local(Klass::cast(method->method_holder())->java_mirror()), O1);
2103 // Now handlize the static class mirror in O1. It's known not-null.
2104 __ st_ptr(O1, SP, klass_offset + STACK_BIAS);
2105 map->set_oop(VMRegImpl::stack2reg(klass_slot_offset));
2106 __ add(SP, klass_offset + STACK_BIAS, O1);
2107 }
2110 const Register L6_handle = L6;
2112 if (method->is_synchronized()) {
2113 __ mov(O1, L6_handle);
2114 }
2116 // We have all of the arguments setup at this point. We MUST NOT touch any Oregs
2117 // except O6/O7. So if we must call out we must push a new frame. We immediately
2118 // push a new frame and flush the windows.
2120 #ifdef _LP64
2121 intptr_t thepc = (intptr_t) __ pc();
2122 {
2123 address here = __ pc();
2124 // Call the next instruction
2125 __ call(here + 8, relocInfo::none);
2126 __ delayed()->nop();
2127 }
2128 #else
2129 intptr_t thepc = __ load_pc_address(O7, 0);
2130 #endif /* _LP64 */
2132 // We use the same pc/oopMap repeatedly when we call out
2133 oop_maps->add_gc_map(thepc - start, map);
2135 // O7 now has the pc loaded that we will use when we finally call to native.
2137 // Save thread in L7; it crosses a bunch of VM calls below
2138 // Don't use save_thread because it smashes G2 and we merely
2139 // want to save a copy
2140 __ mov(G2_thread, L7_thread_cache);
2143 // If we create an inner frame once is plenty
2144 // when we create it we must also save G2_thread
2145 bool inner_frame_created = false;
2147 // dtrace method entry support
2148 {
2149 SkipIfEqual skip_if(
2150 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero);
2151 // create inner frame
2152 __ save_frame(0);
2153 __ mov(G2_thread, L7_thread_cache);
2154 __ set_oop_constant(JNIHandles::make_local(method()), O1);
2155 __ call_VM_leaf(L7_thread_cache,
2156 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry),
2157 G2_thread, O1);
2158 __ restore();
2159 }
2161 // RedefineClasses() tracing support for obsolete method entry
2162 if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) {
2163 // create inner frame
2164 __ save_frame(0);
2165 __ mov(G2_thread, L7_thread_cache);
2166 __ set_oop_constant(JNIHandles::make_local(method()), O1);
2167 __ call_VM_leaf(L7_thread_cache,
2168 CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry),
2169 G2_thread, O1);
2170 __ restore();
2171 }
2173 // We are in the jni frame unless saved_frame is true in which case
2174 // we are in one frame deeper (the "inner" frame). If we are in the
2175 // "inner" frames the args are in the Iregs and if the jni frame then
2176 // they are in the Oregs.
2177 // If we ever need to go to the VM (for locking, jvmti) then
2178 // we will always be in the "inner" frame.
2180 // Lock a synchronized method
2181 int lock_offset = -1; // Set if locked
2182 if (method->is_synchronized()) {
2183 Register Roop = O1;
2184 const Register L3_box = L3;
2186 create_inner_frame(masm, &inner_frame_created);
2188 __ ld_ptr(I1, 0, O1);
2189 Label done;
2191 lock_offset = (lock_slot_offset * VMRegImpl::stack_slot_size);
2192 __ add(FP, lock_offset+STACK_BIAS, L3_box);
2193 #ifdef ASSERT
2194 if (UseBiasedLocking) {
2195 // making the box point to itself will make it clear it went unused
2196 // but also be obviously invalid
2197 __ st_ptr(L3_box, L3_box, 0);
2198 }
2199 #endif // ASSERT
2200 //
2201 // Compiler_lock_object (Roop, Rmark, Rbox, Rscratch) -- kills Rmark, Rbox, Rscratch
2202 //
2203 __ compiler_lock_object(Roop, L1, L3_box, L2);
2204 __ br(Assembler::equal, false, Assembler::pt, done);
2205 __ delayed() -> add(FP, lock_offset+STACK_BIAS, L3_box);
2208 // None of the above fast optimizations worked so we have to get into the
2209 // slow case of monitor enter. Inline a special case of call_VM that
2210 // disallows any pending_exception.
2211 __ mov(Roop, O0); // Need oop in O0
2212 __ mov(L3_box, O1);
2214 // Record last_Java_sp, in case the VM code releases the JVM lock.
2216 __ set_last_Java_frame(FP, I7);
2218 // do the call
2219 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), relocInfo::runtime_call_type);
2220 __ delayed()->mov(L7_thread_cache, O2);
2222 __ restore_thread(L7_thread_cache); // restore G2_thread
2223 __ reset_last_Java_frame();
2225 #ifdef ASSERT
2226 { Label L;
2227 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0);
2228 __ br_null(O0, false, Assembler::pt, L);
2229 __ delayed()->nop();
2230 __ stop("no pending exception allowed on exit from IR::monitorenter");
2231 __ bind(L);
2232 }
2233 #endif
2234 __ bind(done);
2235 }
2238 // Finally just about ready to make the JNI call
2240 __ flush_windows();
2241 if (inner_frame_created) {
2242 __ restore();
2243 } else {
2244 // Store only what we need from this frame
2245 // QQQ I think that non-v9 (like we care) we don't need these saves
2246 // either as the flush traps and the current window goes too.
2247 __ st_ptr(FP, SP, FP->sp_offset_in_saved_window()*wordSize + STACK_BIAS);
2248 __ st_ptr(I7, SP, I7->sp_offset_in_saved_window()*wordSize + STACK_BIAS);
2249 }
2251 // get JNIEnv* which is first argument to native
2253 __ add(G2_thread, in_bytes(JavaThread::jni_environment_offset()), O0);
2255 // Use that pc we placed in O7 a while back as the current frame anchor
2257 __ set_last_Java_frame(SP, O7);
2259 // Transition from _thread_in_Java to _thread_in_native.
2260 __ set(_thread_in_native, G3_scratch);
2261 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
2263 // We flushed the windows ages ago now mark them as flushed
2265 // mark windows as flushed
2266 __ set(JavaFrameAnchor::flushed, G3_scratch);
2268 Address flags(G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset());
2270 #ifdef _LP64
2271 AddressLiteral dest(method->native_function());
2272 __ relocate(relocInfo::runtime_call_type);
2273 __ jumpl_to(dest, O7, O7);
2274 #else
2275 __ call(method->native_function(), relocInfo::runtime_call_type);
2276 #endif
2277 __ delayed()->st(G3_scratch, flags);
2279 __ restore_thread(L7_thread_cache); // restore G2_thread
2281 // Unpack native results. For int-types, we do any needed sign-extension
2282 // and move things into I0. The return value there will survive any VM
2283 // calls for blocking or unlocking. An FP or OOP result (handle) is done
2284 // specially in the slow-path code.
2285 switch (ret_type) {
2286 case T_VOID: break; // Nothing to do!
2287 case T_FLOAT: break; // Got it where we want it (unless slow-path)
2288 case T_DOUBLE: break; // Got it where we want it (unless slow-path)
2289 // In 64 bits build result is in O0, in O0, O1 in 32bit build
2290 case T_LONG:
2291 #ifndef _LP64
2292 __ mov(O1, I1);
2293 #endif
2294 // Fall thru
2295 case T_OBJECT: // Really a handle
2296 case T_ARRAY:
2297 case T_INT:
2298 __ mov(O0, I0);
2299 break;
2300 case T_BOOLEAN: __ subcc(G0, O0, G0); __ addc(G0, 0, I0); break; // !0 => true; 0 => false
2301 case T_BYTE : __ sll(O0, 24, O0); __ sra(O0, 24, I0); break;
2302 case T_CHAR : __ sll(O0, 16, O0); __ srl(O0, 16, I0); break; // cannot use and3, 0xFFFF too big as immediate value!
2303 case T_SHORT : __ sll(O0, 16, O0); __ sra(O0, 16, I0); break;
2304 break; // Cannot de-handlize until after reclaiming jvm_lock
2305 default:
2306 ShouldNotReachHere();
2307 }
2309 // must we block?
2311 // Block, if necessary, before resuming in _thread_in_Java state.
2312 // In order for GC to work, don't clear the last_Java_sp until after blocking.
2313 { Label no_block;
2314 AddressLiteral sync_state(SafepointSynchronize::address_of_state());
2316 // Switch thread to "native transition" state before reading the synchronization state.
2317 // This additional state is necessary because reading and testing the synchronization
2318 // state is not atomic w.r.t. GC, as this scenario demonstrates:
2319 // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted.
2320 // VM thread changes sync state to synchronizing and suspends threads for GC.
2321 // Thread A is resumed to finish this native method, but doesn't block here since it
2322 // didn't see any synchronization is progress, and escapes.
2323 __ set(_thread_in_native_trans, G3_scratch);
2324 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
2325 if(os::is_MP()) {
2326 if (UseMembar) {
2327 // Force this write out before the read below
2328 __ membar(Assembler::StoreLoad);
2329 } else {
2330 // Write serialization page so VM thread can do a pseudo remote membar.
2331 // We use the current thread pointer to calculate a thread specific
2332 // offset to write to within the page. This minimizes bus traffic
2333 // due to cache line collision.
2334 __ serialize_memory(G2_thread, G1_scratch, G3_scratch);
2335 }
2336 }
2337 __ load_contents(sync_state, G3_scratch);
2338 __ cmp(G3_scratch, SafepointSynchronize::_not_synchronized);
2340 Label L;
2341 Address suspend_state(G2_thread, JavaThread::suspend_flags_offset());
2342 __ br(Assembler::notEqual, false, Assembler::pn, L);
2343 __ delayed()->ld(suspend_state, G3_scratch);
2344 __ cmp(G3_scratch, 0);
2345 __ br(Assembler::equal, false, Assembler::pt, no_block);
2346 __ delayed()->nop();
2347 __ bind(L);
2349 // Block. Save any potential method result value before the operation and
2350 // use a leaf call to leave the last_Java_frame setup undisturbed. Doing this
2351 // lets us share the oopMap we used when we went native rather the create
2352 // a distinct one for this pc
2353 //
2354 save_native_result(masm, ret_type, stack_slots);
2355 __ call_VM_leaf(L7_thread_cache,
2356 CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans),
2357 G2_thread);
2359 // Restore any method result value
2360 restore_native_result(masm, ret_type, stack_slots);
2361 __ bind(no_block);
2362 }
2364 // thread state is thread_in_native_trans. Any safepoint blocking has already
2365 // happened so we can now change state to _thread_in_Java.
2368 __ set(_thread_in_Java, G3_scratch);
2369 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
2372 Label no_reguard;
2373 __ ld(G2_thread, JavaThread::stack_guard_state_offset(), G3_scratch);
2374 __ cmp(G3_scratch, JavaThread::stack_guard_yellow_disabled);
2375 __ br(Assembler::notEqual, false, Assembler::pt, no_reguard);
2376 __ delayed()->nop();
2378 save_native_result(masm, ret_type, stack_slots);
2379 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages));
2380 __ delayed()->nop();
2382 __ restore_thread(L7_thread_cache); // restore G2_thread
2383 restore_native_result(masm, ret_type, stack_slots);
2385 __ bind(no_reguard);
2387 // Handle possible exception (will unlock if necessary)
2389 // native result if any is live in freg or I0 (and I1 if long and 32bit vm)
2391 // Unlock
2392 if (method->is_synchronized()) {
2393 Label done;
2394 Register I2_ex_oop = I2;
2395 const Register L3_box = L3;
2396 // Get locked oop from the handle we passed to jni
2397 __ ld_ptr(L6_handle, 0, L4);
2398 __ add(SP, lock_offset+STACK_BIAS, L3_box);
2399 // Must save pending exception around the slow-path VM call. Since it's a
2400 // leaf call, the pending exception (if any) can be kept in a register.
2401 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), I2_ex_oop);
2402 // Now unlock
2403 // (Roop, Rmark, Rbox, Rscratch)
2404 __ compiler_unlock_object(L4, L1, L3_box, L2);
2405 __ br(Assembler::equal, false, Assembler::pt, done);
2406 __ delayed()-> add(SP, lock_offset+STACK_BIAS, L3_box);
2408 // save and restore any potential method result value around the unlocking
2409 // operation. Will save in I0 (or stack for FP returns).
2410 save_native_result(masm, ret_type, stack_slots);
2412 // Must clear pending-exception before re-entering the VM. Since this is
2413 // a leaf call, pending-exception-oop can be safely kept in a register.
2414 __ st_ptr(G0, G2_thread, in_bytes(Thread::pending_exception_offset()));
2416 // slow case of monitor enter. Inline a special case of call_VM that
2417 // disallows any pending_exception.
2418 __ mov(L3_box, O1);
2420 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C), relocInfo::runtime_call_type);
2421 __ delayed()->mov(L4, O0); // Need oop in O0
2423 __ restore_thread(L7_thread_cache); // restore G2_thread
2425 #ifdef ASSERT
2426 { Label L;
2427 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0);
2428 __ br_null(O0, false, Assembler::pt, L);
2429 __ delayed()->nop();
2430 __ stop("no pending exception allowed on exit from IR::monitorexit");
2431 __ bind(L);
2432 }
2433 #endif
2434 restore_native_result(masm, ret_type, stack_slots);
2435 // check_forward_pending_exception jump to forward_exception if any pending
2436 // exception is set. The forward_exception routine expects to see the
2437 // exception in pending_exception and not in a register. Kind of clumsy,
2438 // since all folks who branch to forward_exception must have tested
2439 // pending_exception first and hence have it in a register already.
2440 __ st_ptr(I2_ex_oop, G2_thread, in_bytes(Thread::pending_exception_offset()));
2441 __ bind(done);
2442 }
2444 // Tell dtrace about this method exit
2445 {
2446 SkipIfEqual skip_if(
2447 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero);
2448 save_native_result(masm, ret_type, stack_slots);
2449 __ set_oop_constant(JNIHandles::make_local(method()), O1);
2450 __ call_VM_leaf(L7_thread_cache,
2451 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit),
2452 G2_thread, O1);
2453 restore_native_result(masm, ret_type, stack_slots);
2454 }
2456 // Clear "last Java frame" SP and PC.
2457 __ verify_thread(); // G2_thread must be correct
2458 __ reset_last_Java_frame();
2460 // Unpack oop result
2461 if (ret_type == T_OBJECT || ret_type == T_ARRAY) {
2462 Label L;
2463 __ addcc(G0, I0, G0);
2464 __ brx(Assembler::notZero, true, Assembler::pt, L);
2465 __ delayed()->ld_ptr(I0, 0, I0);
2466 __ mov(G0, I0);
2467 __ bind(L);
2468 __ verify_oop(I0);
2469 }
2471 // reset handle block
2472 __ ld_ptr(G2_thread, in_bytes(JavaThread::active_handles_offset()), L5);
2473 __ st_ptr(G0, L5, JNIHandleBlock::top_offset_in_bytes());
2475 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), G3_scratch);
2476 check_forward_pending_exception(masm, G3_scratch);
2479 // Return
2481 #ifndef _LP64
2482 if (ret_type == T_LONG) {
2484 // Must leave proper result in O0,O1 and G1 (c2/tiered only)
2485 __ sllx(I0, 32, G1); // Shift bits into high G1
2486 __ srl (I1, 0, I1); // Zero extend O1 (harmless?)
2487 __ or3 (I1, G1, G1); // OR 64 bits into G1
2488 }
2489 #endif
2491 __ ret();
2492 __ delayed()->restore();
2494 __ flush();
2496 nmethod *nm = nmethod::new_native_nmethod(method,
2497 masm->code(),
2498 vep_offset,
2499 frame_complete,
2500 stack_slots / VMRegImpl::slots_per_word,
2501 (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)),
2502 in_ByteSize(lock_offset),
2503 oop_maps);
2504 return nm;
2506 }
2508 #ifdef HAVE_DTRACE_H
2509 // ---------------------------------------------------------------------------
2510 // Generate a dtrace nmethod for a given signature. The method takes arguments
2511 // in the Java compiled code convention, marshals them to the native
2512 // abi and then leaves nops at the position you would expect to call a native
2513 // function. When the probe is enabled the nops are replaced with a trap
2514 // instruction that dtrace inserts and the trace will cause a notification
2515 // to dtrace.
2516 //
2517 // The probes are only able to take primitive types and java/lang/String as
2518 // arguments. No other java types are allowed. Strings are converted to utf8
2519 // strings so that from dtrace point of view java strings are converted to C
2520 // strings. There is an arbitrary fixed limit on the total space that a method
2521 // can use for converting the strings. (256 chars per string in the signature).
2522 // So any java string larger then this is truncated.
2524 static int fp_offset[ConcreteRegisterImpl::number_of_registers] = { 0 };
2525 static bool offsets_initialized = false;
2527 static VMRegPair reg64_to_VMRegPair(Register r) {
2528 VMRegPair ret;
2529 if (wordSize == 8) {
2530 ret.set2(r->as_VMReg());
2531 } else {
2532 ret.set_pair(r->successor()->as_VMReg(), r->as_VMReg());
2533 }
2534 return ret;
2535 }
2538 nmethod *SharedRuntime::generate_dtrace_nmethod(
2539 MacroAssembler *masm, methodHandle method) {
2542 // generate_dtrace_nmethod is guarded by a mutex so we are sure to
2543 // be single threaded in this method.
2544 assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be");
2546 // Fill in the signature array, for the calling-convention call.
2547 int total_args_passed = method->size_of_parameters();
2549 BasicType* in_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed);
2550 VMRegPair *in_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed);
2552 // The signature we are going to use for the trap that dtrace will see
2553 // java/lang/String is converted. We drop "this" and any other object
2554 // is converted to NULL. (A one-slot java/lang/Long object reference
2555 // is converted to a two-slot long, which is why we double the allocation).
2556 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2);
2557 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2);
2559 int i=0;
2560 int total_strings = 0;
2561 int first_arg_to_pass = 0;
2562 int total_c_args = 0;
2564 // Skip the receiver as dtrace doesn't want to see it
2565 if( !method->is_static() ) {
2566 in_sig_bt[i++] = T_OBJECT;
2567 first_arg_to_pass = 1;
2568 }
2570 SignatureStream ss(method->signature());
2571 for ( ; !ss.at_return_type(); ss.next()) {
2572 BasicType bt = ss.type();
2573 in_sig_bt[i++] = bt; // Collect remaining bits of signature
2574 out_sig_bt[total_c_args++] = bt;
2575 if( bt == T_OBJECT) {
2576 symbolOop s = ss.as_symbol_or_null();
2577 if (s == vmSymbols::java_lang_String()) {
2578 total_strings++;
2579 out_sig_bt[total_c_args-1] = T_ADDRESS;
2580 } else if (s == vmSymbols::java_lang_Boolean() ||
2581 s == vmSymbols::java_lang_Byte()) {
2582 out_sig_bt[total_c_args-1] = T_BYTE;
2583 } else if (s == vmSymbols::java_lang_Character() ||
2584 s == vmSymbols::java_lang_Short()) {
2585 out_sig_bt[total_c_args-1] = T_SHORT;
2586 } else if (s == vmSymbols::java_lang_Integer() ||
2587 s == vmSymbols::java_lang_Float()) {
2588 out_sig_bt[total_c_args-1] = T_INT;
2589 } else if (s == vmSymbols::java_lang_Long() ||
2590 s == vmSymbols::java_lang_Double()) {
2591 out_sig_bt[total_c_args-1] = T_LONG;
2592 out_sig_bt[total_c_args++] = T_VOID;
2593 }
2594 } else if ( bt == T_LONG || bt == T_DOUBLE ) {
2595 in_sig_bt[i++] = T_VOID; // Longs & doubles take 2 Java slots
2596 // We convert double to long
2597 out_sig_bt[total_c_args-1] = T_LONG;
2598 out_sig_bt[total_c_args++] = T_VOID;
2599 } else if ( bt == T_FLOAT) {
2600 // We convert float to int
2601 out_sig_bt[total_c_args-1] = T_INT;
2602 }
2603 }
2605 assert(i==total_args_passed, "validly parsed signature");
2607 // Now get the compiled-Java layout as input arguments
2608 int comp_args_on_stack;
2609 comp_args_on_stack = SharedRuntime::java_calling_convention(
2610 in_sig_bt, in_regs, total_args_passed, false);
2612 // We have received a description of where all the java arg are located
2613 // on entry to the wrapper. We need to convert these args to where
2614 // the a native (non-jni) function would expect them. To figure out
2615 // where they go we convert the java signature to a C signature and remove
2616 // T_VOID for any long/double we might have received.
2619 // Now figure out where the args must be stored and how much stack space
2620 // they require (neglecting out_preserve_stack_slots but space for storing
2621 // the 1st six register arguments). It's weird see int_stk_helper.
2622 //
2623 int out_arg_slots;
2624 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
2626 // Calculate the total number of stack slots we will need.
2628 // First count the abi requirement plus all of the outgoing args
2629 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
2631 // Plus a temp for possible converion of float/double/long register args
2633 int conversion_temp = stack_slots;
2634 stack_slots += 2;
2637 // Now space for the string(s) we must convert
2639 int string_locs = stack_slots;
2640 stack_slots += total_strings *
2641 (max_dtrace_string_size / VMRegImpl::stack_slot_size);
2643 // Ok The space we have allocated will look like:
2644 //
2645 //
2646 // FP-> | |
2647 // |---------------------|
2648 // | string[n] |
2649 // |---------------------| <- string_locs[n]
2650 // | string[n-1] |
2651 // |---------------------| <- string_locs[n-1]
2652 // | ... |
2653 // | ... |
2654 // |---------------------| <- string_locs[1]
2655 // | string[0] |
2656 // |---------------------| <- string_locs[0]
2657 // | temp |
2658 // |---------------------| <- conversion_temp
2659 // | outbound memory |
2660 // | based arguments |
2661 // | |
2662 // |---------------------|
2663 // | |
2664 // SP-> | out_preserved_slots |
2665 //
2666 //
2668 // Now compute actual number of stack words we need rounding to make
2669 // stack properly aligned.
2670 stack_slots = round_to(stack_slots, 4 * VMRegImpl::slots_per_word);
2672 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
2674 intptr_t start = (intptr_t)__ pc();
2676 // First thing make an ic check to see if we should even be here
2678 {
2679 Label L;
2680 const Register temp_reg = G3_scratch;
2681 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
2682 __ verify_oop(O0);
2683 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), temp_reg);
2684 __ cmp(temp_reg, G5_inline_cache_reg);
2685 __ brx(Assembler::equal, true, Assembler::pt, L);
2686 __ delayed()->nop();
2688 __ jump_to(ic_miss, temp_reg);
2689 __ delayed()->nop();
2690 __ align(CodeEntryAlignment);
2691 __ bind(L);
2692 }
2694 int vep_offset = ((intptr_t)__ pc()) - start;
2697 // The instruction at the verified entry point must be 5 bytes or longer
2698 // because it can be patched on the fly by make_non_entrant. The stack bang
2699 // instruction fits that requirement.
2701 // Generate stack overflow check before creating frame
2702 __ generate_stack_overflow_check(stack_size);
2704 assert(((intptr_t)__ pc() - start - vep_offset) >= 5,
2705 "valid size for make_non_entrant");
2707 // Generate a new frame for the wrapper.
2708 __ save(SP, -stack_size, SP);
2710 // Frame is now completed as far a size and linkage.
2712 int frame_complete = ((intptr_t)__ pc()) - start;
2714 #ifdef ASSERT
2715 bool reg_destroyed[RegisterImpl::number_of_registers];
2716 bool freg_destroyed[FloatRegisterImpl::number_of_registers];
2717 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
2718 reg_destroyed[r] = false;
2719 }
2720 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) {
2721 freg_destroyed[f] = false;
2722 }
2724 #endif /* ASSERT */
2726 VMRegPair zero;
2727 const Register g0 = G0; // without this we get a compiler warning (why??)
2728 zero.set2(g0->as_VMReg());
2730 int c_arg, j_arg;
2732 Register conversion_off = noreg;
2734 for (j_arg = first_arg_to_pass, c_arg = 0 ;
2735 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
2737 VMRegPair src = in_regs[j_arg];
2738 VMRegPair dst = out_regs[c_arg];
2740 #ifdef ASSERT
2741 if (src.first()->is_Register()) {
2742 assert(!reg_destroyed[src.first()->as_Register()->encoding()], "ack!");
2743 } else if (src.first()->is_FloatRegister()) {
2744 assert(!freg_destroyed[src.first()->as_FloatRegister()->encoding(
2745 FloatRegisterImpl::S)], "ack!");
2746 }
2747 if (dst.first()->is_Register()) {
2748 reg_destroyed[dst.first()->as_Register()->encoding()] = true;
2749 } else if (dst.first()->is_FloatRegister()) {
2750 freg_destroyed[dst.first()->as_FloatRegister()->encoding(
2751 FloatRegisterImpl::S)] = true;
2752 }
2753 #endif /* ASSERT */
2755 switch (in_sig_bt[j_arg]) {
2756 case T_ARRAY:
2757 case T_OBJECT:
2758 {
2759 if (out_sig_bt[c_arg] == T_BYTE || out_sig_bt[c_arg] == T_SHORT ||
2760 out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) {
2761 // need to unbox a one-slot value
2762 Register in_reg = L0;
2763 Register tmp = L2;
2764 if ( src.first()->is_reg() ) {
2765 in_reg = src.first()->as_Register();
2766 } else {
2767 assert(Assembler::is_simm13(reg2offset(src.first()) + STACK_BIAS),
2768 "must be");
2769 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, in_reg);
2770 }
2771 // If the final destination is an acceptable register
2772 if ( dst.first()->is_reg() ) {
2773 if ( dst.is_single_phys_reg() || out_sig_bt[c_arg] != T_LONG ) {
2774 tmp = dst.first()->as_Register();
2775 }
2776 }
2778 Label skipUnbox;
2779 if ( wordSize == 4 && out_sig_bt[c_arg] == T_LONG ) {
2780 __ mov(G0, tmp->successor());
2781 }
2782 __ br_null(in_reg, true, Assembler::pn, skipUnbox);
2783 __ delayed()->mov(G0, tmp);
2785 BasicType bt = out_sig_bt[c_arg];
2786 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt);
2787 switch (bt) {
2788 case T_BYTE:
2789 __ ldub(in_reg, box_offset, tmp); break;
2790 case T_SHORT:
2791 __ lduh(in_reg, box_offset, tmp); break;
2792 case T_INT:
2793 __ ld(in_reg, box_offset, tmp); break;
2794 case T_LONG:
2795 __ ld_long(in_reg, box_offset, tmp); break;
2796 default: ShouldNotReachHere();
2797 }
2799 __ bind(skipUnbox);
2800 // If tmp wasn't final destination copy to final destination
2801 if (tmp == L2) {
2802 VMRegPair tmp_as_VM = reg64_to_VMRegPair(L2);
2803 if (out_sig_bt[c_arg] == T_LONG) {
2804 long_move(masm, tmp_as_VM, dst);
2805 } else {
2806 move32_64(masm, tmp_as_VM, out_regs[c_arg]);
2807 }
2808 }
2809 if (out_sig_bt[c_arg] == T_LONG) {
2810 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
2811 ++c_arg; // move over the T_VOID to keep the loop indices in sync
2812 }
2813 } else if (out_sig_bt[c_arg] == T_ADDRESS) {
2814 Register s =
2815 src.first()->is_reg() ? src.first()->as_Register() : L2;
2816 Register d =
2817 dst.first()->is_reg() ? dst.first()->as_Register() : L2;
2819 // We store the oop now so that the conversion pass can reach
2820 // while in the inner frame. This will be the only store if
2821 // the oop is NULL.
2822 if (s != L2) {
2823 // src is register
2824 if (d != L2) {
2825 // dst is register
2826 __ mov(s, d);
2827 } else {
2828 assert(Assembler::is_simm13(reg2offset(dst.first()) +
2829 STACK_BIAS), "must be");
2830 __ st_ptr(s, SP, reg2offset(dst.first()) + STACK_BIAS);
2831 }
2832 } else {
2833 // src not a register
2834 assert(Assembler::is_simm13(reg2offset(src.first()) +
2835 STACK_BIAS), "must be");
2836 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, d);
2837 if (d == L2) {
2838 assert(Assembler::is_simm13(reg2offset(dst.first()) +
2839 STACK_BIAS), "must be");
2840 __ st_ptr(d, SP, reg2offset(dst.first()) + STACK_BIAS);
2841 }
2842 }
2843 } else if (out_sig_bt[c_arg] != T_VOID) {
2844 // Convert the arg to NULL
2845 if (dst.first()->is_reg()) {
2846 __ mov(G0, dst.first()->as_Register());
2847 } else {
2848 assert(Assembler::is_simm13(reg2offset(dst.first()) +
2849 STACK_BIAS), "must be");
2850 __ st_ptr(G0, SP, reg2offset(dst.first()) + STACK_BIAS);
2851 }
2852 }
2853 }
2854 break;
2855 case T_VOID:
2856 break;
2858 case T_FLOAT:
2859 if (src.first()->is_stack()) {
2860 // Stack to stack/reg is simple
2861 move32_64(masm, src, dst);
2862 } else {
2863 if (dst.first()->is_reg()) {
2864 // freg -> reg
2865 int off =
2866 STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
2867 Register d = dst.first()->as_Register();
2868 if (Assembler::is_simm13(off)) {
2869 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
2870 SP, off);
2871 __ ld(SP, off, d);
2872 } else {
2873 if (conversion_off == noreg) {
2874 __ set(off, L6);
2875 conversion_off = L6;
2876 }
2877 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
2878 SP, conversion_off);
2879 __ ld(SP, conversion_off , d);
2880 }
2881 } else {
2882 // freg -> mem
2883 int off = STACK_BIAS + reg2offset(dst.first());
2884 if (Assembler::is_simm13(off)) {
2885 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
2886 SP, off);
2887 } else {
2888 if (conversion_off == noreg) {
2889 __ set(off, L6);
2890 conversion_off = L6;
2891 }
2892 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
2893 SP, conversion_off);
2894 }
2895 }
2896 }
2897 break;
2899 case T_DOUBLE:
2900 assert( j_arg + 1 < total_args_passed &&
2901 in_sig_bt[j_arg + 1] == T_VOID &&
2902 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
2903 if (src.first()->is_stack()) {
2904 // Stack to stack/reg is simple
2905 long_move(masm, src, dst);
2906 } else {
2907 Register d = dst.first()->is_reg() ? dst.first()->as_Register() : L2;
2909 // Destination could be an odd reg on 32bit in which case
2910 // we can't load direct to the destination.
2912 if (!d->is_even() && wordSize == 4) {
2913 d = L2;
2914 }
2915 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
2916 if (Assembler::is_simm13(off)) {
2917 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(),
2918 SP, off);
2919 __ ld_long(SP, off, d);
2920 } else {
2921 if (conversion_off == noreg) {
2922 __ set(off, L6);
2923 conversion_off = L6;
2924 }
2925 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(),
2926 SP, conversion_off);
2927 __ ld_long(SP, conversion_off, d);
2928 }
2929 if (d == L2) {
2930 long_move(masm, reg64_to_VMRegPair(L2), dst);
2931 }
2932 }
2933 break;
2935 case T_LONG :
2936 // 32bit can't do a split move of something like g1 -> O0, O1
2937 // so use a memory temp
2938 if (src.is_single_phys_reg() && wordSize == 4) {
2939 Register tmp = L2;
2940 if (dst.first()->is_reg() &&
2941 (wordSize == 8 || dst.first()->as_Register()->is_even())) {
2942 tmp = dst.first()->as_Register();
2943 }
2945 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
2946 if (Assembler::is_simm13(off)) {
2947 __ stx(src.first()->as_Register(), SP, off);
2948 __ ld_long(SP, off, tmp);
2949 } else {
2950 if (conversion_off == noreg) {
2951 __ set(off, L6);
2952 conversion_off = L6;
2953 }
2954 __ stx(src.first()->as_Register(), SP, conversion_off);
2955 __ ld_long(SP, conversion_off, tmp);
2956 }
2958 if (tmp == L2) {
2959 long_move(masm, reg64_to_VMRegPair(L2), dst);
2960 }
2961 } else {
2962 long_move(masm, src, dst);
2963 }
2964 break;
2966 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
2968 default:
2969 move32_64(masm, src, dst);
2970 }
2971 }
2974 // If we have any strings we must store any register based arg to the stack
2975 // This includes any still live xmm registers too.
2977 if (total_strings > 0 ) {
2979 // protect all the arg registers
2980 __ save_frame(0);
2981 __ mov(G2_thread, L7_thread_cache);
2982 const Register L2_string_off = L2;
2984 // Get first string offset
2985 __ set(string_locs * VMRegImpl::stack_slot_size, L2_string_off);
2987 for (c_arg = 0 ; c_arg < total_c_args ; c_arg++ ) {
2988 if (out_sig_bt[c_arg] == T_ADDRESS) {
2990 VMRegPair dst = out_regs[c_arg];
2991 const Register d = dst.first()->is_reg() ?
2992 dst.first()->as_Register()->after_save() : noreg;
2994 // It's a string the oop and it was already copied to the out arg
2995 // position
2996 if (d != noreg) {
2997 __ mov(d, O0);
2998 } else {
2999 assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS),
3000 "must be");
3001 __ ld_ptr(FP, reg2offset(dst.first()) + STACK_BIAS, O0);
3002 }
3003 Label skip;
3005 __ br_null(O0, false, Assembler::pn, skip);
3006 __ delayed()->add(FP, L2_string_off, O1);
3008 if (d != noreg) {
3009 __ mov(O1, d);
3010 } else {
3011 assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS),
3012 "must be");
3013 __ st_ptr(O1, FP, reg2offset(dst.first()) + STACK_BIAS);
3014 }
3016 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::get_utf),
3017 relocInfo::runtime_call_type);
3018 __ delayed()->add(L2_string_off, max_dtrace_string_size, L2_string_off);
3020 __ bind(skip);
3022 }
3024 }
3025 __ mov(L7_thread_cache, G2_thread);
3026 __ restore();
3028 }
3031 // Ok now we are done. Need to place the nop that dtrace wants in order to
3032 // patch in the trap
3034 int patch_offset = ((intptr_t)__ pc()) - start;
3036 __ nop();
3039 // Return
3041 __ ret();
3042 __ delayed()->restore();
3044 __ flush();
3046 nmethod *nm = nmethod::new_dtrace_nmethod(
3047 method, masm->code(), vep_offset, patch_offset, frame_complete,
3048 stack_slots / VMRegImpl::slots_per_word);
3049 return nm;
3051 }
3053 #endif // HAVE_DTRACE_H
3055 // this function returns the adjust size (in number of words) to a c2i adapter
3056 // activation for use during deoptimization
3057 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals) {
3058 assert(callee_locals >= callee_parameters,
3059 "test and remove; got more parms than locals");
3060 if (callee_locals < callee_parameters)
3061 return 0; // No adjustment for negative locals
3062 int diff = (callee_locals - callee_parameters) * Interpreter::stackElementWords();
3063 return round_to(diff, WordsPerLong);
3064 }
3066 // "Top of Stack" slots that may be unused by the calling convention but must
3067 // otherwise be preserved.
3068 // On Intel these are not necessary and the value can be zero.
3069 // On Sparc this describes the words reserved for storing a register window
3070 // when an interrupt occurs.
3071 uint SharedRuntime::out_preserve_stack_slots() {
3072 return frame::register_save_words * VMRegImpl::slots_per_word;
3073 }
3075 static void gen_new_frame(MacroAssembler* masm, bool deopt) {
3076 //
3077 // Common out the new frame generation for deopt and uncommon trap
3078 //
3079 Register G3pcs = G3_scratch; // Array of new pcs (input)
3080 Register Oreturn0 = O0;
3081 Register Oreturn1 = O1;
3082 Register O2UnrollBlock = O2;
3083 Register O3array = O3; // Array of frame sizes (input)
3084 Register O4array_size = O4; // number of frames (input)
3085 Register O7frame_size = O7; // number of frames (input)
3087 __ ld_ptr(O3array, 0, O7frame_size);
3088 __ sub(G0, O7frame_size, O7frame_size);
3089 __ save(SP, O7frame_size, SP);
3090 __ ld_ptr(G3pcs, 0, I7); // load frame's new pc
3092 #ifdef ASSERT
3093 // make sure that the frames are aligned properly
3094 #ifndef _LP64
3095 __ btst(wordSize*2-1, SP);
3096 __ breakpoint_trap(Assembler::notZero);
3097 #endif
3098 #endif
3100 // Deopt needs to pass some extra live values from frame to frame
3102 if (deopt) {
3103 __ mov(Oreturn0->after_save(), Oreturn0);
3104 __ mov(Oreturn1->after_save(), Oreturn1);
3105 }
3107 __ mov(O4array_size->after_save(), O4array_size);
3108 __ sub(O4array_size, 1, O4array_size);
3109 __ mov(O3array->after_save(), O3array);
3110 __ mov(O2UnrollBlock->after_save(), O2UnrollBlock);
3111 __ add(G3pcs, wordSize, G3pcs); // point to next pc value
3113 #ifdef ASSERT
3114 // trash registers to show a clear pattern in backtraces
3115 __ set(0xDEAD0000, I0);
3116 __ add(I0, 2, I1);
3117 __ add(I0, 4, I2);
3118 __ add(I0, 6, I3);
3119 __ add(I0, 8, I4);
3120 // Don't touch I5 could have valuable savedSP
3121 __ set(0xDEADBEEF, L0);
3122 __ mov(L0, L1);
3123 __ mov(L0, L2);
3124 __ mov(L0, L3);
3125 __ mov(L0, L4);
3126 __ mov(L0, L5);
3128 // trash the return value as there is nothing to return yet
3129 __ set(0xDEAD0001, O7);
3130 #endif
3132 __ mov(SP, O5_savedSP);
3133 }
3136 static void make_new_frames(MacroAssembler* masm, bool deopt) {
3137 //
3138 // loop through the UnrollBlock info and create new frames
3139 //
3140 Register G3pcs = G3_scratch;
3141 Register Oreturn0 = O0;
3142 Register Oreturn1 = O1;
3143 Register O2UnrollBlock = O2;
3144 Register O3array = O3;
3145 Register O4array_size = O4;
3146 Label loop;
3148 // Before we make new frames, check to see if stack is available.
3149 // Do this after the caller's return address is on top of stack
3150 if (UseStackBanging) {
3151 // Get total frame size for interpreted frames
3152 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes(), O4);
3153 __ bang_stack_size(O4, O3, G3_scratch);
3154 }
3156 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes(), O4array_size);
3157 __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes(), G3pcs);
3158 __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes(), O3array);
3160 // Adjust old interpreter frame to make space for new frame's extra java locals
3161 //
3162 // We capture the original sp for the transition frame only because it is needed in
3163 // order to properly calculate interpreter_sp_adjustment. Even though in real life
3164 // every interpreter frame captures a savedSP it is only needed at the transition
3165 // (fortunately). If we had to have it correct everywhere then we would need to
3166 // be told the sp_adjustment for each frame we create. If the frame size array
3167 // were to have twice the frame count entries then we could have pairs [sp_adjustment, frame_size]
3168 // for each frame we create and keep up the illusion every where.
3169 //
3171 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes(), O7);
3172 __ mov(SP, O5_savedSP); // remember initial sender's original sp before adjustment
3173 __ sub(SP, O7, SP);
3175 #ifdef ASSERT
3176 // make sure that there is at least one entry in the array
3177 __ tst(O4array_size);
3178 __ breakpoint_trap(Assembler::zero);
3179 #endif
3181 // Now push the new interpreter frames
3182 __ bind(loop);
3184 // allocate a new frame, filling the registers
3186 gen_new_frame(masm, deopt); // allocate an interpreter frame
3188 __ tst(O4array_size);
3189 __ br(Assembler::notZero, false, Assembler::pn, loop);
3190 __ delayed()->add(O3array, wordSize, O3array);
3191 __ ld_ptr(G3pcs, 0, O7); // load final frame new pc
3193 }
3195 //------------------------------generate_deopt_blob----------------------------
3196 // Ought to generate an ideal graph & compile, but here's some SPARC ASM
3197 // instead.
3198 void SharedRuntime::generate_deopt_blob() {
3199 // allocate space for the code
3200 ResourceMark rm;
3201 // setup code generation tools
3202 int pad = VerifyThread ? 512 : 0;// Extra slop space for more verify code
3203 #ifdef _LP64
3204 CodeBuffer buffer("deopt_blob", 2100+pad, 512);
3205 #else
3206 // Measured 8/7/03 at 1212 in 32bit debug build (no VerifyThread)
3207 // Measured 8/7/03 at 1396 in 32bit debug build (VerifyThread)
3208 CodeBuffer buffer("deopt_blob", 1600+pad, 512);
3209 #endif /* _LP64 */
3210 MacroAssembler* masm = new MacroAssembler(&buffer);
3211 FloatRegister Freturn0 = F0;
3212 Register Greturn1 = G1;
3213 Register Oreturn0 = O0;
3214 Register Oreturn1 = O1;
3215 Register O2UnrollBlock = O2;
3216 Register O3tmp = O3;
3217 Register I5exception_tmp = I5;
3218 Register G4exception_tmp = G4_scratch;
3219 int frame_size_words;
3220 Address saved_Freturn0_addr(FP, -sizeof(double) + STACK_BIAS);
3221 #if !defined(_LP64) && defined(COMPILER2)
3222 Address saved_Greturn1_addr(FP, -sizeof(double) -sizeof(jlong) + STACK_BIAS);
3223 #endif
3224 Label cont;
3226 OopMapSet *oop_maps = new OopMapSet();
3228 //
3229 // This is the entry point for code which is returning to a de-optimized
3230 // frame.
3231 // The steps taken by this frame are as follows:
3232 // - push a dummy "register_save" and save the return values (O0, O1, F0/F1, G1)
3233 // and all potentially live registers (at a pollpoint many registers can be live).
3234 //
3235 // - call the C routine: Deoptimization::fetch_unroll_info (this function
3236 // returns information about the number and size of interpreter frames
3237 // which are equivalent to the frame which is being deoptimized)
3238 // - deallocate the unpack frame, restoring only results values. Other
3239 // volatile registers will now be captured in the vframeArray as needed.
3240 // - deallocate the deoptimization frame
3241 // - in a loop using the information returned in the previous step
3242 // push new interpreter frames (take care to propagate the return
3243 // values through each new frame pushed)
3244 // - create a dummy "unpack_frame" and save the return values (O0, O1, F0)
3245 // - call the C routine: Deoptimization::unpack_frames (this function
3246 // lays out values on the interpreter frame which was just created)
3247 // - deallocate the dummy unpack_frame
3248 // - ensure that all the return values are correctly set and then do
3249 // a return to the interpreter entry point
3250 //
3251 // Refer to the following methods for more information:
3252 // - Deoptimization::fetch_unroll_info
3253 // - Deoptimization::unpack_frames
3255 OopMap* map = NULL;
3257 int start = __ offset();
3259 // restore G2, the trampoline destroyed it
3260 __ get_thread();
3262 // On entry we have been called by the deoptimized nmethod with a call that
3263 // replaced the original call (or safepoint polling location) so the deoptimizing
3264 // pc is now in O7. Return values are still in the expected places
3266 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
3267 __ ba(false, cont);
3268 __ delayed()->mov(Deoptimization::Unpack_deopt, I5exception_tmp);
3270 int exception_offset = __ offset() - start;
3272 // restore G2, the trampoline destroyed it
3273 __ get_thread();
3275 // On entry we have been jumped to by the exception handler (or exception_blob
3276 // for server). O0 contains the exception oop and O7 contains the original
3277 // exception pc. So if we push a frame here it will look to the
3278 // stack walking code (fetch_unroll_info) just like a normal call so
3279 // state will be extracted normally.
3281 // save exception oop in JavaThread and fall through into the
3282 // exception_in_tls case since they are handled in same way except
3283 // for where the pending exception is kept.
3284 __ st_ptr(Oexception, G2_thread, JavaThread::exception_oop_offset());
3286 //
3287 // Vanilla deoptimization with an exception pending in exception_oop
3288 //
3289 int exception_in_tls_offset = __ offset() - start;
3291 // No need to update oop_map as each call to save_live_registers will produce identical oopmap
3292 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
3294 // Restore G2_thread
3295 __ get_thread();
3297 #ifdef ASSERT
3298 {
3299 // verify that there is really an exception oop in exception_oop
3300 Label has_exception;
3301 __ ld_ptr(G2_thread, JavaThread::exception_oop_offset(), Oexception);
3302 __ br_notnull(Oexception, false, Assembler::pt, has_exception);
3303 __ delayed()-> nop();
3304 __ stop("no exception in thread");
3305 __ bind(has_exception);
3307 // verify that there is no pending exception
3308 Label no_pending_exception;
3309 Address exception_addr(G2_thread, Thread::pending_exception_offset());
3310 __ ld_ptr(exception_addr, Oexception);
3311 __ br_null(Oexception, false, Assembler::pt, no_pending_exception);
3312 __ delayed()->nop();
3313 __ stop("must not have pending exception here");
3314 __ bind(no_pending_exception);
3315 }
3316 #endif
3318 __ ba(false, cont);
3319 __ delayed()->mov(Deoptimization::Unpack_exception, I5exception_tmp);;
3321 //
3322 // Reexecute entry, similar to c2 uncommon trap
3323 //
3324 int reexecute_offset = __ offset() - start;
3326 // No need to update oop_map as each call to save_live_registers will produce identical oopmap
3327 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
3329 __ mov(Deoptimization::Unpack_reexecute, I5exception_tmp);
3331 __ bind(cont);
3333 __ set_last_Java_frame(SP, noreg);
3335 // do the call by hand so we can get the oopmap
3337 __ mov(G2_thread, L7_thread_cache);
3338 __ call(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info), relocInfo::runtime_call_type);
3339 __ delayed()->mov(G2_thread, O0);
3341 // Set an oopmap for the call site this describes all our saved volatile registers
3343 oop_maps->add_gc_map( __ offset()-start, map);
3345 __ mov(L7_thread_cache, G2_thread);
3347 __ reset_last_Java_frame();
3349 // NOTE: we know that only O0/O1 will be reloaded by restore_result_registers
3350 // so this move will survive
3352 __ mov(I5exception_tmp, G4exception_tmp);
3354 __ mov(O0, O2UnrollBlock->after_save());
3356 RegisterSaver::restore_result_registers(masm);
3358 Label noException;
3359 __ cmp(G4exception_tmp, Deoptimization::Unpack_exception); // Was exception pending?
3360 __ br(Assembler::notEqual, false, Assembler::pt, noException);
3361 __ delayed()->nop();
3363 // Move the pending exception from exception_oop to Oexception so
3364 // the pending exception will be picked up the interpreter.
3365 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), Oexception);
3366 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset()));
3367 __ bind(noException);
3369 // deallocate the deoptimization frame taking care to preserve the return values
3370 __ mov(Oreturn0, Oreturn0->after_save());
3371 __ mov(Oreturn1, Oreturn1->after_save());
3372 __ mov(O2UnrollBlock, O2UnrollBlock->after_save());
3373 __ restore();
3375 // Allocate new interpreter frame(s) and possible c2i adapter frame
3377 make_new_frames(masm, true);
3379 // push a dummy "unpack_frame" taking care of float return values and
3380 // call Deoptimization::unpack_frames to have the unpacker layout
3381 // information in the interpreter frames just created and then return
3382 // to the interpreter entry point
3383 __ save(SP, -frame_size_words*wordSize, SP);
3384 __ stf(FloatRegisterImpl::D, Freturn0, saved_Freturn0_addr);
3385 #if !defined(_LP64)
3386 #if defined(COMPILER2)
3387 if (!TieredCompilation) {
3388 // 32-bit 1-register longs return longs in G1
3389 __ stx(Greturn1, saved_Greturn1_addr);
3390 }
3391 #endif
3392 __ set_last_Java_frame(SP, noreg);
3393 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, G4exception_tmp);
3394 #else
3395 // LP64 uses g4 in set_last_Java_frame
3396 __ mov(G4exception_tmp, O1);
3397 __ set_last_Java_frame(SP, G0);
3398 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O1);
3399 #endif
3400 __ reset_last_Java_frame();
3401 __ ldf(FloatRegisterImpl::D, saved_Freturn0_addr, Freturn0);
3403 // In tiered we never use C2 to compile methods returning longs so
3404 // the result is where we expect it already.
3406 #if !defined(_LP64) && defined(COMPILER2)
3407 // In 32 bit, C2 returns longs in G1 so restore the saved G1 into
3408 // I0/I1 if the return value is long. In the tiered world there is
3409 // a mismatch between how C1 and C2 return longs compiles and so
3410 // currently compilation of methods which return longs is disabled
3411 // for C2 and so is this code. Eventually C1 and C2 will do the
3412 // same thing for longs in the tiered world.
3413 if (!TieredCompilation) {
3414 Label not_long;
3415 __ cmp(O0,T_LONG);
3416 __ br(Assembler::notEqual, false, Assembler::pt, not_long);
3417 __ delayed()->nop();
3418 __ ldd(saved_Greturn1_addr,I0);
3419 __ bind(not_long);
3420 }
3421 #endif
3422 __ ret();
3423 __ delayed()->restore();
3425 masm->flush();
3426 _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_words);
3427 _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset);
3428 }
3430 #ifdef COMPILER2
3432 //------------------------------generate_uncommon_trap_blob--------------------
3433 // Ought to generate an ideal graph & compile, but here's some SPARC ASM
3434 // instead.
3435 void SharedRuntime::generate_uncommon_trap_blob() {
3436 // allocate space for the code
3437 ResourceMark rm;
3438 // setup code generation tools
3439 int pad = VerifyThread ? 512 : 0;
3440 #ifdef _LP64
3441 CodeBuffer buffer("uncommon_trap_blob", 2700+pad, 512);
3442 #else
3443 // Measured 8/7/03 at 660 in 32bit debug build (no VerifyThread)
3444 // Measured 8/7/03 at 1028 in 32bit debug build (VerifyThread)
3445 CodeBuffer buffer("uncommon_trap_blob", 2000+pad, 512);
3446 #endif
3447 MacroAssembler* masm = new MacroAssembler(&buffer);
3448 Register O2UnrollBlock = O2;
3449 Register O3tmp = O3;
3450 Register O2klass_index = O2;
3452 //
3453 // This is the entry point for all traps the compiler takes when it thinks
3454 // it cannot handle further execution of compilation code. The frame is
3455 // deoptimized in these cases and converted into interpreter frames for
3456 // execution
3457 // The steps taken by this frame are as follows:
3458 // - push a fake "unpack_frame"
3459 // - call the C routine Deoptimization::uncommon_trap (this function
3460 // packs the current compiled frame into vframe arrays and returns
3461 // information about the number and size of interpreter frames which
3462 // are equivalent to the frame which is being deoptimized)
3463 // - deallocate the "unpack_frame"
3464 // - deallocate the deoptimization frame
3465 // - in a loop using the information returned in the previous step
3466 // push interpreter frames;
3467 // - create a dummy "unpack_frame"
3468 // - call the C routine: Deoptimization::unpack_frames (this function
3469 // lays out values on the interpreter frame which was just created)
3470 // - deallocate the dummy unpack_frame
3471 // - return to the interpreter entry point
3472 //
3473 // Refer to the following methods for more information:
3474 // - Deoptimization::uncommon_trap
3475 // - Deoptimization::unpack_frame
3477 // the unloaded class index is in O0 (first parameter to this blob)
3479 // push a dummy "unpack_frame"
3480 // and call Deoptimization::uncommon_trap to pack the compiled frame into
3481 // vframe array and return the UnrollBlock information
3482 __ save_frame(0);
3483 __ set_last_Java_frame(SP, noreg);
3484 __ mov(I0, O2klass_index);
3485 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap), G2_thread, O2klass_index);
3486 __ reset_last_Java_frame();
3487 __ mov(O0, O2UnrollBlock->after_save());
3488 __ restore();
3490 // deallocate the deoptimized frame taking care to preserve the return values
3491 __ mov(O2UnrollBlock, O2UnrollBlock->after_save());
3492 __ restore();
3494 // Allocate new interpreter frame(s) and possible c2i adapter frame
3496 make_new_frames(masm, false);
3498 // push a dummy "unpack_frame" taking care of float return values and
3499 // call Deoptimization::unpack_frames to have the unpacker layout
3500 // information in the interpreter frames just created and then return
3501 // to the interpreter entry point
3502 __ save_frame(0);
3503 __ set_last_Java_frame(SP, noreg);
3504 __ mov(Deoptimization::Unpack_uncommon_trap, O3); // indicate it is the uncommon trap case
3505 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O3);
3506 __ reset_last_Java_frame();
3507 __ ret();
3508 __ delayed()->restore();
3510 masm->flush();
3511 _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, NULL, __ total_frame_size_in_bytes(0)/wordSize);
3512 }
3514 #endif // COMPILER2
3516 //------------------------------generate_handler_blob-------------------
3517 //
3518 // Generate a special Compile2Runtime blob that saves all registers, and sets
3519 // up an OopMap.
3520 //
3521 // This blob is jumped to (via a breakpoint and the signal handler) from a
3522 // safepoint in compiled code. On entry to this blob, O7 contains the
3523 // address in the original nmethod at which we should resume normal execution.
3524 // Thus, this blob looks like a subroutine which must preserve lots of
3525 // registers and return normally. Note that O7 is never register-allocated,
3526 // so it is guaranteed to be free here.
3527 //
3529 // The hardest part of what this blob must do is to save the 64-bit %o
3530 // registers in the 32-bit build. A simple 'save' turn the %o's to %i's and
3531 // an interrupt will chop off their heads. Making space in the caller's frame
3532 // first will let us save the 64-bit %o's before save'ing, but we cannot hand
3533 // the adjusted FP off to the GC stack-crawler: this will modify the caller's
3534 // SP and mess up HIS OopMaps. So we first adjust the caller's SP, then save
3535 // the 64-bit %o's, then do a save, then fixup the caller's SP (our FP).
3536 // Tricky, tricky, tricky...
3538 static SafepointBlob* generate_handler_blob(address call_ptr, bool cause_return) {
3539 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
3541 // allocate space for the code
3542 ResourceMark rm;
3543 // setup code generation tools
3544 // Measured 8/7/03 at 896 in 32bit debug build (no VerifyThread)
3545 // Measured 8/7/03 at 1080 in 32bit debug build (VerifyThread)
3546 // even larger with TraceJumps
3547 int pad = TraceJumps ? 512 : 0;
3548 CodeBuffer buffer("handler_blob", 1600 + pad, 512);
3549 MacroAssembler* masm = new MacroAssembler(&buffer);
3550 int frame_size_words;
3551 OopMapSet *oop_maps = new OopMapSet();
3552 OopMap* map = NULL;
3554 int start = __ offset();
3556 // If this causes a return before the processing, then do a "restore"
3557 if (cause_return) {
3558 __ restore();
3559 } else {
3560 // Make it look like we were called via the poll
3561 // so that frame constructor always sees a valid return address
3562 __ ld_ptr(G2_thread, in_bytes(JavaThread::saved_exception_pc_offset()), O7);
3563 __ sub(O7, frame::pc_return_offset, O7);
3564 }
3566 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
3568 // setup last_Java_sp (blows G4)
3569 __ set_last_Java_frame(SP, noreg);
3571 // call into the runtime to handle illegal instructions exception
3572 // Do not use call_VM_leaf, because we need to make a GC map at this call site.
3573 __ mov(G2_thread, O0);
3574 __ save_thread(L7_thread_cache);
3575 __ call(call_ptr);
3576 __ delayed()->nop();
3578 // Set an oopmap for the call site.
3579 // We need this not only for callee-saved registers, but also for volatile
3580 // registers that the compiler might be keeping live across a safepoint.
3582 oop_maps->add_gc_map( __ offset() - start, map);
3584 __ restore_thread(L7_thread_cache);
3585 // clear last_Java_sp
3586 __ reset_last_Java_frame();
3588 // Check for exceptions
3589 Label pending;
3591 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O1);
3592 __ tst(O1);
3593 __ brx(Assembler::notEqual, true, Assembler::pn, pending);
3594 __ delayed()->nop();
3596 RegisterSaver::restore_live_registers(masm);
3598 // We are back the the original state on entry and ready to go.
3600 __ retl();
3601 __ delayed()->nop();
3603 // Pending exception after the safepoint
3605 __ bind(pending);
3607 RegisterSaver::restore_live_registers(masm);
3609 // We are back the the original state on entry.
3611 // Tail-call forward_exception_entry, with the issuing PC in O7,
3612 // so it looks like the original nmethod called forward_exception_entry.
3613 __ set((intptr_t)StubRoutines::forward_exception_entry(), O0);
3614 __ JMP(O0, 0);
3615 __ delayed()->nop();
3617 // -------------
3618 // make sure all code is generated
3619 masm->flush();
3621 // return exception blob
3622 return SafepointBlob::create(&buffer, oop_maps, frame_size_words);
3623 }
3625 //
3626 // generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss
3627 //
3628 // Generate a stub that calls into vm to find out the proper destination
3629 // of a java call. All the argument registers are live at this point
3630 // but since this is generic code we don't know what they are and the caller
3631 // must do any gc of the args.
3632 //
3633 static RuntimeStub* generate_resolve_blob(address destination, const char* name) {
3634 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
3636 // allocate space for the code
3637 ResourceMark rm;
3638 // setup code generation tools
3639 // Measured 8/7/03 at 896 in 32bit debug build (no VerifyThread)
3640 // Measured 8/7/03 at 1080 in 32bit debug build (VerifyThread)
3641 // even larger with TraceJumps
3642 int pad = TraceJumps ? 512 : 0;
3643 CodeBuffer buffer(name, 1600 + pad, 512);
3644 MacroAssembler* masm = new MacroAssembler(&buffer);
3645 int frame_size_words;
3646 OopMapSet *oop_maps = new OopMapSet();
3647 OopMap* map = NULL;
3649 int start = __ offset();
3651 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
3653 int frame_complete = __ offset();
3655 // setup last_Java_sp (blows G4)
3656 __ set_last_Java_frame(SP, noreg);
3658 // call into the runtime to handle illegal instructions exception
3659 // Do not use call_VM_leaf, because we need to make a GC map at this call site.
3660 __ mov(G2_thread, O0);
3661 __ save_thread(L7_thread_cache);
3662 __ call(destination, relocInfo::runtime_call_type);
3663 __ delayed()->nop();
3665 // O0 contains the address we are going to jump to assuming no exception got installed
3667 // Set an oopmap for the call site.
3668 // We need this not only for callee-saved registers, but also for volatile
3669 // registers that the compiler might be keeping live across a safepoint.
3671 oop_maps->add_gc_map( __ offset() - start, map);
3673 __ restore_thread(L7_thread_cache);
3674 // clear last_Java_sp
3675 __ reset_last_Java_frame();
3677 // Check for exceptions
3678 Label pending;
3680 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O1);
3681 __ tst(O1);
3682 __ brx(Assembler::notEqual, true, Assembler::pn, pending);
3683 __ delayed()->nop();
3685 // get the returned methodOop
3687 __ get_vm_result(G5_method);
3688 __ stx(G5_method, SP, RegisterSaver::G5_offset()+STACK_BIAS);
3690 // O0 is where we want to jump, overwrite G3 which is saved and scratch
3692 __ stx(O0, SP, RegisterSaver::G3_offset()+STACK_BIAS);
3694 RegisterSaver::restore_live_registers(masm);
3696 // We are back the the original state on entry and ready to go.
3698 __ JMP(G3, 0);
3699 __ delayed()->nop();
3701 // Pending exception after the safepoint
3703 __ bind(pending);
3705 RegisterSaver::restore_live_registers(masm);
3707 // We are back the the original state on entry.
3709 // Tail-call forward_exception_entry, with the issuing PC in O7,
3710 // so it looks like the original nmethod called forward_exception_entry.
3711 __ set((intptr_t)StubRoutines::forward_exception_entry(), O0);
3712 __ JMP(O0, 0);
3713 __ delayed()->nop();
3715 // -------------
3716 // make sure all code is generated
3717 masm->flush();
3719 // return the blob
3720 // frame_size_words or bytes??
3721 return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_words, oop_maps, true);
3722 }
3724 void SharedRuntime::generate_stubs() {
3726 _wrong_method_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::handle_wrong_method),
3727 "wrong_method_stub");
3729 _ic_miss_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::handle_wrong_method_ic_miss),
3730 "ic_miss_stub");
3732 _resolve_opt_virtual_call_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::resolve_opt_virtual_call_C),
3733 "resolve_opt_virtual_call");
3735 _resolve_virtual_call_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::resolve_virtual_call_C),
3736 "resolve_virtual_call");
3738 _resolve_static_call_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::resolve_static_call_C),
3739 "resolve_static_call");
3741 _polling_page_safepoint_handler_blob =
3742 generate_handler_blob(CAST_FROM_FN_PTR(address,
3743 SafepointSynchronize::handle_polling_page_exception), false);
3745 _polling_page_return_handler_blob =
3746 generate_handler_blob(CAST_FROM_FN_PTR(address,
3747 SafepointSynchronize::handle_polling_page_exception), true);
3749 generate_deopt_blob();
3751 #ifdef COMPILER2
3752 generate_uncommon_trap_blob();
3753 #endif // COMPILER2
3754 }