Fri, 26 Jun 2009 07:26:10 -0700
5057225: Remove useless I2L conversions
Summary: The optimizer should be told to normalize (AndL (ConvI2L x) 0xFF) to (ConvI2L (AndI x 0xFF)), and then the existing matcher rule will work for free.
Reviewed-by: kvn
1 //
2 // Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 // CA 95054 USA or visit www.sun.com if you need additional information or
21 // have any questions.
22 //
23 //
25 // X86 Architecture Description File
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
77 // Special Registers
78 reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad());
80 // Float registers. We treat TOS/FPR0 special. It is invisible to the
81 // allocator, and only shows up in the encodings.
82 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
83 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
84 // Ok so here's the trick FPR1 is really st(0) except in the midst
85 // of emission of assembly for a machnode. During the emission the fpu stack
86 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
87 // the stack will not have this element so FPR1 == st(0) from the
88 // oopMap viewpoint. This same weirdness with numbering causes
89 // instruction encoding to have to play games with the register
90 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
91 // where it does flt->flt moves to see an example
92 //
93 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
94 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
95 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
96 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
97 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
98 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
99 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
100 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
101 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
102 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
103 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
104 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
105 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
106 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
108 // XMM registers. 128-bit registers or 4 words each, labeled a-d.
109 // Word a in each register holds a Float, words ab hold a Double.
110 // We currently do not use the SIMD capabilities, so registers cd
111 // are unused at the moment.
112 reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
113 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
114 reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
115 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
116 reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
117 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
118 reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
119 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
120 reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
121 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
122 reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
123 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
124 reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
125 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
126 reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
127 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
129 // Specify priority of register selection within phases of register
130 // allocation. Highest priority is first. A useful heuristic is to
131 // give registers a low priority when they are required by machine
132 // instructions, like EAX and EDX. Registers which are used as
133 // pairs must fall on an even boundary (witness the FPR#L's in this list).
134 // For the Intel integer registers, the equivalent Long pairs are
135 // EDX:EAX, EBX:ECX, and EDI:EBP.
136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
139 FPR6L, FPR6H, FPR7L, FPR7H );
141 alloc_class chunk1( XMM0a, XMM0b,
142 XMM1a, XMM1b,
143 XMM2a, XMM2b,
144 XMM3a, XMM3b,
145 XMM4a, XMM4b,
146 XMM5a, XMM5b,
147 XMM6a, XMM6b,
148 XMM7a, XMM7b, EFLAGS);
151 //----------Architecture Description Register Classes--------------------------
152 // Several register classes are automatically defined based upon information in
153 // this architecture description.
154 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
155 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
156 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
157 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
158 //
159 // Class for all registers
160 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
161 // Class for general registers
162 reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
163 // Class for general registers which may be used for implicit null checks on win95
164 // Also safe for use by tailjump. We don't want to allocate in rbp,
165 reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
166 // Class of "X" registers
167 reg_class x_reg(EBX, ECX, EDX, EAX);
168 // Class of registers that can appear in an address with no offset.
169 // EBP and ESP require an extra instruction byte for zero offset.
170 // Used in fast-unlock
171 reg_class p_reg(EDX, EDI, ESI, EBX);
172 // Class for general registers not including ECX
173 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
174 // Class for general registers not including EAX
175 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
176 // Class for general registers not including EAX or EBX.
177 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
178 // Class of EAX (for multiply and divide operations)
179 reg_class eax_reg(EAX);
180 // Class of EBX (for atomic add)
181 reg_class ebx_reg(EBX);
182 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
183 reg_class ecx_reg(ECX);
184 // Class of EDX (for multiply and divide operations)
185 reg_class edx_reg(EDX);
186 // Class of EDI (for synchronization)
187 reg_class edi_reg(EDI);
188 // Class of ESI (for synchronization)
189 reg_class esi_reg(ESI);
190 // Singleton class for interpreter's stack pointer
191 reg_class ebp_reg(EBP);
192 // Singleton class for stack pointer
193 reg_class sp_reg(ESP);
194 // Singleton class for instruction pointer
195 // reg_class ip_reg(EIP);
196 // Singleton class for condition codes
197 reg_class int_flags(EFLAGS);
198 // Class of integer register pairs
199 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
200 // Class of integer register pairs that aligns with calling convention
201 reg_class eadx_reg( EAX,EDX );
202 reg_class ebcx_reg( ECX,EBX );
203 // Not AX or DX, used in divides
204 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
206 // Floating point registers. Notice FPR0 is not a choice.
207 // FPR0 is not ever allocated; we use clever encodings to fake
208 // a 2-address instructions out of Intels FP stack.
209 reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
211 // make a register class for SSE registers
212 reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a);
214 // make a double register class for SSE2 registers
215 reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b,
216 XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b );
218 reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
219 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
220 FPR7L,FPR7H );
222 reg_class flt_reg0( FPR1L );
223 reg_class dbl_reg0( FPR1L,FPR1H );
224 reg_class dbl_reg1( FPR2L,FPR2H );
225 reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
226 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
228 // XMM6 and XMM7 could be used as temporary registers for long, float and
229 // double values for SSE2.
230 reg_class xdb_reg6( XMM6a,XMM6b );
231 reg_class xdb_reg7( XMM7a,XMM7b );
232 %}
235 //----------SOURCE BLOCK-------------------------------------------------------
236 // This is a block of C++ code which provides values, functions, and
237 // definitions necessary in the rest of the architecture description
238 source %{
239 #define RELOC_IMM32 Assembler::imm_operand
240 #define RELOC_DISP32 Assembler::disp32_operand
242 #define __ _masm.
244 // How to find the high register of a Long pair, given the low register
245 #define HIGH_FROM_LOW(x) ((x)+2)
247 // These masks are used to provide 128-bit aligned bitmasks to the XMM
248 // instructions, to allow sign-masking or sign-bit flipping. They allow
249 // fast versions of NegF/NegD and AbsF/AbsD.
251 // Note: 'double' and 'long long' have 32-bits alignment on x86.
252 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
253 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
254 // of 128-bits operands for SSE instructions.
255 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
256 // Store the value to a 128-bits operand.
257 operand[0] = lo;
258 operand[1] = hi;
259 return operand;
260 }
262 // Buffer for 128-bits masks used by SSE instructions.
263 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
265 // Static initialization during VM startup.
266 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
267 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
268 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
269 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
271 // !!!!! Special hack to get all type of calls to specify the byte offset
272 // from the start of the call to the point where the return address
273 // will point.
274 int MachCallStaticJavaNode::ret_addr_offset() {
275 return 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); // 5 bytes from start of call to where return address points
276 }
278 int MachCallDynamicJavaNode::ret_addr_offset() {
279 return 10 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); // 10 bytes from start of call to where return address points
280 }
282 static int sizeof_FFree_Float_Stack_All = -1;
284 int MachCallRuntimeNode::ret_addr_offset() {
285 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
286 return sizeof_FFree_Float_Stack_All + 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0);
287 }
289 // Indicate if the safepoint node needs the polling page as an input.
290 // Since x86 does have absolute addressing, it doesn't.
291 bool SafePointNode::needs_polling_address_input() {
292 return false;
293 }
295 //
296 // Compute padding required for nodes which need alignment
297 //
299 // The address of the call instruction needs to be 4-byte aligned to
300 // ensure that it does not span a cache line so that it can be patched.
301 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
302 if (Compile::current()->in_24_bit_fp_mode())
303 current_offset += 6; // skip fldcw in pre_call_FPU, if any
304 current_offset += 1; // skip call opcode byte
305 return round_to(current_offset, alignment_required()) - current_offset;
306 }
308 // The address of the call instruction needs to be 4-byte aligned to
309 // ensure that it does not span a cache line so that it can be patched.
310 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
311 if (Compile::current()->in_24_bit_fp_mode())
312 current_offset += 6; // skip fldcw in pre_call_FPU, if any
313 current_offset += 5; // skip MOV instruction
314 current_offset += 1; // skip call opcode byte
315 return round_to(current_offset, alignment_required()) - current_offset;
316 }
318 #ifndef PRODUCT
319 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const {
320 st->print("INT3");
321 }
322 #endif
324 // EMIT_RM()
325 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
326 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
327 *(cbuf.code_end()) = c;
328 cbuf.set_code_end(cbuf.code_end() + 1);
329 }
331 // EMIT_CC()
332 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
333 unsigned char c = (unsigned char)( f1 | f2 );
334 *(cbuf.code_end()) = c;
335 cbuf.set_code_end(cbuf.code_end() + 1);
336 }
338 // EMIT_OPCODE()
339 void emit_opcode(CodeBuffer &cbuf, int code) {
340 *(cbuf.code_end()) = (unsigned char)code;
341 cbuf.set_code_end(cbuf.code_end() + 1);
342 }
344 // EMIT_OPCODE() w/ relocation information
345 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
346 cbuf.relocate(cbuf.inst_mark() + offset, reloc);
347 emit_opcode(cbuf, code);
348 }
350 // EMIT_D8()
351 void emit_d8(CodeBuffer &cbuf, int d8) {
352 *(cbuf.code_end()) = (unsigned char)d8;
353 cbuf.set_code_end(cbuf.code_end() + 1);
354 }
356 // EMIT_D16()
357 void emit_d16(CodeBuffer &cbuf, int d16) {
358 *((short *)(cbuf.code_end())) = d16;
359 cbuf.set_code_end(cbuf.code_end() + 2);
360 }
362 // EMIT_D32()
363 void emit_d32(CodeBuffer &cbuf, int d32) {
364 *((int *)(cbuf.code_end())) = d32;
365 cbuf.set_code_end(cbuf.code_end() + 4);
366 }
368 // emit 32 bit value and construct relocation entry from relocInfo::relocType
369 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
370 int format) {
371 cbuf.relocate(cbuf.inst_mark(), reloc, format);
373 *((int *)(cbuf.code_end())) = d32;
374 cbuf.set_code_end(cbuf.code_end() + 4);
375 }
377 // emit 32 bit value and construct relocation entry from RelocationHolder
378 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
379 int format) {
380 #ifdef ASSERT
381 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
382 assert(oop(d32)->is_oop() && oop(d32)->is_perm(), "cannot embed non-perm oops in code");
383 }
384 #endif
385 cbuf.relocate(cbuf.inst_mark(), rspec, format);
387 *((int *)(cbuf.code_end())) = d32;
388 cbuf.set_code_end(cbuf.code_end() + 4);
389 }
391 // Access stack slot for load or store
392 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
393 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
394 if( -128 <= disp && disp <= 127 ) {
395 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
396 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
397 emit_d8 (cbuf, disp); // Displacement // R/M byte
398 } else {
399 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
400 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
401 emit_d32(cbuf, disp); // Displacement // R/M byte
402 }
403 }
405 // eRegI ereg, memory mem) %{ // emit_reg_mem
406 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) {
407 // There is no index & no scale, use form without SIB byte
408 if ((index == 0x4) &&
409 (scale == 0) && (base != ESP_enc)) {
410 // If no displacement, mode is 0x0; unless base is [EBP]
411 if ( (displace == 0) && (base != EBP_enc) ) {
412 emit_rm(cbuf, 0x0, reg_encoding, base);
413 }
414 else { // If 8-bit displacement, mode 0x1
415 if ((displace >= -128) && (displace <= 127)
416 && !(displace_is_oop) ) {
417 emit_rm(cbuf, 0x1, reg_encoding, base);
418 emit_d8(cbuf, displace);
419 }
420 else { // If 32-bit displacement
421 if (base == -1) { // Special flag for absolute address
422 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
423 // (manual lies; no SIB needed here)
424 if ( displace_is_oop ) {
425 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
426 } else {
427 emit_d32 (cbuf, displace);
428 }
429 }
430 else { // Normal base + offset
431 emit_rm(cbuf, 0x2, reg_encoding, base);
432 if ( displace_is_oop ) {
433 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
434 } else {
435 emit_d32 (cbuf, displace);
436 }
437 }
438 }
439 }
440 }
441 else { // Else, encode with the SIB byte
442 // If no displacement, mode is 0x0; unless base is [EBP]
443 if (displace == 0 && (base != EBP_enc)) { // If no displacement
444 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
445 emit_rm(cbuf, scale, index, base);
446 }
447 else { // If 8-bit displacement, mode 0x1
448 if ((displace >= -128) && (displace <= 127)
449 && !(displace_is_oop) ) {
450 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
451 emit_rm(cbuf, scale, index, base);
452 emit_d8(cbuf, displace);
453 }
454 else { // If 32-bit displacement
455 if (base == 0x04 ) {
456 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
457 emit_rm(cbuf, scale, index, 0x04);
458 } else {
459 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
460 emit_rm(cbuf, scale, index, base);
461 }
462 if ( displace_is_oop ) {
463 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
464 } else {
465 emit_d32 (cbuf, displace);
466 }
467 }
468 }
469 }
470 }
473 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
474 if( dst_encoding == src_encoding ) {
475 // reg-reg copy, use an empty encoding
476 } else {
477 emit_opcode( cbuf, 0x8B );
478 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
479 }
480 }
482 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
483 if( dst_encoding == src_encoding ) {
484 // reg-reg copy, use an empty encoding
485 } else {
486 MacroAssembler _masm(&cbuf);
488 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding));
489 }
490 }
493 //=============================================================================
494 #ifndef PRODUCT
495 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
496 Compile* C = ra_->C;
497 if( C->in_24_bit_fp_mode() ) {
498 st->print("FLDCW 24 bit fpu control word");
499 st->print_cr(""); st->print("\t");
500 }
502 int framesize = C->frame_slots() << LogBytesPerInt;
503 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
504 // Remove two words for return addr and rbp,
505 framesize -= 2*wordSize;
507 // Calls to C2R adapters often do not accept exceptional returns.
508 // We require that their callers must bang for them. But be careful, because
509 // some VM calls (such as call site linkage) can use several kilobytes of
510 // stack. But the stack safety zone should account for that.
511 // See bugs 4446381, 4468289, 4497237.
512 if (C->need_stack_bang(framesize)) {
513 st->print_cr("# stack bang"); st->print("\t");
514 }
515 st->print_cr("PUSHL EBP"); st->print("\t");
517 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
518 st->print("PUSH 0xBADB100D\t# Majik cookie for stack depth check");
519 st->print_cr(""); st->print("\t");
520 framesize -= wordSize;
521 }
523 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
524 if (framesize) {
525 st->print("SUB ESP,%d\t# Create frame",framesize);
526 }
527 } else {
528 st->print("SUB ESP,%d\t# Create frame",framesize);
529 }
530 }
531 #endif
534 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
535 Compile* C = ra_->C;
537 if (UseSSE >= 2 && VerifyFPU) {
538 MacroAssembler masm(&cbuf);
539 masm.verify_FPU(0, "FPU stack must be clean on entry");
540 }
542 // WARNING: Initial instruction MUST be 5 bytes or longer so that
543 // NativeJump::patch_verified_entry will be able to patch out the entry
544 // code safely. The fldcw is ok at 6 bytes, the push to verify stack
545 // depth is ok at 5 bytes, the frame allocation can be either 3 or
546 // 6 bytes. So if we don't do the fldcw or the push then we must
547 // use the 6 byte frame allocation even if we have no frame. :-(
548 // If method sets FPU control word do it now
549 if( C->in_24_bit_fp_mode() ) {
550 MacroAssembler masm(&cbuf);
551 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
552 }
554 int framesize = C->frame_slots() << LogBytesPerInt;
555 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
556 // Remove two words for return addr and rbp,
557 framesize -= 2*wordSize;
559 // Calls to C2R adapters often do not accept exceptional returns.
560 // We require that their callers must bang for them. But be careful, because
561 // some VM calls (such as call site linkage) can use several kilobytes of
562 // stack. But the stack safety zone should account for that.
563 // See bugs 4446381, 4468289, 4497237.
564 if (C->need_stack_bang(framesize)) {
565 MacroAssembler masm(&cbuf);
566 masm.generate_stack_overflow_check(framesize);
567 }
569 // We always push rbp, so that on return to interpreter rbp, will be
570 // restored correctly and we can correct the stack.
571 emit_opcode(cbuf, 0x50 | EBP_enc);
573 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
574 emit_opcode(cbuf, 0x68); // push 0xbadb100d
575 emit_d32(cbuf, 0xbadb100d);
576 framesize -= wordSize;
577 }
579 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
580 if (framesize) {
581 emit_opcode(cbuf, 0x83); // sub SP,#framesize
582 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
583 emit_d8(cbuf, framesize);
584 }
585 } else {
586 emit_opcode(cbuf, 0x81); // sub SP,#framesize
587 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
588 emit_d32(cbuf, framesize);
589 }
590 C->set_frame_complete(cbuf.code_end() - cbuf.code_begin());
592 #ifdef ASSERT
593 if (VerifyStackAtCalls) {
594 Label L;
595 MacroAssembler masm(&cbuf);
596 masm.push(rax);
597 masm.mov(rax, rsp);
598 masm.andptr(rax, StackAlignmentInBytes-1);
599 masm.cmpptr(rax, StackAlignmentInBytes-wordSize);
600 masm.pop(rax);
601 masm.jcc(Assembler::equal, L);
602 masm.stop("Stack is not properly aligned!");
603 masm.bind(L);
604 }
605 #endif
607 }
609 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
610 return MachNode::size(ra_); // too many variables; just compute it the hard way
611 }
613 int MachPrologNode::reloc() const {
614 return 0; // a large enough number
615 }
617 //=============================================================================
618 #ifndef PRODUCT
619 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
620 Compile *C = ra_->C;
621 int framesize = C->frame_slots() << LogBytesPerInt;
622 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
623 // Remove two words for return addr and rbp,
624 framesize -= 2*wordSize;
626 if( C->in_24_bit_fp_mode() ) {
627 st->print("FLDCW standard control word");
628 st->cr(); st->print("\t");
629 }
630 if( framesize ) {
631 st->print("ADD ESP,%d\t# Destroy frame",framesize);
632 st->cr(); st->print("\t");
633 }
634 st->print_cr("POPL EBP"); st->print("\t");
635 if( do_polling() && C->is_method_compilation() ) {
636 st->print("TEST PollPage,EAX\t! Poll Safepoint");
637 st->cr(); st->print("\t");
638 }
639 }
640 #endif
642 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
643 Compile *C = ra_->C;
645 // If method set FPU control word, restore to standard control word
646 if( C->in_24_bit_fp_mode() ) {
647 MacroAssembler masm(&cbuf);
648 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
649 }
651 int framesize = C->frame_slots() << LogBytesPerInt;
652 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
653 // Remove two words for return addr and rbp,
654 framesize -= 2*wordSize;
656 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
658 if( framesize >= 128 ) {
659 emit_opcode(cbuf, 0x81); // add SP, #framesize
660 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
661 emit_d32(cbuf, framesize);
662 }
663 else if( framesize ) {
664 emit_opcode(cbuf, 0x83); // add SP, #framesize
665 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
666 emit_d8(cbuf, framesize);
667 }
669 emit_opcode(cbuf, 0x58 | EBP_enc);
671 if( do_polling() && C->is_method_compilation() ) {
672 cbuf.relocate(cbuf.code_end(), relocInfo::poll_return_type, 0);
673 emit_opcode(cbuf,0x85);
674 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
675 emit_d32(cbuf, (intptr_t)os::get_polling_page());
676 }
677 }
679 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
680 Compile *C = ra_->C;
681 // If method set FPU control word, restore to standard control word
682 int size = C->in_24_bit_fp_mode() ? 6 : 0;
683 if( do_polling() && C->is_method_compilation() ) size += 6;
685 int framesize = C->frame_slots() << LogBytesPerInt;
686 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
687 // Remove two words for return addr and rbp,
688 framesize -= 2*wordSize;
690 size++; // popl rbp,
692 if( framesize >= 128 ) {
693 size += 6;
694 } else {
695 size += framesize ? 3 : 0;
696 }
697 return size;
698 }
700 int MachEpilogNode::reloc() const {
701 return 0; // a large enough number
702 }
704 const Pipeline * MachEpilogNode::pipeline() const {
705 return MachNode::pipeline_class();
706 }
708 int MachEpilogNode::safepoint_offset() const { return 0; }
710 //=============================================================================
712 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
713 static enum RC rc_class( OptoReg::Name reg ) {
715 if( !OptoReg::is_valid(reg) ) return rc_bad;
716 if (OptoReg::is_stack(reg)) return rc_stack;
718 VMReg r = OptoReg::as_VMReg(reg);
719 if (r->is_Register()) return rc_int;
720 if (r->is_FloatRegister()) {
721 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
722 return rc_float;
723 }
724 assert(r->is_XMMRegister(), "must be");
725 return rc_xmm;
726 }
728 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
729 int opcode, const char *op_str, int size, outputStream* st ) {
730 if( cbuf ) {
731 emit_opcode (*cbuf, opcode );
732 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false);
733 #ifndef PRODUCT
734 } else if( !do_size ) {
735 if( size != 0 ) st->print("\n\t");
736 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
737 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
738 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
739 } else { // FLD, FST, PUSH, POP
740 st->print("%s [ESP + #%d]",op_str,offset);
741 }
742 #endif
743 }
744 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
745 return size+3+offset_size;
746 }
748 // Helper for XMM registers. Extra opcode bits, limited syntax.
749 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
750 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
751 if( cbuf ) {
752 if( reg_lo+1 == reg_hi ) { // double move?
753 if( is_load && !UseXmmLoadAndClearUpper )
754 emit_opcode(*cbuf, 0x66 ); // use 'movlpd' for load
755 else
756 emit_opcode(*cbuf, 0xF2 ); // use 'movsd' otherwise
757 } else {
758 emit_opcode(*cbuf, 0xF3 );
759 }
760 emit_opcode(*cbuf, 0x0F );
761 if( reg_lo+1 == reg_hi && is_load && !UseXmmLoadAndClearUpper )
762 emit_opcode(*cbuf, 0x12 ); // use 'movlpd' for load
763 else
764 emit_opcode(*cbuf, is_load ? 0x10 : 0x11 );
765 encode_RegMem(*cbuf, Matcher::_regEncode[reg_lo], ESP_enc, 0x4, 0, offset, false);
766 #ifndef PRODUCT
767 } else if( !do_size ) {
768 if( size != 0 ) st->print("\n\t");
769 if( reg_lo+1 == reg_hi ) { // double move?
770 if( is_load ) st->print("%s %s,[ESP + #%d]",
771 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
772 Matcher::regName[reg_lo], offset);
773 else st->print("MOVSD [ESP + #%d],%s",
774 offset, Matcher::regName[reg_lo]);
775 } else {
776 if( is_load ) st->print("MOVSS %s,[ESP + #%d]",
777 Matcher::regName[reg_lo], offset);
778 else st->print("MOVSS [ESP + #%d],%s",
779 offset, Matcher::regName[reg_lo]);
780 }
781 #endif
782 }
783 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
784 return size+5+offset_size;
785 }
788 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
789 int src_hi, int dst_hi, int size, outputStream* st ) {
790 if( UseXmmRegToRegMoveAll ) {//Use movaps,movapd to move between xmm registers
791 if( cbuf ) {
792 if( (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ) {
793 emit_opcode(*cbuf, 0x66 );
794 }
795 emit_opcode(*cbuf, 0x0F );
796 emit_opcode(*cbuf, 0x28 );
797 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
798 #ifndef PRODUCT
799 } else if( !do_size ) {
800 if( size != 0 ) st->print("\n\t");
801 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
802 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
803 } else {
804 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
805 }
806 #endif
807 }
808 return size + ((src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 4 : 3);
809 } else {
810 if( cbuf ) {
811 emit_opcode(*cbuf, (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 0xF2 : 0xF3 );
812 emit_opcode(*cbuf, 0x0F );
813 emit_opcode(*cbuf, 0x10 );
814 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
815 #ifndef PRODUCT
816 } else if( !do_size ) {
817 if( size != 0 ) st->print("\n\t");
818 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
819 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
820 } else {
821 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
822 }
823 #endif
824 }
825 return size+4;
826 }
827 }
829 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
830 if( cbuf ) {
831 emit_opcode(*cbuf, 0x8B );
832 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
833 #ifndef PRODUCT
834 } else if( !do_size ) {
835 if( size != 0 ) st->print("\n\t");
836 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
837 #endif
838 }
839 return size+2;
840 }
842 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
843 int offset, int size, outputStream* st ) {
844 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
845 if( cbuf ) {
846 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
847 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
848 #ifndef PRODUCT
849 } else if( !do_size ) {
850 if( size != 0 ) st->print("\n\t");
851 st->print("FLD %s",Matcher::regName[src_lo]);
852 #endif
853 }
854 size += 2;
855 }
857 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
858 const char *op_str;
859 int op;
860 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
861 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
862 op = 0xDD;
863 } else { // 32-bit store
864 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
865 op = 0xD9;
866 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
867 }
869 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
870 }
872 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
873 // Get registers to move
874 OptoReg::Name src_second = ra_->get_reg_second(in(1));
875 OptoReg::Name src_first = ra_->get_reg_first(in(1));
876 OptoReg::Name dst_second = ra_->get_reg_second(this );
877 OptoReg::Name dst_first = ra_->get_reg_first(this );
879 enum RC src_second_rc = rc_class(src_second);
880 enum RC src_first_rc = rc_class(src_first);
881 enum RC dst_second_rc = rc_class(dst_second);
882 enum RC dst_first_rc = rc_class(dst_first);
884 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
886 // Generate spill code!
887 int size = 0;
889 if( src_first == dst_first && src_second == dst_second )
890 return size; // Self copy, no move
892 // --------------------------------------
893 // Check for mem-mem move. push/pop to move.
894 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
895 if( src_second == dst_first ) { // overlapping stack copy ranges
896 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
897 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
898 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
899 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
900 }
901 // move low bits
902 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
903 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
904 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
905 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
906 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
907 }
908 return size;
909 }
911 // --------------------------------------
912 // Check for integer reg-reg copy
913 if( src_first_rc == rc_int && dst_first_rc == rc_int )
914 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
916 // Check for integer store
917 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
918 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
920 // Check for integer load
921 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
922 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
924 // --------------------------------------
925 // Check for float reg-reg copy
926 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
927 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
928 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
929 if( cbuf ) {
931 // Note the mucking with the register encode to compensate for the 0/1
932 // indexing issue mentioned in a comment in the reg_def sections
933 // for FPR registers many lines above here.
935 if( src_first != FPR1L_num ) {
936 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
937 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
938 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
939 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
940 } else {
941 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
942 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
943 }
944 #ifndef PRODUCT
945 } else if( !do_size ) {
946 if( size != 0 ) st->print("\n\t");
947 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
948 else st->print( "FST %s", Matcher::regName[dst_first]);
949 #endif
950 }
951 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
952 }
954 // Check for float store
955 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
956 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
957 }
959 // Check for float load
960 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
961 int offset = ra_->reg2offset(src_first);
962 const char *op_str;
963 int op;
964 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
965 op_str = "FLD_D";
966 op = 0xDD;
967 } else { // 32-bit load
968 op_str = "FLD_S";
969 op = 0xD9;
970 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
971 }
972 if( cbuf ) {
973 emit_opcode (*cbuf, op );
974 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false);
975 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
976 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
977 #ifndef PRODUCT
978 } else if( !do_size ) {
979 if( size != 0 ) st->print("\n\t");
980 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
981 #endif
982 }
983 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
984 return size + 3+offset_size+2;
985 }
987 // Check for xmm reg-reg copy
988 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
989 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
990 (src_first+1 == src_second && dst_first+1 == dst_second),
991 "no non-adjacent float-moves" );
992 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
993 }
995 // Check for xmm store
996 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
997 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
998 }
1000 // Check for float xmm load
1001 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1002 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1003 }
1005 // Copy from float reg to xmm reg
1006 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1007 // copy to the top of stack from floating point reg
1008 // and use LEA to preserve flags
1009 if( cbuf ) {
1010 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1011 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1012 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1013 emit_d8(*cbuf,0xF8);
1014 #ifndef PRODUCT
1015 } else if( !do_size ) {
1016 if( size != 0 ) st->print("\n\t");
1017 st->print("LEA ESP,[ESP-8]");
1018 #endif
1019 }
1020 size += 4;
1022 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1024 // Copy from the temp memory to the xmm reg.
1025 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1027 if( cbuf ) {
1028 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1029 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1030 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1031 emit_d8(*cbuf,0x08);
1032 #ifndef PRODUCT
1033 } else if( !do_size ) {
1034 if( size != 0 ) st->print("\n\t");
1035 st->print("LEA ESP,[ESP+8]");
1036 #endif
1037 }
1038 size += 4;
1039 return size;
1040 }
1042 assert( size > 0, "missed a case" );
1044 // --------------------------------------------------------------------
1045 // Check for second bits still needing moving.
1046 if( src_second == dst_second )
1047 return size; // Self copy; no move
1048 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1050 // Check for second word int-int move
1051 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1052 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1054 // Check for second word integer store
1055 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1056 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1058 // Check for second word integer load
1059 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1060 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1063 Unimplemented();
1064 }
1066 #ifndef PRODUCT
1067 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1068 implementation( NULL, ra_, false, st );
1069 }
1070 #endif
1072 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1073 implementation( &cbuf, ra_, false, NULL );
1074 }
1076 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1077 return implementation( NULL, ra_, true, NULL );
1078 }
1080 //=============================================================================
1081 #ifndef PRODUCT
1082 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const {
1083 st->print("NOP \t# %d bytes pad for loops and calls", _count);
1084 }
1085 #endif
1087 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1088 MacroAssembler _masm(&cbuf);
1089 __ nop(_count);
1090 }
1092 uint MachNopNode::size(PhaseRegAlloc *) const {
1093 return _count;
1094 }
1097 //=============================================================================
1098 #ifndef PRODUCT
1099 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1100 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1101 int reg = ra_->get_reg_first(this);
1102 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1103 }
1104 #endif
1106 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1107 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1108 int reg = ra_->get_encode(this);
1109 if( offset >= 128 ) {
1110 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1111 emit_rm(cbuf, 0x2, reg, 0x04);
1112 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1113 emit_d32(cbuf, offset);
1114 }
1115 else {
1116 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1117 emit_rm(cbuf, 0x1, reg, 0x04);
1118 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1119 emit_d8(cbuf, offset);
1120 }
1121 }
1123 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1124 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1125 if( offset >= 128 ) {
1126 return 7;
1127 }
1128 else {
1129 return 4;
1130 }
1131 }
1133 //=============================================================================
1135 // emit call stub, compiled java to interpreter
1136 void emit_java_to_interp(CodeBuffer &cbuf ) {
1137 // Stub is fixed up when the corresponding call is converted from calling
1138 // compiled code to calling interpreted code.
1139 // mov rbx,0
1140 // jmp -1
1142 address mark = cbuf.inst_mark(); // get mark within main instrs section
1144 // Note that the code buffer's inst_mark is always relative to insts.
1145 // That's why we must use the macroassembler to generate a stub.
1146 MacroAssembler _masm(&cbuf);
1148 address base =
1149 __ start_a_stub(Compile::MAX_stubs_size);
1150 if (base == NULL) return; // CodeBuffer::expand failed
1151 // static stub relocation stores the instruction address of the call
1152 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
1153 // static stub relocation also tags the methodOop in the code-stream.
1154 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time
1155 // This is recognized as unresolved by relocs/nativeInst/ic code
1156 __ jump(RuntimeAddress(__ pc()));
1158 __ end_a_stub();
1159 // Update current stubs pointer and restore code_end.
1160 }
1161 // size of call stub, compiled java to interpretor
1162 uint size_java_to_interp() {
1163 return 10; // movl; jmp
1164 }
1165 // relocation entries for call stub, compiled java to interpretor
1166 uint reloc_java_to_interp() {
1167 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1168 }
1170 //=============================================================================
1171 #ifndef PRODUCT
1172 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1173 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1174 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1175 st->print_cr("\tNOP");
1176 st->print_cr("\tNOP");
1177 if( !OptoBreakpoint )
1178 st->print_cr("\tNOP");
1179 }
1180 #endif
1182 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1183 MacroAssembler masm(&cbuf);
1184 #ifdef ASSERT
1185 uint code_size = cbuf.code_size();
1186 #endif
1187 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1188 masm.jump_cc(Assembler::notEqual,
1189 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1190 /* WARNING these NOPs are critical so that verified entry point is properly
1191 aligned for patching by NativeJump::patch_verified_entry() */
1192 int nops_cnt = 2;
1193 if( !OptoBreakpoint ) // Leave space for int3
1194 nops_cnt += 1;
1195 masm.nop(nops_cnt);
1197 assert(cbuf.code_size() - code_size == size(ra_), "checking code size of inline cache node");
1198 }
1200 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1201 return OptoBreakpoint ? 11 : 12;
1202 }
1205 //=============================================================================
1206 uint size_exception_handler() {
1207 // NativeCall instruction size is the same as NativeJump.
1208 // exception handler starts out as jump and can be patched to
1209 // a call be deoptimization. (4932387)
1210 // Note that this value is also credited (in output.cpp) to
1211 // the size of the code section.
1212 return NativeJump::instruction_size;
1213 }
1215 // Emit exception handler code. Stuff framesize into a register
1216 // and call a VM stub routine.
1217 int emit_exception_handler(CodeBuffer& cbuf) {
1219 // Note that the code buffer's inst_mark is always relative to insts.
1220 // That's why we must use the macroassembler to generate a handler.
1221 MacroAssembler _masm(&cbuf);
1222 address base =
1223 __ start_a_stub(size_exception_handler());
1224 if (base == NULL) return 0; // CodeBuffer::expand failed
1225 int offset = __ offset();
1226 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->instructions_begin()));
1227 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1228 __ end_a_stub();
1229 return offset;
1230 }
1232 uint size_deopt_handler() {
1233 // NativeCall instruction size is the same as NativeJump.
1234 // exception handler starts out as jump and can be patched to
1235 // a call be deoptimization. (4932387)
1236 // Note that this value is also credited (in output.cpp) to
1237 // the size of the code section.
1238 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1239 }
1241 // Emit deopt handler code.
1242 int emit_deopt_handler(CodeBuffer& cbuf) {
1244 // Note that the code buffer's inst_mark is always relative to insts.
1245 // That's why we must use the macroassembler to generate a handler.
1246 MacroAssembler _masm(&cbuf);
1247 address base =
1248 __ start_a_stub(size_exception_handler());
1249 if (base == NULL) return 0; // CodeBuffer::expand failed
1250 int offset = __ offset();
1251 InternalAddress here(__ pc());
1252 __ pushptr(here.addr());
1254 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1255 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1256 __ end_a_stub();
1257 return offset;
1258 }
1261 static void emit_double_constant(CodeBuffer& cbuf, double x) {
1262 int mark = cbuf.insts()->mark_off();
1263 MacroAssembler _masm(&cbuf);
1264 address double_address = __ double_constant(x);
1265 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1266 emit_d32_reloc(cbuf,
1267 (int)double_address,
1268 internal_word_Relocation::spec(double_address),
1269 RELOC_DISP32);
1270 }
1272 static void emit_float_constant(CodeBuffer& cbuf, float x) {
1273 int mark = cbuf.insts()->mark_off();
1274 MacroAssembler _masm(&cbuf);
1275 address float_address = __ float_constant(x);
1276 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1277 emit_d32_reloc(cbuf,
1278 (int)float_address,
1279 internal_word_Relocation::spec(float_address),
1280 RELOC_DISP32);
1281 }
1284 const bool Matcher::match_rule_supported(int opcode) {
1285 if (!has_match_rule(opcode))
1286 return false;
1288 return true; // Per default match rules are supported.
1289 }
1291 int Matcher::regnum_to_fpu_offset(int regnum) {
1292 return regnum - 32; // The FP registers are in the second chunk
1293 }
1295 bool is_positive_zero_float(jfloat f) {
1296 return jint_cast(f) == jint_cast(0.0F);
1297 }
1299 bool is_positive_one_float(jfloat f) {
1300 return jint_cast(f) == jint_cast(1.0F);
1301 }
1303 bool is_positive_zero_double(jdouble d) {
1304 return jlong_cast(d) == jlong_cast(0.0);
1305 }
1307 bool is_positive_one_double(jdouble d) {
1308 return jlong_cast(d) == jlong_cast(1.0);
1309 }
1311 // This is UltraSparc specific, true just means we have fast l2f conversion
1312 const bool Matcher::convL2FSupported(void) {
1313 return true;
1314 }
1316 // Vector width in bytes
1317 const uint Matcher::vector_width_in_bytes(void) {
1318 return UseSSE >= 2 ? 8 : 0;
1319 }
1321 // Vector ideal reg
1322 const uint Matcher::vector_ideal_reg(void) {
1323 return Op_RegD;
1324 }
1326 // Is this branch offset short enough that a short branch can be used?
1327 //
1328 // NOTE: If the platform does not provide any short branch variants, then
1329 // this method should return false for offset 0.
1330 bool Matcher::is_short_branch_offset(int rule, int offset) {
1331 // the short version of jmpConUCF2 contains multiple branches,
1332 // making the reach slightly less
1333 if (rule == jmpConUCF2_rule)
1334 return (-126 <= offset && offset <= 125);
1335 return (-128 <= offset && offset <= 127);
1336 }
1338 const bool Matcher::isSimpleConstant64(jlong value) {
1339 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1340 return false;
1341 }
1343 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1344 const bool Matcher::init_array_count_is_in_bytes = false;
1346 // Threshold size for cleararray.
1347 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1349 // Should the Matcher clone shifts on addressing modes, expecting them to
1350 // be subsumed into complex addressing expressions or compute them into
1351 // registers? True for Intel but false for most RISCs
1352 const bool Matcher::clone_shift_expressions = true;
1354 // Is it better to copy float constants, or load them directly from memory?
1355 // Intel can load a float constant from a direct address, requiring no
1356 // extra registers. Most RISCs will have to materialize an address into a
1357 // register first, so they would do better to copy the constant from stack.
1358 const bool Matcher::rematerialize_float_constants = true;
1360 // If CPU can load and store mis-aligned doubles directly then no fixup is
1361 // needed. Else we split the double into 2 integer pieces and move it
1362 // piece-by-piece. Only happens when passing doubles into C code as the
1363 // Java calling convention forces doubles to be aligned.
1364 const bool Matcher::misaligned_doubles_ok = true;
1367 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1368 // Get the memory operand from the node
1369 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1370 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1371 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1372 uint opcnt = 1; // First operand
1373 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1374 while( idx >= skipped+num_edges ) {
1375 skipped += num_edges;
1376 opcnt++; // Bump operand count
1377 assert( opcnt < numopnds, "Accessing non-existent operand" );
1378 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1379 }
1381 MachOper *memory = node->_opnds[opcnt];
1382 MachOper *new_memory = NULL;
1383 switch (memory->opcode()) {
1384 case DIRECT:
1385 case INDOFFSET32X:
1386 // No transformation necessary.
1387 return;
1388 case INDIRECT:
1389 new_memory = new (C) indirect_win95_safeOper( );
1390 break;
1391 case INDOFFSET8:
1392 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1393 break;
1394 case INDOFFSET32:
1395 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1396 break;
1397 case INDINDEXOFFSET:
1398 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1399 break;
1400 case INDINDEXSCALE:
1401 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1402 break;
1403 case INDINDEXSCALEOFFSET:
1404 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1405 break;
1406 case LOAD_LONG_INDIRECT:
1407 case LOAD_LONG_INDOFFSET32:
1408 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1409 return;
1410 default:
1411 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1412 return;
1413 }
1414 node->_opnds[opcnt] = new_memory;
1415 }
1417 // Advertise here if the CPU requires explicit rounding operations
1418 // to implement the UseStrictFP mode.
1419 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1421 // Do floats take an entire double register or just half?
1422 const bool Matcher::float_in_double = true;
1423 // Do ints take an entire long register or just half?
1424 const bool Matcher::int_in_long = false;
1426 // Return whether or not this register is ever used as an argument. This
1427 // function is used on startup to build the trampoline stubs in generateOptoStub.
1428 // Registers not mentioned will be killed by the VM call in the trampoline, and
1429 // arguments in those registers not be available to the callee.
1430 bool Matcher::can_be_java_arg( int reg ) {
1431 if( reg == ECX_num || reg == EDX_num ) return true;
1432 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true;
1433 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1434 return false;
1435 }
1437 bool Matcher::is_spillable_arg( int reg ) {
1438 return can_be_java_arg(reg);
1439 }
1441 // Register for DIVI projection of divmodI
1442 RegMask Matcher::divI_proj_mask() {
1443 return EAX_REG_mask;
1444 }
1446 // Register for MODI projection of divmodI
1447 RegMask Matcher::modI_proj_mask() {
1448 return EDX_REG_mask;
1449 }
1451 // Register for DIVL projection of divmodL
1452 RegMask Matcher::divL_proj_mask() {
1453 ShouldNotReachHere();
1454 return RegMask();
1455 }
1457 // Register for MODL projection of divmodL
1458 RegMask Matcher::modL_proj_mask() {
1459 ShouldNotReachHere();
1460 return RegMask();
1461 }
1463 %}
1465 //----------ENCODING BLOCK-----------------------------------------------------
1466 // This block specifies the encoding classes used by the compiler to output
1467 // byte streams. Encoding classes generate functions which are called by
1468 // Machine Instruction Nodes in order to generate the bit encoding of the
1469 // instruction. Operands specify their base encoding interface with the
1470 // interface keyword. There are currently supported four interfaces,
1471 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1472 // operand to generate a function which returns its register number when
1473 // queried. CONST_INTER causes an operand to generate a function which
1474 // returns the value of the constant when queried. MEMORY_INTER causes an
1475 // operand to generate four functions which return the Base Register, the
1476 // Index Register, the Scale Value, and the Offset Value of the operand when
1477 // queried. COND_INTER causes an operand to generate six functions which
1478 // return the encoding code (ie - encoding bits for the instruction)
1479 // associated with each basic boolean condition for a conditional instruction.
1480 // Instructions specify two basic values for encoding. They use the
1481 // ins_encode keyword to specify their encoding class (which must be one of
1482 // the class names specified in the encoding block), and they use the
1483 // opcode keyword to specify, in order, their primary, secondary, and
1484 // tertiary opcode. Only the opcode sections which a particular instruction
1485 // needs for encoding need to be specified.
1486 encode %{
1487 // Build emit functions for each basic byte or larger field in the intel
1488 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1489 // code in the enc_class source block. Emit functions will live in the
1490 // main source block for now. In future, we can generalize this by
1491 // adding a syntax that specifies the sizes of fields in an order,
1492 // so that the adlc can build the emit functions automagically
1494 // Emit primary opcode
1495 enc_class OpcP %{
1496 emit_opcode(cbuf, $primary);
1497 %}
1499 // Emit secondary opcode
1500 enc_class OpcS %{
1501 emit_opcode(cbuf, $secondary);
1502 %}
1504 // Emit opcode directly
1505 enc_class Opcode(immI d8) %{
1506 emit_opcode(cbuf, $d8$$constant);
1507 %}
1509 enc_class SizePrefix %{
1510 emit_opcode(cbuf,0x66);
1511 %}
1513 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
1514 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1515 %}
1517 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many)
1518 emit_opcode(cbuf,$opcode$$constant);
1519 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1520 %}
1522 enc_class mov_r32_imm0( eRegI dst ) %{
1523 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1524 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1525 %}
1527 enc_class cdq_enc %{
1528 // Full implementation of Java idiv and irem; checks for
1529 // special case as described in JVM spec., p.243 & p.271.
1530 //
1531 // normal case special case
1532 //
1533 // input : rax,: dividend min_int
1534 // reg: divisor -1
1535 //
1536 // output: rax,: quotient (= rax, idiv reg) min_int
1537 // rdx: remainder (= rax, irem reg) 0
1538 //
1539 // Code sequnce:
1540 //
1541 // 81 F8 00 00 00 80 cmp rax,80000000h
1542 // 0F 85 0B 00 00 00 jne normal_case
1543 // 33 D2 xor rdx,edx
1544 // 83 F9 FF cmp rcx,0FFh
1545 // 0F 84 03 00 00 00 je done
1546 // normal_case:
1547 // 99 cdq
1548 // F7 F9 idiv rax,ecx
1549 // done:
1550 //
1551 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1552 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1553 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1554 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1555 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1556 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1557 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1558 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1559 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1560 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1561 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1562 // normal_case:
1563 emit_opcode(cbuf,0x99); // cdq
1564 // idiv (note: must be emitted by the user of this rule)
1565 // normal:
1566 %}
1568 // Dense encoding for older common ops
1569 enc_class Opc_plus(immI opcode, eRegI reg) %{
1570 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1571 %}
1574 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1575 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1576 // Check for 8-bit immediate, and set sign extend bit in opcode
1577 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1578 emit_opcode(cbuf, $primary | 0x02);
1579 }
1580 else { // If 32-bit immediate
1581 emit_opcode(cbuf, $primary);
1582 }
1583 %}
1585 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m
1586 // Emit primary opcode and set sign-extend bit
1587 // Check for 8-bit immediate, and set sign extend bit in opcode
1588 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1589 emit_opcode(cbuf, $primary | 0x02); }
1590 else { // If 32-bit immediate
1591 emit_opcode(cbuf, $primary);
1592 }
1593 // Emit r/m byte with secondary opcode, after primary opcode.
1594 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1595 %}
1597 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1598 // Check for 8-bit immediate, and set sign extend bit in opcode
1599 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1600 $$$emit8$imm$$constant;
1601 }
1602 else { // If 32-bit immediate
1603 // Output immediate
1604 $$$emit32$imm$$constant;
1605 }
1606 %}
1608 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1609 // Emit primary opcode and set sign-extend bit
1610 // Check for 8-bit immediate, and set sign extend bit in opcode
1611 int con = (int)$imm$$constant; // Throw away top bits
1612 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1613 // Emit r/m byte with secondary opcode, after primary opcode.
1614 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1615 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1616 else emit_d32(cbuf,con);
1617 %}
1619 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1620 // Emit primary opcode and set sign-extend bit
1621 // Check for 8-bit immediate, and set sign extend bit in opcode
1622 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1623 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1624 // Emit r/m byte with tertiary opcode, after primary opcode.
1625 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1626 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1627 else emit_d32(cbuf,con);
1628 %}
1630 enc_class Lbl (label labl) %{ // JMP, CALL
1631 Label *l = $labl$$label;
1632 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0);
1633 %}
1635 enc_class LblShort (label labl) %{ // JMP, CALL
1636 Label *l = $labl$$label;
1637 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0;
1638 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
1639 emit_d8(cbuf, disp);
1640 %}
1642 enc_class OpcSReg (eRegI dst) %{ // BSWAP
1643 emit_cc(cbuf, $secondary, $dst$$reg );
1644 %}
1646 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1647 int destlo = $dst$$reg;
1648 int desthi = HIGH_FROM_LOW(destlo);
1649 // bswap lo
1650 emit_opcode(cbuf, 0x0F);
1651 emit_cc(cbuf, 0xC8, destlo);
1652 // bswap hi
1653 emit_opcode(cbuf, 0x0F);
1654 emit_cc(cbuf, 0xC8, desthi);
1655 // xchg lo and hi
1656 emit_opcode(cbuf, 0x87);
1657 emit_rm(cbuf, 0x3, destlo, desthi);
1658 %}
1660 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1661 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1662 %}
1664 enc_class Jcc (cmpOp cop, label labl) %{ // JCC
1665 Label *l = $labl$$label;
1666 $$$emit8$primary;
1667 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1668 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0);
1669 %}
1671 enc_class JccShort (cmpOp cop, label labl) %{ // JCC
1672 Label *l = $labl$$label;
1673 emit_cc(cbuf, $primary, $cop$$cmpcode);
1674 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0;
1675 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
1676 emit_d8(cbuf, disp);
1677 %}
1679 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1680 $$$emit8$primary;
1681 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1682 %}
1684 enc_class enc_cmov_d(cmpOp cop, regD src ) %{ // CMOV
1685 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1686 emit_d8(cbuf, op >> 8 );
1687 emit_d8(cbuf, op & 255);
1688 %}
1690 // emulate a CMOV with a conditional branch around a MOV
1691 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1692 // Invert sense of branch from sense of CMOV
1693 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1694 emit_d8( cbuf, $brOffs$$constant );
1695 %}
1697 enc_class enc_PartialSubtypeCheck( ) %{
1698 Register Redi = as_Register(EDI_enc); // result register
1699 Register Reax = as_Register(EAX_enc); // super class
1700 Register Recx = as_Register(ECX_enc); // killed
1701 Register Resi = as_Register(ESI_enc); // sub class
1702 Label miss;
1704 MacroAssembler _masm(&cbuf);
1705 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1706 NULL, &miss,
1707 /*set_cond_codes:*/ true);
1708 if ($primary) {
1709 __ xorptr(Redi, Redi);
1710 }
1711 __ bind(miss);
1712 %}
1714 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1715 MacroAssembler masm(&cbuf);
1716 int start = masm.offset();
1717 if (UseSSE >= 2) {
1718 if (VerifyFPU) {
1719 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1720 }
1721 } else {
1722 // External c_calling_convention expects the FPU stack to be 'clean'.
1723 // Compiled code leaves it dirty. Do cleanup now.
1724 masm.empty_FPU_stack();
1725 }
1726 if (sizeof_FFree_Float_Stack_All == -1) {
1727 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1728 } else {
1729 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1730 }
1731 %}
1733 enc_class Verify_FPU_For_Leaf %{
1734 if( VerifyFPU ) {
1735 MacroAssembler masm(&cbuf);
1736 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1737 }
1738 %}
1740 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1741 // This is the instruction starting address for relocation info.
1742 cbuf.set_inst_mark();
1743 $$$emit8$primary;
1744 // CALL directly to the runtime
1745 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1746 runtime_call_Relocation::spec(), RELOC_IMM32 );
1748 if (UseSSE >= 2) {
1749 MacroAssembler _masm(&cbuf);
1750 BasicType rt = tf()->return_type();
1752 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1753 // A C runtime call where the return value is unused. In SSE2+
1754 // mode the result needs to be removed from the FPU stack. It's
1755 // likely that this function call could be removed by the
1756 // optimizer if the C function is a pure function.
1757 __ ffree(0);
1758 } else if (rt == T_FLOAT) {
1759 __ lea(rsp, Address(rsp, -4));
1760 __ fstp_s(Address(rsp, 0));
1761 __ movflt(xmm0, Address(rsp, 0));
1762 __ lea(rsp, Address(rsp, 4));
1763 } else if (rt == T_DOUBLE) {
1764 __ lea(rsp, Address(rsp, -8));
1765 __ fstp_d(Address(rsp, 0));
1766 __ movdbl(xmm0, Address(rsp, 0));
1767 __ lea(rsp, Address(rsp, 8));
1768 }
1769 }
1770 %}
1773 enc_class pre_call_FPU %{
1774 // If method sets FPU control word restore it here
1775 if( Compile::current()->in_24_bit_fp_mode() ) {
1776 MacroAssembler masm(&cbuf);
1777 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1778 }
1779 %}
1781 enc_class post_call_FPU %{
1782 // If method sets FPU control word do it here also
1783 if( Compile::current()->in_24_bit_fp_mode() ) {
1784 MacroAssembler masm(&cbuf);
1785 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1786 }
1787 %}
1789 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1790 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1791 // who we intended to call.
1792 cbuf.set_inst_mark();
1793 $$$emit8$primary;
1794 if ( !_method ) {
1795 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1796 runtime_call_Relocation::spec(), RELOC_IMM32 );
1797 } else if(_optimized_virtual) {
1798 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1799 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1800 } else {
1801 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1802 static_call_Relocation::spec(), RELOC_IMM32 );
1803 }
1804 if( _method ) { // Emit stub for static call
1805 emit_java_to_interp(cbuf);
1806 }
1807 %}
1809 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1810 // !!!!!
1811 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info
1812 // emit_call_dynamic_prologue( cbuf );
1813 cbuf.set_inst_mark();
1814 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1
1815 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32);
1816 address virtual_call_oop_addr = cbuf.inst_mark();
1817 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1818 // who we intended to call.
1819 cbuf.set_inst_mark();
1820 $$$emit8$primary;
1821 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1822 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 );
1823 %}
1825 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1826 int disp = in_bytes(methodOopDesc::from_compiled_offset());
1827 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1829 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())]
1830 cbuf.set_inst_mark();
1831 $$$emit8$primary;
1832 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1833 emit_d8(cbuf, disp); // Displacement
1835 %}
1837 enc_class Xor_Reg (eRegI dst) %{
1838 emit_opcode(cbuf, 0x33);
1839 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
1840 %}
1842 // Following encoding is no longer used, but may be restored if calling
1843 // convention changes significantly.
1844 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1845 //
1846 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1847 // // int ic_reg = Matcher::inline_cache_reg();
1848 // // int ic_encode = Matcher::_regEncode[ic_reg];
1849 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1850 // // int imo_encode = Matcher::_regEncode[imo_reg];
1851 //
1852 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1853 // // // so we load it immediately before the call
1854 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1855 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1856 //
1857 // // xor rbp,ebp
1858 // emit_opcode(cbuf, 0x33);
1859 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1860 //
1861 // // CALL to interpreter.
1862 // cbuf.set_inst_mark();
1863 // $$$emit8$primary;
1864 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.code_end()) - 4),
1865 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1866 // %}
1868 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1869 $$$emit8$primary;
1870 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1871 $$$emit8$shift$$constant;
1872 %}
1874 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate
1875 // Load immediate does not have a zero or sign extended version
1876 // for 8-bit immediates
1877 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1878 $$$emit32$src$$constant;
1879 %}
1881 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate
1882 // Load immediate does not have a zero or sign extended version
1883 // for 8-bit immediates
1884 emit_opcode(cbuf, $primary + $dst$$reg);
1885 $$$emit32$src$$constant;
1886 %}
1888 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1889 // Load immediate does not have a zero or sign extended version
1890 // for 8-bit immediates
1891 int dst_enc = $dst$$reg;
1892 int src_con = $src$$constant & 0x0FFFFFFFFL;
1893 if (src_con == 0) {
1894 // xor dst, dst
1895 emit_opcode(cbuf, 0x33);
1896 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1897 } else {
1898 emit_opcode(cbuf, $primary + dst_enc);
1899 emit_d32(cbuf, src_con);
1900 }
1901 %}
1903 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1904 // Load immediate does not have a zero or sign extended version
1905 // for 8-bit immediates
1906 int dst_enc = $dst$$reg + 2;
1907 int src_con = ((julong)($src$$constant)) >> 32;
1908 if (src_con == 0) {
1909 // xor dst, dst
1910 emit_opcode(cbuf, 0x33);
1911 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1912 } else {
1913 emit_opcode(cbuf, $primary + dst_enc);
1914 emit_d32(cbuf, src_con);
1915 }
1916 %}
1919 enc_class LdImmD (immD src) %{ // Load Immediate
1920 if( is_positive_zero_double($src$$constant)) {
1921 // FLDZ
1922 emit_opcode(cbuf,0xD9);
1923 emit_opcode(cbuf,0xEE);
1924 } else if( is_positive_one_double($src$$constant)) {
1925 // FLD1
1926 emit_opcode(cbuf,0xD9);
1927 emit_opcode(cbuf,0xE8);
1928 } else {
1929 emit_opcode(cbuf,0xDD);
1930 emit_rm(cbuf, 0x0, 0x0, 0x5);
1931 emit_double_constant(cbuf, $src$$constant);
1932 }
1933 %}
1936 enc_class LdImmF (immF src) %{ // Load Immediate
1937 if( is_positive_zero_float($src$$constant)) {
1938 emit_opcode(cbuf,0xD9);
1939 emit_opcode(cbuf,0xEE);
1940 } else if( is_positive_one_float($src$$constant)) {
1941 emit_opcode(cbuf,0xD9);
1942 emit_opcode(cbuf,0xE8);
1943 } else {
1944 $$$emit8$primary;
1945 // Load immediate does not have a zero or sign extended version
1946 // for 8-bit immediates
1947 // First load to TOS, then move to dst
1948 emit_rm(cbuf, 0x0, 0x0, 0x5);
1949 emit_float_constant(cbuf, $src$$constant);
1950 }
1951 %}
1953 enc_class LdImmX (regX dst, immXF con) %{ // Load Immediate
1954 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1955 emit_float_constant(cbuf, $con$$constant);
1956 %}
1958 enc_class LdImmXD (regXD dst, immXD con) %{ // Load Immediate
1959 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1960 emit_double_constant(cbuf, $con$$constant);
1961 %}
1963 enc_class load_conXD (regXD dst, immXD con) %{ // Load double constant
1964 // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con)
1965 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
1966 emit_opcode(cbuf, 0x0F);
1967 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
1968 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1969 emit_double_constant(cbuf, $con$$constant);
1970 %}
1972 enc_class Opc_MemImm_F(immF src) %{
1973 cbuf.set_inst_mark();
1974 $$$emit8$primary;
1975 emit_rm(cbuf, 0x0, $secondary, 0x5);
1976 emit_float_constant(cbuf, $src$$constant);
1977 %}
1980 enc_class MovI2X_reg(regX dst, eRegI src) %{
1981 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
1982 emit_opcode(cbuf, 0x0F );
1983 emit_opcode(cbuf, 0x6E );
1984 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1985 %}
1987 enc_class MovX2I_reg(eRegI dst, regX src) %{
1988 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
1989 emit_opcode(cbuf, 0x0F );
1990 emit_opcode(cbuf, 0x7E );
1991 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
1992 %}
1994 enc_class MovL2XD_reg(regXD dst, eRegL src, regXD tmp) %{
1995 { // MOVD $dst,$src.lo
1996 emit_opcode(cbuf,0x66);
1997 emit_opcode(cbuf,0x0F);
1998 emit_opcode(cbuf,0x6E);
1999 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2000 }
2001 { // MOVD $tmp,$src.hi
2002 emit_opcode(cbuf,0x66);
2003 emit_opcode(cbuf,0x0F);
2004 emit_opcode(cbuf,0x6E);
2005 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2006 }
2007 { // PUNPCKLDQ $dst,$tmp
2008 emit_opcode(cbuf,0x66);
2009 emit_opcode(cbuf,0x0F);
2010 emit_opcode(cbuf,0x62);
2011 emit_rm(cbuf, 0x3, $dst$$reg, $tmp$$reg);
2012 }
2013 %}
2015 enc_class MovXD2L_reg(eRegL dst, regXD src, regXD tmp) %{
2016 { // MOVD $dst.lo,$src
2017 emit_opcode(cbuf,0x66);
2018 emit_opcode(cbuf,0x0F);
2019 emit_opcode(cbuf,0x7E);
2020 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
2021 }
2022 { // PSHUFLW $tmp,$src,0x4E (01001110b)
2023 emit_opcode(cbuf,0xF2);
2024 emit_opcode(cbuf,0x0F);
2025 emit_opcode(cbuf,0x70);
2026 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2027 emit_d8(cbuf, 0x4E);
2028 }
2029 { // MOVD $dst.hi,$tmp
2030 emit_opcode(cbuf,0x66);
2031 emit_opcode(cbuf,0x0F);
2032 emit_opcode(cbuf,0x7E);
2033 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
2034 }
2035 %}
2038 // Encode a reg-reg copy. If it is useless, then empty encoding.
2039 enc_class enc_Copy( eRegI dst, eRegI src ) %{
2040 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2041 %}
2043 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{
2044 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2045 %}
2047 // Encode xmm reg-reg copy. If it is useless, then empty encoding.
2048 enc_class enc_CopyXD( RegXD dst, RegXD src ) %{
2049 encode_CopyXD( cbuf, $dst$$reg, $src$$reg );
2050 %}
2052 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
2053 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2054 %}
2056 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
2057 $$$emit8$primary;
2058 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2059 %}
2061 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2062 $$$emit8$secondary;
2063 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2064 %}
2066 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2067 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2068 %}
2070 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2071 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2072 %}
2074 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{
2075 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2076 %}
2078 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2079 // Output immediate
2080 $$$emit32$src$$constant;
2081 %}
2083 enc_class Con32F_as_bits(immF src) %{ // storeF_imm
2084 // Output Float immediate bits
2085 jfloat jf = $src$$constant;
2086 int jf_as_bits = jint_cast( jf );
2087 emit_d32(cbuf, jf_as_bits);
2088 %}
2090 enc_class Con32XF_as_bits(immXF src) %{ // storeX_imm
2091 // Output Float immediate bits
2092 jfloat jf = $src$$constant;
2093 int jf_as_bits = jint_cast( jf );
2094 emit_d32(cbuf, jf_as_bits);
2095 %}
2097 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2098 // Output immediate
2099 $$$emit16$src$$constant;
2100 %}
2102 enc_class Con_d32(immI src) %{
2103 emit_d32(cbuf,$src$$constant);
2104 %}
2106 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2107 // Output immediate memory reference
2108 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2109 emit_d32(cbuf, 0x00);
2110 %}
2112 enc_class lock_prefix( ) %{
2113 if( os::is_MP() )
2114 emit_opcode(cbuf,0xF0); // [Lock]
2115 %}
2117 // Cmp-xchg long value.
2118 // Note: we need to swap rbx, and rcx before and after the
2119 // cmpxchg8 instruction because the instruction uses
2120 // rcx as the high order word of the new value to store but
2121 // our register encoding uses rbx,.
2122 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2124 // XCHG rbx,ecx
2125 emit_opcode(cbuf,0x87);
2126 emit_opcode(cbuf,0xD9);
2127 // [Lock]
2128 if( os::is_MP() )
2129 emit_opcode(cbuf,0xF0);
2130 // CMPXCHG8 [Eptr]
2131 emit_opcode(cbuf,0x0F);
2132 emit_opcode(cbuf,0xC7);
2133 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2134 // XCHG rbx,ecx
2135 emit_opcode(cbuf,0x87);
2136 emit_opcode(cbuf,0xD9);
2137 %}
2139 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2140 // [Lock]
2141 if( os::is_MP() )
2142 emit_opcode(cbuf,0xF0);
2144 // CMPXCHG [Eptr]
2145 emit_opcode(cbuf,0x0F);
2146 emit_opcode(cbuf,0xB1);
2147 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2148 %}
2150 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2151 int res_encoding = $res$$reg;
2153 // MOV res,0
2154 emit_opcode( cbuf, 0xB8 + res_encoding);
2155 emit_d32( cbuf, 0 );
2156 // JNE,s fail
2157 emit_opcode(cbuf,0x75);
2158 emit_d8(cbuf, 5 );
2159 // MOV res,1
2160 emit_opcode( cbuf, 0xB8 + res_encoding);
2161 emit_d32( cbuf, 1 );
2162 // fail:
2163 %}
2165 enc_class set_instruction_start( ) %{
2166 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2167 %}
2169 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem
2170 int reg_encoding = $ereg$$reg;
2171 int base = $mem$$base;
2172 int index = $mem$$index;
2173 int scale = $mem$$scale;
2174 int displace = $mem$$disp;
2175 bool disp_is_oop = $mem->disp_is_oop();
2176 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2177 %}
2179 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2180 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2181 int base = $mem$$base;
2182 int index = $mem$$index;
2183 int scale = $mem$$scale;
2184 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2185 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" );
2186 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/);
2187 %}
2189 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2190 int r1, r2;
2191 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2192 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2193 emit_opcode(cbuf,0x0F);
2194 emit_opcode(cbuf,$tertiary);
2195 emit_rm(cbuf, 0x3, r1, r2);
2196 emit_d8(cbuf,$cnt$$constant);
2197 emit_d8(cbuf,$primary);
2198 emit_rm(cbuf, 0x3, $secondary, r1);
2199 emit_d8(cbuf,$cnt$$constant);
2200 %}
2202 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2203 emit_opcode( cbuf, 0x8B ); // Move
2204 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2205 emit_d8(cbuf,$primary);
2206 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2207 emit_d8(cbuf,$cnt$$constant-32);
2208 emit_d8(cbuf,$primary);
2209 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2210 emit_d8(cbuf,31);
2211 %}
2213 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2214 int r1, r2;
2215 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2216 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2218 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2219 emit_rm(cbuf, 0x3, r1, r2);
2220 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2221 emit_opcode(cbuf,$primary);
2222 emit_rm(cbuf, 0x3, $secondary, r1);
2223 emit_d8(cbuf,$cnt$$constant-32);
2224 }
2225 emit_opcode(cbuf,0x33); // XOR r2,r2
2226 emit_rm(cbuf, 0x3, r2, r2);
2227 %}
2229 // Clone of RegMem but accepts an extra parameter to access each
2230 // half of a double in memory; it never needs relocation info.
2231 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{
2232 emit_opcode(cbuf,$opcode$$constant);
2233 int reg_encoding = $rm_reg$$reg;
2234 int base = $mem$$base;
2235 int index = $mem$$index;
2236 int scale = $mem$$scale;
2237 int displace = $mem$$disp + $disp_for_half$$constant;
2238 bool disp_is_oop = false;
2239 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2240 %}
2242 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2243 //
2244 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2245 // and it never needs relocation information.
2246 // Frequently used to move data between FPU's Stack Top and memory.
2247 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2248 int rm_byte_opcode = $rm_opcode$$constant;
2249 int base = $mem$$base;
2250 int index = $mem$$index;
2251 int scale = $mem$$scale;
2252 int displace = $mem$$disp;
2253 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" );
2254 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false);
2255 %}
2257 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2258 int rm_byte_opcode = $rm_opcode$$constant;
2259 int base = $mem$$base;
2260 int index = $mem$$index;
2261 int scale = $mem$$scale;
2262 int displace = $mem$$disp;
2263 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2264 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
2265 %}
2267 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea
2268 int reg_encoding = $dst$$reg;
2269 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2270 int index = 0x04; // 0x04 indicates no index
2271 int scale = 0x00; // 0x00 indicates no scale
2272 int displace = $src1$$constant; // 0x00 indicates no displacement
2273 bool disp_is_oop = false;
2274 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2275 %}
2277 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN
2278 // Compare dst,src
2279 emit_opcode(cbuf,0x3B);
2280 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2281 // jmp dst < src around move
2282 emit_opcode(cbuf,0x7C);
2283 emit_d8(cbuf,2);
2284 // move dst,src
2285 emit_opcode(cbuf,0x8B);
2286 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2287 %}
2289 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX
2290 // Compare dst,src
2291 emit_opcode(cbuf,0x3B);
2292 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2293 // jmp dst > src around move
2294 emit_opcode(cbuf,0x7F);
2295 emit_d8(cbuf,2);
2296 // move dst,src
2297 emit_opcode(cbuf,0x8B);
2298 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2299 %}
2301 enc_class enc_FP_store(memory mem, regD src) %{
2302 // If src is FPR1, we can just FST to store it.
2303 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2304 int reg_encoding = 0x2; // Just store
2305 int base = $mem$$base;
2306 int index = $mem$$index;
2307 int scale = $mem$$scale;
2308 int displace = $mem$$disp;
2309 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2310 if( $src$$reg != FPR1L_enc ) {
2311 reg_encoding = 0x3; // Store & pop
2312 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2313 emit_d8( cbuf, 0xC0-1+$src$$reg );
2314 }
2315 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2316 emit_opcode(cbuf,$primary);
2317 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2318 %}
2320 enc_class neg_reg(eRegI dst) %{
2321 // NEG $dst
2322 emit_opcode(cbuf,0xF7);
2323 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2324 %}
2326 enc_class setLT_reg(eCXRegI dst) %{
2327 // SETLT $dst
2328 emit_opcode(cbuf,0x0F);
2329 emit_opcode(cbuf,0x9C);
2330 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2331 %}
2333 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2334 int tmpReg = $tmp$$reg;
2336 // SUB $p,$q
2337 emit_opcode(cbuf,0x2B);
2338 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2339 // SBB $tmp,$tmp
2340 emit_opcode(cbuf,0x1B);
2341 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2342 // AND $tmp,$y
2343 emit_opcode(cbuf,0x23);
2344 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2345 // ADD $p,$tmp
2346 emit_opcode(cbuf,0x03);
2347 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2348 %}
2350 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
2351 int tmpReg = $tmp$$reg;
2353 // SUB $p,$q
2354 emit_opcode(cbuf,0x2B);
2355 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2356 // SBB $tmp,$tmp
2357 emit_opcode(cbuf,0x1B);
2358 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2359 // AND $tmp,$y
2360 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2361 emit_opcode(cbuf,0x23);
2362 int reg_encoding = tmpReg;
2363 int base = $mem$$base;
2364 int index = $mem$$index;
2365 int scale = $mem$$scale;
2366 int displace = $mem$$disp;
2367 bool disp_is_oop = $mem->disp_is_oop();
2368 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2369 // ADD $p,$tmp
2370 emit_opcode(cbuf,0x03);
2371 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2372 %}
2374 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2375 // TEST shift,32
2376 emit_opcode(cbuf,0xF7);
2377 emit_rm(cbuf, 0x3, 0, ECX_enc);
2378 emit_d32(cbuf,0x20);
2379 // JEQ,s small
2380 emit_opcode(cbuf, 0x74);
2381 emit_d8(cbuf, 0x04);
2382 // MOV $dst.hi,$dst.lo
2383 emit_opcode( cbuf, 0x8B );
2384 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2385 // CLR $dst.lo
2386 emit_opcode(cbuf, 0x33);
2387 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2388 // small:
2389 // SHLD $dst.hi,$dst.lo,$shift
2390 emit_opcode(cbuf,0x0F);
2391 emit_opcode(cbuf,0xA5);
2392 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2393 // SHL $dst.lo,$shift"
2394 emit_opcode(cbuf,0xD3);
2395 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2396 %}
2398 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2399 // TEST shift,32
2400 emit_opcode(cbuf,0xF7);
2401 emit_rm(cbuf, 0x3, 0, ECX_enc);
2402 emit_d32(cbuf,0x20);
2403 // JEQ,s small
2404 emit_opcode(cbuf, 0x74);
2405 emit_d8(cbuf, 0x04);
2406 // MOV $dst.lo,$dst.hi
2407 emit_opcode( cbuf, 0x8B );
2408 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2409 // CLR $dst.hi
2410 emit_opcode(cbuf, 0x33);
2411 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2412 // small:
2413 // SHRD $dst.lo,$dst.hi,$shift
2414 emit_opcode(cbuf,0x0F);
2415 emit_opcode(cbuf,0xAD);
2416 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2417 // SHR $dst.hi,$shift"
2418 emit_opcode(cbuf,0xD3);
2419 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2420 %}
2422 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2423 // TEST shift,32
2424 emit_opcode(cbuf,0xF7);
2425 emit_rm(cbuf, 0x3, 0, ECX_enc);
2426 emit_d32(cbuf,0x20);
2427 // JEQ,s small
2428 emit_opcode(cbuf, 0x74);
2429 emit_d8(cbuf, 0x05);
2430 // MOV $dst.lo,$dst.hi
2431 emit_opcode( cbuf, 0x8B );
2432 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2433 // SAR $dst.hi,31
2434 emit_opcode(cbuf, 0xC1);
2435 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2436 emit_d8(cbuf, 0x1F );
2437 // small:
2438 // SHRD $dst.lo,$dst.hi,$shift
2439 emit_opcode(cbuf,0x0F);
2440 emit_opcode(cbuf,0xAD);
2441 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2442 // SAR $dst.hi,$shift"
2443 emit_opcode(cbuf,0xD3);
2444 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2445 %}
2448 // ----------------- Encodings for floating point unit -----------------
2449 // May leave result in FPU-TOS or FPU reg depending on opcodes
2450 enc_class OpcReg_F (regF src) %{ // FMUL, FDIV
2451 $$$emit8$primary;
2452 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2453 %}
2455 // Pop argument in FPR0 with FSTP ST(0)
2456 enc_class PopFPU() %{
2457 emit_opcode( cbuf, 0xDD );
2458 emit_d8( cbuf, 0xD8 );
2459 %}
2461 // !!!!! equivalent to Pop_Reg_F
2462 enc_class Pop_Reg_D( regD dst ) %{
2463 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2464 emit_d8( cbuf, 0xD8+$dst$$reg );
2465 %}
2467 enc_class Push_Reg_D( regD dst ) %{
2468 emit_opcode( cbuf, 0xD9 );
2469 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2470 %}
2472 enc_class strictfp_bias1( regD dst ) %{
2473 emit_opcode( cbuf, 0xDB ); // FLD m80real
2474 emit_opcode( cbuf, 0x2D );
2475 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2476 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2477 emit_opcode( cbuf, 0xC8+$dst$$reg );
2478 %}
2480 enc_class strictfp_bias2( regD dst ) %{
2481 emit_opcode( cbuf, 0xDB ); // FLD m80real
2482 emit_opcode( cbuf, 0x2D );
2483 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2484 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2485 emit_opcode( cbuf, 0xC8+$dst$$reg );
2486 %}
2488 // Special case for moving an integer register to a stack slot.
2489 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2490 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2491 %}
2493 // Special case for moving a register to a stack slot.
2494 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2495 // Opcode already emitted
2496 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2497 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2498 emit_d32(cbuf, $dst$$disp); // Displacement
2499 %}
2501 // Push the integer in stackSlot 'src' onto FP-stack
2502 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2503 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2504 %}
2506 // Push the float in stackSlot 'src' onto FP-stack
2507 enc_class Push_Mem_F( memory src ) %{ // FLD_S [ESP+src]
2508 store_to_stackslot( cbuf, 0xD9, 0x00, $src$$disp );
2509 %}
2511 // Push the double in stackSlot 'src' onto FP-stack
2512 enc_class Push_Mem_D( memory src ) %{ // FLD_D [ESP+src]
2513 store_to_stackslot( cbuf, 0xDD, 0x00, $src$$disp );
2514 %}
2516 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2517 enc_class Pop_Mem_F( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2518 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2519 %}
2521 // Same as Pop_Mem_F except for opcode
2522 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2523 enc_class Pop_Mem_D( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2524 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2525 %}
2527 enc_class Pop_Reg_F( regF dst ) %{
2528 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2529 emit_d8( cbuf, 0xD8+$dst$$reg );
2530 %}
2532 enc_class Push_Reg_F( regF dst ) %{
2533 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2534 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2535 %}
2537 // Push FPU's float to a stack-slot, and pop FPU-stack
2538 enc_class Pop_Mem_Reg_F( stackSlotF dst, regF src ) %{
2539 int pop = 0x02;
2540 if ($src$$reg != FPR1L_enc) {
2541 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2542 emit_d8( cbuf, 0xC0-1+$src$$reg );
2543 pop = 0x03;
2544 }
2545 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2546 %}
2548 // Push FPU's double to a stack-slot, and pop FPU-stack
2549 enc_class Pop_Mem_Reg_D( stackSlotD dst, regD src ) %{
2550 int pop = 0x02;
2551 if ($src$$reg != FPR1L_enc) {
2552 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2553 emit_d8( cbuf, 0xC0-1+$src$$reg );
2554 pop = 0x03;
2555 }
2556 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2557 %}
2559 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2560 enc_class Pop_Reg_Reg_D( regD dst, regF src ) %{
2561 int pop = 0xD0 - 1; // -1 since we skip FLD
2562 if ($src$$reg != FPR1L_enc) {
2563 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2564 emit_d8( cbuf, 0xC0-1+$src$$reg );
2565 pop = 0xD8;
2566 }
2567 emit_opcode( cbuf, 0xDD );
2568 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2569 %}
2572 enc_class Mul_Add_F( regF dst, regF src, regF src1, regF src2 ) %{
2573 MacroAssembler masm(&cbuf);
2574 masm.fld_s( $src1$$reg-1); // nothing at TOS, load TOS from src1.reg
2575 masm.fmul( $src2$$reg+0); // value at TOS
2576 masm.fadd( $src$$reg+0); // value at TOS
2577 masm.fstp_d( $dst$$reg+0); // value at TOS, popped off after store
2578 %}
2581 enc_class Push_Reg_Mod_D( regD dst, regD src) %{
2582 // load dst in FPR0
2583 emit_opcode( cbuf, 0xD9 );
2584 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2585 if ($src$$reg != FPR1L_enc) {
2586 // fincstp
2587 emit_opcode (cbuf, 0xD9);
2588 emit_opcode (cbuf, 0xF7);
2589 // swap src with FPR1:
2590 // FXCH FPR1 with src
2591 emit_opcode(cbuf, 0xD9);
2592 emit_d8(cbuf, 0xC8-1+$src$$reg );
2593 // fdecstp
2594 emit_opcode (cbuf, 0xD9);
2595 emit_opcode (cbuf, 0xF6);
2596 }
2597 %}
2599 enc_class Push_ModD_encoding( regXD src0, regXD src1) %{
2600 // Allocate a word
2601 emit_opcode(cbuf,0x83); // SUB ESP,8
2602 emit_opcode(cbuf,0xEC);
2603 emit_d8(cbuf,0x08);
2605 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src1
2606 emit_opcode (cbuf, 0x0F );
2607 emit_opcode (cbuf, 0x11 );
2608 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2610 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2611 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2613 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src0
2614 emit_opcode (cbuf, 0x0F );
2615 emit_opcode (cbuf, 0x11 );
2616 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2618 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2619 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2621 %}
2623 enc_class Push_ModX_encoding( regX src0, regX src1) %{
2624 // Allocate a word
2625 emit_opcode(cbuf,0x83); // SUB ESP,4
2626 emit_opcode(cbuf,0xEC);
2627 emit_d8(cbuf,0x04);
2629 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src1
2630 emit_opcode (cbuf, 0x0F );
2631 emit_opcode (cbuf, 0x11 );
2632 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2634 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2635 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2637 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src0
2638 emit_opcode (cbuf, 0x0F );
2639 emit_opcode (cbuf, 0x11 );
2640 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2642 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2643 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2645 %}
2647 enc_class Push_ResultXD(regXD dst) %{
2648 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [ESP]
2650 // UseXmmLoadAndClearUpper ? movsd dst,[esp] : movlpd dst,[esp]
2651 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
2652 emit_opcode (cbuf, 0x0F );
2653 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
2654 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2656 emit_opcode(cbuf,0x83); // ADD ESP,8
2657 emit_opcode(cbuf,0xC4);
2658 emit_d8(cbuf,0x08);
2659 %}
2661 enc_class Push_ResultX(regX dst, immI d8) %{
2662 store_to_stackslot( cbuf, 0xD9, 0x03, 0 ); //FSTP_S [ESP]
2664 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
2665 emit_opcode (cbuf, 0x0F );
2666 emit_opcode (cbuf, 0x10 );
2667 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2669 emit_opcode(cbuf,0x83); // ADD ESP,d8 (4 or 8)
2670 emit_opcode(cbuf,0xC4);
2671 emit_d8(cbuf,$d8$$constant);
2672 %}
2674 enc_class Push_SrcXD(regXD src) %{
2675 // Allocate a word
2676 emit_opcode(cbuf,0x83); // SUB ESP,8
2677 emit_opcode(cbuf,0xEC);
2678 emit_d8(cbuf,0x08);
2680 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
2681 emit_opcode (cbuf, 0x0F );
2682 emit_opcode (cbuf, 0x11 );
2683 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
2685 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2686 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2687 %}
2689 enc_class push_stack_temp_qword() %{
2690 emit_opcode(cbuf,0x83); // SUB ESP,8
2691 emit_opcode(cbuf,0xEC);
2692 emit_d8 (cbuf,0x08);
2693 %}
2695 enc_class pop_stack_temp_qword() %{
2696 emit_opcode(cbuf,0x83); // ADD ESP,8
2697 emit_opcode(cbuf,0xC4);
2698 emit_d8 (cbuf,0x08);
2699 %}
2701 enc_class push_xmm_to_fpr1( regXD xmm_src ) %{
2702 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], xmm_src
2703 emit_opcode (cbuf, 0x0F );
2704 emit_opcode (cbuf, 0x11 );
2705 encode_RegMem(cbuf, $xmm_src$$reg, ESP_enc, 0x4, 0, 0, false);
2707 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2708 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2709 %}
2711 // Compute X^Y using Intel's fast hardware instructions, if possible.
2712 // Otherwise return a NaN.
2713 enc_class pow_exp_core_encoding %{
2714 // FPR1 holds Y*ln2(X). Compute FPR1 = 2^(Y*ln2(X))
2715 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xC0); // fdup = fld st(0) Q Q
2716 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xFC); // frndint int(Q) Q
2717 emit_opcode(cbuf,0xDC); emit_opcode(cbuf,0xE9); // fsub st(1) -= st(0); int(Q) frac(Q)
2718 emit_opcode(cbuf,0xDB); // FISTP [ESP] frac(Q)
2719 emit_opcode(cbuf,0x1C);
2720 emit_d8(cbuf,0x24);
2721 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xF0); // f2xm1 2^frac(Q)-1
2722 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xE8); // fld1 1 2^frac(Q)-1
2723 emit_opcode(cbuf,0xDE); emit_opcode(cbuf,0xC1); // faddp 2^frac(Q)
2724 emit_opcode(cbuf,0x8B); // mov rax,[esp+0]=int(Q)
2725 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 0, false);
2726 emit_opcode(cbuf,0xC7); // mov rcx,0xFFFFF800 - overflow mask
2727 emit_rm(cbuf, 0x3, 0x0, ECX_enc);
2728 emit_d32(cbuf,0xFFFFF800);
2729 emit_opcode(cbuf,0x81); // add rax,1023 - the double exponent bias
2730 emit_rm(cbuf, 0x3, 0x0, EAX_enc);
2731 emit_d32(cbuf,1023);
2732 emit_opcode(cbuf,0x8B); // mov rbx,eax
2733 emit_rm(cbuf, 0x3, EBX_enc, EAX_enc);
2734 emit_opcode(cbuf,0xC1); // shl rax,20 - Slide to exponent position
2735 emit_rm(cbuf,0x3,0x4,EAX_enc);
2736 emit_d8(cbuf,20);
2737 emit_opcode(cbuf,0x85); // test rbx,ecx - check for overflow
2738 emit_rm(cbuf, 0x3, EBX_enc, ECX_enc);
2739 emit_opcode(cbuf,0x0F); emit_opcode(cbuf,0x45); // CMOVne rax,ecx - overflow; stuff NAN into EAX
2740 emit_rm(cbuf, 0x3, EAX_enc, ECX_enc);
2741 emit_opcode(cbuf,0x89); // mov [esp+4],eax - Store as part of double word
2742 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 4, false);
2743 emit_opcode(cbuf,0xC7); // mov [esp+0],0 - [ESP] = (double)(1<<int(Q)) = 2^int(Q)
2744 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2745 emit_d32(cbuf,0);
2746 emit_opcode(cbuf,0xDC); // fmul dword st(0),[esp+0]; FPR1 = 2^int(Q)*2^frac(Q) = 2^Q
2747 encode_RegMem(cbuf, 0x1, ESP_enc, 0x4, 0, 0, false);
2748 %}
2750 // enc_class Pop_Reg_Mod_D( regD dst, regD src)
2751 // was replaced by Push_Result_Mod_D followed by Pop_Reg_X() or Pop_Mem_X()
2753 enc_class Push_Result_Mod_D( regD src) %{
2754 if ($src$$reg != FPR1L_enc) {
2755 // fincstp
2756 emit_opcode (cbuf, 0xD9);
2757 emit_opcode (cbuf, 0xF7);
2758 // FXCH FPR1 with src
2759 emit_opcode(cbuf, 0xD9);
2760 emit_d8(cbuf, 0xC8-1+$src$$reg );
2761 // fdecstp
2762 emit_opcode (cbuf, 0xD9);
2763 emit_opcode (cbuf, 0xF6);
2764 }
2765 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2766 // // FSTP FPR$dst$$reg
2767 // emit_opcode( cbuf, 0xDD );
2768 // emit_d8( cbuf, 0xD8+$dst$$reg );
2769 %}
2771 enc_class fnstsw_sahf_skip_parity() %{
2772 // fnstsw ax
2773 emit_opcode( cbuf, 0xDF );
2774 emit_opcode( cbuf, 0xE0 );
2775 // sahf
2776 emit_opcode( cbuf, 0x9E );
2777 // jnp ::skip
2778 emit_opcode( cbuf, 0x7B );
2779 emit_opcode( cbuf, 0x05 );
2780 %}
2782 enc_class emitModD() %{
2783 // fprem must be iterative
2784 // :: loop
2785 // fprem
2786 emit_opcode( cbuf, 0xD9 );
2787 emit_opcode( cbuf, 0xF8 );
2788 // wait
2789 emit_opcode( cbuf, 0x9b );
2790 // fnstsw ax
2791 emit_opcode( cbuf, 0xDF );
2792 emit_opcode( cbuf, 0xE0 );
2793 // sahf
2794 emit_opcode( cbuf, 0x9E );
2795 // jp ::loop
2796 emit_opcode( cbuf, 0x0F );
2797 emit_opcode( cbuf, 0x8A );
2798 emit_opcode( cbuf, 0xF4 );
2799 emit_opcode( cbuf, 0xFF );
2800 emit_opcode( cbuf, 0xFF );
2801 emit_opcode( cbuf, 0xFF );
2802 %}
2804 enc_class fpu_flags() %{
2805 // fnstsw_ax
2806 emit_opcode( cbuf, 0xDF);
2807 emit_opcode( cbuf, 0xE0);
2808 // test ax,0x0400
2809 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2810 emit_opcode( cbuf, 0xA9 );
2811 emit_d16 ( cbuf, 0x0400 );
2812 // // // This sequence works, but stalls for 12-16 cycles on PPro
2813 // // test rax,0x0400
2814 // emit_opcode( cbuf, 0xA9 );
2815 // emit_d32 ( cbuf, 0x00000400 );
2816 //
2817 // jz exit (no unordered comparison)
2818 emit_opcode( cbuf, 0x74 );
2819 emit_d8 ( cbuf, 0x02 );
2820 // mov ah,1 - treat as LT case (set carry flag)
2821 emit_opcode( cbuf, 0xB4 );
2822 emit_d8 ( cbuf, 0x01 );
2823 // sahf
2824 emit_opcode( cbuf, 0x9E);
2825 %}
2827 enc_class cmpF_P6_fixup() %{
2828 // Fixup the integer flags in case comparison involved a NaN
2829 //
2830 // JNP exit (no unordered comparison, P-flag is set by NaN)
2831 emit_opcode( cbuf, 0x7B );
2832 emit_d8 ( cbuf, 0x03 );
2833 // MOV AH,1 - treat as LT case (set carry flag)
2834 emit_opcode( cbuf, 0xB4 );
2835 emit_d8 ( cbuf, 0x01 );
2836 // SAHF
2837 emit_opcode( cbuf, 0x9E);
2838 // NOP // target for branch to avoid branch to branch
2839 emit_opcode( cbuf, 0x90);
2840 %}
2842 // fnstsw_ax();
2843 // sahf();
2844 // movl(dst, nan_result);
2845 // jcc(Assembler::parity, exit);
2846 // movl(dst, less_result);
2847 // jcc(Assembler::below, exit);
2848 // movl(dst, equal_result);
2849 // jcc(Assembler::equal, exit);
2850 // movl(dst, greater_result);
2852 // less_result = 1;
2853 // greater_result = -1;
2854 // equal_result = 0;
2855 // nan_result = -1;
2857 enc_class CmpF_Result(eRegI dst) %{
2858 // fnstsw_ax();
2859 emit_opcode( cbuf, 0xDF);
2860 emit_opcode( cbuf, 0xE0);
2861 // sahf
2862 emit_opcode( cbuf, 0x9E);
2863 // movl(dst, nan_result);
2864 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2865 emit_d32( cbuf, -1 );
2866 // jcc(Assembler::parity, exit);
2867 emit_opcode( cbuf, 0x7A );
2868 emit_d8 ( cbuf, 0x13 );
2869 // movl(dst, less_result);
2870 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2871 emit_d32( cbuf, -1 );
2872 // jcc(Assembler::below, exit);
2873 emit_opcode( cbuf, 0x72 );
2874 emit_d8 ( cbuf, 0x0C );
2875 // movl(dst, equal_result);
2876 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2877 emit_d32( cbuf, 0 );
2878 // jcc(Assembler::equal, exit);
2879 emit_opcode( cbuf, 0x74 );
2880 emit_d8 ( cbuf, 0x05 );
2881 // movl(dst, greater_result);
2882 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2883 emit_d32( cbuf, 1 );
2884 %}
2887 // XMM version of CmpF_Result. Because the XMM compare
2888 // instructions set the EFLAGS directly. It becomes simpler than
2889 // the float version above.
2890 enc_class CmpX_Result(eRegI dst) %{
2891 MacroAssembler _masm(&cbuf);
2892 Label nan, inc, done;
2894 __ jccb(Assembler::parity, nan);
2895 __ jccb(Assembler::equal, done);
2896 __ jccb(Assembler::above, inc);
2897 __ bind(nan);
2898 __ decrement(as_Register($dst$$reg)); // NO L qqq
2899 __ jmpb(done);
2900 __ bind(inc);
2901 __ increment(as_Register($dst$$reg)); // NO L qqq
2902 __ bind(done);
2903 %}
2905 // Compare the longs and set flags
2906 // BROKEN! Do Not use as-is
2907 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2908 // CMP $src1.hi,$src2.hi
2909 emit_opcode( cbuf, 0x3B );
2910 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2911 // JNE,s done
2912 emit_opcode(cbuf,0x75);
2913 emit_d8(cbuf, 2 );
2914 // CMP $src1.lo,$src2.lo
2915 emit_opcode( cbuf, 0x3B );
2916 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2917 // done:
2918 %}
2920 enc_class convert_int_long( regL dst, eRegI src ) %{
2921 // mov $dst.lo,$src
2922 int dst_encoding = $dst$$reg;
2923 int src_encoding = $src$$reg;
2924 encode_Copy( cbuf, dst_encoding , src_encoding );
2925 // mov $dst.hi,$src
2926 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2927 // sar $dst.hi,31
2928 emit_opcode( cbuf, 0xC1 );
2929 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2930 emit_d8(cbuf, 0x1F );
2931 %}
2933 enc_class convert_long_double( eRegL src ) %{
2934 // push $src.hi
2935 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2936 // push $src.lo
2937 emit_opcode(cbuf, 0x50+$src$$reg );
2938 // fild 64-bits at [SP]
2939 emit_opcode(cbuf,0xdf);
2940 emit_d8(cbuf, 0x6C);
2941 emit_d8(cbuf, 0x24);
2942 emit_d8(cbuf, 0x00);
2943 // pop stack
2944 emit_opcode(cbuf, 0x83); // add SP, #8
2945 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2946 emit_d8(cbuf, 0x8);
2947 %}
2949 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2950 // IMUL EDX:EAX,$src1
2951 emit_opcode( cbuf, 0xF7 );
2952 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2953 // SAR EDX,$cnt-32
2954 int shift_count = ((int)$cnt$$constant) - 32;
2955 if (shift_count > 0) {
2956 emit_opcode(cbuf, 0xC1);
2957 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2958 emit_d8(cbuf, shift_count);
2959 }
2960 %}
2962 // this version doesn't have add sp, 8
2963 enc_class convert_long_double2( eRegL src ) %{
2964 // push $src.hi
2965 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2966 // push $src.lo
2967 emit_opcode(cbuf, 0x50+$src$$reg );
2968 // fild 64-bits at [SP]
2969 emit_opcode(cbuf,0xdf);
2970 emit_d8(cbuf, 0x6C);
2971 emit_d8(cbuf, 0x24);
2972 emit_d8(cbuf, 0x00);
2973 %}
2975 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2976 // Basic idea: long = (long)int * (long)int
2977 // IMUL EDX:EAX, src
2978 emit_opcode( cbuf, 0xF7 );
2979 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2980 %}
2982 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2983 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2984 // MUL EDX:EAX, src
2985 emit_opcode( cbuf, 0xF7 );
2986 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2987 %}
2989 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{
2990 // Basic idea: lo(result) = lo(x_lo * y_lo)
2991 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2992 // MOV $tmp,$src.lo
2993 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2994 // IMUL $tmp,EDX
2995 emit_opcode( cbuf, 0x0F );
2996 emit_opcode( cbuf, 0xAF );
2997 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2998 // MOV EDX,$src.hi
2999 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
3000 // IMUL EDX,EAX
3001 emit_opcode( cbuf, 0x0F );
3002 emit_opcode( cbuf, 0xAF );
3003 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
3004 // ADD $tmp,EDX
3005 emit_opcode( cbuf, 0x03 );
3006 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3007 // MUL EDX:EAX,$src.lo
3008 emit_opcode( cbuf, 0xF7 );
3009 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
3010 // ADD EDX,ESI
3011 emit_opcode( cbuf, 0x03 );
3012 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
3013 %}
3015 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{
3016 // Basic idea: lo(result) = lo(src * y_lo)
3017 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
3018 // IMUL $tmp,EDX,$src
3019 emit_opcode( cbuf, 0x6B );
3020 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3021 emit_d8( cbuf, (int)$src$$constant );
3022 // MOV EDX,$src
3023 emit_opcode(cbuf, 0xB8 + EDX_enc);
3024 emit_d32( cbuf, (int)$src$$constant );
3025 // MUL EDX:EAX,EDX
3026 emit_opcode( cbuf, 0xF7 );
3027 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
3028 // ADD EDX,ESI
3029 emit_opcode( cbuf, 0x03 );
3030 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
3031 %}
3033 enc_class long_div( eRegL src1, eRegL src2 ) %{
3034 // PUSH src1.hi
3035 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3036 // PUSH src1.lo
3037 emit_opcode(cbuf, 0x50+$src1$$reg );
3038 // PUSH src2.hi
3039 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3040 // PUSH src2.lo
3041 emit_opcode(cbuf, 0x50+$src2$$reg );
3042 // CALL directly to the runtime
3043 cbuf.set_inst_mark();
3044 emit_opcode(cbuf,0xE8); // Call into runtime
3045 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3046 // Restore stack
3047 emit_opcode(cbuf, 0x83); // add SP, #framesize
3048 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3049 emit_d8(cbuf, 4*4);
3050 %}
3052 enc_class long_mod( eRegL src1, eRegL src2 ) %{
3053 // PUSH src1.hi
3054 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3055 // PUSH src1.lo
3056 emit_opcode(cbuf, 0x50+$src1$$reg );
3057 // PUSH src2.hi
3058 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3059 // PUSH src2.lo
3060 emit_opcode(cbuf, 0x50+$src2$$reg );
3061 // CALL directly to the runtime
3062 cbuf.set_inst_mark();
3063 emit_opcode(cbuf,0xE8); // Call into runtime
3064 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3065 // Restore stack
3066 emit_opcode(cbuf, 0x83); // add SP, #framesize
3067 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3068 emit_d8(cbuf, 4*4);
3069 %}
3071 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{
3072 // MOV $tmp,$src.lo
3073 emit_opcode(cbuf, 0x8B);
3074 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
3075 // OR $tmp,$src.hi
3076 emit_opcode(cbuf, 0x0B);
3077 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
3078 %}
3080 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
3081 // CMP $src1.lo,$src2.lo
3082 emit_opcode( cbuf, 0x3B );
3083 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3084 // JNE,s skip
3085 emit_cc(cbuf, 0x70, 0x5);
3086 emit_d8(cbuf,2);
3087 // CMP $src1.hi,$src2.hi
3088 emit_opcode( cbuf, 0x3B );
3089 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
3090 %}
3092 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{
3093 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
3094 emit_opcode( cbuf, 0x3B );
3095 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3096 // MOV $tmp,$src1.hi
3097 emit_opcode( cbuf, 0x8B );
3098 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
3099 // SBB $tmp,$src2.hi\t! Compute flags for long compare
3100 emit_opcode( cbuf, 0x1B );
3101 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
3102 %}
3104 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{
3105 // XOR $tmp,$tmp
3106 emit_opcode(cbuf,0x33); // XOR
3107 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
3108 // CMP $tmp,$src.lo
3109 emit_opcode( cbuf, 0x3B );
3110 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
3111 // SBB $tmp,$src.hi
3112 emit_opcode( cbuf, 0x1B );
3113 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
3114 %}
3116 // Sniff, sniff... smells like Gnu Superoptimizer
3117 enc_class neg_long( eRegL dst ) %{
3118 emit_opcode(cbuf,0xF7); // NEG hi
3119 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3120 emit_opcode(cbuf,0xF7); // NEG lo
3121 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
3122 emit_opcode(cbuf,0x83); // SBB hi,0
3123 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3124 emit_d8 (cbuf,0 );
3125 %}
3127 enc_class movq_ld(regXD dst, memory mem) %{
3128 MacroAssembler _masm(&cbuf);
3129 __ movq($dst$$XMMRegister, $mem$$Address);
3130 %}
3132 enc_class movq_st(memory mem, regXD src) %{
3133 MacroAssembler _masm(&cbuf);
3134 __ movq($mem$$Address, $src$$XMMRegister);
3135 %}
3137 enc_class pshufd_8x8(regX dst, regX src) %{
3138 MacroAssembler _masm(&cbuf);
3140 encode_CopyXD(cbuf, $dst$$reg, $src$$reg);
3141 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg));
3142 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00);
3143 %}
3145 enc_class pshufd_4x16(regX dst, regX src) %{
3146 MacroAssembler _masm(&cbuf);
3148 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00);
3149 %}
3151 enc_class pshufd(regXD dst, regXD src, int mode) %{
3152 MacroAssembler _masm(&cbuf);
3154 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode);
3155 %}
3157 enc_class pxor(regXD dst, regXD src) %{
3158 MacroAssembler _masm(&cbuf);
3160 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg));
3161 %}
3163 enc_class mov_i2x(regXD dst, eRegI src) %{
3164 MacroAssembler _masm(&cbuf);
3166 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg));
3167 %}
3170 // Because the transitions from emitted code to the runtime
3171 // monitorenter/exit helper stubs are so slow it's critical that
3172 // we inline both the stack-locking fast-path and the inflated fast path.
3173 //
3174 // See also: cmpFastLock and cmpFastUnlock.
3175 //
3176 // What follows is a specialized inline transliteration of the code
3177 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
3178 // another option would be to emit TrySlowEnter and TrySlowExit methods
3179 // at startup-time. These methods would accept arguments as
3180 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
3181 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
3182 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
3183 // In practice, however, the # of lock sites is bounded and is usually small.
3184 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
3185 // if the processor uses simple bimodal branch predictors keyed by EIP
3186 // Since the helper routines would be called from multiple synchronization
3187 // sites.
3188 //
3189 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
3190 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
3191 // to those specialized methods. That'd give us a mostly platform-independent
3192 // implementation that the JITs could optimize and inline at their pleasure.
3193 // Done correctly, the only time we'd need to cross to native could would be
3194 // to park() or unpark() threads. We'd also need a few more unsafe operators
3195 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
3196 // (b) explicit barriers or fence operations.
3197 //
3198 // TODO:
3199 //
3200 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
3201 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
3202 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
3203 // the lock operators would typically be faster than reifying Self.
3204 //
3205 // * Ideally I'd define the primitives as:
3206 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
3207 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
3208 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
3209 // Instead, we're stuck with a rather awkward and brittle register assignments below.
3210 // Furthermore the register assignments are overconstrained, possibly resulting in
3211 // sub-optimal code near the synchronization site.
3212 //
3213 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
3214 // Alternately, use a better sp-proximity test.
3215 //
3216 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
3217 // Either one is sufficient to uniquely identify a thread.
3218 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
3219 //
3220 // * Intrinsify notify() and notifyAll() for the common cases where the
3221 // object is locked by the calling thread but the waitlist is empty.
3222 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
3223 //
3224 // * use jccb and jmpb instead of jcc and jmp to improve code density.
3225 // But beware of excessive branch density on AMD Opterons.
3226 //
3227 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
3228 // or failure of the fast-path. If the fast-path fails then we pass
3229 // control to the slow-path, typically in C. In Fast_Lock and
3230 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
3231 // will emit a conditional branch immediately after the node.
3232 // So we have branches to branches and lots of ICC.ZF games.
3233 // Instead, it might be better to have C2 pass a "FailureLabel"
3234 // into Fast_Lock and Fast_Unlock. In the case of success, control
3235 // will drop through the node. ICC.ZF is undefined at exit.
3236 // In the case of failure, the node will branch directly to the
3237 // FailureLabel
3240 // obj: object to lock
3241 // box: on-stack box address (displaced header location) - KILLED
3242 // rax,: tmp -- KILLED
3243 // scr: tmp -- KILLED
3244 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
3246 Register objReg = as_Register($obj$$reg);
3247 Register boxReg = as_Register($box$$reg);
3248 Register tmpReg = as_Register($tmp$$reg);
3249 Register scrReg = as_Register($scr$$reg);
3251 // Ensure the register assignents are disjoint
3252 guarantee (objReg != boxReg, "") ;
3253 guarantee (objReg != tmpReg, "") ;
3254 guarantee (objReg != scrReg, "") ;
3255 guarantee (boxReg != tmpReg, "") ;
3256 guarantee (boxReg != scrReg, "") ;
3257 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3259 MacroAssembler masm(&cbuf);
3261 if (_counters != NULL) {
3262 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3263 }
3264 if (EmitSync & 1) {
3265 // set box->dhw = unused_mark (3)
3266 // Force all sync thru slow-path: slow_enter() and slow_exit()
3267 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3268 masm.cmpptr (rsp, (int32_t)0) ;
3269 } else
3270 if (EmitSync & 2) {
3271 Label DONE_LABEL ;
3272 if (UseBiasedLocking) {
3273 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3274 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3275 }
3277 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3278 masm.orptr (tmpReg, 0x1);
3279 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3280 if (os::is_MP()) { masm.lock(); }
3281 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3282 masm.jcc(Assembler::equal, DONE_LABEL);
3283 // Recursive locking
3284 masm.subptr(tmpReg, rsp);
3285 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3286 masm.movptr(Address(boxReg, 0), tmpReg);
3287 masm.bind(DONE_LABEL) ;
3288 } else {
3289 // Possible cases that we'll encounter in fast_lock
3290 // ------------------------------------------------
3291 // * Inflated
3292 // -- unlocked
3293 // -- Locked
3294 // = by self
3295 // = by other
3296 // * biased
3297 // -- by Self
3298 // -- by other
3299 // * neutral
3300 // * stack-locked
3301 // -- by self
3302 // = sp-proximity test hits
3303 // = sp-proximity test generates false-negative
3304 // -- by other
3305 //
3307 Label IsInflated, DONE_LABEL, PopDone ;
3309 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3310 // order to reduce the number of conditional branches in the most common cases.
3311 // Beware -- there's a subtle invariant that fetch of the markword
3312 // at [FETCH], below, will never observe a biased encoding (*101b).
3313 // If this invariant is not held we risk exclusion (safety) failure.
3314 if (UseBiasedLocking && !UseOptoBiasInlining) {
3315 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3316 }
3318 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3319 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3320 masm.jccb (Assembler::notZero, IsInflated) ;
3322 // Attempt stack-locking ...
3323 masm.orptr (tmpReg, 0x1);
3324 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3325 if (os::is_MP()) { masm.lock(); }
3326 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3327 if (_counters != NULL) {
3328 masm.cond_inc32(Assembler::equal,
3329 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3330 }
3331 masm.jccb (Assembler::equal, DONE_LABEL);
3333 // Recursive locking
3334 masm.subptr(tmpReg, rsp);
3335 masm.andptr(tmpReg, 0xFFFFF003 );
3336 masm.movptr(Address(boxReg, 0), tmpReg);
3337 if (_counters != NULL) {
3338 masm.cond_inc32(Assembler::equal,
3339 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3340 }
3341 masm.jmp (DONE_LABEL) ;
3343 masm.bind (IsInflated) ;
3345 // The object is inflated.
3346 //
3347 // TODO-FIXME: eliminate the ugly use of manifest constants:
3348 // Use markOopDesc::monitor_value instead of "2".
3349 // use markOop::unused_mark() instead of "3".
3350 // The tmpReg value is an objectMonitor reference ORed with
3351 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3352 // objectmonitor pointer by masking off the "2" bit or we can just
3353 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3354 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3355 //
3356 // I use the latter as it avoids AGI stalls.
3357 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3358 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3359 //
3360 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3362 // boxReg refers to the on-stack BasicLock in the current frame.
3363 // We'd like to write:
3364 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3365 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3366 // additional latency as we have another ST in the store buffer that must drain.
3368 if (EmitSync & 8192) {
3369 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3370 masm.get_thread (scrReg) ;
3371 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3372 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3373 if (os::is_MP()) { masm.lock(); }
3374 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3375 } else
3376 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3377 masm.movptr(scrReg, boxReg) ;
3378 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3380 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3381 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
3382 // prefetchw [eax + Offset(_owner)-2]
3383 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3384 }
3386 if ((EmitSync & 64) == 0) {
3387 // Optimistic form: consider XORL tmpReg,tmpReg
3388 masm.movptr(tmpReg, NULL_WORD) ;
3389 } else {
3390 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3391 // Test-And-CAS instead of CAS
3392 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3393 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3394 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3395 }
3397 // Appears unlocked - try to swing _owner from null to non-null.
3398 // Ideally, I'd manifest "Self" with get_thread and then attempt
3399 // to CAS the register containing Self into m->Owner.
3400 // But we don't have enough registers, so instead we can either try to CAS
3401 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3402 // we later store "Self" into m->Owner. Transiently storing a stack address
3403 // (rsp or the address of the box) into m->owner is harmless.
3404 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3405 if (os::is_MP()) { masm.lock(); }
3406 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3407 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3408 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3409 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3410 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3411 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3413 // If the CAS fails we can either retry or pass control to the slow-path.
3414 // We use the latter tactic.
3415 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3416 // If the CAS was successful ...
3417 // Self has acquired the lock
3418 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3419 // Intentional fall-through into DONE_LABEL ...
3420 } else {
3421 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3422 masm.movptr(boxReg, tmpReg) ;
3424 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3425 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
3426 // prefetchw [eax + Offset(_owner)-2]
3427 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3428 }
3430 if ((EmitSync & 64) == 0) {
3431 // Optimistic form
3432 masm.xorptr (tmpReg, tmpReg) ;
3433 } else {
3434 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3435 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3436 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3437 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3438 }
3440 // Appears unlocked - try to swing _owner from null to non-null.
3441 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3442 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3443 masm.get_thread (scrReg) ;
3444 if (os::is_MP()) { masm.lock(); }
3445 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3447 // If the CAS fails we can either retry or pass control to the slow-path.
3448 // We use the latter tactic.
3449 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3450 // If the CAS was successful ...
3451 // Self has acquired the lock
3452 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3453 // Intentional fall-through into DONE_LABEL ...
3454 }
3456 // DONE_LABEL is a hot target - we'd really like to place it at the
3457 // start of cache line by padding with NOPs.
3458 // See the AMD and Intel software optimization manuals for the
3459 // most efficient "long" NOP encodings.
3460 // Unfortunately none of our alignment mechanisms suffice.
3461 masm.bind(DONE_LABEL);
3463 // Avoid branch-to-branch on AMD processors
3464 // This appears to be superstition.
3465 if (EmitSync & 32) masm.nop() ;
3468 // At DONE_LABEL the icc ZFlag is set as follows ...
3469 // Fast_Unlock uses the same protocol.
3470 // ZFlag == 1 -> Success
3471 // ZFlag == 0 -> Failure - force control through the slow-path
3472 }
3473 %}
3475 // obj: object to unlock
3476 // box: box address (displaced header location), killed. Must be EAX.
3477 // rbx,: killed tmp; cannot be obj nor box.
3478 //
3479 // Some commentary on balanced locking:
3480 //
3481 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3482 // Methods that don't have provably balanced locking are forced to run in the
3483 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3484 // The interpreter provides two properties:
3485 // I1: At return-time the interpreter automatically and quietly unlocks any
3486 // objects acquired the current activation (frame). Recall that the
3487 // interpreter maintains an on-stack list of locks currently held by
3488 // a frame.
3489 // I2: If a method attempts to unlock an object that is not held by the
3490 // the frame the interpreter throws IMSX.
3491 //
3492 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3493 // B() doesn't have provably balanced locking so it runs in the interpreter.
3494 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3495 // is still locked by A().
3496 //
3497 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3498 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3499 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3500 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3502 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3504 Register objReg = as_Register($obj$$reg);
3505 Register boxReg = as_Register($box$$reg);
3506 Register tmpReg = as_Register($tmp$$reg);
3508 guarantee (objReg != boxReg, "") ;
3509 guarantee (objReg != tmpReg, "") ;
3510 guarantee (boxReg != tmpReg, "") ;
3511 guarantee (boxReg == as_Register(EAX_enc), "") ;
3512 MacroAssembler masm(&cbuf);
3514 if (EmitSync & 4) {
3515 // Disable - inhibit all inlining. Force control through the slow-path
3516 masm.cmpptr (rsp, 0) ;
3517 } else
3518 if (EmitSync & 8) {
3519 Label DONE_LABEL ;
3520 if (UseBiasedLocking) {
3521 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3522 }
3523 // classic stack-locking code ...
3524 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3525 masm.testptr(tmpReg, tmpReg) ;
3526 masm.jcc (Assembler::zero, DONE_LABEL) ;
3527 if (os::is_MP()) { masm.lock(); }
3528 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3529 masm.bind(DONE_LABEL);
3530 } else {
3531 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3533 // Critically, the biased locking test must have precedence over
3534 // and appear before the (box->dhw == 0) recursive stack-lock test.
3535 if (UseBiasedLocking && !UseOptoBiasInlining) {
3536 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3537 }
3539 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3540 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3541 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3543 masm.testptr(tmpReg, 0x02) ; // Inflated?
3544 masm.jccb (Assembler::zero, Stacked) ;
3546 masm.bind (Inflated) ;
3547 // It's inflated.
3548 // Despite our balanced locking property we still check that m->_owner == Self
3549 // as java routines or native JNI code called by this thread might
3550 // have released the lock.
3551 // Refer to the comments in synchronizer.cpp for how we might encode extra
3552 // state in _succ so we can avoid fetching EntryList|cxq.
3553 //
3554 // I'd like to add more cases in fast_lock() and fast_unlock() --
3555 // such as recursive enter and exit -- but we have to be wary of
3556 // I$ bloat, T$ effects and BP$ effects.
3557 //
3558 // If there's no contention try a 1-0 exit. That is, exit without
3559 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3560 // we detect and recover from the race that the 1-0 exit admits.
3561 //
3562 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3563 // before it STs null into _owner, releasing the lock. Updates
3564 // to data protected by the critical section must be visible before
3565 // we drop the lock (and thus before any other thread could acquire
3566 // the lock and observe the fields protected by the lock).
3567 // IA32's memory-model is SPO, so STs are ordered with respect to
3568 // each other and there's no need for an explicit barrier (fence).
3569 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3571 masm.get_thread (boxReg) ;
3572 if ((EmitSync & 4096) && VM_Version::supports_3dnow() && os::is_MP()) {
3573 // prefetchw [ebx + Offset(_owner)-2]
3574 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3575 }
3577 // Note that we could employ various encoding schemes to reduce
3578 // the number of loads below (currently 4) to just 2 or 3.
3579 // Refer to the comments in synchronizer.cpp.
3580 // In practice the chain of fetches doesn't seem to impact performance, however.
3581 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3582 // Attempt to reduce branch density - AMD's branch predictor.
3583 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3584 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3585 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3586 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3587 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3588 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3589 masm.jmpb (DONE_LABEL) ;
3590 } else {
3591 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3592 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3593 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3594 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3595 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3596 masm.jccb (Assembler::notZero, CheckSucc) ;
3597 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3598 masm.jmpb (DONE_LABEL) ;
3599 }
3601 // The Following code fragment (EmitSync & 65536) improves the performance of
3602 // contended applications and contended synchronization microbenchmarks.
3603 // Unfortunately the emission of the code - even though not executed - causes regressions
3604 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3605 // with an equal number of never-executed NOPs results in the same regression.
3606 // We leave it off by default.
3608 if ((EmitSync & 65536) != 0) {
3609 Label LSuccess, LGoSlowPath ;
3611 masm.bind (CheckSucc) ;
3613 // Optional pre-test ... it's safe to elide this
3614 if ((EmitSync & 16) == 0) {
3615 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3616 masm.jccb (Assembler::zero, LGoSlowPath) ;
3617 }
3619 // We have a classic Dekker-style idiom:
3620 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3621 // There are a number of ways to implement the barrier:
3622 // (1) lock:andl &m->_owner, 0
3623 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3624 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3625 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3626 // (2) If supported, an explicit MFENCE is appealing.
3627 // In older IA32 processors MFENCE is slower than lock:add or xchg
3628 // particularly if the write-buffer is full as might be the case if
3629 // if stores closely precede the fence or fence-equivalent instruction.
3630 // In more modern implementations MFENCE appears faster, however.
3631 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3632 // The $lines underlying the top-of-stack should be in M-state.
3633 // The locked add instruction is serializing, of course.
3634 // (4) Use xchg, which is serializing
3635 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3636 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3637 // The integer condition codes will tell us if succ was 0.
3638 // Since _succ and _owner should reside in the same $line and
3639 // we just stored into _owner, it's likely that the $line
3640 // remains in M-state for the lock:orl.
3641 //
3642 // We currently use (3), although it's likely that switching to (2)
3643 // is correct for the future.
3645 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3646 if (os::is_MP()) {
3647 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3648 masm.mfence();
3649 } else {
3650 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3651 }
3652 }
3653 // Ratify _succ remains non-null
3654 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3655 masm.jccb (Assembler::notZero, LSuccess) ;
3657 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3658 if (os::is_MP()) { masm.lock(); }
3659 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3660 masm.jccb (Assembler::notEqual, LSuccess) ;
3661 // Since we're low on registers we installed rsp as a placeholding in _owner.
3662 // Now install Self over rsp. This is safe as we're transitioning from
3663 // non-null to non=null
3664 masm.get_thread (boxReg) ;
3665 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3666 // Intentional fall-through into LGoSlowPath ...
3668 masm.bind (LGoSlowPath) ;
3669 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3670 masm.jmpb (DONE_LABEL) ;
3672 masm.bind (LSuccess) ;
3673 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3674 masm.jmpb (DONE_LABEL) ;
3675 }
3677 masm.bind (Stacked) ;
3678 // It's not inflated and it's not recursively stack-locked and it's not biased.
3679 // It must be stack-locked.
3680 // Try to reset the header to displaced header.
3681 // The "box" value on the stack is stable, so we can reload
3682 // and be assured we observe the same value as above.
3683 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3684 if (os::is_MP()) { masm.lock(); }
3685 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3686 // Intention fall-thru into DONE_LABEL
3689 // DONE_LABEL is a hot target - we'd really like to place it at the
3690 // start of cache line by padding with NOPs.
3691 // See the AMD and Intel software optimization manuals for the
3692 // most efficient "long" NOP encodings.
3693 // Unfortunately none of our alignment mechanisms suffice.
3694 if ((EmitSync & 65536) == 0) {
3695 masm.bind (CheckSucc) ;
3696 }
3697 masm.bind(DONE_LABEL);
3699 // Avoid branch to branch on AMD processors
3700 if (EmitSync & 32768) { masm.nop() ; }
3701 }
3702 %}
3704 enc_class enc_String_Compare(eDIRegP str1, eSIRegP str2, regXD tmp1, regXD tmp2,
3705 eAXRegI tmp3, eBXRegI tmp4, eCXRegI result) %{
3706 Label ECX_GOOD_LABEL, LENGTH_DIFF_LABEL,
3707 POP_LABEL, DONE_LABEL, CONT_LABEL,
3708 WHILE_HEAD_LABEL;
3709 MacroAssembler masm(&cbuf);
3711 XMMRegister tmp1Reg = as_XMMRegister($tmp1$$reg);
3712 XMMRegister tmp2Reg = as_XMMRegister($tmp2$$reg);
3714 // Get the first character position in both strings
3715 // [8] char array, [12] offset, [16] count
3716 int value_offset = java_lang_String::value_offset_in_bytes();
3717 int offset_offset = java_lang_String::offset_offset_in_bytes();
3718 int count_offset = java_lang_String::count_offset_in_bytes();
3719 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3721 masm.movptr(rax, Address(rsi, value_offset));
3722 masm.movl(rcx, Address(rsi, offset_offset));
3723 masm.lea(rax, Address(rax, rcx, Address::times_2, base_offset));
3724 masm.movptr(rbx, Address(rdi, value_offset));
3725 masm.movl(rcx, Address(rdi, offset_offset));
3726 masm.lea(rbx, Address(rbx, rcx, Address::times_2, base_offset));
3728 // Compute the minimum of the string lengths(rsi) and the
3729 // difference of the string lengths (stack)
3731 if (VM_Version::supports_cmov()) {
3732 masm.movl(rdi, Address(rdi, count_offset));
3733 masm.movl(rsi, Address(rsi, count_offset));
3734 masm.movl(rcx, rdi);
3735 masm.subl(rdi, rsi);
3736 masm.push(rdi);
3737 masm.cmovl(Assembler::lessEqual, rsi, rcx);
3738 } else {
3739 masm.movl(rdi, Address(rdi, count_offset));
3740 masm.movl(rcx, Address(rsi, count_offset));
3741 masm.movl(rsi, rdi);
3742 masm.subl(rdi, rcx);
3743 masm.push(rdi);
3744 masm.jccb(Assembler::lessEqual, ECX_GOOD_LABEL);
3745 masm.movl(rsi, rcx);
3746 // rsi holds min, rcx is unused
3747 }
3749 // Is the minimum length zero?
3750 masm.bind(ECX_GOOD_LABEL);
3751 masm.testl(rsi, rsi);
3752 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL);
3754 // Load first characters
3755 masm.load_unsigned_short(rcx, Address(rbx, 0));
3756 masm.load_unsigned_short(rdi, Address(rax, 0));
3758 // Compare first characters
3759 masm.subl(rcx, rdi);
3760 masm.jcc(Assembler::notZero, POP_LABEL);
3761 masm.decrementl(rsi);
3762 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL);
3764 {
3765 // Check after comparing first character to see if strings are equivalent
3766 Label LSkip2;
3767 // Check if the strings start at same location
3768 masm.cmpptr(rbx,rax);
3769 masm.jccb(Assembler::notEqual, LSkip2);
3771 // Check if the length difference is zero (from stack)
3772 masm.cmpl(Address(rsp, 0), 0x0);
3773 masm.jcc(Assembler::equal, LENGTH_DIFF_LABEL);
3775 // Strings might not be equivalent
3776 masm.bind(LSkip2);
3777 }
3779 // Advance to next character
3780 masm.addptr(rax, 2);
3781 masm.addptr(rbx, 2);
3783 if (UseSSE42Intrinsics) {
3784 // With SSE4.2, use double quad vector compare
3785 Label COMPARE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
3786 // Setup to compare 16-byte vectors
3787 masm.movl(rdi, rsi);
3788 masm.andl(rsi, 0xfffffff8); // rsi holds the vector count
3789 masm.andl(rdi, 0x00000007); // rdi holds the tail count
3790 masm.testl(rsi, rsi);
3791 masm.jccb(Assembler::zero, COMPARE_TAIL);
3793 masm.lea(rax, Address(rax, rsi, Address::times_2));
3794 masm.lea(rbx, Address(rbx, rsi, Address::times_2));
3795 masm.negl(rsi);
3797 masm.bind(COMPARE_VECTORS);
3798 masm.movdqu(tmp1Reg, Address(rax, rsi, Address::times_2));
3799 masm.movdqu(tmp2Reg, Address(rbx, rsi, Address::times_2));
3800 masm.pxor(tmp1Reg, tmp2Reg);
3801 masm.ptest(tmp1Reg, tmp1Reg);
3802 masm.jccb(Assembler::notZero, VECTOR_NOT_EQUAL);
3803 masm.addl(rsi, 8);
3804 masm.jcc(Assembler::notZero, COMPARE_VECTORS);
3805 masm.jmpb(COMPARE_TAIL);
3807 // Mismatched characters in the vectors
3808 masm.bind(VECTOR_NOT_EQUAL);
3809 masm.lea(rax, Address(rax, rsi, Address::times_2));
3810 masm.lea(rbx, Address(rbx, rsi, Address::times_2));
3811 masm.movl(rdi, 8);
3813 // Compare tail (< 8 chars), or rescan last vectors to
3814 // find 1st mismatched characters
3815 masm.bind(COMPARE_TAIL);
3816 masm.testl(rdi, rdi);
3817 masm.jccb(Assembler::zero, LENGTH_DIFF_LABEL);
3818 masm.movl(rsi, rdi);
3819 // Fallthru to tail compare
3820 }
3822 //Shift rax, and rbx, to the end of the arrays, negate min
3823 masm.lea(rax, Address(rax, rsi, Address::times_2, 0));
3824 masm.lea(rbx, Address(rbx, rsi, Address::times_2, 0));
3825 masm.negl(rsi);
3827 // Compare the rest of the characters
3828 masm.bind(WHILE_HEAD_LABEL);
3829 masm.load_unsigned_short(rcx, Address(rbx, rsi, Address::times_2, 0));
3830 masm.load_unsigned_short(rdi, Address(rax, rsi, Address::times_2, 0));
3831 masm.subl(rcx, rdi);
3832 masm.jccb(Assembler::notZero, POP_LABEL);
3833 masm.incrementl(rsi);
3834 masm.jcc(Assembler::notZero, WHILE_HEAD_LABEL);
3836 // Strings are equal up to min length. Return the length difference.
3837 masm.bind(LENGTH_DIFF_LABEL);
3838 masm.pop(rcx);
3839 masm.jmpb(DONE_LABEL);
3841 // Discard the stored length difference
3842 masm.bind(POP_LABEL);
3843 masm.addptr(rsp, 4);
3845 // That's it
3846 masm.bind(DONE_LABEL);
3847 %}
3849 enc_class enc_String_Equals(eDIRegP str1, eSIRegP str2, regXD tmp1, regXD tmp2,
3850 eBXRegI tmp3, eCXRegI tmp4, eAXRegI result) %{
3851 Label RET_TRUE, RET_FALSE, DONE, COMPARE_VECTORS, COMPARE_CHAR;
3852 MacroAssembler masm(&cbuf);
3854 XMMRegister tmp1Reg = as_XMMRegister($tmp1$$reg);
3855 XMMRegister tmp2Reg = as_XMMRegister($tmp2$$reg);
3857 int value_offset = java_lang_String::value_offset_in_bytes();
3858 int offset_offset = java_lang_String::offset_offset_in_bytes();
3859 int count_offset = java_lang_String::count_offset_in_bytes();
3860 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3862 // does source == target string?
3863 masm.cmpptr(rdi, rsi);
3864 masm.jcc(Assembler::equal, RET_TRUE);
3866 // get and compare counts
3867 masm.movl(rcx, Address(rdi, count_offset));
3868 masm.movl(rax, Address(rsi, count_offset));
3869 masm.cmpl(rcx, rax);
3870 masm.jcc(Assembler::notEqual, RET_FALSE);
3871 masm.testl(rax, rax);
3872 masm.jcc(Assembler::zero, RET_TRUE);
3874 // get source string offset and value
3875 masm.movptr(rbx, Address(rsi, value_offset));
3876 masm.movl(rax, Address(rsi, offset_offset));
3877 masm.leal(rsi, Address(rbx, rax, Address::times_2, base_offset));
3879 // get compare string offset and value
3880 masm.movptr(rbx, Address(rdi, value_offset));
3881 masm.movl(rax, Address(rdi, offset_offset));
3882 masm.leal(rdi, Address(rbx, rax, Address::times_2, base_offset));
3884 // Set byte count
3885 masm.shll(rcx, 1);
3886 masm.movl(rax, rcx);
3888 if (UseSSE42Intrinsics) {
3889 // With SSE4.2, use double quad vector compare
3890 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
3891 // Compare 16-byte vectors
3892 masm.andl(rcx, 0xfffffff0); // vector count (in bytes)
3893 masm.andl(rax, 0x0000000e); // tail count (in bytes)
3894 masm.testl(rcx, rcx);
3895 masm.jccb(Assembler::zero, COMPARE_TAIL);
3896 masm.lea(rdi, Address(rdi, rcx, Address::times_1));
3897 masm.lea(rsi, Address(rsi, rcx, Address::times_1));
3898 masm.negl(rcx);
3900 masm.bind(COMPARE_WIDE_VECTORS);
3901 masm.movdqu(tmp1Reg, Address(rdi, rcx, Address::times_1));
3902 masm.movdqu(tmp2Reg, Address(rsi, rcx, Address::times_1));
3903 masm.pxor(tmp1Reg, tmp2Reg);
3904 masm.ptest(tmp1Reg, tmp1Reg);
3905 masm.jccb(Assembler::notZero, RET_FALSE);
3906 masm.addl(rcx, 16);
3907 masm.jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
3908 masm.bind(COMPARE_TAIL);
3909 masm.movl(rcx, rax);
3910 // Fallthru to tail compare
3911 }
3913 // Compare 4-byte vectors
3914 masm.andl(rcx, 0xfffffffc); // vector count (in bytes)
3915 masm.andl(rax, 0x00000002); // tail char (in bytes)
3916 masm.testl(rcx, rcx);
3917 masm.jccb(Assembler::zero, COMPARE_CHAR);
3918 masm.lea(rdi, Address(rdi, rcx, Address::times_1));
3919 masm.lea(rsi, Address(rsi, rcx, Address::times_1));
3920 masm.negl(rcx);
3922 masm.bind(COMPARE_VECTORS);
3923 masm.movl(rbx, Address(rdi, rcx, Address::times_1));
3924 masm.cmpl(rbx, Address(rsi, rcx, Address::times_1));
3925 masm.jccb(Assembler::notEqual, RET_FALSE);
3926 masm.addl(rcx, 4);
3927 masm.jcc(Assembler::notZero, COMPARE_VECTORS);
3929 // Compare trailing char (final 2 bytes), if any
3930 masm.bind(COMPARE_CHAR);
3931 masm.testl(rax, rax);
3932 masm.jccb(Assembler::zero, RET_TRUE);
3933 masm.load_unsigned_short(rbx, Address(rdi, 0));
3934 masm.load_unsigned_short(rcx, Address(rsi, 0));
3935 masm.cmpl(rbx, rcx);
3936 masm.jccb(Assembler::notEqual, RET_FALSE);
3938 masm.bind(RET_TRUE);
3939 masm.movl(rax, 1); // return true
3940 masm.jmpb(DONE);
3942 masm.bind(RET_FALSE);
3943 masm.xorl(rax, rax); // return false
3945 masm.bind(DONE);
3946 %}
3948 enc_class enc_String_IndexOf(eSIRegP str1, eDIRegP str2, regXD tmp1, eAXRegI tmp2,
3949 eCXRegI tmp3, eDXRegI tmp4, eBXRegI result) %{
3950 // SSE4.2 version
3951 Label LOAD_SUBSTR, PREP_FOR_SCAN, SCAN_TO_SUBSTR,
3952 SCAN_SUBSTR, RET_NEG_ONE, RET_NOT_FOUND, CLEANUP, DONE;
3953 MacroAssembler masm(&cbuf);
3955 XMMRegister tmp1Reg = as_XMMRegister($tmp1$$reg);
3957 // Get the first character position in both strings
3958 // [8] char array, [12] offset, [16] count
3959 int value_offset = java_lang_String::value_offset_in_bytes();
3960 int offset_offset = java_lang_String::offset_offset_in_bytes();
3961 int count_offset = java_lang_String::count_offset_in_bytes();
3962 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3964 // Get counts for string and substr
3965 masm.movl(rdx, Address(rsi, count_offset));
3966 masm.movl(rax, Address(rdi, count_offset));
3967 // Check for substr count > string count
3968 masm.cmpl(rax, rdx);
3969 masm.jcc(Assembler::greater, RET_NEG_ONE);
3971 // Start the indexOf operation
3972 // Get start addr of string
3973 masm.movptr(rbx, Address(rsi, value_offset));
3974 masm.movl(rcx, Address(rsi, offset_offset));
3975 masm.lea(rsi, Address(rbx, rcx, Address::times_2, base_offset));
3976 masm.push(rsi);
3978 // Get start addr of substr
3979 masm.movptr(rbx, Address(rdi, value_offset));
3980 masm.movl(rcx, Address(rdi, offset_offset));
3981 masm.lea(rdi, Address(rbx, rcx, Address::times_2, base_offset));
3982 masm.push(rdi);
3983 masm.push(rax);
3984 masm.jmpb(PREP_FOR_SCAN);
3986 // Substr count saved at sp
3987 // Substr saved at sp+4
3988 // String saved at sp+8
3990 // Prep to load substr for scan
3991 masm.bind(LOAD_SUBSTR);
3992 masm.movptr(rdi, Address(rsp, 4));
3993 masm.movl(rax, Address(rsp, 0));
3995 // Load substr
3996 masm.bind(PREP_FOR_SCAN);
3997 masm.movdqu(tmp1Reg, Address(rdi, 0));
3998 masm.addl(rdx, 8); // prime the loop
3999 masm.subptr(rsi, 16);
4001 // Scan string for substr in 16-byte vectors
4002 masm.bind(SCAN_TO_SUBSTR);
4003 masm.subl(rdx, 8);
4004 masm.addptr(rsi, 16);
4005 masm.pcmpestri(tmp1Reg, Address(rsi, 0), 0x0d);
4006 masm.jcc(Assembler::above, SCAN_TO_SUBSTR); // CF == 0 && ZF == 0
4007 masm.jccb(Assembler::aboveEqual, RET_NOT_FOUND); // CF == 0
4009 // Fallthru: found a potential substr
4011 // Make sure string is still long enough
4012 masm.subl(rdx, rcx);
4013 masm.cmpl(rdx, rax);
4014 masm.jccb(Assembler::negative, RET_NOT_FOUND);
4015 // Compute start addr of substr
4016 masm.lea(rsi, Address(rsi, rcx, Address::times_2));
4017 masm.movptr(rbx, rsi);
4019 // Compare potential substr
4020 masm.addl(rdx, 8); // prime the loop
4021 masm.addl(rax, 8);
4022 masm.subptr(rsi, 16);
4023 masm.subptr(rdi, 16);
4025 // Scan 16-byte vectors of string and substr
4026 masm.bind(SCAN_SUBSTR);
4027 masm.subl(rax, 8);
4028 masm.subl(rdx, 8);
4029 masm.addptr(rsi, 16);
4030 masm.addptr(rdi, 16);
4031 masm.movdqu(tmp1Reg, Address(rdi, 0));
4032 masm.pcmpestri(tmp1Reg, Address(rsi, 0), 0x0d);
4033 masm.jcc(Assembler::noOverflow, LOAD_SUBSTR); // OF == 0
4034 masm.jcc(Assembler::positive, SCAN_SUBSTR); // SF == 0
4036 // Compute substr offset
4037 masm.movptr(rsi, Address(rsp, 8));
4038 masm.subptr(rbx, rsi);
4039 masm.shrl(rbx, 1);
4040 masm.jmpb(CLEANUP);
4042 masm.bind(RET_NEG_ONE);
4043 masm.movl(rbx, -1);
4044 masm.jmpb(DONE);
4046 masm.bind(RET_NOT_FOUND);
4047 masm.movl(rbx, -1);
4049 masm.bind(CLEANUP);
4050 masm.addptr(rsp, 12);
4052 masm.bind(DONE);
4053 %}
4055 enc_class enc_Array_Equals(eDIRegP ary1, eSIRegP ary2, regXD tmp1, regXD tmp2,
4056 eBXRegI tmp3, eDXRegI tmp4, eAXRegI result) %{
4057 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR;
4058 MacroAssembler masm(&cbuf);
4060 XMMRegister tmp1Reg = as_XMMRegister($tmp1$$reg);
4061 XMMRegister tmp2Reg = as_XMMRegister($tmp2$$reg);
4062 Register ary1Reg = as_Register($ary1$$reg);
4063 Register ary2Reg = as_Register($ary2$$reg);
4064 Register tmp3Reg = as_Register($tmp3$$reg);
4065 Register tmp4Reg = as_Register($tmp4$$reg);
4066 Register resultReg = as_Register($result$$reg);
4068 int length_offset = arrayOopDesc::length_offset_in_bytes();
4069 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
4071 // Check the input args
4072 masm.cmpptr(ary1Reg, ary2Reg);
4073 masm.jcc(Assembler::equal, TRUE_LABEL);
4074 masm.testptr(ary1Reg, ary1Reg);
4075 masm.jcc(Assembler::zero, FALSE_LABEL);
4076 masm.testptr(ary2Reg, ary2Reg);
4077 masm.jcc(Assembler::zero, FALSE_LABEL);
4079 // Check the lengths
4080 masm.movl(tmp4Reg, Address(ary1Reg, length_offset));
4081 masm.movl(resultReg, Address(ary2Reg, length_offset));
4082 masm.cmpl(tmp4Reg, resultReg);
4083 masm.jcc(Assembler::notEqual, FALSE_LABEL);
4084 masm.testl(resultReg, resultReg);
4085 masm.jcc(Assembler::zero, TRUE_LABEL);
4087 // Load array addrs
4088 masm.lea(ary1Reg, Address(ary1Reg, base_offset));
4089 masm.lea(ary2Reg, Address(ary2Reg, base_offset));
4091 // Set byte count
4092 masm.shll(tmp4Reg, 1);
4093 masm.movl(resultReg, tmp4Reg);
4095 if (UseSSE42Intrinsics) {
4096 // With SSE4.2, use double quad vector compare
4097 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
4098 // Compare 16-byte vectors
4099 masm.andl(tmp4Reg, 0xfffffff0); // vector count (in bytes)
4100 masm.andl(resultReg, 0x0000000e); // tail count (in bytes)
4101 masm.testl(tmp4Reg, tmp4Reg);
4102 masm.jccb(Assembler::zero, COMPARE_TAIL);
4103 masm.lea(ary1Reg, Address(ary1Reg, tmp4Reg, Address::times_1));
4104 masm.lea(ary2Reg, Address(ary2Reg, tmp4Reg, Address::times_1));
4105 masm.negl(tmp4Reg);
4107 masm.bind(COMPARE_WIDE_VECTORS);
4108 masm.movdqu(tmp1Reg, Address(ary1Reg, tmp4Reg, Address::times_1));
4109 masm.movdqu(tmp2Reg, Address(ary2Reg, tmp4Reg, Address::times_1));
4110 masm.pxor(tmp1Reg, tmp2Reg);
4111 masm.ptest(tmp1Reg, tmp1Reg);
4113 masm.jccb(Assembler::notZero, FALSE_LABEL);
4114 masm.addl(tmp4Reg, 16);
4115 masm.jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
4116 masm.bind(COMPARE_TAIL);
4117 masm.movl(tmp4Reg, resultReg);
4118 // Fallthru to tail compare
4119 }
4121 // Compare 4-byte vectors
4122 masm.andl(tmp4Reg, 0xfffffffc); // vector count (in bytes)
4123 masm.andl(resultReg, 0x00000002); // tail char (in bytes)
4124 masm.testl(tmp4Reg, tmp4Reg);
4125 masm.jccb(Assembler::zero, COMPARE_CHAR);
4126 masm.lea(ary1Reg, Address(ary1Reg, tmp4Reg, Address::times_1));
4127 masm.lea(ary2Reg, Address(ary2Reg, tmp4Reg, Address::times_1));
4128 masm.negl(tmp4Reg);
4130 masm.bind(COMPARE_VECTORS);
4131 masm.movl(tmp3Reg, Address(ary1Reg, tmp4Reg, Address::times_1));
4132 masm.cmpl(tmp3Reg, Address(ary2Reg, tmp4Reg, Address::times_1));
4133 masm.jccb(Assembler::notEqual, FALSE_LABEL);
4134 masm.addl(tmp4Reg, 4);
4135 masm.jcc(Assembler::notZero, COMPARE_VECTORS);
4137 // Compare trailing char (final 2 bytes), if any
4138 masm.bind(COMPARE_CHAR);
4139 masm.testl(resultReg, resultReg);
4140 masm.jccb(Assembler::zero, TRUE_LABEL);
4141 masm.load_unsigned_short(tmp3Reg, Address(ary1Reg, 0));
4142 masm.load_unsigned_short(tmp4Reg, Address(ary2Reg, 0));
4143 masm.cmpl(tmp3Reg, tmp4Reg);
4144 masm.jccb(Assembler::notEqual, FALSE_LABEL);
4146 masm.bind(TRUE_LABEL);
4147 masm.movl(resultReg, 1); // return true
4148 masm.jmpb(DONE);
4150 masm.bind(FALSE_LABEL);
4151 masm.xorl(resultReg, resultReg); // return false
4153 // That's it
4154 masm.bind(DONE);
4155 %}
4157 enc_class enc_pop_rdx() %{
4158 emit_opcode(cbuf,0x5A);
4159 %}
4161 enc_class enc_rethrow() %{
4162 cbuf.set_inst_mark();
4163 emit_opcode(cbuf, 0xE9); // jmp entry
4164 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.code_end())-4,
4165 runtime_call_Relocation::spec(), RELOC_IMM32 );
4166 %}
4169 // Convert a double to an int. Java semantics require we do complex
4170 // manglelations in the corner cases. So we set the rounding mode to
4171 // 'zero', store the darned double down as an int, and reset the
4172 // rounding mode to 'nearest'. The hardware throws an exception which
4173 // patches up the correct value directly to the stack.
4174 enc_class D2I_encoding( regD src ) %{
4175 // Flip to round-to-zero mode. We attempted to allow invalid-op
4176 // exceptions here, so that a NAN or other corner-case value will
4177 // thrown an exception (but normal values get converted at full speed).
4178 // However, I2C adapters and other float-stack manglers leave pending
4179 // invalid-op exceptions hanging. We would have to clear them before
4180 // enabling them and that is more expensive than just testing for the
4181 // invalid value Intel stores down in the corner cases.
4182 emit_opcode(cbuf,0xD9); // FLDCW trunc
4183 emit_opcode(cbuf,0x2D);
4184 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
4185 // Allocate a word
4186 emit_opcode(cbuf,0x83); // SUB ESP,4
4187 emit_opcode(cbuf,0xEC);
4188 emit_d8(cbuf,0x04);
4189 // Encoding assumes a double has been pushed into FPR0.
4190 // Store down the double as an int, popping the FPU stack
4191 emit_opcode(cbuf,0xDB); // FISTP [ESP]
4192 emit_opcode(cbuf,0x1C);
4193 emit_d8(cbuf,0x24);
4194 // Restore the rounding mode; mask the exception
4195 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
4196 emit_opcode(cbuf,0x2D);
4197 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
4198 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
4199 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
4201 // Load the converted int; adjust CPU stack
4202 emit_opcode(cbuf,0x58); // POP EAX
4203 emit_opcode(cbuf,0x3D); // CMP EAX,imm
4204 emit_d32 (cbuf,0x80000000); // 0x80000000
4205 emit_opcode(cbuf,0x75); // JNE around_slow_call
4206 emit_d8 (cbuf,0x07); // Size of slow_call
4207 // Push src onto stack slow-path
4208 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
4209 emit_d8 (cbuf,0xC0-1+$src$$reg );
4210 // CALL directly to the runtime
4211 cbuf.set_inst_mark();
4212 emit_opcode(cbuf,0xE8); // Call into runtime
4213 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4214 // Carry on here...
4215 %}
4217 enc_class D2L_encoding( regD src ) %{
4218 emit_opcode(cbuf,0xD9); // FLDCW trunc
4219 emit_opcode(cbuf,0x2D);
4220 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
4221 // Allocate a word
4222 emit_opcode(cbuf,0x83); // SUB ESP,8
4223 emit_opcode(cbuf,0xEC);
4224 emit_d8(cbuf,0x08);
4225 // Encoding assumes a double has been pushed into FPR0.
4226 // Store down the double as a long, popping the FPU stack
4227 emit_opcode(cbuf,0xDF); // FISTP [ESP]
4228 emit_opcode(cbuf,0x3C);
4229 emit_d8(cbuf,0x24);
4230 // Restore the rounding mode; mask the exception
4231 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
4232 emit_opcode(cbuf,0x2D);
4233 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
4234 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
4235 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
4237 // Load the converted int; adjust CPU stack
4238 emit_opcode(cbuf,0x58); // POP EAX
4239 emit_opcode(cbuf,0x5A); // POP EDX
4240 emit_opcode(cbuf,0x81); // CMP EDX,imm
4241 emit_d8 (cbuf,0xFA); // rdx
4242 emit_d32 (cbuf,0x80000000); // 0x80000000
4243 emit_opcode(cbuf,0x75); // JNE around_slow_call
4244 emit_d8 (cbuf,0x07+4); // Size of slow_call
4245 emit_opcode(cbuf,0x85); // TEST EAX,EAX
4246 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
4247 emit_opcode(cbuf,0x75); // JNE around_slow_call
4248 emit_d8 (cbuf,0x07); // Size of slow_call
4249 // Push src onto stack slow-path
4250 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
4251 emit_d8 (cbuf,0xC0-1+$src$$reg );
4252 // CALL directly to the runtime
4253 cbuf.set_inst_mark();
4254 emit_opcode(cbuf,0xE8); // Call into runtime
4255 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4256 // Carry on here...
4257 %}
4259 enc_class X2L_encoding( regX src ) %{
4260 // Allocate a word
4261 emit_opcode(cbuf,0x83); // SUB ESP,8
4262 emit_opcode(cbuf,0xEC);
4263 emit_d8(cbuf,0x08);
4265 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
4266 emit_opcode (cbuf, 0x0F );
4267 emit_opcode (cbuf, 0x11 );
4268 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4270 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4271 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4273 emit_opcode(cbuf,0xD9); // FLDCW trunc
4274 emit_opcode(cbuf,0x2D);
4275 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
4277 // Encoding assumes a double has been pushed into FPR0.
4278 // Store down the double as a long, popping the FPU stack
4279 emit_opcode(cbuf,0xDF); // FISTP [ESP]
4280 emit_opcode(cbuf,0x3C);
4281 emit_d8(cbuf,0x24);
4283 // Restore the rounding mode; mask the exception
4284 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
4285 emit_opcode(cbuf,0x2D);
4286 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
4287 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
4288 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
4290 // Load the converted int; adjust CPU stack
4291 emit_opcode(cbuf,0x58); // POP EAX
4293 emit_opcode(cbuf,0x5A); // POP EDX
4295 emit_opcode(cbuf,0x81); // CMP EDX,imm
4296 emit_d8 (cbuf,0xFA); // rdx
4297 emit_d32 (cbuf,0x80000000);// 0x80000000
4299 emit_opcode(cbuf,0x75); // JNE around_slow_call
4300 emit_d8 (cbuf,0x13+4); // Size of slow_call
4302 emit_opcode(cbuf,0x85); // TEST EAX,EAX
4303 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
4305 emit_opcode(cbuf,0x75); // JNE around_slow_call
4306 emit_d8 (cbuf,0x13); // Size of slow_call
4308 // Allocate a word
4309 emit_opcode(cbuf,0x83); // SUB ESP,4
4310 emit_opcode(cbuf,0xEC);
4311 emit_d8(cbuf,0x04);
4313 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
4314 emit_opcode (cbuf, 0x0F );
4315 emit_opcode (cbuf, 0x11 );
4316 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4318 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4319 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4321 emit_opcode(cbuf,0x83); // ADD ESP,4
4322 emit_opcode(cbuf,0xC4);
4323 emit_d8(cbuf,0x04);
4325 // CALL directly to the runtime
4326 cbuf.set_inst_mark();
4327 emit_opcode(cbuf,0xE8); // Call into runtime
4328 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4329 // Carry on here...
4330 %}
4332 enc_class XD2L_encoding( regXD src ) %{
4333 // Allocate a word
4334 emit_opcode(cbuf,0x83); // SUB ESP,8
4335 emit_opcode(cbuf,0xEC);
4336 emit_d8(cbuf,0x08);
4338 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
4339 emit_opcode (cbuf, 0x0F );
4340 emit_opcode (cbuf, 0x11 );
4341 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4343 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
4344 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4346 emit_opcode(cbuf,0xD9); // FLDCW trunc
4347 emit_opcode(cbuf,0x2D);
4348 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
4350 // Encoding assumes a double has been pushed into FPR0.
4351 // Store down the double as a long, popping the FPU stack
4352 emit_opcode(cbuf,0xDF); // FISTP [ESP]
4353 emit_opcode(cbuf,0x3C);
4354 emit_d8(cbuf,0x24);
4356 // Restore the rounding mode; mask the exception
4357 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
4358 emit_opcode(cbuf,0x2D);
4359 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
4360 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
4361 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
4363 // Load the converted int; adjust CPU stack
4364 emit_opcode(cbuf,0x58); // POP EAX
4366 emit_opcode(cbuf,0x5A); // POP EDX
4368 emit_opcode(cbuf,0x81); // CMP EDX,imm
4369 emit_d8 (cbuf,0xFA); // rdx
4370 emit_d32 (cbuf,0x80000000); // 0x80000000
4372 emit_opcode(cbuf,0x75); // JNE around_slow_call
4373 emit_d8 (cbuf,0x13+4); // Size of slow_call
4375 emit_opcode(cbuf,0x85); // TEST EAX,EAX
4376 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
4378 emit_opcode(cbuf,0x75); // JNE around_slow_call
4379 emit_d8 (cbuf,0x13); // Size of slow_call
4381 // Push src onto stack slow-path
4382 // Allocate a word
4383 emit_opcode(cbuf,0x83); // SUB ESP,8
4384 emit_opcode(cbuf,0xEC);
4385 emit_d8(cbuf,0x08);
4387 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
4388 emit_opcode (cbuf, 0x0F );
4389 emit_opcode (cbuf, 0x11 );
4390 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4392 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
4393 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4395 emit_opcode(cbuf,0x83); // ADD ESP,8
4396 emit_opcode(cbuf,0xC4);
4397 emit_d8(cbuf,0x08);
4399 // CALL directly to the runtime
4400 cbuf.set_inst_mark();
4401 emit_opcode(cbuf,0xE8); // Call into runtime
4402 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4403 // Carry on here...
4404 %}
4406 enc_class D2X_encoding( regX dst, regD src ) %{
4407 // Allocate a word
4408 emit_opcode(cbuf,0x83); // SUB ESP,4
4409 emit_opcode(cbuf,0xEC);
4410 emit_d8(cbuf,0x04);
4411 int pop = 0x02;
4412 if ($src$$reg != FPR1L_enc) {
4413 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
4414 emit_d8( cbuf, 0xC0-1+$src$$reg );
4415 pop = 0x03;
4416 }
4417 store_to_stackslot( cbuf, 0xD9, pop, 0 ); // FST<P>_S [ESP]
4419 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
4420 emit_opcode (cbuf, 0x0F );
4421 emit_opcode (cbuf, 0x10 );
4422 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
4424 emit_opcode(cbuf,0x83); // ADD ESP,4
4425 emit_opcode(cbuf,0xC4);
4426 emit_d8(cbuf,0x04);
4427 // Carry on here...
4428 %}
4430 enc_class FX2I_encoding( regX src, eRegI dst ) %{
4431 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
4433 // Compare the result to see if we need to go to the slow path
4434 emit_opcode(cbuf,0x81); // CMP dst,imm
4435 emit_rm (cbuf,0x3,0x7,$dst$$reg);
4436 emit_d32 (cbuf,0x80000000); // 0x80000000
4438 emit_opcode(cbuf,0x75); // JNE around_slow_call
4439 emit_d8 (cbuf,0x13); // Size of slow_call
4440 // Store xmm to a temp memory
4441 // location and push it onto stack.
4443 emit_opcode(cbuf,0x83); // SUB ESP,4
4444 emit_opcode(cbuf,0xEC);
4445 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4447 emit_opcode (cbuf, $primary ? 0xF2 : 0xF3 ); // MOVSS [ESP], xmm
4448 emit_opcode (cbuf, 0x0F );
4449 emit_opcode (cbuf, 0x11 );
4450 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4452 emit_opcode(cbuf, $primary ? 0xDD : 0xD9 ); // FLD [ESP]
4453 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4455 emit_opcode(cbuf,0x83); // ADD ESP,4
4456 emit_opcode(cbuf,0xC4);
4457 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4459 // CALL directly to the runtime
4460 cbuf.set_inst_mark();
4461 emit_opcode(cbuf,0xE8); // Call into runtime
4462 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4464 // Carry on here...
4465 %}
4467 enc_class X2D_encoding( regD dst, regX src ) %{
4468 // Allocate a word
4469 emit_opcode(cbuf,0x83); // SUB ESP,4
4470 emit_opcode(cbuf,0xEC);
4471 emit_d8(cbuf,0x04);
4473 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], xmm
4474 emit_opcode (cbuf, 0x0F );
4475 emit_opcode (cbuf, 0x11 );
4476 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4478 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4479 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4481 emit_opcode(cbuf,0x83); // ADD ESP,4
4482 emit_opcode(cbuf,0xC4);
4483 emit_d8(cbuf,0x04);
4485 // Carry on here...
4486 %}
4488 enc_class AbsXF_encoding(regX dst) %{
4489 address signmask_address=(address)float_signmask_pool;
4490 // andpd:\tANDPS $dst,[signconst]
4491 emit_opcode(cbuf, 0x0F);
4492 emit_opcode(cbuf, 0x54);
4493 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4494 emit_d32(cbuf, (int)signmask_address);
4495 %}
4497 enc_class AbsXD_encoding(regXD dst) %{
4498 address signmask_address=(address)double_signmask_pool;
4499 // andpd:\tANDPD $dst,[signconst]
4500 emit_opcode(cbuf, 0x66);
4501 emit_opcode(cbuf, 0x0F);
4502 emit_opcode(cbuf, 0x54);
4503 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4504 emit_d32(cbuf, (int)signmask_address);
4505 %}
4507 enc_class NegXF_encoding(regX dst) %{
4508 address signmask_address=(address)float_signflip_pool;
4509 // andpd:\tXORPS $dst,[signconst]
4510 emit_opcode(cbuf, 0x0F);
4511 emit_opcode(cbuf, 0x57);
4512 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4513 emit_d32(cbuf, (int)signmask_address);
4514 %}
4516 enc_class NegXD_encoding(regXD dst) %{
4517 address signmask_address=(address)double_signflip_pool;
4518 // andpd:\tXORPD $dst,[signconst]
4519 emit_opcode(cbuf, 0x66);
4520 emit_opcode(cbuf, 0x0F);
4521 emit_opcode(cbuf, 0x57);
4522 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4523 emit_d32(cbuf, (int)signmask_address);
4524 %}
4526 enc_class FMul_ST_reg( eRegF src1 ) %{
4527 // Operand was loaded from memory into fp ST (stack top)
4528 // FMUL ST,$src /* D8 C8+i */
4529 emit_opcode(cbuf, 0xD8);
4530 emit_opcode(cbuf, 0xC8 + $src1$$reg);
4531 %}
4533 enc_class FAdd_ST_reg( eRegF src2 ) %{
4534 // FADDP ST,src2 /* D8 C0+i */
4535 emit_opcode(cbuf, 0xD8);
4536 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4537 //could use FADDP src2,fpST /* DE C0+i */
4538 %}
4540 enc_class FAddP_reg_ST( eRegF src2 ) %{
4541 // FADDP src2,ST /* DE C0+i */
4542 emit_opcode(cbuf, 0xDE);
4543 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4544 %}
4546 enc_class subF_divF_encode( eRegF src1, eRegF src2) %{
4547 // Operand has been loaded into fp ST (stack top)
4548 // FSUB ST,$src1
4549 emit_opcode(cbuf, 0xD8);
4550 emit_opcode(cbuf, 0xE0 + $src1$$reg);
4552 // FDIV
4553 emit_opcode(cbuf, 0xD8);
4554 emit_opcode(cbuf, 0xF0 + $src2$$reg);
4555 %}
4557 enc_class MulFAddF (eRegF src1, eRegF src2) %{
4558 // Operand was loaded from memory into fp ST (stack top)
4559 // FADD ST,$src /* D8 C0+i */
4560 emit_opcode(cbuf, 0xD8);
4561 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4563 // FMUL ST,src2 /* D8 C*+i */
4564 emit_opcode(cbuf, 0xD8);
4565 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4566 %}
4569 enc_class MulFAddFreverse (eRegF src1, eRegF src2) %{
4570 // Operand was loaded from memory into fp ST (stack top)
4571 // FADD ST,$src /* D8 C0+i */
4572 emit_opcode(cbuf, 0xD8);
4573 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4575 // FMULP src2,ST /* DE C8+i */
4576 emit_opcode(cbuf, 0xDE);
4577 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4578 %}
4580 // Atomically load the volatile long
4581 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
4582 emit_opcode(cbuf,0xDF);
4583 int rm_byte_opcode = 0x05;
4584 int base = $mem$$base;
4585 int index = $mem$$index;
4586 int scale = $mem$$scale;
4587 int displace = $mem$$disp;
4588 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4589 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4590 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
4591 %}
4593 enc_class enc_loadLX_volatile( memory mem, stackSlotL dst, regXD tmp ) %{
4594 { // Atomic long load
4595 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4596 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4597 emit_opcode(cbuf,0x0F);
4598 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4599 int base = $mem$$base;
4600 int index = $mem$$index;
4601 int scale = $mem$$scale;
4602 int displace = $mem$$disp;
4603 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4604 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4605 }
4606 { // MOVSD $dst,$tmp ! atomic long store
4607 emit_opcode(cbuf,0xF2);
4608 emit_opcode(cbuf,0x0F);
4609 emit_opcode(cbuf,0x11);
4610 int base = $dst$$base;
4611 int index = $dst$$index;
4612 int scale = $dst$$scale;
4613 int displace = $dst$$disp;
4614 bool disp_is_oop = $dst->disp_is_oop(); // disp-as-oop when working with static globals
4615 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4616 }
4617 %}
4619 enc_class enc_loadLX_reg_volatile( memory mem, eRegL dst, regXD tmp ) %{
4620 { // Atomic long load
4621 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4622 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4623 emit_opcode(cbuf,0x0F);
4624 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4625 int base = $mem$$base;
4626 int index = $mem$$index;
4627 int scale = $mem$$scale;
4628 int displace = $mem$$disp;
4629 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4630 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4631 }
4632 { // MOVD $dst.lo,$tmp
4633 emit_opcode(cbuf,0x66);
4634 emit_opcode(cbuf,0x0F);
4635 emit_opcode(cbuf,0x7E);
4636 emit_rm(cbuf, 0x3, $tmp$$reg, $dst$$reg);
4637 }
4638 { // PSRLQ $tmp,32
4639 emit_opcode(cbuf,0x66);
4640 emit_opcode(cbuf,0x0F);
4641 emit_opcode(cbuf,0x73);
4642 emit_rm(cbuf, 0x3, 0x02, $tmp$$reg);
4643 emit_d8(cbuf, 0x20);
4644 }
4645 { // MOVD $dst.hi,$tmp
4646 emit_opcode(cbuf,0x66);
4647 emit_opcode(cbuf,0x0F);
4648 emit_opcode(cbuf,0x7E);
4649 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
4650 }
4651 %}
4653 // Volatile Store Long. Must be atomic, so move it into
4654 // the FP TOS and then do a 64-bit FIST. Has to probe the
4655 // target address before the store (for null-ptr checks)
4656 // so the memory operand is used twice in the encoding.
4657 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
4658 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
4659 cbuf.set_inst_mark(); // Mark start of FIST in case $mem has an oop
4660 emit_opcode(cbuf,0xDF);
4661 int rm_byte_opcode = 0x07;
4662 int base = $mem$$base;
4663 int index = $mem$$index;
4664 int scale = $mem$$scale;
4665 int displace = $mem$$disp;
4666 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4667 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4668 %}
4670 enc_class enc_storeLX_volatile( memory mem, stackSlotL src, regXD tmp) %{
4671 { // Atomic long load
4672 // UseXmmLoadAndClearUpper ? movsd $tmp,[$src] : movlpd $tmp,[$src]
4673 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4674 emit_opcode(cbuf,0x0F);
4675 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4676 int base = $src$$base;
4677 int index = $src$$index;
4678 int scale = $src$$scale;
4679 int displace = $src$$disp;
4680 bool disp_is_oop = $src->disp_is_oop(); // disp-as-oop when working with static globals
4681 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4682 }
4683 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop
4684 { // MOVSD $mem,$tmp ! atomic long store
4685 emit_opcode(cbuf,0xF2);
4686 emit_opcode(cbuf,0x0F);
4687 emit_opcode(cbuf,0x11);
4688 int base = $mem$$base;
4689 int index = $mem$$index;
4690 int scale = $mem$$scale;
4691 int displace = $mem$$disp;
4692 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4693 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4694 }
4695 %}
4697 enc_class enc_storeLX_reg_volatile( memory mem, eRegL src, regXD tmp, regXD tmp2) %{
4698 { // MOVD $tmp,$src.lo
4699 emit_opcode(cbuf,0x66);
4700 emit_opcode(cbuf,0x0F);
4701 emit_opcode(cbuf,0x6E);
4702 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
4703 }
4704 { // MOVD $tmp2,$src.hi
4705 emit_opcode(cbuf,0x66);
4706 emit_opcode(cbuf,0x0F);
4707 emit_opcode(cbuf,0x6E);
4708 emit_rm(cbuf, 0x3, $tmp2$$reg, HIGH_FROM_LOW($src$$reg));
4709 }
4710 { // PUNPCKLDQ $tmp,$tmp2
4711 emit_opcode(cbuf,0x66);
4712 emit_opcode(cbuf,0x0F);
4713 emit_opcode(cbuf,0x62);
4714 emit_rm(cbuf, 0x3, $tmp$$reg, $tmp2$$reg);
4715 }
4716 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop
4717 { // MOVSD $mem,$tmp ! atomic long store
4718 emit_opcode(cbuf,0xF2);
4719 emit_opcode(cbuf,0x0F);
4720 emit_opcode(cbuf,0x11);
4721 int base = $mem$$base;
4722 int index = $mem$$index;
4723 int scale = $mem$$scale;
4724 int displace = $mem$$disp;
4725 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4726 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4727 }
4728 %}
4730 // Safepoint Poll. This polls the safepoint page, and causes an
4731 // exception if it is not readable. Unfortunately, it kills the condition code
4732 // in the process
4733 // We current use TESTL [spp],EDI
4734 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
4736 enc_class Safepoint_Poll() %{
4737 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_type, 0);
4738 emit_opcode(cbuf,0x85);
4739 emit_rm (cbuf, 0x0, 0x7, 0x5);
4740 emit_d32(cbuf, (intptr_t)os::get_polling_page());
4741 %}
4742 %}
4745 //----------FRAME--------------------------------------------------------------
4746 // Definition of frame structure and management information.
4747 //
4748 // S T A C K L A Y O U T Allocators stack-slot number
4749 // | (to get allocators register number
4750 // G Owned by | | v add OptoReg::stack0())
4751 // r CALLER | |
4752 // o | +--------+ pad to even-align allocators stack-slot
4753 // w V | pad0 | numbers; owned by CALLER
4754 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
4755 // h ^ | in | 5
4756 // | | args | 4 Holes in incoming args owned by SELF
4757 // | | | | 3
4758 // | | +--------+
4759 // V | | old out| Empty on Intel, window on Sparc
4760 // | old |preserve| Must be even aligned.
4761 // | SP-+--------+----> Matcher::_old_SP, even aligned
4762 // | | in | 3 area for Intel ret address
4763 // Owned by |preserve| Empty on Sparc.
4764 // SELF +--------+
4765 // | | pad2 | 2 pad to align old SP
4766 // | +--------+ 1
4767 // | | locks | 0
4768 // | +--------+----> OptoReg::stack0(), even aligned
4769 // | | pad1 | 11 pad to align new SP
4770 // | +--------+
4771 // | | | 10
4772 // | | spills | 9 spills
4773 // V | | 8 (pad0 slot for callee)
4774 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
4775 // ^ | out | 7
4776 // | | args | 6 Holes in outgoing args owned by CALLEE
4777 // Owned by +--------+
4778 // CALLEE | new out| 6 Empty on Intel, window on Sparc
4779 // | new |preserve| Must be even-aligned.
4780 // | SP-+--------+----> Matcher::_new_SP, even aligned
4781 // | | |
4782 //
4783 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
4784 // known from SELF's arguments and the Java calling convention.
4785 // Region 6-7 is determined per call site.
4786 // Note 2: If the calling convention leaves holes in the incoming argument
4787 // area, those holes are owned by SELF. Holes in the outgoing area
4788 // are owned by the CALLEE. Holes should not be nessecary in the
4789 // incoming area, as the Java calling convention is completely under
4790 // the control of the AD file. Doubles can be sorted and packed to
4791 // avoid holes. Holes in the outgoing arguments may be nessecary for
4792 // varargs C calling conventions.
4793 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
4794 // even aligned with pad0 as needed.
4795 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
4796 // region 6-11 is even aligned; it may be padded out more so that
4797 // the region from SP to FP meets the minimum stack alignment.
4799 frame %{
4800 // What direction does stack grow in (assumed to be same for C & Java)
4801 stack_direction(TOWARDS_LOW);
4803 // These three registers define part of the calling convention
4804 // between compiled code and the interpreter.
4805 inline_cache_reg(EAX); // Inline Cache Register
4806 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
4808 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
4809 cisc_spilling_operand_name(indOffset32);
4811 // Number of stack slots consumed by locking an object
4812 sync_stack_slots(1);
4814 // Compiled code's Frame Pointer
4815 frame_pointer(ESP);
4816 // Interpreter stores its frame pointer in a register which is
4817 // stored to the stack by I2CAdaptors.
4818 // I2CAdaptors convert from interpreted java to compiled java.
4819 interpreter_frame_pointer(EBP);
4821 // Stack alignment requirement
4822 // Alignment size in bytes (128-bit -> 16 bytes)
4823 stack_alignment(StackAlignmentInBytes);
4825 // Number of stack slots between incoming argument block and the start of
4826 // a new frame. The PROLOG must add this many slots to the stack. The
4827 // EPILOG must remove this many slots. Intel needs one slot for
4828 // return address and one for rbp, (must save rbp)
4829 in_preserve_stack_slots(2+VerifyStackAtCalls);
4831 // Number of outgoing stack slots killed above the out_preserve_stack_slots
4832 // for calls to C. Supports the var-args backing area for register parms.
4833 varargs_C_out_slots_killed(0);
4835 // The after-PROLOG location of the return address. Location of
4836 // return address specifies a type (REG or STACK) and a number
4837 // representing the register number (i.e. - use a register name) or
4838 // stack slot.
4839 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
4840 // Otherwise, it is above the locks and verification slot and alignment word
4841 return_addr(STACK - 1 +
4842 round_to(1+VerifyStackAtCalls+
4843 Compile::current()->fixed_slots(),
4844 (StackAlignmentInBytes/wordSize)));
4846 // Body of function which returns an integer array locating
4847 // arguments either in registers or in stack slots. Passed an array
4848 // of ideal registers called "sig" and a "length" count. Stack-slot
4849 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4850 // arguments for a CALLEE. Incoming stack arguments are
4851 // automatically biased by the preserve_stack_slots field above.
4852 calling_convention %{
4853 // No difference between ingoing/outgoing just pass false
4854 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
4855 %}
4858 // Body of function which returns an integer array locating
4859 // arguments either in registers or in stack slots. Passed an array
4860 // of ideal registers called "sig" and a "length" count. Stack-slot
4861 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4862 // arguments for a CALLEE. Incoming stack arguments are
4863 // automatically biased by the preserve_stack_slots field above.
4864 c_calling_convention %{
4865 // This is obviously always outgoing
4866 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
4867 %}
4869 // Location of C & interpreter return values
4870 c_return_value %{
4871 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4872 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4873 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4875 // in SSE2+ mode we want to keep the FPU stack clean so pretend
4876 // that C functions return float and double results in XMM0.
4877 if( ideal_reg == Op_RegD && UseSSE>=2 )
4878 return OptoRegPair(XMM0b_num,XMM0a_num);
4879 if( ideal_reg == Op_RegF && UseSSE>=2 )
4880 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4882 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4883 %}
4885 // Location of return values
4886 return_value %{
4887 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4888 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4889 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4890 if( ideal_reg == Op_RegD && UseSSE>=2 )
4891 return OptoRegPair(XMM0b_num,XMM0a_num);
4892 if( ideal_reg == Op_RegF && UseSSE>=1 )
4893 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4894 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4895 %}
4897 %}
4899 //----------ATTRIBUTES---------------------------------------------------------
4900 //----------Operand Attributes-------------------------------------------------
4901 op_attrib op_cost(0); // Required cost attribute
4903 //----------Instruction Attributes---------------------------------------------
4904 ins_attrib ins_cost(100); // Required cost attribute
4905 ins_attrib ins_size(8); // Required size attribute (in bits)
4906 ins_attrib ins_pc_relative(0); // Required PC Relative flag
4907 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
4908 // non-matching short branch variant of some
4909 // long branch?
4910 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
4911 // specifies the alignment that some part of the instruction (not
4912 // necessarily the start) requires. If > 1, a compute_padding()
4913 // function must be provided for the instruction
4915 //----------OPERANDS-----------------------------------------------------------
4916 // Operand definitions must precede instruction definitions for correct parsing
4917 // in the ADLC because operands constitute user defined types which are used in
4918 // instruction definitions.
4920 //----------Simple Operands----------------------------------------------------
4921 // Immediate Operands
4922 // Integer Immediate
4923 operand immI() %{
4924 match(ConI);
4926 op_cost(10);
4927 format %{ %}
4928 interface(CONST_INTER);
4929 %}
4931 // Constant for test vs zero
4932 operand immI0() %{
4933 predicate(n->get_int() == 0);
4934 match(ConI);
4936 op_cost(0);
4937 format %{ %}
4938 interface(CONST_INTER);
4939 %}
4941 // Constant for increment
4942 operand immI1() %{
4943 predicate(n->get_int() == 1);
4944 match(ConI);
4946 op_cost(0);
4947 format %{ %}
4948 interface(CONST_INTER);
4949 %}
4951 // Constant for decrement
4952 operand immI_M1() %{
4953 predicate(n->get_int() == -1);
4954 match(ConI);
4956 op_cost(0);
4957 format %{ %}
4958 interface(CONST_INTER);
4959 %}
4961 // Valid scale values for addressing modes
4962 operand immI2() %{
4963 predicate(0 <= n->get_int() && (n->get_int() <= 3));
4964 match(ConI);
4966 format %{ %}
4967 interface(CONST_INTER);
4968 %}
4970 operand immI8() %{
4971 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
4972 match(ConI);
4974 op_cost(5);
4975 format %{ %}
4976 interface(CONST_INTER);
4977 %}
4979 operand immI16() %{
4980 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
4981 match(ConI);
4983 op_cost(10);
4984 format %{ %}
4985 interface(CONST_INTER);
4986 %}
4988 // Constant for long shifts
4989 operand immI_32() %{
4990 predicate( n->get_int() == 32 );
4991 match(ConI);
4993 op_cost(0);
4994 format %{ %}
4995 interface(CONST_INTER);
4996 %}
4998 operand immI_1_31() %{
4999 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
5000 match(ConI);
5002 op_cost(0);
5003 format %{ %}
5004 interface(CONST_INTER);
5005 %}
5007 operand immI_32_63() %{
5008 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
5009 match(ConI);
5010 op_cost(0);
5012 format %{ %}
5013 interface(CONST_INTER);
5014 %}
5016 operand immI_1() %{
5017 predicate( n->get_int() == 1 );
5018 match(ConI);
5020 op_cost(0);
5021 format %{ %}
5022 interface(CONST_INTER);
5023 %}
5025 operand immI_2() %{
5026 predicate( n->get_int() == 2 );
5027 match(ConI);
5029 op_cost(0);
5030 format %{ %}
5031 interface(CONST_INTER);
5032 %}
5034 operand immI_3() %{
5035 predicate( n->get_int() == 3 );
5036 match(ConI);
5038 op_cost(0);
5039 format %{ %}
5040 interface(CONST_INTER);
5041 %}
5043 // Pointer Immediate
5044 operand immP() %{
5045 match(ConP);
5047 op_cost(10);
5048 format %{ %}
5049 interface(CONST_INTER);
5050 %}
5052 // NULL Pointer Immediate
5053 operand immP0() %{
5054 predicate( n->get_ptr() == 0 );
5055 match(ConP);
5056 op_cost(0);
5058 format %{ %}
5059 interface(CONST_INTER);
5060 %}
5062 // Long Immediate
5063 operand immL() %{
5064 match(ConL);
5066 op_cost(20);
5067 format %{ %}
5068 interface(CONST_INTER);
5069 %}
5071 // Long Immediate zero
5072 operand immL0() %{
5073 predicate( n->get_long() == 0L );
5074 match(ConL);
5075 op_cost(0);
5077 format %{ %}
5078 interface(CONST_INTER);
5079 %}
5081 // Long Immediate zero
5082 operand immL_M1() %{
5083 predicate( n->get_long() == -1L );
5084 match(ConL);
5085 op_cost(0);
5087 format %{ %}
5088 interface(CONST_INTER);
5089 %}
5091 // Long immediate from 0 to 127.
5092 // Used for a shorter form of long mul by 10.
5093 operand immL_127() %{
5094 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
5095 match(ConL);
5096 op_cost(0);
5098 format %{ %}
5099 interface(CONST_INTER);
5100 %}
5102 // Long Immediate: low 32-bit mask
5103 operand immL_32bits() %{
5104 predicate(n->get_long() == 0xFFFFFFFFL);
5105 match(ConL);
5106 op_cost(0);
5108 format %{ %}
5109 interface(CONST_INTER);
5110 %}
5112 // Long Immediate: low 32-bit mask
5113 operand immL32() %{
5114 predicate(n->get_long() == (int)(n->get_long()));
5115 match(ConL);
5116 op_cost(20);
5118 format %{ %}
5119 interface(CONST_INTER);
5120 %}
5122 //Double Immediate zero
5123 operand immD0() %{
5124 // Do additional (and counter-intuitive) test against NaN to work around VC++
5125 // bug that generates code such that NaNs compare equal to 0.0
5126 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
5127 match(ConD);
5129 op_cost(5);
5130 format %{ %}
5131 interface(CONST_INTER);
5132 %}
5134 // Double Immediate
5135 operand immD1() %{
5136 predicate( UseSSE<=1 && n->getd() == 1.0 );
5137 match(ConD);
5139 op_cost(5);
5140 format %{ %}
5141 interface(CONST_INTER);
5142 %}
5144 // Double Immediate
5145 operand immD() %{
5146 predicate(UseSSE<=1);
5147 match(ConD);
5149 op_cost(5);
5150 format %{ %}
5151 interface(CONST_INTER);
5152 %}
5154 operand immXD() %{
5155 predicate(UseSSE>=2);
5156 match(ConD);
5158 op_cost(5);
5159 format %{ %}
5160 interface(CONST_INTER);
5161 %}
5163 // Double Immediate zero
5164 operand immXD0() %{
5165 // Do additional (and counter-intuitive) test against NaN to work around VC++
5166 // bug that generates code such that NaNs compare equal to 0.0 AND do not
5167 // compare equal to -0.0.
5168 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
5169 match(ConD);
5171 format %{ %}
5172 interface(CONST_INTER);
5173 %}
5175 // Float Immediate zero
5176 operand immF0() %{
5177 predicate( UseSSE == 0 && n->getf() == 0.0 );
5178 match(ConF);
5180 op_cost(5);
5181 format %{ %}
5182 interface(CONST_INTER);
5183 %}
5185 // Float Immediate
5186 operand immF() %{
5187 predicate( UseSSE == 0 );
5188 match(ConF);
5190 op_cost(5);
5191 format %{ %}
5192 interface(CONST_INTER);
5193 %}
5195 // Float Immediate
5196 operand immXF() %{
5197 predicate(UseSSE >= 1);
5198 match(ConF);
5200 op_cost(5);
5201 format %{ %}
5202 interface(CONST_INTER);
5203 %}
5205 // Float Immediate zero. Zero and not -0.0
5206 operand immXF0() %{
5207 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
5208 match(ConF);
5210 op_cost(5);
5211 format %{ %}
5212 interface(CONST_INTER);
5213 %}
5215 // Immediates for special shifts (sign extend)
5217 // Constants for increment
5218 operand immI_16() %{
5219 predicate( n->get_int() == 16 );
5220 match(ConI);
5222 format %{ %}
5223 interface(CONST_INTER);
5224 %}
5226 operand immI_24() %{
5227 predicate( n->get_int() == 24 );
5228 match(ConI);
5230 format %{ %}
5231 interface(CONST_INTER);
5232 %}
5234 // Constant for byte-wide masking
5235 operand immI_255() %{
5236 predicate( n->get_int() == 255 );
5237 match(ConI);
5239 format %{ %}
5240 interface(CONST_INTER);
5241 %}
5243 // Constant for short-wide masking
5244 operand immI_65535() %{
5245 predicate(n->get_int() == 65535);
5246 match(ConI);
5248 format %{ %}
5249 interface(CONST_INTER);
5250 %}
5252 // Register Operands
5253 // Integer Register
5254 operand eRegI() %{
5255 constraint(ALLOC_IN_RC(e_reg));
5256 match(RegI);
5257 match(xRegI);
5258 match(eAXRegI);
5259 match(eBXRegI);
5260 match(eCXRegI);
5261 match(eDXRegI);
5262 match(eDIRegI);
5263 match(eSIRegI);
5265 format %{ %}
5266 interface(REG_INTER);
5267 %}
5269 // Subset of Integer Register
5270 operand xRegI(eRegI reg) %{
5271 constraint(ALLOC_IN_RC(x_reg));
5272 match(reg);
5273 match(eAXRegI);
5274 match(eBXRegI);
5275 match(eCXRegI);
5276 match(eDXRegI);
5278 format %{ %}
5279 interface(REG_INTER);
5280 %}
5282 // Special Registers
5283 operand eAXRegI(xRegI reg) %{
5284 constraint(ALLOC_IN_RC(eax_reg));
5285 match(reg);
5286 match(eRegI);
5288 format %{ "EAX" %}
5289 interface(REG_INTER);
5290 %}
5292 // Special Registers
5293 operand eBXRegI(xRegI reg) %{
5294 constraint(ALLOC_IN_RC(ebx_reg));
5295 match(reg);
5296 match(eRegI);
5298 format %{ "EBX" %}
5299 interface(REG_INTER);
5300 %}
5302 operand eCXRegI(xRegI reg) %{
5303 constraint(ALLOC_IN_RC(ecx_reg));
5304 match(reg);
5305 match(eRegI);
5307 format %{ "ECX" %}
5308 interface(REG_INTER);
5309 %}
5311 operand eDXRegI(xRegI reg) %{
5312 constraint(ALLOC_IN_RC(edx_reg));
5313 match(reg);
5314 match(eRegI);
5316 format %{ "EDX" %}
5317 interface(REG_INTER);
5318 %}
5320 operand eDIRegI(xRegI reg) %{
5321 constraint(ALLOC_IN_RC(edi_reg));
5322 match(reg);
5323 match(eRegI);
5325 format %{ "EDI" %}
5326 interface(REG_INTER);
5327 %}
5329 operand naxRegI() %{
5330 constraint(ALLOC_IN_RC(nax_reg));
5331 match(RegI);
5332 match(eCXRegI);
5333 match(eDXRegI);
5334 match(eSIRegI);
5335 match(eDIRegI);
5337 format %{ %}
5338 interface(REG_INTER);
5339 %}
5341 operand nadxRegI() %{
5342 constraint(ALLOC_IN_RC(nadx_reg));
5343 match(RegI);
5344 match(eBXRegI);
5345 match(eCXRegI);
5346 match(eSIRegI);
5347 match(eDIRegI);
5349 format %{ %}
5350 interface(REG_INTER);
5351 %}
5353 operand ncxRegI() %{
5354 constraint(ALLOC_IN_RC(ncx_reg));
5355 match(RegI);
5356 match(eAXRegI);
5357 match(eDXRegI);
5358 match(eSIRegI);
5359 match(eDIRegI);
5361 format %{ %}
5362 interface(REG_INTER);
5363 %}
5365 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
5366 // //
5367 operand eSIRegI(xRegI reg) %{
5368 constraint(ALLOC_IN_RC(esi_reg));
5369 match(reg);
5370 match(eRegI);
5372 format %{ "ESI" %}
5373 interface(REG_INTER);
5374 %}
5376 // Pointer Register
5377 operand anyRegP() %{
5378 constraint(ALLOC_IN_RC(any_reg));
5379 match(RegP);
5380 match(eAXRegP);
5381 match(eBXRegP);
5382 match(eCXRegP);
5383 match(eDIRegP);
5384 match(eRegP);
5386 format %{ %}
5387 interface(REG_INTER);
5388 %}
5390 operand eRegP() %{
5391 constraint(ALLOC_IN_RC(e_reg));
5392 match(RegP);
5393 match(eAXRegP);
5394 match(eBXRegP);
5395 match(eCXRegP);
5396 match(eDIRegP);
5398 format %{ %}
5399 interface(REG_INTER);
5400 %}
5402 // On windows95, EBP is not safe to use for implicit null tests.
5403 operand eRegP_no_EBP() %{
5404 constraint(ALLOC_IN_RC(e_reg_no_rbp));
5405 match(RegP);
5406 match(eAXRegP);
5407 match(eBXRegP);
5408 match(eCXRegP);
5409 match(eDIRegP);
5411 op_cost(100);
5412 format %{ %}
5413 interface(REG_INTER);
5414 %}
5416 operand naxRegP() %{
5417 constraint(ALLOC_IN_RC(nax_reg));
5418 match(RegP);
5419 match(eBXRegP);
5420 match(eDXRegP);
5421 match(eCXRegP);
5422 match(eSIRegP);
5423 match(eDIRegP);
5425 format %{ %}
5426 interface(REG_INTER);
5427 %}
5429 operand nabxRegP() %{
5430 constraint(ALLOC_IN_RC(nabx_reg));
5431 match(RegP);
5432 match(eCXRegP);
5433 match(eDXRegP);
5434 match(eSIRegP);
5435 match(eDIRegP);
5437 format %{ %}
5438 interface(REG_INTER);
5439 %}
5441 operand pRegP() %{
5442 constraint(ALLOC_IN_RC(p_reg));
5443 match(RegP);
5444 match(eBXRegP);
5445 match(eDXRegP);
5446 match(eSIRegP);
5447 match(eDIRegP);
5449 format %{ %}
5450 interface(REG_INTER);
5451 %}
5453 // Special Registers
5454 // Return a pointer value
5455 operand eAXRegP(eRegP reg) %{
5456 constraint(ALLOC_IN_RC(eax_reg));
5457 match(reg);
5458 format %{ "EAX" %}
5459 interface(REG_INTER);
5460 %}
5462 // Used in AtomicAdd
5463 operand eBXRegP(eRegP reg) %{
5464 constraint(ALLOC_IN_RC(ebx_reg));
5465 match(reg);
5466 format %{ "EBX" %}
5467 interface(REG_INTER);
5468 %}
5470 // Tail-call (interprocedural jump) to interpreter
5471 operand eCXRegP(eRegP reg) %{
5472 constraint(ALLOC_IN_RC(ecx_reg));
5473 match(reg);
5474 format %{ "ECX" %}
5475 interface(REG_INTER);
5476 %}
5478 operand eSIRegP(eRegP reg) %{
5479 constraint(ALLOC_IN_RC(esi_reg));
5480 match(reg);
5481 format %{ "ESI" %}
5482 interface(REG_INTER);
5483 %}
5485 // Used in rep stosw
5486 operand eDIRegP(eRegP reg) %{
5487 constraint(ALLOC_IN_RC(edi_reg));
5488 match(reg);
5489 format %{ "EDI" %}
5490 interface(REG_INTER);
5491 %}
5493 operand eBPRegP() %{
5494 constraint(ALLOC_IN_RC(ebp_reg));
5495 match(RegP);
5496 format %{ "EBP" %}
5497 interface(REG_INTER);
5498 %}
5500 operand eRegL() %{
5501 constraint(ALLOC_IN_RC(long_reg));
5502 match(RegL);
5503 match(eADXRegL);
5505 format %{ %}
5506 interface(REG_INTER);
5507 %}
5509 operand eADXRegL( eRegL reg ) %{
5510 constraint(ALLOC_IN_RC(eadx_reg));
5511 match(reg);
5513 format %{ "EDX:EAX" %}
5514 interface(REG_INTER);
5515 %}
5517 operand eBCXRegL( eRegL reg ) %{
5518 constraint(ALLOC_IN_RC(ebcx_reg));
5519 match(reg);
5521 format %{ "EBX:ECX" %}
5522 interface(REG_INTER);
5523 %}
5525 // Special case for integer high multiply
5526 operand eADXRegL_low_only() %{
5527 constraint(ALLOC_IN_RC(eadx_reg));
5528 match(RegL);
5530 format %{ "EAX" %}
5531 interface(REG_INTER);
5532 %}
5534 // Flags register, used as output of compare instructions
5535 operand eFlagsReg() %{
5536 constraint(ALLOC_IN_RC(int_flags));
5537 match(RegFlags);
5539 format %{ "EFLAGS" %}
5540 interface(REG_INTER);
5541 %}
5543 // Flags register, used as output of FLOATING POINT compare instructions
5544 operand eFlagsRegU() %{
5545 constraint(ALLOC_IN_RC(int_flags));
5546 match(RegFlags);
5548 format %{ "EFLAGS_U" %}
5549 interface(REG_INTER);
5550 %}
5552 operand eFlagsRegUCF() %{
5553 constraint(ALLOC_IN_RC(int_flags));
5554 match(RegFlags);
5555 predicate(false);
5557 format %{ "EFLAGS_U_CF" %}
5558 interface(REG_INTER);
5559 %}
5561 // Condition Code Register used by long compare
5562 operand flagsReg_long_LTGE() %{
5563 constraint(ALLOC_IN_RC(int_flags));
5564 match(RegFlags);
5565 format %{ "FLAGS_LTGE" %}
5566 interface(REG_INTER);
5567 %}
5568 operand flagsReg_long_EQNE() %{
5569 constraint(ALLOC_IN_RC(int_flags));
5570 match(RegFlags);
5571 format %{ "FLAGS_EQNE" %}
5572 interface(REG_INTER);
5573 %}
5574 operand flagsReg_long_LEGT() %{
5575 constraint(ALLOC_IN_RC(int_flags));
5576 match(RegFlags);
5577 format %{ "FLAGS_LEGT" %}
5578 interface(REG_INTER);
5579 %}
5581 // Float register operands
5582 operand regD() %{
5583 predicate( UseSSE < 2 );
5584 constraint(ALLOC_IN_RC(dbl_reg));
5585 match(RegD);
5586 match(regDPR1);
5587 match(regDPR2);
5588 format %{ %}
5589 interface(REG_INTER);
5590 %}
5592 operand regDPR1(regD reg) %{
5593 predicate( UseSSE < 2 );
5594 constraint(ALLOC_IN_RC(dbl_reg0));
5595 match(reg);
5596 format %{ "FPR1" %}
5597 interface(REG_INTER);
5598 %}
5600 operand regDPR2(regD reg) %{
5601 predicate( UseSSE < 2 );
5602 constraint(ALLOC_IN_RC(dbl_reg1));
5603 match(reg);
5604 format %{ "FPR2" %}
5605 interface(REG_INTER);
5606 %}
5608 operand regnotDPR1(regD reg) %{
5609 predicate( UseSSE < 2 );
5610 constraint(ALLOC_IN_RC(dbl_notreg0));
5611 match(reg);
5612 format %{ %}
5613 interface(REG_INTER);
5614 %}
5616 // XMM Double register operands
5617 operand regXD() %{
5618 predicate( UseSSE>=2 );
5619 constraint(ALLOC_IN_RC(xdb_reg));
5620 match(RegD);
5621 match(regXD6);
5622 match(regXD7);
5623 format %{ %}
5624 interface(REG_INTER);
5625 %}
5627 // XMM6 double register operands
5628 operand regXD6(regXD reg) %{
5629 predicate( UseSSE>=2 );
5630 constraint(ALLOC_IN_RC(xdb_reg6));
5631 match(reg);
5632 format %{ "XMM6" %}
5633 interface(REG_INTER);
5634 %}
5636 // XMM7 double register operands
5637 operand regXD7(regXD reg) %{
5638 predicate( UseSSE>=2 );
5639 constraint(ALLOC_IN_RC(xdb_reg7));
5640 match(reg);
5641 format %{ "XMM7" %}
5642 interface(REG_INTER);
5643 %}
5645 // Float register operands
5646 operand regF() %{
5647 predicate( UseSSE < 2 );
5648 constraint(ALLOC_IN_RC(flt_reg));
5649 match(RegF);
5650 match(regFPR1);
5651 format %{ %}
5652 interface(REG_INTER);
5653 %}
5655 // Float register operands
5656 operand regFPR1(regF reg) %{
5657 predicate( UseSSE < 2 );
5658 constraint(ALLOC_IN_RC(flt_reg0));
5659 match(reg);
5660 format %{ "FPR1" %}
5661 interface(REG_INTER);
5662 %}
5664 // XMM register operands
5665 operand regX() %{
5666 predicate( UseSSE>=1 );
5667 constraint(ALLOC_IN_RC(xmm_reg));
5668 match(RegF);
5669 format %{ %}
5670 interface(REG_INTER);
5671 %}
5674 //----------Memory Operands----------------------------------------------------
5675 // Direct Memory Operand
5676 operand direct(immP addr) %{
5677 match(addr);
5679 format %{ "[$addr]" %}
5680 interface(MEMORY_INTER) %{
5681 base(0xFFFFFFFF);
5682 index(0x4);
5683 scale(0x0);
5684 disp($addr);
5685 %}
5686 %}
5688 // Indirect Memory Operand
5689 operand indirect(eRegP reg) %{
5690 constraint(ALLOC_IN_RC(e_reg));
5691 match(reg);
5693 format %{ "[$reg]" %}
5694 interface(MEMORY_INTER) %{
5695 base($reg);
5696 index(0x4);
5697 scale(0x0);
5698 disp(0x0);
5699 %}
5700 %}
5702 // Indirect Memory Plus Short Offset Operand
5703 operand indOffset8(eRegP reg, immI8 off) %{
5704 match(AddP reg off);
5706 format %{ "[$reg + $off]" %}
5707 interface(MEMORY_INTER) %{
5708 base($reg);
5709 index(0x4);
5710 scale(0x0);
5711 disp($off);
5712 %}
5713 %}
5715 // Indirect Memory Plus Long Offset Operand
5716 operand indOffset32(eRegP reg, immI off) %{
5717 match(AddP reg off);
5719 format %{ "[$reg + $off]" %}
5720 interface(MEMORY_INTER) %{
5721 base($reg);
5722 index(0x4);
5723 scale(0x0);
5724 disp($off);
5725 %}
5726 %}
5728 // Indirect Memory Plus Long Offset Operand
5729 operand indOffset32X(eRegI reg, immP off) %{
5730 match(AddP off reg);
5732 format %{ "[$reg + $off]" %}
5733 interface(MEMORY_INTER) %{
5734 base($reg);
5735 index(0x4);
5736 scale(0x0);
5737 disp($off);
5738 %}
5739 %}
5741 // Indirect Memory Plus Index Register Plus Offset Operand
5742 operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{
5743 match(AddP (AddP reg ireg) off);
5745 op_cost(10);
5746 format %{"[$reg + $off + $ireg]" %}
5747 interface(MEMORY_INTER) %{
5748 base($reg);
5749 index($ireg);
5750 scale(0x0);
5751 disp($off);
5752 %}
5753 %}
5755 // Indirect Memory Plus Index Register Plus Offset Operand
5756 operand indIndex(eRegP reg, eRegI ireg) %{
5757 match(AddP reg ireg);
5759 op_cost(10);
5760 format %{"[$reg + $ireg]" %}
5761 interface(MEMORY_INTER) %{
5762 base($reg);
5763 index($ireg);
5764 scale(0x0);
5765 disp(0x0);
5766 %}
5767 %}
5769 // // -------------------------------------------------------------------------
5770 // // 486 architecture doesn't support "scale * index + offset" with out a base
5771 // // -------------------------------------------------------------------------
5772 // // Scaled Memory Operands
5773 // // Indirect Memory Times Scale Plus Offset Operand
5774 // operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{
5775 // match(AddP off (LShiftI ireg scale));
5776 //
5777 // op_cost(10);
5778 // format %{"[$off + $ireg << $scale]" %}
5779 // interface(MEMORY_INTER) %{
5780 // base(0x4);
5781 // index($ireg);
5782 // scale($scale);
5783 // disp($off);
5784 // %}
5785 // %}
5787 // Indirect Memory Times Scale Plus Index Register
5788 operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{
5789 match(AddP reg (LShiftI ireg scale));
5791 op_cost(10);
5792 format %{"[$reg + $ireg << $scale]" %}
5793 interface(MEMORY_INTER) %{
5794 base($reg);
5795 index($ireg);
5796 scale($scale);
5797 disp(0x0);
5798 %}
5799 %}
5801 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5802 operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{
5803 match(AddP (AddP reg (LShiftI ireg scale)) off);
5805 op_cost(10);
5806 format %{"[$reg + $off + $ireg << $scale]" %}
5807 interface(MEMORY_INTER) %{
5808 base($reg);
5809 index($ireg);
5810 scale($scale);
5811 disp($off);
5812 %}
5813 %}
5815 //----------Load Long Memory Operands------------------------------------------
5816 // The load-long idiom will use it's address expression again after loading
5817 // the first word of the long. If the load-long destination overlaps with
5818 // registers used in the addressing expression, the 2nd half will be loaded
5819 // from a clobbered address. Fix this by requiring that load-long use
5820 // address registers that do not overlap with the load-long target.
5822 // load-long support
5823 operand load_long_RegP() %{
5824 constraint(ALLOC_IN_RC(esi_reg));
5825 match(RegP);
5826 match(eSIRegP);
5827 op_cost(100);
5828 format %{ %}
5829 interface(REG_INTER);
5830 %}
5832 // Indirect Memory Operand Long
5833 operand load_long_indirect(load_long_RegP reg) %{
5834 constraint(ALLOC_IN_RC(esi_reg));
5835 match(reg);
5837 format %{ "[$reg]" %}
5838 interface(MEMORY_INTER) %{
5839 base($reg);
5840 index(0x4);
5841 scale(0x0);
5842 disp(0x0);
5843 %}
5844 %}
5846 // Indirect Memory Plus Long Offset Operand
5847 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
5848 match(AddP reg off);
5850 format %{ "[$reg + $off]" %}
5851 interface(MEMORY_INTER) %{
5852 base($reg);
5853 index(0x4);
5854 scale(0x0);
5855 disp($off);
5856 %}
5857 %}
5859 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
5862 //----------Special Memory Operands--------------------------------------------
5863 // Stack Slot Operand - This operand is used for loading and storing temporary
5864 // values on the stack where a match requires a value to
5865 // flow through memory.
5866 operand stackSlotP(sRegP reg) %{
5867 constraint(ALLOC_IN_RC(stack_slots));
5868 // No match rule because this operand is only generated in matching
5869 format %{ "[$reg]" %}
5870 interface(MEMORY_INTER) %{
5871 base(0x4); // ESP
5872 index(0x4); // No Index
5873 scale(0x0); // No Scale
5874 disp($reg); // Stack Offset
5875 %}
5876 %}
5878 operand stackSlotI(sRegI reg) %{
5879 constraint(ALLOC_IN_RC(stack_slots));
5880 // No match rule because this operand is only generated in matching
5881 format %{ "[$reg]" %}
5882 interface(MEMORY_INTER) %{
5883 base(0x4); // ESP
5884 index(0x4); // No Index
5885 scale(0x0); // No Scale
5886 disp($reg); // Stack Offset
5887 %}
5888 %}
5890 operand stackSlotF(sRegF reg) %{
5891 constraint(ALLOC_IN_RC(stack_slots));
5892 // No match rule because this operand is only generated in matching
5893 format %{ "[$reg]" %}
5894 interface(MEMORY_INTER) %{
5895 base(0x4); // ESP
5896 index(0x4); // No Index
5897 scale(0x0); // No Scale
5898 disp($reg); // Stack Offset
5899 %}
5900 %}
5902 operand stackSlotD(sRegD reg) %{
5903 constraint(ALLOC_IN_RC(stack_slots));
5904 // No match rule because this operand is only generated in matching
5905 format %{ "[$reg]" %}
5906 interface(MEMORY_INTER) %{
5907 base(0x4); // ESP
5908 index(0x4); // No Index
5909 scale(0x0); // No Scale
5910 disp($reg); // Stack Offset
5911 %}
5912 %}
5914 operand stackSlotL(sRegL reg) %{
5915 constraint(ALLOC_IN_RC(stack_slots));
5916 // No match rule because this operand is only generated in matching
5917 format %{ "[$reg]" %}
5918 interface(MEMORY_INTER) %{
5919 base(0x4); // ESP
5920 index(0x4); // No Index
5921 scale(0x0); // No Scale
5922 disp($reg); // Stack Offset
5923 %}
5924 %}
5926 //----------Memory Operands - Win95 Implicit Null Variants----------------
5927 // Indirect Memory Operand
5928 operand indirect_win95_safe(eRegP_no_EBP reg)
5929 %{
5930 constraint(ALLOC_IN_RC(e_reg));
5931 match(reg);
5933 op_cost(100);
5934 format %{ "[$reg]" %}
5935 interface(MEMORY_INTER) %{
5936 base($reg);
5937 index(0x4);
5938 scale(0x0);
5939 disp(0x0);
5940 %}
5941 %}
5943 // Indirect Memory Plus Short Offset Operand
5944 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
5945 %{
5946 match(AddP reg off);
5948 op_cost(100);
5949 format %{ "[$reg + $off]" %}
5950 interface(MEMORY_INTER) %{
5951 base($reg);
5952 index(0x4);
5953 scale(0x0);
5954 disp($off);
5955 %}
5956 %}
5958 // Indirect Memory Plus Long Offset Operand
5959 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
5960 %{
5961 match(AddP reg off);
5963 op_cost(100);
5964 format %{ "[$reg + $off]" %}
5965 interface(MEMORY_INTER) %{
5966 base($reg);
5967 index(0x4);
5968 scale(0x0);
5969 disp($off);
5970 %}
5971 %}
5973 // Indirect Memory Plus Index Register Plus Offset Operand
5974 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off)
5975 %{
5976 match(AddP (AddP reg ireg) off);
5978 op_cost(100);
5979 format %{"[$reg + $off + $ireg]" %}
5980 interface(MEMORY_INTER) %{
5981 base($reg);
5982 index($ireg);
5983 scale(0x0);
5984 disp($off);
5985 %}
5986 %}
5988 // Indirect Memory Times Scale Plus Index Register
5989 operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale)
5990 %{
5991 match(AddP reg (LShiftI ireg scale));
5993 op_cost(100);
5994 format %{"[$reg + $ireg << $scale]" %}
5995 interface(MEMORY_INTER) %{
5996 base($reg);
5997 index($ireg);
5998 scale($scale);
5999 disp(0x0);
6000 %}
6001 %}
6003 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
6004 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale)
6005 %{
6006 match(AddP (AddP reg (LShiftI ireg scale)) off);
6008 op_cost(100);
6009 format %{"[$reg + $off + $ireg << $scale]" %}
6010 interface(MEMORY_INTER) %{
6011 base($reg);
6012 index($ireg);
6013 scale($scale);
6014 disp($off);
6015 %}
6016 %}
6018 //----------Conditional Branch Operands----------------------------------------
6019 // Comparison Op - This is the operation of the comparison, and is limited to
6020 // the following set of codes:
6021 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
6022 //
6023 // Other attributes of the comparison, such as unsignedness, are specified
6024 // by the comparison instruction that sets a condition code flags register.
6025 // That result is represented by a flags operand whose subtype is appropriate
6026 // to the unsignedness (etc.) of the comparison.
6027 //
6028 // Later, the instruction which matches both the Comparison Op (a Bool) and
6029 // the flags (produced by the Cmp) specifies the coding of the comparison op
6030 // by matching a specific subtype of Bool operand below, such as cmpOpU.
6032 // Comparision Code
6033 operand cmpOp() %{
6034 match(Bool);
6036 format %{ "" %}
6037 interface(COND_INTER) %{
6038 equal(0x4, "e");
6039 not_equal(0x5, "ne");
6040 less(0xC, "l");
6041 greater_equal(0xD, "ge");
6042 less_equal(0xE, "le");
6043 greater(0xF, "g");
6044 %}
6045 %}
6047 // Comparison Code, unsigned compare. Used by FP also, with
6048 // C2 (unordered) turned into GT or LT already. The other bits
6049 // C0 and C3 are turned into Carry & Zero flags.
6050 operand cmpOpU() %{
6051 match(Bool);
6053 format %{ "" %}
6054 interface(COND_INTER) %{
6055 equal(0x4, "e");
6056 not_equal(0x5, "ne");
6057 less(0x2, "b");
6058 greater_equal(0x3, "nb");
6059 less_equal(0x6, "be");
6060 greater(0x7, "nbe");
6061 %}
6062 %}
6064 // Floating comparisons that don't require any fixup for the unordered case
6065 operand cmpOpUCF() %{
6066 match(Bool);
6067 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
6068 n->as_Bool()->_test._test == BoolTest::ge ||
6069 n->as_Bool()->_test._test == BoolTest::le ||
6070 n->as_Bool()->_test._test == BoolTest::gt);
6071 format %{ "" %}
6072 interface(COND_INTER) %{
6073 equal(0x4, "e");
6074 not_equal(0x5, "ne");
6075 less(0x2, "b");
6076 greater_equal(0x3, "nb");
6077 less_equal(0x6, "be");
6078 greater(0x7, "nbe");
6079 %}
6080 %}
6083 // Floating comparisons that can be fixed up with extra conditional jumps
6084 operand cmpOpUCF2() %{
6085 match(Bool);
6086 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
6087 n->as_Bool()->_test._test == BoolTest::eq);
6088 format %{ "" %}
6089 interface(COND_INTER) %{
6090 equal(0x4, "e");
6091 not_equal(0x5, "ne");
6092 less(0x2, "b");
6093 greater_equal(0x3, "nb");
6094 less_equal(0x6, "be");
6095 greater(0x7, "nbe");
6096 %}
6097 %}
6099 // Comparison Code for FP conditional move
6100 operand cmpOp_fcmov() %{
6101 match(Bool);
6103 format %{ "" %}
6104 interface(COND_INTER) %{
6105 equal (0x0C8);
6106 not_equal (0x1C8);
6107 less (0x0C0);
6108 greater_equal(0x1C0);
6109 less_equal (0x0D0);
6110 greater (0x1D0);
6111 %}
6112 %}
6114 // Comparision Code used in long compares
6115 operand cmpOp_commute() %{
6116 match(Bool);
6118 format %{ "" %}
6119 interface(COND_INTER) %{
6120 equal(0x4, "e");
6121 not_equal(0x5, "ne");
6122 less(0xF, "g");
6123 greater_equal(0xE, "le");
6124 less_equal(0xD, "ge");
6125 greater(0xC, "l");
6126 %}
6127 %}
6129 //----------OPERAND CLASSES----------------------------------------------------
6130 // Operand Classes are groups of operands that are used as to simplify
6131 // instruction definitions by not requiring the AD writer to specify separate
6132 // instructions for every form of operand when the instruction accepts
6133 // multiple operand types with the same basic encoding and format. The classic
6134 // case of this is memory operands.
6136 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
6137 indIndex, indIndexScale, indIndexScaleOffset);
6139 // Long memory operations are encoded in 2 instructions and a +4 offset.
6140 // This means some kind of offset is always required and you cannot use
6141 // an oop as the offset (done when working on static globals).
6142 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
6143 indIndex, indIndexScale, indIndexScaleOffset);
6146 //----------PIPELINE-----------------------------------------------------------
6147 // Rules which define the behavior of the target architectures pipeline.
6148 pipeline %{
6150 //----------ATTRIBUTES---------------------------------------------------------
6151 attributes %{
6152 variable_size_instructions; // Fixed size instructions
6153 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
6154 instruction_unit_size = 1; // An instruction is 1 bytes long
6155 instruction_fetch_unit_size = 16; // The processor fetches one line
6156 instruction_fetch_units = 1; // of 16 bytes
6158 // List of nop instructions
6159 nops( MachNop );
6160 %}
6162 //----------RESOURCES----------------------------------------------------------
6163 // Resources are the functional units available to the machine
6165 // Generic P2/P3 pipeline
6166 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
6167 // 3 instructions decoded per cycle.
6168 // 2 load/store ops per cycle, 1 branch, 1 FPU,
6169 // 2 ALU op, only ALU0 handles mul/div instructions.
6170 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
6171 MS0, MS1, MEM = MS0 | MS1,
6172 BR, FPU,
6173 ALU0, ALU1, ALU = ALU0 | ALU1 );
6175 //----------PIPELINE DESCRIPTION-----------------------------------------------
6176 // Pipeline Description specifies the stages in the machine's pipeline
6178 // Generic P2/P3 pipeline
6179 pipe_desc(S0, S1, S2, S3, S4, S5);
6181 //----------PIPELINE CLASSES---------------------------------------------------
6182 // Pipeline Classes describe the stages in which input and output are
6183 // referenced by the hardware pipeline.
6185 // Naming convention: ialu or fpu
6186 // Then: _reg
6187 // Then: _reg if there is a 2nd register
6188 // Then: _long if it's a pair of instructions implementing a long
6189 // Then: _fat if it requires the big decoder
6190 // Or: _mem if it requires the big decoder and a memory unit.
6192 // Integer ALU reg operation
6193 pipe_class ialu_reg(eRegI dst) %{
6194 single_instruction;
6195 dst : S4(write);
6196 dst : S3(read);
6197 DECODE : S0; // any decoder
6198 ALU : S3; // any alu
6199 %}
6201 // Long ALU reg operation
6202 pipe_class ialu_reg_long(eRegL dst) %{
6203 instruction_count(2);
6204 dst : S4(write);
6205 dst : S3(read);
6206 DECODE : S0(2); // any 2 decoders
6207 ALU : S3(2); // both alus
6208 %}
6210 // Integer ALU reg operation using big decoder
6211 pipe_class ialu_reg_fat(eRegI dst) %{
6212 single_instruction;
6213 dst : S4(write);
6214 dst : S3(read);
6215 D0 : S0; // big decoder only
6216 ALU : S3; // any alu
6217 %}
6219 // Long ALU reg operation using big decoder
6220 pipe_class ialu_reg_long_fat(eRegL dst) %{
6221 instruction_count(2);
6222 dst : S4(write);
6223 dst : S3(read);
6224 D0 : S0(2); // big decoder only; twice
6225 ALU : S3(2); // any 2 alus
6226 %}
6228 // Integer ALU reg-reg operation
6229 pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{
6230 single_instruction;
6231 dst : S4(write);
6232 src : S3(read);
6233 DECODE : S0; // any decoder
6234 ALU : S3; // any alu
6235 %}
6237 // Long ALU reg-reg operation
6238 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
6239 instruction_count(2);
6240 dst : S4(write);
6241 src : S3(read);
6242 DECODE : S0(2); // any 2 decoders
6243 ALU : S3(2); // both alus
6244 %}
6246 // Integer ALU reg-reg operation
6247 pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{
6248 single_instruction;
6249 dst : S4(write);
6250 src : S3(read);
6251 D0 : S0; // big decoder only
6252 ALU : S3; // any alu
6253 %}
6255 // Long ALU reg-reg operation
6256 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
6257 instruction_count(2);
6258 dst : S4(write);
6259 src : S3(read);
6260 D0 : S0(2); // big decoder only; twice
6261 ALU : S3(2); // both alus
6262 %}
6264 // Integer ALU reg-mem operation
6265 pipe_class ialu_reg_mem(eRegI dst, memory mem) %{
6266 single_instruction;
6267 dst : S5(write);
6268 mem : S3(read);
6269 D0 : S0; // big decoder only
6270 ALU : S4; // any alu
6271 MEM : S3; // any mem
6272 %}
6274 // Long ALU reg-mem operation
6275 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
6276 instruction_count(2);
6277 dst : S5(write);
6278 mem : S3(read);
6279 D0 : S0(2); // big decoder only; twice
6280 ALU : S4(2); // any 2 alus
6281 MEM : S3(2); // both mems
6282 %}
6284 // Integer mem operation (prefetch)
6285 pipe_class ialu_mem(memory mem)
6286 %{
6287 single_instruction;
6288 mem : S3(read);
6289 D0 : S0; // big decoder only
6290 MEM : S3; // any mem
6291 %}
6293 // Integer Store to Memory
6294 pipe_class ialu_mem_reg(memory mem, eRegI src) %{
6295 single_instruction;
6296 mem : S3(read);
6297 src : S5(read);
6298 D0 : S0; // big decoder only
6299 ALU : S4; // any alu
6300 MEM : S3;
6301 %}
6303 // Long Store to Memory
6304 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
6305 instruction_count(2);
6306 mem : S3(read);
6307 src : S5(read);
6308 D0 : S0(2); // big decoder only; twice
6309 ALU : S4(2); // any 2 alus
6310 MEM : S3(2); // Both mems
6311 %}
6313 // Integer Store to Memory
6314 pipe_class ialu_mem_imm(memory mem) %{
6315 single_instruction;
6316 mem : S3(read);
6317 D0 : S0; // big decoder only
6318 ALU : S4; // any alu
6319 MEM : S3;
6320 %}
6322 // Integer ALU0 reg-reg operation
6323 pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{
6324 single_instruction;
6325 dst : S4(write);
6326 src : S3(read);
6327 D0 : S0; // Big decoder only
6328 ALU0 : S3; // only alu0
6329 %}
6331 // Integer ALU0 reg-mem operation
6332 pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{
6333 single_instruction;
6334 dst : S5(write);
6335 mem : S3(read);
6336 D0 : S0; // big decoder only
6337 ALU0 : S4; // ALU0 only
6338 MEM : S3; // any mem
6339 %}
6341 // Integer ALU reg-reg operation
6342 pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{
6343 single_instruction;
6344 cr : S4(write);
6345 src1 : S3(read);
6346 src2 : S3(read);
6347 DECODE : S0; // any decoder
6348 ALU : S3; // any alu
6349 %}
6351 // Integer ALU reg-imm operation
6352 pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{
6353 single_instruction;
6354 cr : S4(write);
6355 src1 : S3(read);
6356 DECODE : S0; // any decoder
6357 ALU : S3; // any alu
6358 %}
6360 // Integer ALU reg-mem operation
6361 pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{
6362 single_instruction;
6363 cr : S4(write);
6364 src1 : S3(read);
6365 src2 : S3(read);
6366 D0 : S0; // big decoder only
6367 ALU : S4; // any alu
6368 MEM : S3;
6369 %}
6371 // Conditional move reg-reg
6372 pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{
6373 instruction_count(4);
6374 y : S4(read);
6375 q : S3(read);
6376 p : S3(read);
6377 DECODE : S0(4); // any decoder
6378 %}
6380 // Conditional move reg-reg
6381 pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{
6382 single_instruction;
6383 dst : S4(write);
6384 src : S3(read);
6385 cr : S3(read);
6386 DECODE : S0; // any decoder
6387 %}
6389 // Conditional move reg-mem
6390 pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{
6391 single_instruction;
6392 dst : S4(write);
6393 src : S3(read);
6394 cr : S3(read);
6395 DECODE : S0; // any decoder
6396 MEM : S3;
6397 %}
6399 // Conditional move reg-reg long
6400 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
6401 single_instruction;
6402 dst : S4(write);
6403 src : S3(read);
6404 cr : S3(read);
6405 DECODE : S0(2); // any 2 decoders
6406 %}
6408 // Conditional move double reg-reg
6409 pipe_class pipe_cmovD_reg( eFlagsReg cr, regDPR1 dst, regD src) %{
6410 single_instruction;
6411 dst : S4(write);
6412 src : S3(read);
6413 cr : S3(read);
6414 DECODE : S0; // any decoder
6415 %}
6417 // Float reg-reg operation
6418 pipe_class fpu_reg(regD dst) %{
6419 instruction_count(2);
6420 dst : S3(read);
6421 DECODE : S0(2); // any 2 decoders
6422 FPU : S3;
6423 %}
6425 // Float reg-reg operation
6426 pipe_class fpu_reg_reg(regD dst, regD src) %{
6427 instruction_count(2);
6428 dst : S4(write);
6429 src : S3(read);
6430 DECODE : S0(2); // any 2 decoders
6431 FPU : S3;
6432 %}
6434 // Float reg-reg operation
6435 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) %{
6436 instruction_count(3);
6437 dst : S4(write);
6438 src1 : S3(read);
6439 src2 : S3(read);
6440 DECODE : S0(3); // any 3 decoders
6441 FPU : S3(2);
6442 %}
6444 // Float reg-reg operation
6445 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
6446 instruction_count(4);
6447 dst : S4(write);
6448 src1 : S3(read);
6449 src2 : S3(read);
6450 src3 : S3(read);
6451 DECODE : S0(4); // any 3 decoders
6452 FPU : S3(2);
6453 %}
6455 // Float reg-reg operation
6456 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) %{
6457 instruction_count(4);
6458 dst : S4(write);
6459 src1 : S3(read);
6460 src2 : S3(read);
6461 src3 : S3(read);
6462 DECODE : S1(3); // any 3 decoders
6463 D0 : S0; // Big decoder only
6464 FPU : S3(2);
6465 MEM : S3;
6466 %}
6468 // Float reg-mem operation
6469 pipe_class fpu_reg_mem(regD dst, memory mem) %{
6470 instruction_count(2);
6471 dst : S5(write);
6472 mem : S3(read);
6473 D0 : S0; // big decoder only
6474 DECODE : S1; // any decoder for FPU POP
6475 FPU : S4;
6476 MEM : S3; // any mem
6477 %}
6479 // Float reg-mem operation
6480 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) %{
6481 instruction_count(3);
6482 dst : S5(write);
6483 src1 : S3(read);
6484 mem : S3(read);
6485 D0 : S0; // big decoder only
6486 DECODE : S1(2); // any decoder for FPU POP
6487 FPU : S4;
6488 MEM : S3; // any mem
6489 %}
6491 // Float mem-reg operation
6492 pipe_class fpu_mem_reg(memory mem, regD src) %{
6493 instruction_count(2);
6494 src : S5(read);
6495 mem : S3(read);
6496 DECODE : S0; // any decoder for FPU PUSH
6497 D0 : S1; // big decoder only
6498 FPU : S4;
6499 MEM : S3; // any mem
6500 %}
6502 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) %{
6503 instruction_count(3);
6504 src1 : S3(read);
6505 src2 : S3(read);
6506 mem : S3(read);
6507 DECODE : S0(2); // any decoder for FPU PUSH
6508 D0 : S1; // big decoder only
6509 FPU : S4;
6510 MEM : S3; // any mem
6511 %}
6513 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) %{
6514 instruction_count(3);
6515 src1 : S3(read);
6516 src2 : S3(read);
6517 mem : S4(read);
6518 DECODE : S0; // any decoder for FPU PUSH
6519 D0 : S0(2); // big decoder only
6520 FPU : S4;
6521 MEM : S3(2); // any mem
6522 %}
6524 pipe_class fpu_mem_mem(memory dst, memory src1) %{
6525 instruction_count(2);
6526 src1 : S3(read);
6527 dst : S4(read);
6528 D0 : S0(2); // big decoder only
6529 MEM : S3(2); // any mem
6530 %}
6532 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
6533 instruction_count(3);
6534 src1 : S3(read);
6535 src2 : S3(read);
6536 dst : S4(read);
6537 D0 : S0(3); // big decoder only
6538 FPU : S4;
6539 MEM : S3(3); // any mem
6540 %}
6542 pipe_class fpu_mem_reg_con(memory mem, regD src1) %{
6543 instruction_count(3);
6544 src1 : S4(read);
6545 mem : S4(read);
6546 DECODE : S0; // any decoder for FPU PUSH
6547 D0 : S0(2); // big decoder only
6548 FPU : S4;
6549 MEM : S3(2); // any mem
6550 %}
6552 // Float load constant
6553 pipe_class fpu_reg_con(regD dst) %{
6554 instruction_count(2);
6555 dst : S5(write);
6556 D0 : S0; // big decoder only for the load
6557 DECODE : S1; // any decoder for FPU POP
6558 FPU : S4;
6559 MEM : S3; // any mem
6560 %}
6562 // Float load constant
6563 pipe_class fpu_reg_reg_con(regD dst, regD src) %{
6564 instruction_count(3);
6565 dst : S5(write);
6566 src : S3(read);
6567 D0 : S0; // big decoder only for the load
6568 DECODE : S1(2); // any decoder for FPU POP
6569 FPU : S4;
6570 MEM : S3; // any mem
6571 %}
6573 // UnConditional branch
6574 pipe_class pipe_jmp( label labl ) %{
6575 single_instruction;
6576 BR : S3;
6577 %}
6579 // Conditional branch
6580 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
6581 single_instruction;
6582 cr : S1(read);
6583 BR : S3;
6584 %}
6586 // Allocation idiom
6587 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
6588 instruction_count(1); force_serialization;
6589 fixed_latency(6);
6590 heap_ptr : S3(read);
6591 DECODE : S0(3);
6592 D0 : S2;
6593 MEM : S3;
6594 ALU : S3(2);
6595 dst : S5(write);
6596 BR : S5;
6597 %}
6599 // Generic big/slow expanded idiom
6600 pipe_class pipe_slow( ) %{
6601 instruction_count(10); multiple_bundles; force_serialization;
6602 fixed_latency(100);
6603 D0 : S0(2);
6604 MEM : S3(2);
6605 %}
6607 // The real do-nothing guy
6608 pipe_class empty( ) %{
6609 instruction_count(0);
6610 %}
6612 // Define the class for the Nop node
6613 define %{
6614 MachNop = empty;
6615 %}
6617 %}
6619 //----------INSTRUCTIONS-------------------------------------------------------
6620 //
6621 // match -- States which machine-independent subtree may be replaced
6622 // by this instruction.
6623 // ins_cost -- The estimated cost of this instruction is used by instruction
6624 // selection to identify a minimum cost tree of machine
6625 // instructions that matches a tree of machine-independent
6626 // instructions.
6627 // format -- A string providing the disassembly for this instruction.
6628 // The value of an instruction's operand may be inserted
6629 // by referring to it with a '$' prefix.
6630 // opcode -- Three instruction opcodes may be provided. These are referred
6631 // to within an encode class as $primary, $secondary, and $tertiary
6632 // respectively. The primary opcode is commonly used to
6633 // indicate the type of machine instruction, while secondary
6634 // and tertiary are often used for prefix options or addressing
6635 // modes.
6636 // ins_encode -- A list of encode classes with parameters. The encode class
6637 // name must have been defined in an 'enc_class' specification
6638 // in the encode section of the architecture description.
6640 //----------BSWAP-Instruction--------------------------------------------------
6641 instruct bytes_reverse_int(eRegI dst) %{
6642 match(Set dst (ReverseBytesI dst));
6644 format %{ "BSWAP $dst" %}
6645 opcode(0x0F, 0xC8);
6646 ins_encode( OpcP, OpcSReg(dst) );
6647 ins_pipe( ialu_reg );
6648 %}
6650 instruct bytes_reverse_long(eRegL dst) %{
6651 match(Set dst (ReverseBytesL dst));
6653 format %{ "BSWAP $dst.lo\n\t"
6654 "BSWAP $dst.hi\n\t"
6655 "XCHG $dst.lo $dst.hi" %}
6657 ins_cost(125);
6658 ins_encode( bswap_long_bytes(dst) );
6659 ins_pipe( ialu_reg_reg);
6660 %}
6663 //---------- Zeros Count Instructions ------------------------------------------
6665 instruct countLeadingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
6666 predicate(UseCountLeadingZerosInstruction);
6667 match(Set dst (CountLeadingZerosI src));
6668 effect(KILL cr);
6670 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
6671 ins_encode %{
6672 __ lzcntl($dst$$Register, $src$$Register);
6673 %}
6674 ins_pipe(ialu_reg);
6675 %}
6677 instruct countLeadingZerosI_bsr(eRegI dst, eRegI src, eFlagsReg cr) %{
6678 predicate(!UseCountLeadingZerosInstruction);
6679 match(Set dst (CountLeadingZerosI src));
6680 effect(KILL cr);
6682 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
6683 "JNZ skip\n\t"
6684 "MOV $dst, -1\n"
6685 "skip:\n\t"
6686 "NEG $dst\n\t"
6687 "ADD $dst, 31" %}
6688 ins_encode %{
6689 Register Rdst = $dst$$Register;
6690 Register Rsrc = $src$$Register;
6691 Label skip;
6692 __ bsrl(Rdst, Rsrc);
6693 __ jccb(Assembler::notZero, skip);
6694 __ movl(Rdst, -1);
6695 __ bind(skip);
6696 __ negl(Rdst);
6697 __ addl(Rdst, BitsPerInt - 1);
6698 %}
6699 ins_pipe(ialu_reg);
6700 %}
6702 instruct countLeadingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
6703 predicate(UseCountLeadingZerosInstruction);
6704 match(Set dst (CountLeadingZerosL src));
6705 effect(TEMP dst, KILL cr);
6707 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
6708 "JNC done\n\t"
6709 "LZCNT $dst, $src.lo\n\t"
6710 "ADD $dst, 32\n"
6711 "done:" %}
6712 ins_encode %{
6713 Register Rdst = $dst$$Register;
6714 Register Rsrc = $src$$Register;
6715 Label done;
6716 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
6717 __ jccb(Assembler::carryClear, done);
6718 __ lzcntl(Rdst, Rsrc);
6719 __ addl(Rdst, BitsPerInt);
6720 __ bind(done);
6721 %}
6722 ins_pipe(ialu_reg);
6723 %}
6725 instruct countLeadingZerosL_bsr(eRegI dst, eRegL src, eFlagsReg cr) %{
6726 predicate(!UseCountLeadingZerosInstruction);
6727 match(Set dst (CountLeadingZerosL src));
6728 effect(TEMP dst, KILL cr);
6730 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
6731 "JZ msw_is_zero\n\t"
6732 "ADD $dst, 32\n\t"
6733 "JMP not_zero\n"
6734 "msw_is_zero:\n\t"
6735 "BSR $dst, $src.lo\n\t"
6736 "JNZ not_zero\n\t"
6737 "MOV $dst, -1\n"
6738 "not_zero:\n\t"
6739 "NEG $dst\n\t"
6740 "ADD $dst, 63\n" %}
6741 ins_encode %{
6742 Register Rdst = $dst$$Register;
6743 Register Rsrc = $src$$Register;
6744 Label msw_is_zero;
6745 Label not_zero;
6746 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
6747 __ jccb(Assembler::zero, msw_is_zero);
6748 __ addl(Rdst, BitsPerInt);
6749 __ jmpb(not_zero);
6750 __ bind(msw_is_zero);
6751 __ bsrl(Rdst, Rsrc);
6752 __ jccb(Assembler::notZero, not_zero);
6753 __ movl(Rdst, -1);
6754 __ bind(not_zero);
6755 __ negl(Rdst);
6756 __ addl(Rdst, BitsPerLong - 1);
6757 %}
6758 ins_pipe(ialu_reg);
6759 %}
6761 instruct countTrailingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
6762 match(Set dst (CountTrailingZerosI src));
6763 effect(KILL cr);
6765 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
6766 "JNZ done\n\t"
6767 "MOV $dst, 32\n"
6768 "done:" %}
6769 ins_encode %{
6770 Register Rdst = $dst$$Register;
6771 Label done;
6772 __ bsfl(Rdst, $src$$Register);
6773 __ jccb(Assembler::notZero, done);
6774 __ movl(Rdst, BitsPerInt);
6775 __ bind(done);
6776 %}
6777 ins_pipe(ialu_reg);
6778 %}
6780 instruct countTrailingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
6781 match(Set dst (CountTrailingZerosL src));
6782 effect(TEMP dst, KILL cr);
6784 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
6785 "JNZ done\n\t"
6786 "BSF $dst, $src.hi\n\t"
6787 "JNZ msw_not_zero\n\t"
6788 "MOV $dst, 32\n"
6789 "msw_not_zero:\n\t"
6790 "ADD $dst, 32\n"
6791 "done:" %}
6792 ins_encode %{
6793 Register Rdst = $dst$$Register;
6794 Register Rsrc = $src$$Register;
6795 Label msw_not_zero;
6796 Label done;
6797 __ bsfl(Rdst, Rsrc);
6798 __ jccb(Assembler::notZero, done);
6799 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
6800 __ jccb(Assembler::notZero, msw_not_zero);
6801 __ movl(Rdst, BitsPerInt);
6802 __ bind(msw_not_zero);
6803 __ addl(Rdst, BitsPerInt);
6804 __ bind(done);
6805 %}
6806 ins_pipe(ialu_reg);
6807 %}
6810 //---------- Population Count Instructions -------------------------------------
6812 instruct popCountI(eRegI dst, eRegI src) %{
6813 predicate(UsePopCountInstruction);
6814 match(Set dst (PopCountI src));
6816 format %{ "POPCNT $dst, $src" %}
6817 ins_encode %{
6818 __ popcntl($dst$$Register, $src$$Register);
6819 %}
6820 ins_pipe(ialu_reg);
6821 %}
6823 instruct popCountI_mem(eRegI dst, memory mem) %{
6824 predicate(UsePopCountInstruction);
6825 match(Set dst (PopCountI (LoadI mem)));
6827 format %{ "POPCNT $dst, $mem" %}
6828 ins_encode %{
6829 __ popcntl($dst$$Register, $mem$$Address);
6830 %}
6831 ins_pipe(ialu_reg);
6832 %}
6834 // Note: Long.bitCount(long) returns an int.
6835 instruct popCountL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
6836 predicate(UsePopCountInstruction);
6837 match(Set dst (PopCountL src));
6838 effect(KILL cr, TEMP tmp, TEMP dst);
6840 format %{ "POPCNT $dst, $src.lo\n\t"
6841 "POPCNT $tmp, $src.hi\n\t"
6842 "ADD $dst, $tmp" %}
6843 ins_encode %{
6844 __ popcntl($dst$$Register, $src$$Register);
6845 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
6846 __ addl($dst$$Register, $tmp$$Register);
6847 %}
6848 ins_pipe(ialu_reg);
6849 %}
6851 // Note: Long.bitCount(long) returns an int.
6852 instruct popCountL_mem(eRegI dst, memory mem, eRegI tmp, eFlagsReg cr) %{
6853 predicate(UsePopCountInstruction);
6854 match(Set dst (PopCountL (LoadL mem)));
6855 effect(KILL cr, TEMP tmp, TEMP dst);
6857 format %{ "POPCNT $dst, $mem\n\t"
6858 "POPCNT $tmp, $mem+4\n\t"
6859 "ADD $dst, $tmp" %}
6860 ins_encode %{
6861 //__ popcntl($dst$$Register, $mem$$Address$$first);
6862 //__ popcntl($tmp$$Register, $mem$$Address$$second);
6863 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false));
6864 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false));
6865 __ addl($dst$$Register, $tmp$$Register);
6866 %}
6867 ins_pipe(ialu_reg);
6868 %}
6871 //----------Load/Store/Move Instructions---------------------------------------
6872 //----------Load Instructions--------------------------------------------------
6873 // Load Byte (8bit signed)
6874 instruct loadB(xRegI dst, memory mem) %{
6875 match(Set dst (LoadB mem));
6877 ins_cost(125);
6878 format %{ "MOVSX8 $dst,$mem\t# byte" %}
6880 ins_encode %{
6881 __ movsbl($dst$$Register, $mem$$Address);
6882 %}
6884 ins_pipe(ialu_reg_mem);
6885 %}
6887 // Load Byte (8bit signed) into Long Register
6888 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
6889 match(Set dst (ConvI2L (LoadB mem)));
6890 effect(KILL cr);
6892 ins_cost(375);
6893 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
6894 "MOV $dst.hi,$dst.lo\n\t"
6895 "SAR $dst.hi,7" %}
6897 ins_encode %{
6898 __ movsbl($dst$$Register, $mem$$Address);
6899 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6900 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
6901 %}
6903 ins_pipe(ialu_reg_mem);
6904 %}
6906 // Load Unsigned Byte (8bit UNsigned)
6907 instruct loadUB(xRegI dst, memory mem) %{
6908 match(Set dst (LoadUB mem));
6910 ins_cost(125);
6911 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
6913 ins_encode %{
6914 __ movzbl($dst$$Register, $mem$$Address);
6915 %}
6917 ins_pipe(ialu_reg_mem);
6918 %}
6920 // Load Unsigned Byte (8 bit UNsigned) into Long Register
6921 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
6922 match(Set dst (ConvI2L (LoadUB mem)));
6923 effect(KILL cr);
6925 ins_cost(250);
6926 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
6927 "XOR $dst.hi,$dst.hi" %}
6929 ins_encode %{
6930 Register Rdst = $dst$$Register;
6931 __ movzbl(Rdst, $mem$$Address);
6932 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6933 %}
6935 ins_pipe(ialu_reg_mem);
6936 %}
6938 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
6939 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
6940 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
6941 effect(KILL cr);
6943 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
6944 "XOR $dst.hi,$dst.hi\n\t"
6945 "AND $dst.lo,$mask" %}
6946 ins_encode %{
6947 Register Rdst = $dst$$Register;
6948 __ movzbl(Rdst, $mem$$Address);
6949 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6950 __ andl(Rdst, $mask$$constant);
6951 %}
6952 ins_pipe(ialu_reg_mem);
6953 %}
6955 // Load Short (16bit signed)
6956 instruct loadS(eRegI dst, memory mem) %{
6957 match(Set dst (LoadS mem));
6959 ins_cost(125);
6960 format %{ "MOVSX $dst,$mem\t# short" %}
6962 ins_encode %{
6963 __ movswl($dst$$Register, $mem$$Address);
6964 %}
6966 ins_pipe(ialu_reg_mem);
6967 %}
6969 // Load Short (16 bit signed) to Byte (8 bit signed)
6970 instruct loadS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6971 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
6973 ins_cost(125);
6974 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
6975 ins_encode %{
6976 __ movsbl($dst$$Register, $mem$$Address);
6977 %}
6978 ins_pipe(ialu_reg_mem);
6979 %}
6981 // Load Short (16bit signed) into Long Register
6982 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
6983 match(Set dst (ConvI2L (LoadS mem)));
6984 effect(KILL cr);
6986 ins_cost(375);
6987 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
6988 "MOV $dst.hi,$dst.lo\n\t"
6989 "SAR $dst.hi,15" %}
6991 ins_encode %{
6992 __ movswl($dst$$Register, $mem$$Address);
6993 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6994 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
6995 %}
6997 ins_pipe(ialu_reg_mem);
6998 %}
7000 // Load Unsigned Short/Char (16bit unsigned)
7001 instruct loadUS(eRegI dst, memory mem) %{
7002 match(Set dst (LoadUS mem));
7004 ins_cost(125);
7005 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
7007 ins_encode %{
7008 __ movzwl($dst$$Register, $mem$$Address);
7009 %}
7011 ins_pipe(ialu_reg_mem);
7012 %}
7014 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
7015 instruct loadUS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
7016 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
7018 ins_cost(125);
7019 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
7020 ins_encode %{
7021 __ movsbl($dst$$Register, $mem$$Address);
7022 %}
7023 ins_pipe(ialu_reg_mem);
7024 %}
7026 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
7027 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
7028 match(Set dst (ConvI2L (LoadUS mem)));
7029 effect(KILL cr);
7031 ins_cost(250);
7032 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
7033 "XOR $dst.hi,$dst.hi" %}
7035 ins_encode %{
7036 __ movzwl($dst$$Register, $mem$$Address);
7037 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
7038 %}
7040 ins_pipe(ialu_reg_mem);
7041 %}
7043 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
7044 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
7045 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
7046 effect(KILL cr);
7048 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
7049 "XOR $dst.hi,$dst.hi" %}
7050 ins_encode %{
7051 Register Rdst = $dst$$Register;
7052 __ movzbl(Rdst, $mem$$Address);
7053 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
7054 %}
7055 ins_pipe(ialu_reg_mem);
7056 %}
7058 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
7059 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
7060 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
7061 effect(KILL cr);
7063 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
7064 "XOR $dst.hi,$dst.hi\n\t"
7065 "AND $dst.lo,$mask" %}
7066 ins_encode %{
7067 Register Rdst = $dst$$Register;
7068 __ movzwl(Rdst, $mem$$Address);
7069 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
7070 __ andl(Rdst, $mask$$constant);
7071 %}
7072 ins_pipe(ialu_reg_mem);
7073 %}
7075 // Load Integer
7076 instruct loadI(eRegI dst, memory mem) %{
7077 match(Set dst (LoadI mem));
7079 ins_cost(125);
7080 format %{ "MOV $dst,$mem\t# int" %}
7082 ins_encode %{
7083 __ movl($dst$$Register, $mem$$Address);
7084 %}
7086 ins_pipe(ialu_reg_mem);
7087 %}
7089 // Load Integer (32 bit signed) to Byte (8 bit signed)
7090 instruct loadI2B(eRegI dst, memory mem, immI_24 twentyfour) %{
7091 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
7093 ins_cost(125);
7094 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
7095 ins_encode %{
7096 __ movsbl($dst$$Register, $mem$$Address);
7097 %}
7098 ins_pipe(ialu_reg_mem);
7099 %}
7101 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
7102 instruct loadI2UB(eRegI dst, memory mem, immI_255 mask) %{
7103 match(Set dst (AndI (LoadI mem) mask));
7105 ins_cost(125);
7106 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
7107 ins_encode %{
7108 __ movzbl($dst$$Register, $mem$$Address);
7109 %}
7110 ins_pipe(ialu_reg_mem);
7111 %}
7113 // Load Integer (32 bit signed) to Short (16 bit signed)
7114 instruct loadI2S(eRegI dst, memory mem, immI_16 sixteen) %{
7115 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
7117 ins_cost(125);
7118 format %{ "MOVSX $dst, $mem\t# int -> short" %}
7119 ins_encode %{
7120 __ movswl($dst$$Register, $mem$$Address);
7121 %}
7122 ins_pipe(ialu_reg_mem);
7123 %}
7125 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
7126 instruct loadI2US(eRegI dst, memory mem, immI_65535 mask) %{
7127 match(Set dst (AndI (LoadI mem) mask));
7129 ins_cost(125);
7130 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
7131 ins_encode %{
7132 __ movzwl($dst$$Register, $mem$$Address);
7133 %}
7134 ins_pipe(ialu_reg_mem);
7135 %}
7137 // Load Integer into Long Register
7138 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
7139 match(Set dst (ConvI2L (LoadI mem)));
7140 effect(KILL cr);
7142 ins_cost(375);
7143 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
7144 "MOV $dst.hi,$dst.lo\n\t"
7145 "SAR $dst.hi,31" %}
7147 ins_encode %{
7148 __ movl($dst$$Register, $mem$$Address);
7149 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
7150 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
7151 %}
7153 ins_pipe(ialu_reg_mem);
7154 %}
7156 // Load Integer with mask 0xFF into Long Register
7157 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
7158 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
7159 effect(KILL cr);
7161 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
7162 "XOR $dst.hi,$dst.hi" %}
7163 ins_encode %{
7164 Register Rdst = $dst$$Register;
7165 __ movzbl(Rdst, $mem$$Address);
7166 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
7167 %}
7168 ins_pipe(ialu_reg_mem);
7169 %}
7171 // Load Integer with mask 0xFFFF into Long Register
7172 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
7173 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
7174 effect(KILL cr);
7176 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
7177 "XOR $dst.hi,$dst.hi" %}
7178 ins_encode %{
7179 Register Rdst = $dst$$Register;
7180 __ movzwl(Rdst, $mem$$Address);
7181 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
7182 %}
7183 ins_pipe(ialu_reg_mem);
7184 %}
7186 // Load Integer with 32-bit mask into Long Register
7187 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{
7188 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
7189 effect(KILL cr);
7191 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t"
7192 "XOR $dst.hi,$dst.hi\n\t"
7193 "AND $dst.lo,$mask" %}
7194 ins_encode %{
7195 Register Rdst = $dst$$Register;
7196 __ movl(Rdst, $mem$$Address);
7197 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
7198 __ andl(Rdst, $mask$$constant);
7199 %}
7200 ins_pipe(ialu_reg_mem);
7201 %}
7203 // Load Unsigned Integer into Long Register
7204 instruct loadUI2L(eRegL dst, memory mem, eFlagsReg cr) %{
7205 match(Set dst (LoadUI2L mem));
7206 effect(KILL cr);
7208 ins_cost(250);
7209 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
7210 "XOR $dst.hi,$dst.hi" %}
7212 ins_encode %{
7213 __ movl($dst$$Register, $mem$$Address);
7214 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
7215 %}
7217 ins_pipe(ialu_reg_mem);
7218 %}
7220 // Load Long. Cannot clobber address while loading, so restrict address
7221 // register to ESI
7222 instruct loadL(eRegL dst, load_long_memory mem) %{
7223 predicate(!((LoadLNode*)n)->require_atomic_access());
7224 match(Set dst (LoadL mem));
7226 ins_cost(250);
7227 format %{ "MOV $dst.lo,$mem\t# long\n\t"
7228 "MOV $dst.hi,$mem+4" %}
7230 ins_encode %{
7231 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false);
7232 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false);
7233 __ movl($dst$$Register, Amemlo);
7234 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
7235 %}
7237 ins_pipe(ialu_reg_long_mem);
7238 %}
7240 // Volatile Load Long. Must be atomic, so do 64-bit FILD
7241 // then store it down to the stack and reload on the int
7242 // side.
7243 instruct loadL_volatile(stackSlotL dst, memory mem) %{
7244 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
7245 match(Set dst (LoadL mem));
7247 ins_cost(200);
7248 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
7249 "FISTp $dst" %}
7250 ins_encode(enc_loadL_volatile(mem,dst));
7251 ins_pipe( fpu_reg_mem );
7252 %}
7254 instruct loadLX_volatile(stackSlotL dst, memory mem, regXD tmp) %{
7255 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
7256 match(Set dst (LoadL mem));
7257 effect(TEMP tmp);
7258 ins_cost(180);
7259 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
7260 "MOVSD $dst,$tmp" %}
7261 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
7262 ins_pipe( pipe_slow );
7263 %}
7265 instruct loadLX_reg_volatile(eRegL dst, memory mem, regXD tmp) %{
7266 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
7267 match(Set dst (LoadL mem));
7268 effect(TEMP tmp);
7269 ins_cost(160);
7270 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
7271 "MOVD $dst.lo,$tmp\n\t"
7272 "PSRLQ $tmp,32\n\t"
7273 "MOVD $dst.hi,$tmp" %}
7274 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
7275 ins_pipe( pipe_slow );
7276 %}
7278 // Load Range
7279 instruct loadRange(eRegI dst, memory mem) %{
7280 match(Set dst (LoadRange mem));
7282 ins_cost(125);
7283 format %{ "MOV $dst,$mem" %}
7284 opcode(0x8B);
7285 ins_encode( OpcP, RegMem(dst,mem));
7286 ins_pipe( ialu_reg_mem );
7287 %}
7290 // Load Pointer
7291 instruct loadP(eRegP dst, memory mem) %{
7292 match(Set dst (LoadP mem));
7294 ins_cost(125);
7295 format %{ "MOV $dst,$mem" %}
7296 opcode(0x8B);
7297 ins_encode( OpcP, RegMem(dst,mem));
7298 ins_pipe( ialu_reg_mem );
7299 %}
7301 // Load Klass Pointer
7302 instruct loadKlass(eRegP dst, memory mem) %{
7303 match(Set dst (LoadKlass mem));
7305 ins_cost(125);
7306 format %{ "MOV $dst,$mem" %}
7307 opcode(0x8B);
7308 ins_encode( OpcP, RegMem(dst,mem));
7309 ins_pipe( ialu_reg_mem );
7310 %}
7312 // Load Double
7313 instruct loadD(regD dst, memory mem) %{
7314 predicate(UseSSE<=1);
7315 match(Set dst (LoadD mem));
7317 ins_cost(150);
7318 format %{ "FLD_D ST,$mem\n\t"
7319 "FSTP $dst" %}
7320 opcode(0xDD); /* DD /0 */
7321 ins_encode( OpcP, RMopc_Mem(0x00,mem),
7322 Pop_Reg_D(dst) );
7323 ins_pipe( fpu_reg_mem );
7324 %}
7326 // Load Double to XMM
7327 instruct loadXD(regXD dst, memory mem) %{
7328 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
7329 match(Set dst (LoadD mem));
7330 ins_cost(145);
7331 format %{ "MOVSD $dst,$mem" %}
7332 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
7333 ins_pipe( pipe_slow );
7334 %}
7336 instruct loadXD_partial(regXD dst, memory mem) %{
7337 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
7338 match(Set dst (LoadD mem));
7339 ins_cost(145);
7340 format %{ "MOVLPD $dst,$mem" %}
7341 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,mem));
7342 ins_pipe( pipe_slow );
7343 %}
7345 // Load to XMM register (single-precision floating point)
7346 // MOVSS instruction
7347 instruct loadX(regX dst, memory mem) %{
7348 predicate(UseSSE>=1);
7349 match(Set dst (LoadF mem));
7350 ins_cost(145);
7351 format %{ "MOVSS $dst,$mem" %}
7352 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
7353 ins_pipe( pipe_slow );
7354 %}
7356 // Load Float
7357 instruct loadF(regF dst, memory mem) %{
7358 predicate(UseSSE==0);
7359 match(Set dst (LoadF mem));
7361 ins_cost(150);
7362 format %{ "FLD_S ST,$mem\n\t"
7363 "FSTP $dst" %}
7364 opcode(0xD9); /* D9 /0 */
7365 ins_encode( OpcP, RMopc_Mem(0x00,mem),
7366 Pop_Reg_F(dst) );
7367 ins_pipe( fpu_reg_mem );
7368 %}
7370 // Load Aligned Packed Byte to XMM register
7371 instruct loadA8B(regXD dst, memory mem) %{
7372 predicate(UseSSE>=1);
7373 match(Set dst (Load8B mem));
7374 ins_cost(125);
7375 format %{ "MOVQ $dst,$mem\t! packed8B" %}
7376 ins_encode( movq_ld(dst, mem));
7377 ins_pipe( pipe_slow );
7378 %}
7380 // Load Aligned Packed Short to XMM register
7381 instruct loadA4S(regXD dst, memory mem) %{
7382 predicate(UseSSE>=1);
7383 match(Set dst (Load4S mem));
7384 ins_cost(125);
7385 format %{ "MOVQ $dst,$mem\t! packed4S" %}
7386 ins_encode( movq_ld(dst, mem));
7387 ins_pipe( pipe_slow );
7388 %}
7390 // Load Aligned Packed Char to XMM register
7391 instruct loadA4C(regXD dst, memory mem) %{
7392 predicate(UseSSE>=1);
7393 match(Set dst (Load4C mem));
7394 ins_cost(125);
7395 format %{ "MOVQ $dst,$mem\t! packed4C" %}
7396 ins_encode( movq_ld(dst, mem));
7397 ins_pipe( pipe_slow );
7398 %}
7400 // Load Aligned Packed Integer to XMM register
7401 instruct load2IU(regXD dst, memory mem) %{
7402 predicate(UseSSE>=1);
7403 match(Set dst (Load2I mem));
7404 ins_cost(125);
7405 format %{ "MOVQ $dst,$mem\t! packed2I" %}
7406 ins_encode( movq_ld(dst, mem));
7407 ins_pipe( pipe_slow );
7408 %}
7410 // Load Aligned Packed Single to XMM
7411 instruct loadA2F(regXD dst, memory mem) %{
7412 predicate(UseSSE>=1);
7413 match(Set dst (Load2F mem));
7414 ins_cost(145);
7415 format %{ "MOVQ $dst,$mem\t! packed2F" %}
7416 ins_encode( movq_ld(dst, mem));
7417 ins_pipe( pipe_slow );
7418 %}
7420 // Load Effective Address
7421 instruct leaP8(eRegP dst, indOffset8 mem) %{
7422 match(Set dst mem);
7424 ins_cost(110);
7425 format %{ "LEA $dst,$mem" %}
7426 opcode(0x8D);
7427 ins_encode( OpcP, RegMem(dst,mem));
7428 ins_pipe( ialu_reg_reg_fat );
7429 %}
7431 instruct leaP32(eRegP dst, indOffset32 mem) %{
7432 match(Set dst mem);
7434 ins_cost(110);
7435 format %{ "LEA $dst,$mem" %}
7436 opcode(0x8D);
7437 ins_encode( OpcP, RegMem(dst,mem));
7438 ins_pipe( ialu_reg_reg_fat );
7439 %}
7441 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
7442 match(Set dst mem);
7444 ins_cost(110);
7445 format %{ "LEA $dst,$mem" %}
7446 opcode(0x8D);
7447 ins_encode( OpcP, RegMem(dst,mem));
7448 ins_pipe( ialu_reg_reg_fat );
7449 %}
7451 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
7452 match(Set dst mem);
7454 ins_cost(110);
7455 format %{ "LEA $dst,$mem" %}
7456 opcode(0x8D);
7457 ins_encode( OpcP, RegMem(dst,mem));
7458 ins_pipe( ialu_reg_reg_fat );
7459 %}
7461 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
7462 match(Set dst mem);
7464 ins_cost(110);
7465 format %{ "LEA $dst,$mem" %}
7466 opcode(0x8D);
7467 ins_encode( OpcP, RegMem(dst,mem));
7468 ins_pipe( ialu_reg_reg_fat );
7469 %}
7471 // Load Constant
7472 instruct loadConI(eRegI dst, immI src) %{
7473 match(Set dst src);
7475 format %{ "MOV $dst,$src" %}
7476 ins_encode( LdImmI(dst, src) );
7477 ins_pipe( ialu_reg_fat );
7478 %}
7480 // Load Constant zero
7481 instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{
7482 match(Set dst src);
7483 effect(KILL cr);
7485 ins_cost(50);
7486 format %{ "XOR $dst,$dst" %}
7487 opcode(0x33); /* + rd */
7488 ins_encode( OpcP, RegReg( dst, dst ) );
7489 ins_pipe( ialu_reg );
7490 %}
7492 instruct loadConP(eRegP dst, immP src) %{
7493 match(Set dst src);
7495 format %{ "MOV $dst,$src" %}
7496 opcode(0xB8); /* + rd */
7497 ins_encode( LdImmP(dst, src) );
7498 ins_pipe( ialu_reg_fat );
7499 %}
7501 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
7502 match(Set dst src);
7503 effect(KILL cr);
7504 ins_cost(200);
7505 format %{ "MOV $dst.lo,$src.lo\n\t"
7506 "MOV $dst.hi,$src.hi" %}
7507 opcode(0xB8);
7508 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
7509 ins_pipe( ialu_reg_long_fat );
7510 %}
7512 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
7513 match(Set dst src);
7514 effect(KILL cr);
7515 ins_cost(150);
7516 format %{ "XOR $dst.lo,$dst.lo\n\t"
7517 "XOR $dst.hi,$dst.hi" %}
7518 opcode(0x33,0x33);
7519 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
7520 ins_pipe( ialu_reg_long );
7521 %}
7523 // The instruction usage is guarded by predicate in operand immF().
7524 instruct loadConF(regF dst, immF src) %{
7525 match(Set dst src);
7526 ins_cost(125);
7528 format %{ "FLD_S ST,$src\n\t"
7529 "FSTP $dst" %}
7530 opcode(0xD9, 0x00); /* D9 /0 */
7531 ins_encode(LdImmF(src), Pop_Reg_F(dst) );
7532 ins_pipe( fpu_reg_con );
7533 %}
7535 // The instruction usage is guarded by predicate in operand immXF().
7536 instruct loadConX(regX dst, immXF con) %{
7537 match(Set dst con);
7538 ins_cost(125);
7539 format %{ "MOVSS $dst,[$con]" %}
7540 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), LdImmX(dst, con));
7541 ins_pipe( pipe_slow );
7542 %}
7544 // The instruction usage is guarded by predicate in operand immXF0().
7545 instruct loadConX0(regX dst, immXF0 src) %{
7546 match(Set dst src);
7547 ins_cost(100);
7548 format %{ "XORPS $dst,$dst\t# float 0.0" %}
7549 ins_encode( Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
7550 ins_pipe( pipe_slow );
7551 %}
7553 // The instruction usage is guarded by predicate in operand immD().
7554 instruct loadConD(regD dst, immD src) %{
7555 match(Set dst src);
7556 ins_cost(125);
7558 format %{ "FLD_D ST,$src\n\t"
7559 "FSTP $dst" %}
7560 ins_encode(LdImmD(src), Pop_Reg_D(dst) );
7561 ins_pipe( fpu_reg_con );
7562 %}
7564 // The instruction usage is guarded by predicate in operand immXD().
7565 instruct loadConXD(regXD dst, immXD con) %{
7566 match(Set dst con);
7567 ins_cost(125);
7568 format %{ "MOVSD $dst,[$con]" %}
7569 ins_encode(load_conXD(dst, con));
7570 ins_pipe( pipe_slow );
7571 %}
7573 // The instruction usage is guarded by predicate in operand immXD0().
7574 instruct loadConXD0(regXD dst, immXD0 src) %{
7575 match(Set dst src);
7576 ins_cost(100);
7577 format %{ "XORPD $dst,$dst\t# double 0.0" %}
7578 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
7579 ins_pipe( pipe_slow );
7580 %}
7582 // Load Stack Slot
7583 instruct loadSSI(eRegI dst, stackSlotI src) %{
7584 match(Set dst src);
7585 ins_cost(125);
7587 format %{ "MOV $dst,$src" %}
7588 opcode(0x8B);
7589 ins_encode( OpcP, RegMem(dst,src));
7590 ins_pipe( ialu_reg_mem );
7591 %}
7593 instruct loadSSL(eRegL dst, stackSlotL src) %{
7594 match(Set dst src);
7596 ins_cost(200);
7597 format %{ "MOV $dst,$src.lo\n\t"
7598 "MOV $dst+4,$src.hi" %}
7599 opcode(0x8B, 0x8B);
7600 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
7601 ins_pipe( ialu_mem_long_reg );
7602 %}
7604 // Load Stack Slot
7605 instruct loadSSP(eRegP dst, stackSlotP src) %{
7606 match(Set dst src);
7607 ins_cost(125);
7609 format %{ "MOV $dst,$src" %}
7610 opcode(0x8B);
7611 ins_encode( OpcP, RegMem(dst,src));
7612 ins_pipe( ialu_reg_mem );
7613 %}
7615 // Load Stack Slot
7616 instruct loadSSF(regF dst, stackSlotF src) %{
7617 match(Set dst src);
7618 ins_cost(125);
7620 format %{ "FLD_S $src\n\t"
7621 "FSTP $dst" %}
7622 opcode(0xD9); /* D9 /0, FLD m32real */
7623 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
7624 Pop_Reg_F(dst) );
7625 ins_pipe( fpu_reg_mem );
7626 %}
7628 // Load Stack Slot
7629 instruct loadSSD(regD dst, stackSlotD src) %{
7630 match(Set dst src);
7631 ins_cost(125);
7633 format %{ "FLD_D $src\n\t"
7634 "FSTP $dst" %}
7635 opcode(0xDD); /* DD /0, FLD m64real */
7636 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
7637 Pop_Reg_D(dst) );
7638 ins_pipe( fpu_reg_mem );
7639 %}
7641 // Prefetch instructions.
7642 // Must be safe to execute with invalid address (cannot fault).
7644 instruct prefetchr0( memory mem ) %{
7645 predicate(UseSSE==0 && !VM_Version::supports_3dnow());
7646 match(PrefetchRead mem);
7647 ins_cost(0);
7648 size(0);
7649 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
7650 ins_encode();
7651 ins_pipe(empty);
7652 %}
7654 instruct prefetchr( memory mem ) %{
7655 predicate(UseSSE==0 && VM_Version::supports_3dnow() || ReadPrefetchInstr==3);
7656 match(PrefetchRead mem);
7657 ins_cost(100);
7659 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
7660 opcode(0x0F, 0x0d); /* Opcode 0F 0d /0 */
7661 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7662 ins_pipe(ialu_mem);
7663 %}
7665 instruct prefetchrNTA( memory mem ) %{
7666 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
7667 match(PrefetchRead mem);
7668 ins_cost(100);
7670 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
7671 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
7672 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7673 ins_pipe(ialu_mem);
7674 %}
7676 instruct prefetchrT0( memory mem ) %{
7677 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
7678 match(PrefetchRead mem);
7679 ins_cost(100);
7681 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
7682 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
7683 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7684 ins_pipe(ialu_mem);
7685 %}
7687 instruct prefetchrT2( memory mem ) %{
7688 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
7689 match(PrefetchRead mem);
7690 ins_cost(100);
7692 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
7693 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
7694 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
7695 ins_pipe(ialu_mem);
7696 %}
7698 instruct prefetchw0( memory mem ) %{
7699 predicate(UseSSE==0 && !VM_Version::supports_3dnow());
7700 match(PrefetchWrite mem);
7701 ins_cost(0);
7702 size(0);
7703 format %{ "Prefetch (non-SSE is empty encoding)" %}
7704 ins_encode();
7705 ins_pipe(empty);
7706 %}
7708 instruct prefetchw( memory mem ) %{
7709 predicate(UseSSE==0 && VM_Version::supports_3dnow() || AllocatePrefetchInstr==3);
7710 match( PrefetchWrite mem );
7711 ins_cost(100);
7713 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
7714 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */
7715 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7716 ins_pipe(ialu_mem);
7717 %}
7719 instruct prefetchwNTA( memory mem ) %{
7720 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
7721 match(PrefetchWrite mem);
7722 ins_cost(100);
7724 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
7725 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
7726 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7727 ins_pipe(ialu_mem);
7728 %}
7730 instruct prefetchwT0( memory mem ) %{
7731 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
7732 match(PrefetchWrite mem);
7733 ins_cost(100);
7735 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for write" %}
7736 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
7737 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7738 ins_pipe(ialu_mem);
7739 %}
7741 instruct prefetchwT2( memory mem ) %{
7742 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
7743 match(PrefetchWrite mem);
7744 ins_cost(100);
7746 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for write" %}
7747 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
7748 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
7749 ins_pipe(ialu_mem);
7750 %}
7752 //----------Store Instructions-------------------------------------------------
7754 // Store Byte
7755 instruct storeB(memory mem, xRegI src) %{
7756 match(Set mem (StoreB mem src));
7758 ins_cost(125);
7759 format %{ "MOV8 $mem,$src" %}
7760 opcode(0x88);
7761 ins_encode( OpcP, RegMem( src, mem ) );
7762 ins_pipe( ialu_mem_reg );
7763 %}
7765 // Store Char/Short
7766 instruct storeC(memory mem, eRegI src) %{
7767 match(Set mem (StoreC mem src));
7769 ins_cost(125);
7770 format %{ "MOV16 $mem,$src" %}
7771 opcode(0x89, 0x66);
7772 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
7773 ins_pipe( ialu_mem_reg );
7774 %}
7776 // Store Integer
7777 instruct storeI(memory mem, eRegI src) %{
7778 match(Set mem (StoreI mem src));
7780 ins_cost(125);
7781 format %{ "MOV $mem,$src" %}
7782 opcode(0x89);
7783 ins_encode( OpcP, RegMem( src, mem ) );
7784 ins_pipe( ialu_mem_reg );
7785 %}
7787 // Store Long
7788 instruct storeL(long_memory mem, eRegL src) %{
7789 predicate(!((StoreLNode*)n)->require_atomic_access());
7790 match(Set mem (StoreL mem src));
7792 ins_cost(200);
7793 format %{ "MOV $mem,$src.lo\n\t"
7794 "MOV $mem+4,$src.hi" %}
7795 opcode(0x89, 0x89);
7796 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
7797 ins_pipe( ialu_mem_long_reg );
7798 %}
7800 // Store Long to Integer
7801 instruct storeL2I(memory mem, eRegL src) %{
7802 match(Set mem (StoreI mem (ConvL2I src)));
7804 format %{ "MOV $mem,$src.lo\t# long -> int" %}
7805 ins_encode %{
7806 __ movl($mem$$Address, $src$$Register);
7807 %}
7808 ins_pipe(ialu_mem_reg);
7809 %}
7811 // Volatile Store Long. Must be atomic, so move it into
7812 // the FP TOS and then do a 64-bit FIST. Has to probe the
7813 // target address before the store (for null-ptr checks)
7814 // so the memory operand is used twice in the encoding.
7815 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
7816 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
7817 match(Set mem (StoreL mem src));
7818 effect( KILL cr );
7819 ins_cost(400);
7820 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7821 "FILD $src\n\t"
7822 "FISTp $mem\t # 64-bit atomic volatile long store" %}
7823 opcode(0x3B);
7824 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
7825 ins_pipe( fpu_reg_mem );
7826 %}
7828 instruct storeLX_volatile(memory mem, stackSlotL src, regXD tmp, eFlagsReg cr) %{
7829 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
7830 match(Set mem (StoreL mem src));
7831 effect( TEMP tmp, KILL cr );
7832 ins_cost(380);
7833 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7834 "MOVSD $tmp,$src\n\t"
7835 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7836 opcode(0x3B);
7837 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_volatile(mem, src, tmp));
7838 ins_pipe( pipe_slow );
7839 %}
7841 instruct storeLX_reg_volatile(memory mem, eRegL src, regXD tmp2, regXD tmp, eFlagsReg cr) %{
7842 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
7843 match(Set mem (StoreL mem src));
7844 effect( TEMP tmp2 , TEMP tmp, KILL cr );
7845 ins_cost(360);
7846 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7847 "MOVD $tmp,$src.lo\n\t"
7848 "MOVD $tmp2,$src.hi\n\t"
7849 "PUNPCKLDQ $tmp,$tmp2\n\t"
7850 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7851 opcode(0x3B);
7852 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_reg_volatile(mem, src, tmp, tmp2));
7853 ins_pipe( pipe_slow );
7854 %}
7856 // Store Pointer; for storing unknown oops and raw pointers
7857 instruct storeP(memory mem, anyRegP src) %{
7858 match(Set mem (StoreP mem src));
7860 ins_cost(125);
7861 format %{ "MOV $mem,$src" %}
7862 opcode(0x89);
7863 ins_encode( OpcP, RegMem( src, mem ) );
7864 ins_pipe( ialu_mem_reg );
7865 %}
7867 // Store Integer Immediate
7868 instruct storeImmI(memory mem, immI src) %{
7869 match(Set mem (StoreI mem src));
7871 ins_cost(150);
7872 format %{ "MOV $mem,$src" %}
7873 opcode(0xC7); /* C7 /0 */
7874 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7875 ins_pipe( ialu_mem_imm );
7876 %}
7878 // Store Short/Char Immediate
7879 instruct storeImmI16(memory mem, immI16 src) %{
7880 predicate(UseStoreImmI16);
7881 match(Set mem (StoreC mem src));
7883 ins_cost(150);
7884 format %{ "MOV16 $mem,$src" %}
7885 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
7886 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
7887 ins_pipe( ialu_mem_imm );
7888 %}
7890 // Store Pointer Immediate; null pointers or constant oops that do not
7891 // need card-mark barriers.
7892 instruct storeImmP(memory mem, immP src) %{
7893 match(Set mem (StoreP mem src));
7895 ins_cost(150);
7896 format %{ "MOV $mem,$src" %}
7897 opcode(0xC7); /* C7 /0 */
7898 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7899 ins_pipe( ialu_mem_imm );
7900 %}
7902 // Store Byte Immediate
7903 instruct storeImmB(memory mem, immI8 src) %{
7904 match(Set mem (StoreB mem src));
7906 ins_cost(150);
7907 format %{ "MOV8 $mem,$src" %}
7908 opcode(0xC6); /* C6 /0 */
7909 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7910 ins_pipe( ialu_mem_imm );
7911 %}
7913 // Store Aligned Packed Byte XMM register to memory
7914 instruct storeA8B(memory mem, regXD src) %{
7915 predicate(UseSSE>=1);
7916 match(Set mem (Store8B mem src));
7917 ins_cost(145);
7918 format %{ "MOVQ $mem,$src\t! packed8B" %}
7919 ins_encode( movq_st(mem, src));
7920 ins_pipe( pipe_slow );
7921 %}
7923 // Store Aligned Packed Char/Short XMM register to memory
7924 instruct storeA4C(memory mem, regXD src) %{
7925 predicate(UseSSE>=1);
7926 match(Set mem (Store4C mem src));
7927 ins_cost(145);
7928 format %{ "MOVQ $mem,$src\t! packed4C" %}
7929 ins_encode( movq_st(mem, src));
7930 ins_pipe( pipe_slow );
7931 %}
7933 // Store Aligned Packed Integer XMM register to memory
7934 instruct storeA2I(memory mem, regXD src) %{
7935 predicate(UseSSE>=1);
7936 match(Set mem (Store2I mem src));
7937 ins_cost(145);
7938 format %{ "MOVQ $mem,$src\t! packed2I" %}
7939 ins_encode( movq_st(mem, src));
7940 ins_pipe( pipe_slow );
7941 %}
7943 // Store CMS card-mark Immediate
7944 instruct storeImmCM(memory mem, immI8 src) %{
7945 match(Set mem (StoreCM mem src));
7947 ins_cost(150);
7948 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
7949 opcode(0xC6); /* C6 /0 */
7950 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7951 ins_pipe( ialu_mem_imm );
7952 %}
7954 // Store Double
7955 instruct storeD( memory mem, regDPR1 src) %{
7956 predicate(UseSSE<=1);
7957 match(Set mem (StoreD mem src));
7959 ins_cost(100);
7960 format %{ "FST_D $mem,$src" %}
7961 opcode(0xDD); /* DD /2 */
7962 ins_encode( enc_FP_store(mem,src) );
7963 ins_pipe( fpu_mem_reg );
7964 %}
7966 // Store double does rounding on x86
7967 instruct storeD_rounded( memory mem, regDPR1 src) %{
7968 predicate(UseSSE<=1);
7969 match(Set mem (StoreD mem (RoundDouble src)));
7971 ins_cost(100);
7972 format %{ "FST_D $mem,$src\t# round" %}
7973 opcode(0xDD); /* DD /2 */
7974 ins_encode( enc_FP_store(mem,src) );
7975 ins_pipe( fpu_mem_reg );
7976 %}
7978 // Store XMM register to memory (double-precision floating points)
7979 // MOVSD instruction
7980 instruct storeXD(memory mem, regXD src) %{
7981 predicate(UseSSE>=2);
7982 match(Set mem (StoreD mem src));
7983 ins_cost(95);
7984 format %{ "MOVSD $mem,$src" %}
7985 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7986 ins_pipe( pipe_slow );
7987 %}
7989 // Store XMM register to memory (single-precision floating point)
7990 // MOVSS instruction
7991 instruct storeX(memory mem, regX src) %{
7992 predicate(UseSSE>=1);
7993 match(Set mem (StoreF mem src));
7994 ins_cost(95);
7995 format %{ "MOVSS $mem,$src" %}
7996 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7997 ins_pipe( pipe_slow );
7998 %}
8000 // Store Aligned Packed Single Float XMM register to memory
8001 instruct storeA2F(memory mem, regXD src) %{
8002 predicate(UseSSE>=1);
8003 match(Set mem (Store2F mem src));
8004 ins_cost(145);
8005 format %{ "MOVQ $mem,$src\t! packed2F" %}
8006 ins_encode( movq_st(mem, src));
8007 ins_pipe( pipe_slow );
8008 %}
8010 // Store Float
8011 instruct storeF( memory mem, regFPR1 src) %{
8012 predicate(UseSSE==0);
8013 match(Set mem (StoreF mem src));
8015 ins_cost(100);
8016 format %{ "FST_S $mem,$src" %}
8017 opcode(0xD9); /* D9 /2 */
8018 ins_encode( enc_FP_store(mem,src) );
8019 ins_pipe( fpu_mem_reg );
8020 %}
8022 // Store Float does rounding on x86
8023 instruct storeF_rounded( memory mem, regFPR1 src) %{
8024 predicate(UseSSE==0);
8025 match(Set mem (StoreF mem (RoundFloat src)));
8027 ins_cost(100);
8028 format %{ "FST_S $mem,$src\t# round" %}
8029 opcode(0xD9); /* D9 /2 */
8030 ins_encode( enc_FP_store(mem,src) );
8031 ins_pipe( fpu_mem_reg );
8032 %}
8034 // Store Float does rounding on x86
8035 instruct storeF_Drounded( memory mem, regDPR1 src) %{
8036 predicate(UseSSE<=1);
8037 match(Set mem (StoreF mem (ConvD2F src)));
8039 ins_cost(100);
8040 format %{ "FST_S $mem,$src\t# D-round" %}
8041 opcode(0xD9); /* D9 /2 */
8042 ins_encode( enc_FP_store(mem,src) );
8043 ins_pipe( fpu_mem_reg );
8044 %}
8046 // Store immediate Float value (it is faster than store from FPU register)
8047 // The instruction usage is guarded by predicate in operand immF().
8048 instruct storeF_imm( memory mem, immF src) %{
8049 match(Set mem (StoreF mem src));
8051 ins_cost(50);
8052 format %{ "MOV $mem,$src\t# store float" %}
8053 opcode(0xC7); /* C7 /0 */
8054 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
8055 ins_pipe( ialu_mem_imm );
8056 %}
8058 // Store immediate Float value (it is faster than store from XMM register)
8059 // The instruction usage is guarded by predicate in operand immXF().
8060 instruct storeX_imm( memory mem, immXF src) %{
8061 match(Set mem (StoreF mem src));
8063 ins_cost(50);
8064 format %{ "MOV $mem,$src\t# store float" %}
8065 opcode(0xC7); /* C7 /0 */
8066 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32XF_as_bits( src ));
8067 ins_pipe( ialu_mem_imm );
8068 %}
8070 // Store Integer to stack slot
8071 instruct storeSSI(stackSlotI dst, eRegI src) %{
8072 match(Set dst src);
8074 ins_cost(100);
8075 format %{ "MOV $dst,$src" %}
8076 opcode(0x89);
8077 ins_encode( OpcPRegSS( dst, src ) );
8078 ins_pipe( ialu_mem_reg );
8079 %}
8081 // Store Integer to stack slot
8082 instruct storeSSP(stackSlotP dst, eRegP src) %{
8083 match(Set dst src);
8085 ins_cost(100);
8086 format %{ "MOV $dst,$src" %}
8087 opcode(0x89);
8088 ins_encode( OpcPRegSS( dst, src ) );
8089 ins_pipe( ialu_mem_reg );
8090 %}
8092 // Store Long to stack slot
8093 instruct storeSSL(stackSlotL dst, eRegL src) %{
8094 match(Set dst src);
8096 ins_cost(200);
8097 format %{ "MOV $dst,$src.lo\n\t"
8098 "MOV $dst+4,$src.hi" %}
8099 opcode(0x89, 0x89);
8100 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
8101 ins_pipe( ialu_mem_long_reg );
8102 %}
8104 //----------MemBar Instructions-----------------------------------------------
8105 // Memory barrier flavors
8107 instruct membar_acquire() %{
8108 match(MemBarAcquire);
8109 ins_cost(400);
8111 size(0);
8112 format %{ "MEMBAR-acquire ! (empty encoding)" %}
8113 ins_encode();
8114 ins_pipe(empty);
8115 %}
8117 instruct membar_acquire_lock() %{
8118 match(MemBarAcquire);
8119 predicate(Matcher::prior_fast_lock(n));
8120 ins_cost(0);
8122 size(0);
8123 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
8124 ins_encode( );
8125 ins_pipe(empty);
8126 %}
8128 instruct membar_release() %{
8129 match(MemBarRelease);
8130 ins_cost(400);
8132 size(0);
8133 format %{ "MEMBAR-release ! (empty encoding)" %}
8134 ins_encode( );
8135 ins_pipe(empty);
8136 %}
8138 instruct membar_release_lock() %{
8139 match(MemBarRelease);
8140 predicate(Matcher::post_fast_unlock(n));
8141 ins_cost(0);
8143 size(0);
8144 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
8145 ins_encode( );
8146 ins_pipe(empty);
8147 %}
8149 instruct membar_volatile(eFlagsReg cr) %{
8150 match(MemBarVolatile);
8151 effect(KILL cr);
8152 ins_cost(400);
8154 format %{
8155 $$template
8156 if (os::is_MP()) {
8157 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
8158 } else {
8159 $$emit$$"MEMBAR-volatile ! (empty encoding)"
8160 }
8161 %}
8162 ins_encode %{
8163 __ membar(Assembler::StoreLoad);
8164 %}
8165 ins_pipe(pipe_slow);
8166 %}
8168 instruct unnecessary_membar_volatile() %{
8169 match(MemBarVolatile);
8170 predicate(Matcher::post_store_load_barrier(n));
8171 ins_cost(0);
8173 size(0);
8174 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
8175 ins_encode( );
8176 ins_pipe(empty);
8177 %}
8179 //----------Move Instructions--------------------------------------------------
8180 instruct castX2P(eAXRegP dst, eAXRegI src) %{
8181 match(Set dst (CastX2P src));
8182 format %{ "# X2P $dst, $src" %}
8183 ins_encode( /*empty encoding*/ );
8184 ins_cost(0);
8185 ins_pipe(empty);
8186 %}
8188 instruct castP2X(eRegI dst, eRegP src ) %{
8189 match(Set dst (CastP2X src));
8190 ins_cost(50);
8191 format %{ "MOV $dst, $src\t# CastP2X" %}
8192 ins_encode( enc_Copy( dst, src) );
8193 ins_pipe( ialu_reg_reg );
8194 %}
8196 //----------Conditional Move---------------------------------------------------
8197 // Conditional move
8198 instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{
8199 predicate(VM_Version::supports_cmov() );
8200 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
8201 ins_cost(200);
8202 format %{ "CMOV$cop $dst,$src" %}
8203 opcode(0x0F,0x40);
8204 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
8205 ins_pipe( pipe_cmov_reg );
8206 %}
8208 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src ) %{
8209 predicate(VM_Version::supports_cmov() );
8210 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
8211 ins_cost(200);
8212 format %{ "CMOV$cop $dst,$src" %}
8213 opcode(0x0F,0x40);
8214 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
8215 ins_pipe( pipe_cmov_reg );
8216 %}
8218 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, eRegI src ) %{
8219 predicate(VM_Version::supports_cmov() );
8220 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
8221 ins_cost(200);
8222 expand %{
8223 cmovI_regU(cop, cr, dst, src);
8224 %}
8225 %}
8227 // Conditional move
8228 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{
8229 predicate(VM_Version::supports_cmov() );
8230 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
8231 ins_cost(250);
8232 format %{ "CMOV$cop $dst,$src" %}
8233 opcode(0x0F,0x40);
8234 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
8235 ins_pipe( pipe_cmov_mem );
8236 %}
8238 // Conditional move
8239 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{
8240 predicate(VM_Version::supports_cmov() );
8241 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
8242 ins_cost(250);
8243 format %{ "CMOV$cop $dst,$src" %}
8244 opcode(0x0F,0x40);
8245 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
8246 ins_pipe( pipe_cmov_mem );
8247 %}
8249 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, memory src) %{
8250 predicate(VM_Version::supports_cmov() );
8251 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
8252 ins_cost(250);
8253 expand %{
8254 cmovI_memU(cop, cr, dst, src);
8255 %}
8256 %}
8258 // Conditional move
8259 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
8260 predicate(VM_Version::supports_cmov() );
8261 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
8262 ins_cost(200);
8263 format %{ "CMOV$cop $dst,$src\t# ptr" %}
8264 opcode(0x0F,0x40);
8265 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
8266 ins_pipe( pipe_cmov_reg );
8267 %}
8269 // Conditional move (non-P6 version)
8270 // Note: a CMoveP is generated for stubs and native wrappers
8271 // regardless of whether we are on a P6, so we
8272 // emulate a cmov here
8273 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
8274 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
8275 ins_cost(300);
8276 format %{ "Jn$cop skip\n\t"
8277 "MOV $dst,$src\t# pointer\n"
8278 "skip:" %}
8279 opcode(0x8b);
8280 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
8281 ins_pipe( pipe_cmov_reg );
8282 %}
8284 // Conditional move
8285 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
8286 predicate(VM_Version::supports_cmov() );
8287 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
8288 ins_cost(200);
8289 format %{ "CMOV$cop $dst,$src\t# ptr" %}
8290 opcode(0x0F,0x40);
8291 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
8292 ins_pipe( pipe_cmov_reg );
8293 %}
8295 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
8296 predicate(VM_Version::supports_cmov() );
8297 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
8298 ins_cost(200);
8299 expand %{
8300 cmovP_regU(cop, cr, dst, src);
8301 %}
8302 %}
8304 // DISABLED: Requires the ADLC to emit a bottom_type call that
8305 // correctly meets the two pointer arguments; one is an incoming
8306 // register but the other is a memory operand. ALSO appears to
8307 // be buggy with implicit null checks.
8308 //
8309 //// Conditional move
8310 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
8311 // predicate(VM_Version::supports_cmov() );
8312 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
8313 // ins_cost(250);
8314 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
8315 // opcode(0x0F,0x40);
8316 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
8317 // ins_pipe( pipe_cmov_mem );
8318 //%}
8319 //
8320 //// Conditional move
8321 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
8322 // predicate(VM_Version::supports_cmov() );
8323 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
8324 // ins_cost(250);
8325 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
8326 // opcode(0x0F,0x40);
8327 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
8328 // ins_pipe( pipe_cmov_mem );
8329 //%}
8331 // Conditional move
8332 instruct fcmovD_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regD src) %{
8333 predicate(UseSSE<=1);
8334 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8335 ins_cost(200);
8336 format %{ "FCMOV$cop $dst,$src\t# double" %}
8337 opcode(0xDA);
8338 ins_encode( enc_cmov_d(cop,src) );
8339 ins_pipe( pipe_cmovD_reg );
8340 %}
8342 // Conditional move
8343 instruct fcmovF_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regF src) %{
8344 predicate(UseSSE==0);
8345 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8346 ins_cost(200);
8347 format %{ "FCMOV$cop $dst,$src\t# float" %}
8348 opcode(0xDA);
8349 ins_encode( enc_cmov_d(cop,src) );
8350 ins_pipe( pipe_cmovD_reg );
8351 %}
8353 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
8354 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
8355 predicate(UseSSE<=1);
8356 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8357 ins_cost(200);
8358 format %{ "Jn$cop skip\n\t"
8359 "MOV $dst,$src\t# double\n"
8360 "skip:" %}
8361 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
8362 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_D(src), OpcP, RegOpc(dst) );
8363 ins_pipe( pipe_cmovD_reg );
8364 %}
8366 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
8367 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
8368 predicate(UseSSE==0);
8369 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8370 ins_cost(200);
8371 format %{ "Jn$cop skip\n\t"
8372 "MOV $dst,$src\t# float\n"
8373 "skip:" %}
8374 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
8375 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_F(src), OpcP, RegOpc(dst) );
8376 ins_pipe( pipe_cmovD_reg );
8377 %}
8379 // No CMOVE with SSE/SSE2
8380 instruct fcmovX_regS(cmpOp cop, eFlagsReg cr, regX dst, regX src) %{
8381 predicate (UseSSE>=1);
8382 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8383 ins_cost(200);
8384 format %{ "Jn$cop skip\n\t"
8385 "MOVSS $dst,$src\t# float\n"
8386 "skip:" %}
8387 ins_encode %{
8388 Label skip;
8389 // Invert sense of branch from sense of CMOV
8390 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8391 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
8392 __ bind(skip);
8393 %}
8394 ins_pipe( pipe_slow );
8395 %}
8397 // No CMOVE with SSE/SSE2
8398 instruct fcmovXD_regS(cmpOp cop, eFlagsReg cr, regXD dst, regXD src) %{
8399 predicate (UseSSE>=2);
8400 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8401 ins_cost(200);
8402 format %{ "Jn$cop skip\n\t"
8403 "MOVSD $dst,$src\t# float\n"
8404 "skip:" %}
8405 ins_encode %{
8406 Label skip;
8407 // Invert sense of branch from sense of CMOV
8408 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8409 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
8410 __ bind(skip);
8411 %}
8412 ins_pipe( pipe_slow );
8413 %}
8415 // unsigned version
8416 instruct fcmovX_regU(cmpOpU cop, eFlagsRegU cr, regX dst, regX src) %{
8417 predicate (UseSSE>=1);
8418 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8419 ins_cost(200);
8420 format %{ "Jn$cop skip\n\t"
8421 "MOVSS $dst,$src\t# float\n"
8422 "skip:" %}
8423 ins_encode %{
8424 Label skip;
8425 // Invert sense of branch from sense of CMOV
8426 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8427 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
8428 __ bind(skip);
8429 %}
8430 ins_pipe( pipe_slow );
8431 %}
8433 instruct fcmovX_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regX dst, regX src) %{
8434 predicate (UseSSE>=1);
8435 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8436 ins_cost(200);
8437 expand %{
8438 fcmovX_regU(cop, cr, dst, src);
8439 %}
8440 %}
8442 // unsigned version
8443 instruct fcmovXD_regU(cmpOpU cop, eFlagsRegU cr, regXD dst, regXD src) %{
8444 predicate (UseSSE>=2);
8445 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8446 ins_cost(200);
8447 format %{ "Jn$cop skip\n\t"
8448 "MOVSD $dst,$src\t# float\n"
8449 "skip:" %}
8450 ins_encode %{
8451 Label skip;
8452 // Invert sense of branch from sense of CMOV
8453 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8454 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
8455 __ bind(skip);
8456 %}
8457 ins_pipe( pipe_slow );
8458 %}
8460 instruct fcmovXD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regXD dst, regXD src) %{
8461 predicate (UseSSE>=2);
8462 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8463 ins_cost(200);
8464 expand %{
8465 fcmovXD_regU(cop, cr, dst, src);
8466 %}
8467 %}
8469 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
8470 predicate(VM_Version::supports_cmov() );
8471 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8472 ins_cost(200);
8473 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
8474 "CMOV$cop $dst.hi,$src.hi" %}
8475 opcode(0x0F,0x40);
8476 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
8477 ins_pipe( pipe_cmov_reg_long );
8478 %}
8480 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
8481 predicate(VM_Version::supports_cmov() );
8482 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8483 ins_cost(200);
8484 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
8485 "CMOV$cop $dst.hi,$src.hi" %}
8486 opcode(0x0F,0x40);
8487 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
8488 ins_pipe( pipe_cmov_reg_long );
8489 %}
8491 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
8492 predicate(VM_Version::supports_cmov() );
8493 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8494 ins_cost(200);
8495 expand %{
8496 cmovL_regU(cop, cr, dst, src);
8497 %}
8498 %}
8500 //----------Arithmetic Instructions--------------------------------------------
8501 //----------Addition Instructions----------------------------------------------
8502 // Integer Addition Instructions
8503 instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8504 match(Set dst (AddI dst src));
8505 effect(KILL cr);
8507 size(2);
8508 format %{ "ADD $dst,$src" %}
8509 opcode(0x03);
8510 ins_encode( OpcP, RegReg( dst, src) );
8511 ins_pipe( ialu_reg_reg );
8512 %}
8514 instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8515 match(Set dst (AddI dst src));
8516 effect(KILL cr);
8518 format %{ "ADD $dst,$src" %}
8519 opcode(0x81, 0x00); /* /0 id */
8520 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8521 ins_pipe( ialu_reg );
8522 %}
8524 instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
8525 predicate(UseIncDec);
8526 match(Set dst (AddI dst src));
8527 effect(KILL cr);
8529 size(1);
8530 format %{ "INC $dst" %}
8531 opcode(0x40); /* */
8532 ins_encode( Opc_plus( primary, dst ) );
8533 ins_pipe( ialu_reg );
8534 %}
8536 instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{
8537 match(Set dst (AddI src0 src1));
8538 ins_cost(110);
8540 format %{ "LEA $dst,[$src0 + $src1]" %}
8541 opcode(0x8D); /* 0x8D /r */
8542 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
8543 ins_pipe( ialu_reg_reg );
8544 %}
8546 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
8547 match(Set dst (AddP src0 src1));
8548 ins_cost(110);
8550 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
8551 opcode(0x8D); /* 0x8D /r */
8552 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
8553 ins_pipe( ialu_reg_reg );
8554 %}
8556 instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{
8557 predicate(UseIncDec);
8558 match(Set dst (AddI dst src));
8559 effect(KILL cr);
8561 size(1);
8562 format %{ "DEC $dst" %}
8563 opcode(0x48); /* */
8564 ins_encode( Opc_plus( primary, dst ) );
8565 ins_pipe( ialu_reg );
8566 %}
8568 instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{
8569 match(Set dst (AddP dst src));
8570 effect(KILL cr);
8572 size(2);
8573 format %{ "ADD $dst,$src" %}
8574 opcode(0x03);
8575 ins_encode( OpcP, RegReg( dst, src) );
8576 ins_pipe( ialu_reg_reg );
8577 %}
8579 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
8580 match(Set dst (AddP dst src));
8581 effect(KILL cr);
8583 format %{ "ADD $dst,$src" %}
8584 opcode(0x81,0x00); /* Opcode 81 /0 id */
8585 // ins_encode( RegImm( dst, src) );
8586 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8587 ins_pipe( ialu_reg );
8588 %}
8590 instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8591 match(Set dst (AddI dst (LoadI src)));
8592 effect(KILL cr);
8594 ins_cost(125);
8595 format %{ "ADD $dst,$src" %}
8596 opcode(0x03);
8597 ins_encode( OpcP, RegMem( dst, src) );
8598 ins_pipe( ialu_reg_mem );
8599 %}
8601 instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8602 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8603 effect(KILL cr);
8605 ins_cost(150);
8606 format %{ "ADD $dst,$src" %}
8607 opcode(0x01); /* Opcode 01 /r */
8608 ins_encode( OpcP, RegMem( src, dst ) );
8609 ins_pipe( ialu_mem_reg );
8610 %}
8612 // Add Memory with Immediate
8613 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8614 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8615 effect(KILL cr);
8617 ins_cost(125);
8618 format %{ "ADD $dst,$src" %}
8619 opcode(0x81); /* Opcode 81 /0 id */
8620 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
8621 ins_pipe( ialu_mem_imm );
8622 %}
8624 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
8625 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8626 effect(KILL cr);
8628 ins_cost(125);
8629 format %{ "INC $dst" %}
8630 opcode(0xFF); /* Opcode FF /0 */
8631 ins_encode( OpcP, RMopc_Mem(0x00,dst));
8632 ins_pipe( ialu_mem_imm );
8633 %}
8635 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
8636 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8637 effect(KILL cr);
8639 ins_cost(125);
8640 format %{ "DEC $dst" %}
8641 opcode(0xFF); /* Opcode FF /1 */
8642 ins_encode( OpcP, RMopc_Mem(0x01,dst));
8643 ins_pipe( ialu_mem_imm );
8644 %}
8647 instruct checkCastPP( eRegP dst ) %{
8648 match(Set dst (CheckCastPP dst));
8650 size(0);
8651 format %{ "#checkcastPP of $dst" %}
8652 ins_encode( /*empty encoding*/ );
8653 ins_pipe( empty );
8654 %}
8656 instruct castPP( eRegP dst ) %{
8657 match(Set dst (CastPP dst));
8658 format %{ "#castPP of $dst" %}
8659 ins_encode( /*empty encoding*/ );
8660 ins_pipe( empty );
8661 %}
8663 instruct castII( eRegI dst ) %{
8664 match(Set dst (CastII dst));
8665 format %{ "#castII of $dst" %}
8666 ins_encode( /*empty encoding*/ );
8667 ins_cost(0);
8668 ins_pipe( empty );
8669 %}
8672 // Load-locked - same as a regular pointer load when used with compare-swap
8673 instruct loadPLocked(eRegP dst, memory mem) %{
8674 match(Set dst (LoadPLocked mem));
8676 ins_cost(125);
8677 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
8678 opcode(0x8B);
8679 ins_encode( OpcP, RegMem(dst,mem));
8680 ins_pipe( ialu_reg_mem );
8681 %}
8683 // LoadLong-locked - same as a volatile long load when used with compare-swap
8684 instruct loadLLocked(stackSlotL dst, load_long_memory mem) %{
8685 predicate(UseSSE<=1);
8686 match(Set dst (LoadLLocked mem));
8688 ins_cost(200);
8689 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
8690 "FISTp $dst" %}
8691 ins_encode(enc_loadL_volatile(mem,dst));
8692 ins_pipe( fpu_reg_mem );
8693 %}
8695 instruct loadLX_Locked(stackSlotL dst, load_long_memory mem, regXD tmp) %{
8696 predicate(UseSSE>=2);
8697 match(Set dst (LoadLLocked mem));
8698 effect(TEMP tmp);
8699 ins_cost(180);
8700 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
8701 "MOVSD $dst,$tmp" %}
8702 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
8703 ins_pipe( pipe_slow );
8704 %}
8706 instruct loadLX_reg_Locked(eRegL dst, load_long_memory mem, regXD tmp) %{
8707 predicate(UseSSE>=2);
8708 match(Set dst (LoadLLocked mem));
8709 effect(TEMP tmp);
8710 ins_cost(160);
8711 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
8712 "MOVD $dst.lo,$tmp\n\t"
8713 "PSRLQ $tmp,32\n\t"
8714 "MOVD $dst.hi,$tmp" %}
8715 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
8716 ins_pipe( pipe_slow );
8717 %}
8719 // Conditional-store of the updated heap-top.
8720 // Used during allocation of the shared heap.
8721 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
8722 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
8723 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
8724 // EAX is killed if there is contention, but then it's also unused.
8725 // In the common case of no contention, EAX holds the new oop address.
8726 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
8727 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
8728 ins_pipe( pipe_cmpxchg );
8729 %}
8731 // Conditional-store of an int value.
8732 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
8733 instruct storeIConditional( memory mem, eAXRegI oldval, eRegI newval, eFlagsReg cr ) %{
8734 match(Set cr (StoreIConditional mem (Binary oldval newval)));
8735 effect(KILL oldval);
8736 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
8737 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
8738 ins_pipe( pipe_cmpxchg );
8739 %}
8741 // Conditional-store of a long value.
8742 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
8743 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
8744 match(Set cr (StoreLConditional mem (Binary oldval newval)));
8745 effect(KILL oldval);
8746 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
8747 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
8748 "XCHG EBX,ECX"
8749 %}
8750 ins_encode %{
8751 // Note: we need to swap rbx, and rcx before and after the
8752 // cmpxchg8 instruction because the instruction uses
8753 // rcx as the high order word of the new value to store but
8754 // our register encoding uses rbx.
8755 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
8756 if( os::is_MP() )
8757 __ lock();
8758 __ cmpxchg8($mem$$Address);
8759 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
8760 %}
8761 ins_pipe( pipe_cmpxchg );
8762 %}
8764 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
8766 instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
8767 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
8768 effect(KILL cr, KILL oldval);
8769 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8770 "MOV $res,0\n\t"
8771 "JNE,s fail\n\t"
8772 "MOV $res,1\n"
8773 "fail:" %}
8774 ins_encode( enc_cmpxchg8(mem_ptr),
8775 enc_flags_ne_to_boolean(res) );
8776 ins_pipe( pipe_cmpxchg );
8777 %}
8779 instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
8780 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
8781 effect(KILL cr, KILL oldval);
8782 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8783 "MOV $res,0\n\t"
8784 "JNE,s fail\n\t"
8785 "MOV $res,1\n"
8786 "fail:" %}
8787 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
8788 ins_pipe( pipe_cmpxchg );
8789 %}
8791 instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
8792 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
8793 effect(KILL cr, KILL oldval);
8794 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8795 "MOV $res,0\n\t"
8796 "JNE,s fail\n\t"
8797 "MOV $res,1\n"
8798 "fail:" %}
8799 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
8800 ins_pipe( pipe_cmpxchg );
8801 %}
8803 //----------Subtraction Instructions-------------------------------------------
8804 // Integer Subtraction Instructions
8805 instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8806 match(Set dst (SubI dst src));
8807 effect(KILL cr);
8809 size(2);
8810 format %{ "SUB $dst,$src" %}
8811 opcode(0x2B);
8812 ins_encode( OpcP, RegReg( dst, src) );
8813 ins_pipe( ialu_reg_reg );
8814 %}
8816 instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8817 match(Set dst (SubI dst src));
8818 effect(KILL cr);
8820 format %{ "SUB $dst,$src" %}
8821 opcode(0x81,0x05); /* Opcode 81 /5 */
8822 // ins_encode( RegImm( dst, src) );
8823 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8824 ins_pipe( ialu_reg );
8825 %}
8827 instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8828 match(Set dst (SubI dst (LoadI src)));
8829 effect(KILL cr);
8831 ins_cost(125);
8832 format %{ "SUB $dst,$src" %}
8833 opcode(0x2B);
8834 ins_encode( OpcP, RegMem( dst, src) );
8835 ins_pipe( ialu_reg_mem );
8836 %}
8838 instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8839 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8840 effect(KILL cr);
8842 ins_cost(150);
8843 format %{ "SUB $dst,$src" %}
8844 opcode(0x29); /* Opcode 29 /r */
8845 ins_encode( OpcP, RegMem( src, dst ) );
8846 ins_pipe( ialu_mem_reg );
8847 %}
8849 // Subtract from a pointer
8850 instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{
8851 match(Set dst (AddP dst (SubI zero src)));
8852 effect(KILL cr);
8854 size(2);
8855 format %{ "SUB $dst,$src" %}
8856 opcode(0x2B);
8857 ins_encode( OpcP, RegReg( dst, src) );
8858 ins_pipe( ialu_reg_reg );
8859 %}
8861 instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{
8862 match(Set dst (SubI zero dst));
8863 effect(KILL cr);
8865 size(2);
8866 format %{ "NEG $dst" %}
8867 opcode(0xF7,0x03); // Opcode F7 /3
8868 ins_encode( OpcP, RegOpc( dst ) );
8869 ins_pipe( ialu_reg );
8870 %}
8873 //----------Multiplication/Division Instructions-------------------------------
8874 // Integer Multiplication Instructions
8875 // Multiply Register
8876 instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8877 match(Set dst (MulI dst src));
8878 effect(KILL cr);
8880 size(3);
8881 ins_cost(300);
8882 format %{ "IMUL $dst,$src" %}
8883 opcode(0xAF, 0x0F);
8884 ins_encode( OpcS, OpcP, RegReg( dst, src) );
8885 ins_pipe( ialu_reg_reg_alu0 );
8886 %}
8888 // Multiply 32-bit Immediate
8889 instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{
8890 match(Set dst (MulI src imm));
8891 effect(KILL cr);
8893 ins_cost(300);
8894 format %{ "IMUL $dst,$src,$imm" %}
8895 opcode(0x69); /* 69 /r id */
8896 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
8897 ins_pipe( ialu_reg_reg_alu0 );
8898 %}
8900 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
8901 match(Set dst src);
8902 effect(KILL cr);
8904 // Note that this is artificially increased to make it more expensive than loadConL
8905 ins_cost(250);
8906 format %{ "MOV EAX,$src\t// low word only" %}
8907 opcode(0xB8);
8908 ins_encode( LdImmL_Lo(dst, src) );
8909 ins_pipe( ialu_reg_fat );
8910 %}
8912 // Multiply by 32-bit Immediate, taking the shifted high order results
8913 // (special case for shift by 32)
8914 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
8915 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8916 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8917 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8918 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8919 effect(USE src1, KILL cr);
8921 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8922 ins_cost(0*100 + 1*400 - 150);
8923 format %{ "IMUL EDX:EAX,$src1" %}
8924 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8925 ins_pipe( pipe_slow );
8926 %}
8928 // Multiply by 32-bit Immediate, taking the shifted high order results
8929 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
8930 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8931 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8932 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8933 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8934 effect(USE src1, KILL cr);
8936 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8937 ins_cost(1*100 + 1*400 - 150);
8938 format %{ "IMUL EDX:EAX,$src1\n\t"
8939 "SAR EDX,$cnt-32" %}
8940 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8941 ins_pipe( pipe_slow );
8942 %}
8944 // Multiply Memory 32-bit Immediate
8945 instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{
8946 match(Set dst (MulI (LoadI src) imm));
8947 effect(KILL cr);
8949 ins_cost(300);
8950 format %{ "IMUL $dst,$src,$imm" %}
8951 opcode(0x69); /* 69 /r id */
8952 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8953 ins_pipe( ialu_reg_mem_alu0 );
8954 %}
8956 // Multiply Memory
8957 instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{
8958 match(Set dst (MulI dst (LoadI src)));
8959 effect(KILL cr);
8961 ins_cost(350);
8962 format %{ "IMUL $dst,$src" %}
8963 opcode(0xAF, 0x0F);
8964 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8965 ins_pipe( ialu_reg_mem_alu0 );
8966 %}
8968 // Multiply Register Int to Long
8969 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8970 // Basic Idea: long = (long)int * (long)int
8971 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8972 effect(DEF dst, USE src, USE src1, KILL flags);
8974 ins_cost(300);
8975 format %{ "IMUL $dst,$src1" %}
8977 ins_encode( long_int_multiply( dst, src1 ) );
8978 ins_pipe( ialu_reg_reg_alu0 );
8979 %}
8981 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8982 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8983 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8984 effect(KILL flags);
8986 ins_cost(300);
8987 format %{ "MUL $dst,$src1" %}
8989 ins_encode( long_uint_multiply(dst, src1) );
8990 ins_pipe( ialu_reg_reg_alu0 );
8991 %}
8993 // Multiply Register Long
8994 instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8995 match(Set dst (MulL dst src));
8996 effect(KILL cr, TEMP tmp);
8997 ins_cost(4*100+3*400);
8998 // Basic idea: lo(result) = lo(x_lo * y_lo)
8999 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
9000 format %{ "MOV $tmp,$src.lo\n\t"
9001 "IMUL $tmp,EDX\n\t"
9002 "MOV EDX,$src.hi\n\t"
9003 "IMUL EDX,EAX\n\t"
9004 "ADD $tmp,EDX\n\t"
9005 "MUL EDX:EAX,$src.lo\n\t"
9006 "ADD EDX,$tmp" %}
9007 ins_encode( long_multiply( dst, src, tmp ) );
9008 ins_pipe( pipe_slow );
9009 %}
9011 // Multiply Register Long by small constant
9012 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{
9013 match(Set dst (MulL dst src));
9014 effect(KILL cr, TEMP tmp);
9015 ins_cost(2*100+2*400);
9016 size(12);
9017 // Basic idea: lo(result) = lo(src * EAX)
9018 // hi(result) = hi(src * EAX) + lo(src * EDX)
9019 format %{ "IMUL $tmp,EDX,$src\n\t"
9020 "MOV EDX,$src\n\t"
9021 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
9022 "ADD EDX,$tmp" %}
9023 ins_encode( long_multiply_con( dst, src, tmp ) );
9024 ins_pipe( pipe_slow );
9025 %}
9027 // Integer DIV with Register
9028 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
9029 match(Set rax (DivI rax div));
9030 effect(KILL rdx, KILL cr);
9031 size(26);
9032 ins_cost(30*100+10*100);
9033 format %{ "CMP EAX,0x80000000\n\t"
9034 "JNE,s normal\n\t"
9035 "XOR EDX,EDX\n\t"
9036 "CMP ECX,-1\n\t"
9037 "JE,s done\n"
9038 "normal: CDQ\n\t"
9039 "IDIV $div\n\t"
9040 "done:" %}
9041 opcode(0xF7, 0x7); /* Opcode F7 /7 */
9042 ins_encode( cdq_enc, OpcP, RegOpc(div) );
9043 ins_pipe( ialu_reg_reg_alu0 );
9044 %}
9046 // Divide Register Long
9047 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
9048 match(Set dst (DivL src1 src2));
9049 effect( KILL cr, KILL cx, KILL bx );
9050 ins_cost(10000);
9051 format %{ "PUSH $src1.hi\n\t"
9052 "PUSH $src1.lo\n\t"
9053 "PUSH $src2.hi\n\t"
9054 "PUSH $src2.lo\n\t"
9055 "CALL SharedRuntime::ldiv\n\t"
9056 "ADD ESP,16" %}
9057 ins_encode( long_div(src1,src2) );
9058 ins_pipe( pipe_slow );
9059 %}
9061 // Integer DIVMOD with Register, both quotient and mod results
9062 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
9063 match(DivModI rax div);
9064 effect(KILL cr);
9065 size(26);
9066 ins_cost(30*100+10*100);
9067 format %{ "CMP EAX,0x80000000\n\t"
9068 "JNE,s normal\n\t"
9069 "XOR EDX,EDX\n\t"
9070 "CMP ECX,-1\n\t"
9071 "JE,s done\n"
9072 "normal: CDQ\n\t"
9073 "IDIV $div\n\t"
9074 "done:" %}
9075 opcode(0xF7, 0x7); /* Opcode F7 /7 */
9076 ins_encode( cdq_enc, OpcP, RegOpc(div) );
9077 ins_pipe( pipe_slow );
9078 %}
9080 // Integer MOD with Register
9081 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
9082 match(Set rdx (ModI rax div));
9083 effect(KILL rax, KILL cr);
9085 size(26);
9086 ins_cost(300);
9087 format %{ "CDQ\n\t"
9088 "IDIV $div" %}
9089 opcode(0xF7, 0x7); /* Opcode F7 /7 */
9090 ins_encode( cdq_enc, OpcP, RegOpc(div) );
9091 ins_pipe( ialu_reg_reg_alu0 );
9092 %}
9094 // Remainder Register Long
9095 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
9096 match(Set dst (ModL src1 src2));
9097 effect( KILL cr, KILL cx, KILL bx );
9098 ins_cost(10000);
9099 format %{ "PUSH $src1.hi\n\t"
9100 "PUSH $src1.lo\n\t"
9101 "PUSH $src2.hi\n\t"
9102 "PUSH $src2.lo\n\t"
9103 "CALL SharedRuntime::lrem\n\t"
9104 "ADD ESP,16" %}
9105 ins_encode( long_mod(src1,src2) );
9106 ins_pipe( pipe_slow );
9107 %}
9109 // Integer Shift Instructions
9110 // Shift Left by one
9111 instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9112 match(Set dst (LShiftI dst shift));
9113 effect(KILL cr);
9115 size(2);
9116 format %{ "SHL $dst,$shift" %}
9117 opcode(0xD1, 0x4); /* D1 /4 */
9118 ins_encode( OpcP, RegOpc( dst ) );
9119 ins_pipe( ialu_reg );
9120 %}
9122 // Shift Left by 8-bit immediate
9123 instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
9124 match(Set dst (LShiftI dst shift));
9125 effect(KILL cr);
9127 size(3);
9128 format %{ "SHL $dst,$shift" %}
9129 opcode(0xC1, 0x4); /* C1 /4 ib */
9130 ins_encode( RegOpcImm( dst, shift) );
9131 ins_pipe( ialu_reg );
9132 %}
9134 // Shift Left by variable
9135 instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
9136 match(Set dst (LShiftI dst shift));
9137 effect(KILL cr);
9139 size(2);
9140 format %{ "SHL $dst,$shift" %}
9141 opcode(0xD3, 0x4); /* D3 /4 */
9142 ins_encode( OpcP, RegOpc( dst ) );
9143 ins_pipe( ialu_reg_reg );
9144 %}
9146 // Arithmetic shift right by one
9147 instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9148 match(Set dst (RShiftI dst shift));
9149 effect(KILL cr);
9151 size(2);
9152 format %{ "SAR $dst,$shift" %}
9153 opcode(0xD1, 0x7); /* D1 /7 */
9154 ins_encode( OpcP, RegOpc( dst ) );
9155 ins_pipe( ialu_reg );
9156 %}
9158 // Arithmetic shift right by one
9159 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
9160 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
9161 effect(KILL cr);
9162 format %{ "SAR $dst,$shift" %}
9163 opcode(0xD1, 0x7); /* D1 /7 */
9164 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
9165 ins_pipe( ialu_mem_imm );
9166 %}
9168 // Arithmetic Shift Right by 8-bit immediate
9169 instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
9170 match(Set dst (RShiftI dst shift));
9171 effect(KILL cr);
9173 size(3);
9174 format %{ "SAR $dst,$shift" %}
9175 opcode(0xC1, 0x7); /* C1 /7 ib */
9176 ins_encode( RegOpcImm( dst, shift ) );
9177 ins_pipe( ialu_mem_imm );
9178 %}
9180 // Arithmetic Shift Right by 8-bit immediate
9181 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
9182 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
9183 effect(KILL cr);
9185 format %{ "SAR $dst,$shift" %}
9186 opcode(0xC1, 0x7); /* C1 /7 ib */
9187 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
9188 ins_pipe( ialu_mem_imm );
9189 %}
9191 // Arithmetic Shift Right by variable
9192 instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
9193 match(Set dst (RShiftI dst shift));
9194 effect(KILL cr);
9196 size(2);
9197 format %{ "SAR $dst,$shift" %}
9198 opcode(0xD3, 0x7); /* D3 /7 */
9199 ins_encode( OpcP, RegOpc( dst ) );
9200 ins_pipe( ialu_reg_reg );
9201 %}
9203 // Logical shift right by one
9204 instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9205 match(Set dst (URShiftI dst shift));
9206 effect(KILL cr);
9208 size(2);
9209 format %{ "SHR $dst,$shift" %}
9210 opcode(0xD1, 0x5); /* D1 /5 */
9211 ins_encode( OpcP, RegOpc( dst ) );
9212 ins_pipe( ialu_reg );
9213 %}
9215 // Logical Shift Right by 8-bit immediate
9216 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
9217 match(Set dst (URShiftI dst shift));
9218 effect(KILL cr);
9220 size(3);
9221 format %{ "SHR $dst,$shift" %}
9222 opcode(0xC1, 0x5); /* C1 /5 ib */
9223 ins_encode( RegOpcImm( dst, shift) );
9224 ins_pipe( ialu_reg );
9225 %}
9228 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
9229 // This idiom is used by the compiler for the i2b bytecode.
9230 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour) %{
9231 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
9233 size(3);
9234 format %{ "MOVSX $dst,$src :8" %}
9235 ins_encode %{
9236 __ movsbl($dst$$Register, $src$$Register);
9237 %}
9238 ins_pipe(ialu_reg_reg);
9239 %}
9241 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
9242 // This idiom is used by the compiler the i2s bytecode.
9243 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen) %{
9244 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
9246 size(3);
9247 format %{ "MOVSX $dst,$src :16" %}
9248 ins_encode %{
9249 __ movswl($dst$$Register, $src$$Register);
9250 %}
9251 ins_pipe(ialu_reg_reg);
9252 %}
9255 // Logical Shift Right by variable
9256 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
9257 match(Set dst (URShiftI dst shift));
9258 effect(KILL cr);
9260 size(2);
9261 format %{ "SHR $dst,$shift" %}
9262 opcode(0xD3, 0x5); /* D3 /5 */
9263 ins_encode( OpcP, RegOpc( dst ) );
9264 ins_pipe( ialu_reg_reg );
9265 %}
9268 //----------Logical Instructions-----------------------------------------------
9269 //----------Integer Logical Instructions---------------------------------------
9270 // And Instructions
9271 // And Register with Register
9272 instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
9273 match(Set dst (AndI dst src));
9274 effect(KILL cr);
9276 size(2);
9277 format %{ "AND $dst,$src" %}
9278 opcode(0x23);
9279 ins_encode( OpcP, RegReg( dst, src) );
9280 ins_pipe( ialu_reg_reg );
9281 %}
9283 // And Register with Immediate
9284 instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
9285 match(Set dst (AndI dst src));
9286 effect(KILL cr);
9288 format %{ "AND $dst,$src" %}
9289 opcode(0x81,0x04); /* Opcode 81 /4 */
9290 // ins_encode( RegImm( dst, src) );
9291 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
9292 ins_pipe( ialu_reg );
9293 %}
9295 // And Register with Memory
9296 instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
9297 match(Set dst (AndI dst (LoadI src)));
9298 effect(KILL cr);
9300 ins_cost(125);
9301 format %{ "AND $dst,$src" %}
9302 opcode(0x23);
9303 ins_encode( OpcP, RegMem( dst, src) );
9304 ins_pipe( ialu_reg_mem );
9305 %}
9307 // And Memory with Register
9308 instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
9309 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9310 effect(KILL cr);
9312 ins_cost(150);
9313 format %{ "AND $dst,$src" %}
9314 opcode(0x21); /* Opcode 21 /r */
9315 ins_encode( OpcP, RegMem( src, dst ) );
9316 ins_pipe( ialu_mem_reg );
9317 %}
9319 // And Memory with Immediate
9320 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
9321 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9322 effect(KILL cr);
9324 ins_cost(125);
9325 format %{ "AND $dst,$src" %}
9326 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9327 // ins_encode( MemImm( dst, src) );
9328 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
9329 ins_pipe( ialu_mem_imm );
9330 %}
9332 // Or Instructions
9333 // Or Register with Register
9334 instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
9335 match(Set dst (OrI dst src));
9336 effect(KILL cr);
9338 size(2);
9339 format %{ "OR $dst,$src" %}
9340 opcode(0x0B);
9341 ins_encode( OpcP, RegReg( dst, src) );
9342 ins_pipe( ialu_reg_reg );
9343 %}
9345 instruct orI_eReg_castP2X(eRegI dst, eRegP src, eFlagsReg cr) %{
9346 match(Set dst (OrI dst (CastP2X src)));
9347 effect(KILL cr);
9349 size(2);
9350 format %{ "OR $dst,$src" %}
9351 opcode(0x0B);
9352 ins_encode( OpcP, RegReg( dst, src) );
9353 ins_pipe( ialu_reg_reg );
9354 %}
9357 // Or Register with Immediate
9358 instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
9359 match(Set dst (OrI dst src));
9360 effect(KILL cr);
9362 format %{ "OR $dst,$src" %}
9363 opcode(0x81,0x01); /* Opcode 81 /1 id */
9364 // ins_encode( RegImm( dst, src) );
9365 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
9366 ins_pipe( ialu_reg );
9367 %}
9369 // Or Register with Memory
9370 instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
9371 match(Set dst (OrI dst (LoadI src)));
9372 effect(KILL cr);
9374 ins_cost(125);
9375 format %{ "OR $dst,$src" %}
9376 opcode(0x0B);
9377 ins_encode( OpcP, RegMem( dst, src) );
9378 ins_pipe( ialu_reg_mem );
9379 %}
9381 // Or Memory with Register
9382 instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
9383 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9384 effect(KILL cr);
9386 ins_cost(150);
9387 format %{ "OR $dst,$src" %}
9388 opcode(0x09); /* Opcode 09 /r */
9389 ins_encode( OpcP, RegMem( src, dst ) );
9390 ins_pipe( ialu_mem_reg );
9391 %}
9393 // Or Memory with Immediate
9394 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
9395 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9396 effect(KILL cr);
9398 ins_cost(125);
9399 format %{ "OR $dst,$src" %}
9400 opcode(0x81,0x1); /* Opcode 81 /1 id */
9401 // ins_encode( MemImm( dst, src) );
9402 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
9403 ins_pipe( ialu_mem_imm );
9404 %}
9406 // ROL/ROR
9407 // ROL expand
9408 instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9409 effect(USE_DEF dst, USE shift, KILL cr);
9411 format %{ "ROL $dst, $shift" %}
9412 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9413 ins_encode( OpcP, RegOpc( dst ));
9414 ins_pipe( ialu_reg );
9415 %}
9417 instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
9418 effect(USE_DEF dst, USE shift, KILL cr);
9420 format %{ "ROL $dst, $shift" %}
9421 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
9422 ins_encode( RegOpcImm(dst, shift) );
9423 ins_pipe(ialu_reg);
9424 %}
9426 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
9427 effect(USE_DEF dst, USE shift, KILL cr);
9429 format %{ "ROL $dst, $shift" %}
9430 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9431 ins_encode(OpcP, RegOpc(dst));
9432 ins_pipe( ialu_reg_reg );
9433 %}
9434 // end of ROL expand
9436 // ROL 32bit by one once
9437 instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
9438 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9440 expand %{
9441 rolI_eReg_imm1(dst, lshift, cr);
9442 %}
9443 %}
9445 // ROL 32bit var by imm8 once
9446 instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
9447 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9448 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9450 expand %{
9451 rolI_eReg_imm8(dst, lshift, cr);
9452 %}
9453 %}
9455 // ROL 32bit var by var once
9456 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
9457 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
9459 expand %{
9460 rolI_eReg_CL(dst, shift, cr);
9461 %}
9462 %}
9464 // ROL 32bit var by var once
9465 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
9466 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
9468 expand %{
9469 rolI_eReg_CL(dst, shift, cr);
9470 %}
9471 %}
9473 // ROR expand
9474 instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9475 effect(USE_DEF dst, USE shift, KILL cr);
9477 format %{ "ROR $dst, $shift" %}
9478 opcode(0xD1,0x1); /* Opcode D1 /1 */
9479 ins_encode( OpcP, RegOpc( dst ) );
9480 ins_pipe( ialu_reg );
9481 %}
9483 instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
9484 effect (USE_DEF dst, USE shift, KILL cr);
9486 format %{ "ROR $dst, $shift" %}
9487 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
9488 ins_encode( RegOpcImm(dst, shift) );
9489 ins_pipe( ialu_reg );
9490 %}
9492 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
9493 effect(USE_DEF dst, USE shift, KILL cr);
9495 format %{ "ROR $dst, $shift" %}
9496 opcode(0xD3, 0x1); /* Opcode D3 /1 */
9497 ins_encode(OpcP, RegOpc(dst));
9498 ins_pipe( ialu_reg_reg );
9499 %}
9500 // end of ROR expand
9502 // ROR right once
9503 instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
9504 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9506 expand %{
9507 rorI_eReg_imm1(dst, rshift, cr);
9508 %}
9509 %}
9511 // ROR 32bit by immI8 once
9512 instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
9513 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9514 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9516 expand %{
9517 rorI_eReg_imm8(dst, rshift, cr);
9518 %}
9519 %}
9521 // ROR 32bit var by var once
9522 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
9523 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
9525 expand %{
9526 rorI_eReg_CL(dst, shift, cr);
9527 %}
9528 %}
9530 // ROR 32bit var by var once
9531 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
9532 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
9534 expand %{
9535 rorI_eReg_CL(dst, shift, cr);
9536 %}
9537 %}
9539 // Xor Instructions
9540 // Xor Register with Register
9541 instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
9542 match(Set dst (XorI dst src));
9543 effect(KILL cr);
9545 size(2);
9546 format %{ "XOR $dst,$src" %}
9547 opcode(0x33);
9548 ins_encode( OpcP, RegReg( dst, src) );
9549 ins_pipe( ialu_reg_reg );
9550 %}
9552 // Xor Register with Immediate -1
9553 instruct xorI_eReg_im1(eRegI dst, immI_M1 imm) %{
9554 match(Set dst (XorI dst imm));
9556 size(2);
9557 format %{ "NOT $dst" %}
9558 ins_encode %{
9559 __ notl($dst$$Register);
9560 %}
9561 ins_pipe( ialu_reg );
9562 %}
9564 // Xor Register with Immediate
9565 instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
9566 match(Set dst (XorI dst src));
9567 effect(KILL cr);
9569 format %{ "XOR $dst,$src" %}
9570 opcode(0x81,0x06); /* Opcode 81 /6 id */
9571 // ins_encode( RegImm( dst, src) );
9572 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
9573 ins_pipe( ialu_reg );
9574 %}
9576 // Xor Register with Memory
9577 instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
9578 match(Set dst (XorI dst (LoadI src)));
9579 effect(KILL cr);
9581 ins_cost(125);
9582 format %{ "XOR $dst,$src" %}
9583 opcode(0x33);
9584 ins_encode( OpcP, RegMem(dst, src) );
9585 ins_pipe( ialu_reg_mem );
9586 %}
9588 // Xor Memory with Register
9589 instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
9590 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9591 effect(KILL cr);
9593 ins_cost(150);
9594 format %{ "XOR $dst,$src" %}
9595 opcode(0x31); /* Opcode 31 /r */
9596 ins_encode( OpcP, RegMem( src, dst ) );
9597 ins_pipe( ialu_mem_reg );
9598 %}
9600 // Xor Memory with Immediate
9601 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
9602 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9603 effect(KILL cr);
9605 ins_cost(125);
9606 format %{ "XOR $dst,$src" %}
9607 opcode(0x81,0x6); /* Opcode 81 /6 id */
9608 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
9609 ins_pipe( ialu_mem_imm );
9610 %}
9612 //----------Convert Int to Boolean---------------------------------------------
9614 instruct movI_nocopy(eRegI dst, eRegI src) %{
9615 effect( DEF dst, USE src );
9616 format %{ "MOV $dst,$src" %}
9617 ins_encode( enc_Copy( dst, src) );
9618 ins_pipe( ialu_reg_reg );
9619 %}
9621 instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{
9622 effect( USE_DEF dst, USE src, KILL cr );
9624 size(4);
9625 format %{ "NEG $dst\n\t"
9626 "ADC $dst,$src" %}
9627 ins_encode( neg_reg(dst),
9628 OpcRegReg(0x13,dst,src) );
9629 ins_pipe( ialu_reg_reg_long );
9630 %}
9632 instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{
9633 match(Set dst (Conv2B src));
9635 expand %{
9636 movI_nocopy(dst,src);
9637 ci2b(dst,src,cr);
9638 %}
9639 %}
9641 instruct movP_nocopy(eRegI dst, eRegP src) %{
9642 effect( DEF dst, USE src );
9643 format %{ "MOV $dst,$src" %}
9644 ins_encode( enc_Copy( dst, src) );
9645 ins_pipe( ialu_reg_reg );
9646 %}
9648 instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{
9649 effect( USE_DEF dst, USE src, KILL cr );
9650 format %{ "NEG $dst\n\t"
9651 "ADC $dst,$src" %}
9652 ins_encode( neg_reg(dst),
9653 OpcRegReg(0x13,dst,src) );
9654 ins_pipe( ialu_reg_reg_long );
9655 %}
9657 instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{
9658 match(Set dst (Conv2B src));
9660 expand %{
9661 movP_nocopy(dst,src);
9662 cp2b(dst,src,cr);
9663 %}
9664 %}
9666 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{
9667 match(Set dst (CmpLTMask p q));
9668 effect( KILL cr );
9669 ins_cost(400);
9671 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
9672 format %{ "XOR $dst,$dst\n\t"
9673 "CMP $p,$q\n\t"
9674 "SETlt $dst\n\t"
9675 "NEG $dst" %}
9676 ins_encode( OpcRegReg(0x33,dst,dst),
9677 OpcRegReg(0x3B,p,q),
9678 setLT_reg(dst), neg_reg(dst) );
9679 ins_pipe( pipe_slow );
9680 %}
9682 instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{
9683 match(Set dst (CmpLTMask dst zero));
9684 effect( DEF dst, KILL cr );
9685 ins_cost(100);
9687 format %{ "SAR $dst,31" %}
9688 opcode(0xC1, 0x7); /* C1 /7 ib */
9689 ins_encode( RegOpcImm( dst, 0x1F ) );
9690 ins_pipe( ialu_reg );
9691 %}
9694 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{
9695 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9696 effect( KILL tmp, KILL cr );
9697 ins_cost(400);
9698 // annoyingly, $tmp has no edges so you cant ask for it in
9699 // any format or encoding
9700 format %{ "SUB $p,$q\n\t"
9701 "SBB ECX,ECX\n\t"
9702 "AND ECX,$y\n\t"
9703 "ADD $p,ECX" %}
9704 ins_encode( enc_cmpLTP(p,q,y,tmp) );
9705 ins_pipe( pipe_cmplt );
9706 %}
9708 /* If I enable this, I encourage spilling in the inner loop of compress.
9709 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{
9710 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
9711 effect( USE_KILL tmp, KILL cr );
9712 ins_cost(400);
9714 format %{ "SUB $p,$q\n\t"
9715 "SBB ECX,ECX\n\t"
9716 "AND ECX,$y\n\t"
9717 "ADD $p,ECX" %}
9718 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
9719 %}
9720 */
9722 //----------Long Instructions------------------------------------------------
9723 // Add Long Register with Register
9724 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9725 match(Set dst (AddL dst src));
9726 effect(KILL cr);
9727 ins_cost(200);
9728 format %{ "ADD $dst.lo,$src.lo\n\t"
9729 "ADC $dst.hi,$src.hi" %}
9730 opcode(0x03, 0x13);
9731 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9732 ins_pipe( ialu_reg_reg_long );
9733 %}
9735 // Add Long Register with Immediate
9736 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9737 match(Set dst (AddL dst src));
9738 effect(KILL cr);
9739 format %{ "ADD $dst.lo,$src.lo\n\t"
9740 "ADC $dst.hi,$src.hi" %}
9741 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
9742 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9743 ins_pipe( ialu_reg_long );
9744 %}
9746 // Add Long Register with Memory
9747 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9748 match(Set dst (AddL dst (LoadL mem)));
9749 effect(KILL cr);
9750 ins_cost(125);
9751 format %{ "ADD $dst.lo,$mem\n\t"
9752 "ADC $dst.hi,$mem+4" %}
9753 opcode(0x03, 0x13);
9754 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9755 ins_pipe( ialu_reg_long_mem );
9756 %}
9758 // Subtract Long Register with Register.
9759 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9760 match(Set dst (SubL dst src));
9761 effect(KILL cr);
9762 ins_cost(200);
9763 format %{ "SUB $dst.lo,$src.lo\n\t"
9764 "SBB $dst.hi,$src.hi" %}
9765 opcode(0x2B, 0x1B);
9766 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9767 ins_pipe( ialu_reg_reg_long );
9768 %}
9770 // Subtract Long Register with Immediate
9771 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9772 match(Set dst (SubL dst src));
9773 effect(KILL cr);
9774 format %{ "SUB $dst.lo,$src.lo\n\t"
9775 "SBB $dst.hi,$src.hi" %}
9776 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9777 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9778 ins_pipe( ialu_reg_long );
9779 %}
9781 // Subtract Long Register with Memory
9782 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9783 match(Set dst (SubL dst (LoadL mem)));
9784 effect(KILL cr);
9785 ins_cost(125);
9786 format %{ "SUB $dst.lo,$mem\n\t"
9787 "SBB $dst.hi,$mem+4" %}
9788 opcode(0x2B, 0x1B);
9789 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9790 ins_pipe( ialu_reg_long_mem );
9791 %}
9793 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9794 match(Set dst (SubL zero dst));
9795 effect(KILL cr);
9796 ins_cost(300);
9797 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9798 ins_encode( neg_long(dst) );
9799 ins_pipe( ialu_reg_reg_long );
9800 %}
9802 // And Long Register with Register
9803 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9804 match(Set dst (AndL dst src));
9805 effect(KILL cr);
9806 format %{ "AND $dst.lo,$src.lo\n\t"
9807 "AND $dst.hi,$src.hi" %}
9808 opcode(0x23,0x23);
9809 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9810 ins_pipe( ialu_reg_reg_long );
9811 %}
9813 // And Long Register with Immediate
9814 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9815 match(Set dst (AndL dst src));
9816 effect(KILL cr);
9817 format %{ "AND $dst.lo,$src.lo\n\t"
9818 "AND $dst.hi,$src.hi" %}
9819 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9820 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9821 ins_pipe( ialu_reg_long );
9822 %}
9824 // And Long Register with Memory
9825 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9826 match(Set dst (AndL dst (LoadL mem)));
9827 effect(KILL cr);
9828 ins_cost(125);
9829 format %{ "AND $dst.lo,$mem\n\t"
9830 "AND $dst.hi,$mem+4" %}
9831 opcode(0x23, 0x23);
9832 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9833 ins_pipe( ialu_reg_long_mem );
9834 %}
9836 // Or Long Register with Register
9837 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9838 match(Set dst (OrL dst src));
9839 effect(KILL cr);
9840 format %{ "OR $dst.lo,$src.lo\n\t"
9841 "OR $dst.hi,$src.hi" %}
9842 opcode(0x0B,0x0B);
9843 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9844 ins_pipe( ialu_reg_reg_long );
9845 %}
9847 // Or Long Register with Immediate
9848 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9849 match(Set dst (OrL dst src));
9850 effect(KILL cr);
9851 format %{ "OR $dst.lo,$src.lo\n\t"
9852 "OR $dst.hi,$src.hi" %}
9853 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9854 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9855 ins_pipe( ialu_reg_long );
9856 %}
9858 // Or Long Register with Memory
9859 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9860 match(Set dst (OrL dst (LoadL mem)));
9861 effect(KILL cr);
9862 ins_cost(125);
9863 format %{ "OR $dst.lo,$mem\n\t"
9864 "OR $dst.hi,$mem+4" %}
9865 opcode(0x0B,0x0B);
9866 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9867 ins_pipe( ialu_reg_long_mem );
9868 %}
9870 // Xor Long Register with Register
9871 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9872 match(Set dst (XorL dst src));
9873 effect(KILL cr);
9874 format %{ "XOR $dst.lo,$src.lo\n\t"
9875 "XOR $dst.hi,$src.hi" %}
9876 opcode(0x33,0x33);
9877 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9878 ins_pipe( ialu_reg_reg_long );
9879 %}
9881 // Xor Long Register with Immediate -1
9882 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9883 match(Set dst (XorL dst imm));
9884 format %{ "NOT $dst.lo\n\t"
9885 "NOT $dst.hi" %}
9886 ins_encode %{
9887 __ notl($dst$$Register);
9888 __ notl(HIGH_FROM_LOW($dst$$Register));
9889 %}
9890 ins_pipe( ialu_reg_long );
9891 %}
9893 // Xor Long Register with Immediate
9894 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9895 match(Set dst (XorL dst src));
9896 effect(KILL cr);
9897 format %{ "XOR $dst.lo,$src.lo\n\t"
9898 "XOR $dst.hi,$src.hi" %}
9899 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9900 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9901 ins_pipe( ialu_reg_long );
9902 %}
9904 // Xor Long Register with Memory
9905 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9906 match(Set dst (XorL dst (LoadL mem)));
9907 effect(KILL cr);
9908 ins_cost(125);
9909 format %{ "XOR $dst.lo,$mem\n\t"
9910 "XOR $dst.hi,$mem+4" %}
9911 opcode(0x33,0x33);
9912 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9913 ins_pipe( ialu_reg_long_mem );
9914 %}
9916 // Shift Left Long by 1
9917 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9918 predicate(UseNewLongLShift);
9919 match(Set dst (LShiftL dst cnt));
9920 effect(KILL cr);
9921 ins_cost(100);
9922 format %{ "ADD $dst.lo,$dst.lo\n\t"
9923 "ADC $dst.hi,$dst.hi" %}
9924 ins_encode %{
9925 __ addl($dst$$Register,$dst$$Register);
9926 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9927 %}
9928 ins_pipe( ialu_reg_long );
9929 %}
9931 // Shift Left Long by 2
9932 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9933 predicate(UseNewLongLShift);
9934 match(Set dst (LShiftL dst cnt));
9935 effect(KILL cr);
9936 ins_cost(100);
9937 format %{ "ADD $dst.lo,$dst.lo\n\t"
9938 "ADC $dst.hi,$dst.hi\n\t"
9939 "ADD $dst.lo,$dst.lo\n\t"
9940 "ADC $dst.hi,$dst.hi" %}
9941 ins_encode %{
9942 __ addl($dst$$Register,$dst$$Register);
9943 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9944 __ addl($dst$$Register,$dst$$Register);
9945 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9946 %}
9947 ins_pipe( ialu_reg_long );
9948 %}
9950 // Shift Left Long by 3
9951 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9952 predicate(UseNewLongLShift);
9953 match(Set dst (LShiftL dst cnt));
9954 effect(KILL cr);
9955 ins_cost(100);
9956 format %{ "ADD $dst.lo,$dst.lo\n\t"
9957 "ADC $dst.hi,$dst.hi\n\t"
9958 "ADD $dst.lo,$dst.lo\n\t"
9959 "ADC $dst.hi,$dst.hi\n\t"
9960 "ADD $dst.lo,$dst.lo\n\t"
9961 "ADC $dst.hi,$dst.hi" %}
9962 ins_encode %{
9963 __ addl($dst$$Register,$dst$$Register);
9964 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9965 __ addl($dst$$Register,$dst$$Register);
9966 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9967 __ addl($dst$$Register,$dst$$Register);
9968 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9969 %}
9970 ins_pipe( ialu_reg_long );
9971 %}
9973 // Shift Left Long by 1-31
9974 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9975 match(Set dst (LShiftL dst cnt));
9976 effect(KILL cr);
9977 ins_cost(200);
9978 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9979 "SHL $dst.lo,$cnt" %}
9980 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9981 ins_encode( move_long_small_shift(dst,cnt) );
9982 ins_pipe( ialu_reg_long );
9983 %}
9985 // Shift Left Long by 32-63
9986 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9987 match(Set dst (LShiftL dst cnt));
9988 effect(KILL cr);
9989 ins_cost(300);
9990 format %{ "MOV $dst.hi,$dst.lo\n"
9991 "\tSHL $dst.hi,$cnt-32\n"
9992 "\tXOR $dst.lo,$dst.lo" %}
9993 opcode(0xC1, 0x4); /* C1 /4 ib */
9994 ins_encode( move_long_big_shift_clr(dst,cnt) );
9995 ins_pipe( ialu_reg_long );
9996 %}
9998 // Shift Left Long by variable
9999 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
10000 match(Set dst (LShiftL dst shift));
10001 effect(KILL cr);
10002 ins_cost(500+200);
10003 size(17);
10004 format %{ "TEST $shift,32\n\t"
10005 "JEQ,s small\n\t"
10006 "MOV $dst.hi,$dst.lo\n\t"
10007 "XOR $dst.lo,$dst.lo\n"
10008 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
10009 "SHL $dst.lo,$shift" %}
10010 ins_encode( shift_left_long( dst, shift ) );
10011 ins_pipe( pipe_slow );
10012 %}
10014 // Shift Right Long by 1-31
10015 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
10016 match(Set dst (URShiftL dst cnt));
10017 effect(KILL cr);
10018 ins_cost(200);
10019 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
10020 "SHR $dst.hi,$cnt" %}
10021 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
10022 ins_encode( move_long_small_shift(dst,cnt) );
10023 ins_pipe( ialu_reg_long );
10024 %}
10026 // Shift Right Long by 32-63
10027 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
10028 match(Set dst (URShiftL dst cnt));
10029 effect(KILL cr);
10030 ins_cost(300);
10031 format %{ "MOV $dst.lo,$dst.hi\n"
10032 "\tSHR $dst.lo,$cnt-32\n"
10033 "\tXOR $dst.hi,$dst.hi" %}
10034 opcode(0xC1, 0x5); /* C1 /5 ib */
10035 ins_encode( move_long_big_shift_clr(dst,cnt) );
10036 ins_pipe( ialu_reg_long );
10037 %}
10039 // Shift Right Long by variable
10040 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
10041 match(Set dst (URShiftL dst shift));
10042 effect(KILL cr);
10043 ins_cost(600);
10044 size(17);
10045 format %{ "TEST $shift,32\n\t"
10046 "JEQ,s small\n\t"
10047 "MOV $dst.lo,$dst.hi\n\t"
10048 "XOR $dst.hi,$dst.hi\n"
10049 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
10050 "SHR $dst.hi,$shift" %}
10051 ins_encode( shift_right_long( dst, shift ) );
10052 ins_pipe( pipe_slow );
10053 %}
10055 // Shift Right Long by 1-31
10056 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
10057 match(Set dst (RShiftL dst cnt));
10058 effect(KILL cr);
10059 ins_cost(200);
10060 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
10061 "SAR $dst.hi,$cnt" %}
10062 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
10063 ins_encode( move_long_small_shift(dst,cnt) );
10064 ins_pipe( ialu_reg_long );
10065 %}
10067 // Shift Right Long by 32-63
10068 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
10069 match(Set dst (RShiftL dst cnt));
10070 effect(KILL cr);
10071 ins_cost(300);
10072 format %{ "MOV $dst.lo,$dst.hi\n"
10073 "\tSAR $dst.lo,$cnt-32\n"
10074 "\tSAR $dst.hi,31" %}
10075 opcode(0xC1, 0x7); /* C1 /7 ib */
10076 ins_encode( move_long_big_shift_sign(dst,cnt) );
10077 ins_pipe( ialu_reg_long );
10078 %}
10080 // Shift Right arithmetic Long by variable
10081 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
10082 match(Set dst (RShiftL dst shift));
10083 effect(KILL cr);
10084 ins_cost(600);
10085 size(18);
10086 format %{ "TEST $shift,32\n\t"
10087 "JEQ,s small\n\t"
10088 "MOV $dst.lo,$dst.hi\n\t"
10089 "SAR $dst.hi,31\n"
10090 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
10091 "SAR $dst.hi,$shift" %}
10092 ins_encode( shift_right_arith_long( dst, shift ) );
10093 ins_pipe( pipe_slow );
10094 %}
10097 //----------Double Instructions------------------------------------------------
10098 // Double Math
10100 // Compare & branch
10102 // P6 version of float compare, sets condition codes in EFLAGS
10103 instruct cmpD_cc_P6(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
10104 predicate(VM_Version::supports_cmov() && UseSSE <=1);
10105 match(Set cr (CmpD src1 src2));
10106 effect(KILL rax);
10107 ins_cost(150);
10108 format %{ "FLD $src1\n\t"
10109 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10110 "JNP exit\n\t"
10111 "MOV ah,1 // saw a NaN, set CF\n\t"
10112 "SAHF\n"
10113 "exit:\tNOP // avoid branch to branch" %}
10114 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10115 ins_encode( Push_Reg_D(src1),
10116 OpcP, RegOpc(src2),
10117 cmpF_P6_fixup );
10118 ins_pipe( pipe_slow );
10119 %}
10121 instruct cmpD_cc_P6CF(eFlagsRegUCF cr, regD src1, regD src2) %{
10122 predicate(VM_Version::supports_cmov() && UseSSE <=1);
10123 match(Set cr (CmpD src1 src2));
10124 ins_cost(150);
10125 format %{ "FLD $src1\n\t"
10126 "FUCOMIP ST,$src2 // P6 instruction" %}
10127 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10128 ins_encode( Push_Reg_D(src1),
10129 OpcP, RegOpc(src2));
10130 ins_pipe( pipe_slow );
10131 %}
10133 // Compare & branch
10134 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
10135 predicate(UseSSE<=1);
10136 match(Set cr (CmpD src1 src2));
10137 effect(KILL rax);
10138 ins_cost(200);
10139 format %{ "FLD $src1\n\t"
10140 "FCOMp $src2\n\t"
10141 "FNSTSW AX\n\t"
10142 "TEST AX,0x400\n\t"
10143 "JZ,s flags\n\t"
10144 "MOV AH,1\t# unordered treat as LT\n"
10145 "flags:\tSAHF" %}
10146 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10147 ins_encode( Push_Reg_D(src1),
10148 OpcP, RegOpc(src2),
10149 fpu_flags);
10150 ins_pipe( pipe_slow );
10151 %}
10153 // Compare vs zero into -1,0,1
10154 instruct cmpD_0(eRegI dst, regD src1, immD0 zero, eAXRegI rax, eFlagsReg cr) %{
10155 predicate(UseSSE<=1);
10156 match(Set dst (CmpD3 src1 zero));
10157 effect(KILL cr, KILL rax);
10158 ins_cost(280);
10159 format %{ "FTSTD $dst,$src1" %}
10160 opcode(0xE4, 0xD9);
10161 ins_encode( Push_Reg_D(src1),
10162 OpcS, OpcP, PopFPU,
10163 CmpF_Result(dst));
10164 ins_pipe( pipe_slow );
10165 %}
10167 // Compare into -1,0,1
10168 instruct cmpD_reg(eRegI dst, regD src1, regD src2, eAXRegI rax, eFlagsReg cr) %{
10169 predicate(UseSSE<=1);
10170 match(Set dst (CmpD3 src1 src2));
10171 effect(KILL cr, KILL rax);
10172 ins_cost(300);
10173 format %{ "FCMPD $dst,$src1,$src2" %}
10174 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10175 ins_encode( Push_Reg_D(src1),
10176 OpcP, RegOpc(src2),
10177 CmpF_Result(dst));
10178 ins_pipe( pipe_slow );
10179 %}
10181 // float compare and set condition codes in EFLAGS by XMM regs
10182 instruct cmpXD_cc(eFlagsRegU cr, regXD dst, regXD src, eAXRegI rax) %{
10183 predicate(UseSSE>=2);
10184 match(Set cr (CmpD dst src));
10185 effect(KILL rax);
10186 ins_cost(125);
10187 format %{ "COMISD $dst,$src\n"
10188 "\tJNP exit\n"
10189 "\tMOV ah,1 // saw a NaN, set CF\n"
10190 "\tSAHF\n"
10191 "exit:\tNOP // avoid branch to branch" %}
10192 opcode(0x66, 0x0F, 0x2F);
10193 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src), cmpF_P6_fixup);
10194 ins_pipe( pipe_slow );
10195 %}
10197 instruct cmpXD_ccCF(eFlagsRegUCF cr, regXD dst, regXD src) %{
10198 predicate(UseSSE>=2);
10199 match(Set cr (CmpD dst src));
10200 ins_cost(100);
10201 format %{ "COMISD $dst,$src" %}
10202 opcode(0x66, 0x0F, 0x2F);
10203 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
10204 ins_pipe( pipe_slow );
10205 %}
10207 // float compare and set condition codes in EFLAGS by XMM regs
10208 instruct cmpXD_ccmem(eFlagsRegU cr, regXD dst, memory src, eAXRegI rax) %{
10209 predicate(UseSSE>=2);
10210 match(Set cr (CmpD dst (LoadD src)));
10211 effect(KILL rax);
10212 ins_cost(145);
10213 format %{ "COMISD $dst,$src\n"
10214 "\tJNP exit\n"
10215 "\tMOV ah,1 // saw a NaN, set CF\n"
10216 "\tSAHF\n"
10217 "exit:\tNOP // avoid branch to branch" %}
10218 opcode(0x66, 0x0F, 0x2F);
10219 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src), cmpF_P6_fixup);
10220 ins_pipe( pipe_slow );
10221 %}
10223 instruct cmpXD_ccmemCF(eFlagsRegUCF cr, regXD dst, memory src) %{
10224 predicate(UseSSE>=2);
10225 match(Set cr (CmpD dst (LoadD src)));
10226 ins_cost(100);
10227 format %{ "COMISD $dst,$src" %}
10228 opcode(0x66, 0x0F, 0x2F);
10229 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src));
10230 ins_pipe( pipe_slow );
10231 %}
10233 // Compare into -1,0,1 in XMM
10234 instruct cmpXD_reg(eRegI dst, regXD src1, regXD src2, eFlagsReg cr) %{
10235 predicate(UseSSE>=2);
10236 match(Set dst (CmpD3 src1 src2));
10237 effect(KILL cr);
10238 ins_cost(255);
10239 format %{ "XOR $dst,$dst\n"
10240 "\tCOMISD $src1,$src2\n"
10241 "\tJP,s nan\n"
10242 "\tJEQ,s exit\n"
10243 "\tJA,s inc\n"
10244 "nan:\tDEC $dst\n"
10245 "\tJMP,s exit\n"
10246 "inc:\tINC $dst\n"
10247 "exit:"
10248 %}
10249 opcode(0x66, 0x0F, 0x2F);
10250 ins_encode(Xor_Reg(dst), OpcP, OpcS, Opcode(tertiary), RegReg(src1, src2),
10251 CmpX_Result(dst));
10252 ins_pipe( pipe_slow );
10253 %}
10255 // Compare into -1,0,1 in XMM and memory
10256 instruct cmpXD_regmem(eRegI dst, regXD src1, memory mem, eFlagsReg cr) %{
10257 predicate(UseSSE>=2);
10258 match(Set dst (CmpD3 src1 (LoadD mem)));
10259 effect(KILL cr);
10260 ins_cost(275);
10261 format %{ "COMISD $src1,$mem\n"
10262 "\tMOV $dst,0\t\t# do not blow flags\n"
10263 "\tJP,s nan\n"
10264 "\tJEQ,s exit\n"
10265 "\tJA,s inc\n"
10266 "nan:\tDEC $dst\n"
10267 "\tJMP,s exit\n"
10268 "inc:\tINC $dst\n"
10269 "exit:"
10270 %}
10271 opcode(0x66, 0x0F, 0x2F);
10272 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(src1, mem),
10273 LdImmI(dst,0x0), CmpX_Result(dst));
10274 ins_pipe( pipe_slow );
10275 %}
10278 instruct subD_reg(regD dst, regD src) %{
10279 predicate (UseSSE <=1);
10280 match(Set dst (SubD dst src));
10282 format %{ "FLD $src\n\t"
10283 "DSUBp $dst,ST" %}
10284 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10285 ins_cost(150);
10286 ins_encode( Push_Reg_D(src),
10287 OpcP, RegOpc(dst) );
10288 ins_pipe( fpu_reg_reg );
10289 %}
10291 instruct subD_reg_round(stackSlotD dst, regD src1, regD src2) %{
10292 predicate (UseSSE <=1);
10293 match(Set dst (RoundDouble (SubD src1 src2)));
10294 ins_cost(250);
10296 format %{ "FLD $src2\n\t"
10297 "DSUB ST,$src1\n\t"
10298 "FSTP_D $dst\t# D-round" %}
10299 opcode(0xD8, 0x5);
10300 ins_encode( Push_Reg_D(src2),
10301 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
10302 ins_pipe( fpu_mem_reg_reg );
10303 %}
10306 instruct subD_reg_mem(regD dst, memory src) %{
10307 predicate (UseSSE <=1);
10308 match(Set dst (SubD dst (LoadD src)));
10309 ins_cost(150);
10311 format %{ "FLD $src\n\t"
10312 "DSUBp $dst,ST" %}
10313 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
10314 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10315 OpcP, RegOpc(dst) );
10316 ins_pipe( fpu_reg_mem );
10317 %}
10319 instruct absD_reg(regDPR1 dst, regDPR1 src) %{
10320 predicate (UseSSE<=1);
10321 match(Set dst (AbsD src));
10322 ins_cost(100);
10323 format %{ "FABS" %}
10324 opcode(0xE1, 0xD9);
10325 ins_encode( OpcS, OpcP );
10326 ins_pipe( fpu_reg_reg );
10327 %}
10329 instruct absXD_reg( regXD dst ) %{
10330 predicate(UseSSE>=2);
10331 match(Set dst (AbsD dst));
10332 format %{ "ANDPD $dst,[0x7FFFFFFFFFFFFFFF]\t# ABS D by sign masking" %}
10333 ins_encode( AbsXD_encoding(dst));
10334 ins_pipe( pipe_slow );
10335 %}
10337 instruct negD_reg(regDPR1 dst, regDPR1 src) %{
10338 predicate(UseSSE<=1);
10339 match(Set dst (NegD src));
10340 ins_cost(100);
10341 format %{ "FCHS" %}
10342 opcode(0xE0, 0xD9);
10343 ins_encode( OpcS, OpcP );
10344 ins_pipe( fpu_reg_reg );
10345 %}
10347 instruct negXD_reg( regXD dst ) %{
10348 predicate(UseSSE>=2);
10349 match(Set dst (NegD dst));
10350 format %{ "XORPD $dst,[0x8000000000000000]\t# CHS D by sign flipping" %}
10351 ins_encode %{
10352 __ xorpd($dst$$XMMRegister,
10353 ExternalAddress((address)double_signflip_pool));
10354 %}
10355 ins_pipe( pipe_slow );
10356 %}
10358 instruct addD_reg(regD dst, regD src) %{
10359 predicate(UseSSE<=1);
10360 match(Set dst (AddD dst src));
10361 format %{ "FLD $src\n\t"
10362 "DADD $dst,ST" %}
10363 size(4);
10364 ins_cost(150);
10365 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10366 ins_encode( Push_Reg_D(src),
10367 OpcP, RegOpc(dst) );
10368 ins_pipe( fpu_reg_reg );
10369 %}
10372 instruct addD_reg_round(stackSlotD dst, regD src1, regD src2) %{
10373 predicate(UseSSE<=1);
10374 match(Set dst (RoundDouble (AddD src1 src2)));
10375 ins_cost(250);
10377 format %{ "FLD $src2\n\t"
10378 "DADD ST,$src1\n\t"
10379 "FSTP_D $dst\t# D-round" %}
10380 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
10381 ins_encode( Push_Reg_D(src2),
10382 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
10383 ins_pipe( fpu_mem_reg_reg );
10384 %}
10387 instruct addD_reg_mem(regD dst, memory src) %{
10388 predicate(UseSSE<=1);
10389 match(Set dst (AddD dst (LoadD src)));
10390 ins_cost(150);
10392 format %{ "FLD $src\n\t"
10393 "DADDp $dst,ST" %}
10394 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
10395 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10396 OpcP, RegOpc(dst) );
10397 ins_pipe( fpu_reg_mem );
10398 %}
10400 // add-to-memory
10401 instruct addD_mem_reg(memory dst, regD src) %{
10402 predicate(UseSSE<=1);
10403 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
10404 ins_cost(150);
10406 format %{ "FLD_D $dst\n\t"
10407 "DADD ST,$src\n\t"
10408 "FST_D $dst" %}
10409 opcode(0xDD, 0x0);
10410 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
10411 Opcode(0xD8), RegOpc(src),
10412 set_instruction_start,
10413 Opcode(0xDD), RMopc_Mem(0x03,dst) );
10414 ins_pipe( fpu_reg_mem );
10415 %}
10417 instruct addD_reg_imm1(regD dst, immD1 src) %{
10418 predicate(UseSSE<=1);
10419 match(Set dst (AddD dst src));
10420 ins_cost(125);
10421 format %{ "FLD1\n\t"
10422 "DADDp $dst,ST" %}
10423 opcode(0xDE, 0x00);
10424 ins_encode( LdImmD(src),
10425 OpcP, RegOpc(dst) );
10426 ins_pipe( fpu_reg );
10427 %}
10429 instruct addD_reg_imm(regD dst, immD src) %{
10430 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
10431 match(Set dst (AddD dst src));
10432 ins_cost(200);
10433 format %{ "FLD_D [$src]\n\t"
10434 "DADDp $dst,ST" %}
10435 opcode(0xDE, 0x00); /* DE /0 */
10436 ins_encode( LdImmD(src),
10437 OpcP, RegOpc(dst));
10438 ins_pipe( fpu_reg_mem );
10439 %}
10441 instruct addD_reg_imm_round(stackSlotD dst, regD src, immD con) %{
10442 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
10443 match(Set dst (RoundDouble (AddD src con)));
10444 ins_cost(200);
10445 format %{ "FLD_D [$con]\n\t"
10446 "DADD ST,$src\n\t"
10447 "FSTP_D $dst\t# D-round" %}
10448 opcode(0xD8, 0x00); /* D8 /0 */
10449 ins_encode( LdImmD(con),
10450 OpcP, RegOpc(src), Pop_Mem_D(dst));
10451 ins_pipe( fpu_mem_reg_con );
10452 %}
10454 // Add two double precision floating point values in xmm
10455 instruct addXD_reg(regXD dst, regXD src) %{
10456 predicate(UseSSE>=2);
10457 match(Set dst (AddD dst src));
10458 format %{ "ADDSD $dst,$src" %}
10459 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
10460 ins_pipe( pipe_slow );
10461 %}
10463 instruct addXD_imm(regXD dst, immXD con) %{
10464 predicate(UseSSE>=2);
10465 match(Set dst (AddD dst con));
10466 format %{ "ADDSD $dst,[$con]" %}
10467 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), LdImmXD(dst, con) );
10468 ins_pipe( pipe_slow );
10469 %}
10471 instruct addXD_mem(regXD dst, memory mem) %{
10472 predicate(UseSSE>=2);
10473 match(Set dst (AddD dst (LoadD mem)));
10474 format %{ "ADDSD $dst,$mem" %}
10475 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegMem(dst,mem));
10476 ins_pipe( pipe_slow );
10477 %}
10479 // Sub two double precision floating point values in xmm
10480 instruct subXD_reg(regXD dst, regXD src) %{
10481 predicate(UseSSE>=2);
10482 match(Set dst (SubD dst src));
10483 format %{ "SUBSD $dst,$src" %}
10484 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
10485 ins_pipe( pipe_slow );
10486 %}
10488 instruct subXD_imm(regXD dst, immXD con) %{
10489 predicate(UseSSE>=2);
10490 match(Set dst (SubD dst con));
10491 format %{ "SUBSD $dst,[$con]" %}
10492 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), LdImmXD(dst, con) );
10493 ins_pipe( pipe_slow );
10494 %}
10496 instruct subXD_mem(regXD dst, memory mem) %{
10497 predicate(UseSSE>=2);
10498 match(Set dst (SubD dst (LoadD mem)));
10499 format %{ "SUBSD $dst,$mem" %}
10500 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
10501 ins_pipe( pipe_slow );
10502 %}
10504 // Mul two double precision floating point values in xmm
10505 instruct mulXD_reg(regXD dst, regXD src) %{
10506 predicate(UseSSE>=2);
10507 match(Set dst (MulD dst src));
10508 format %{ "MULSD $dst,$src" %}
10509 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
10510 ins_pipe( pipe_slow );
10511 %}
10513 instruct mulXD_imm(regXD dst, immXD con) %{
10514 predicate(UseSSE>=2);
10515 match(Set dst (MulD dst con));
10516 format %{ "MULSD $dst,[$con]" %}
10517 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), LdImmXD(dst, con) );
10518 ins_pipe( pipe_slow );
10519 %}
10521 instruct mulXD_mem(regXD dst, memory mem) %{
10522 predicate(UseSSE>=2);
10523 match(Set dst (MulD dst (LoadD mem)));
10524 format %{ "MULSD $dst,$mem" %}
10525 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
10526 ins_pipe( pipe_slow );
10527 %}
10529 // Div two double precision floating point values in xmm
10530 instruct divXD_reg(regXD dst, regXD src) %{
10531 predicate(UseSSE>=2);
10532 match(Set dst (DivD dst src));
10533 format %{ "DIVSD $dst,$src" %}
10534 opcode(0xF2, 0x0F, 0x5E);
10535 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
10536 ins_pipe( pipe_slow );
10537 %}
10539 instruct divXD_imm(regXD dst, immXD con) %{
10540 predicate(UseSSE>=2);
10541 match(Set dst (DivD dst con));
10542 format %{ "DIVSD $dst,[$con]" %}
10543 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), LdImmXD(dst, con));
10544 ins_pipe( pipe_slow );
10545 %}
10547 instruct divXD_mem(regXD dst, memory mem) %{
10548 predicate(UseSSE>=2);
10549 match(Set dst (DivD dst (LoadD mem)));
10550 format %{ "DIVSD $dst,$mem" %}
10551 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
10552 ins_pipe( pipe_slow );
10553 %}
10556 instruct mulD_reg(regD dst, regD src) %{
10557 predicate(UseSSE<=1);
10558 match(Set dst (MulD dst src));
10559 format %{ "FLD $src\n\t"
10560 "DMULp $dst,ST" %}
10561 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
10562 ins_cost(150);
10563 ins_encode( Push_Reg_D(src),
10564 OpcP, RegOpc(dst) );
10565 ins_pipe( fpu_reg_reg );
10566 %}
10568 // Strict FP instruction biases argument before multiply then
10569 // biases result to avoid double rounding of subnormals.
10570 //
10571 // scale arg1 by multiplying arg1 by 2^(-15360)
10572 // load arg2
10573 // multiply scaled arg1 by arg2
10574 // rescale product by 2^(15360)
10575 //
10576 instruct strictfp_mulD_reg(regDPR1 dst, regnotDPR1 src) %{
10577 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
10578 match(Set dst (MulD dst src));
10579 ins_cost(1); // Select this instruction for all strict FP double multiplies
10581 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
10582 "DMULp $dst,ST\n\t"
10583 "FLD $src\n\t"
10584 "DMULp $dst,ST\n\t"
10585 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
10586 "DMULp $dst,ST\n\t" %}
10587 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
10588 ins_encode( strictfp_bias1(dst),
10589 Push_Reg_D(src),
10590 OpcP, RegOpc(dst),
10591 strictfp_bias2(dst) );
10592 ins_pipe( fpu_reg_reg );
10593 %}
10595 instruct mulD_reg_imm(regD dst, immD src) %{
10596 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
10597 match(Set dst (MulD dst src));
10598 ins_cost(200);
10599 format %{ "FLD_D [$src]\n\t"
10600 "DMULp $dst,ST" %}
10601 opcode(0xDE, 0x1); /* DE /1 */
10602 ins_encode( LdImmD(src),
10603 OpcP, RegOpc(dst) );
10604 ins_pipe( fpu_reg_mem );
10605 %}
10608 instruct mulD_reg_mem(regD dst, memory src) %{
10609 predicate( UseSSE<=1 );
10610 match(Set dst (MulD dst (LoadD src)));
10611 ins_cost(200);
10612 format %{ "FLD_D $src\n\t"
10613 "DMULp $dst,ST" %}
10614 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
10615 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10616 OpcP, RegOpc(dst) );
10617 ins_pipe( fpu_reg_mem );
10618 %}
10620 //
10621 // Cisc-alternate to reg-reg multiply
10622 instruct mulD_reg_mem_cisc(regD dst, regD src, memory mem) %{
10623 predicate( UseSSE<=1 );
10624 match(Set dst (MulD src (LoadD mem)));
10625 ins_cost(250);
10626 format %{ "FLD_D $mem\n\t"
10627 "DMUL ST,$src\n\t"
10628 "FSTP_D $dst" %}
10629 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
10630 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
10631 OpcReg_F(src),
10632 Pop_Reg_D(dst) );
10633 ins_pipe( fpu_reg_reg_mem );
10634 %}
10637 // MACRO3 -- addD a mulD
10638 // This instruction is a '2-address' instruction in that the result goes
10639 // back to src2. This eliminates a move from the macro; possibly the
10640 // register allocator will have to add it back (and maybe not).
10641 instruct addD_mulD_reg(regD src2, regD src1, regD src0) %{
10642 predicate( UseSSE<=1 );
10643 match(Set src2 (AddD (MulD src0 src1) src2));
10644 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10645 "DMUL ST,$src1\n\t"
10646 "DADDp $src2,ST" %}
10647 ins_cost(250);
10648 opcode(0xDD); /* LoadD DD /0 */
10649 ins_encode( Push_Reg_F(src0),
10650 FMul_ST_reg(src1),
10651 FAddP_reg_ST(src2) );
10652 ins_pipe( fpu_reg_reg_reg );
10653 %}
10656 // MACRO3 -- subD a mulD
10657 instruct subD_mulD_reg(regD src2, regD src1, regD src0) %{
10658 predicate( UseSSE<=1 );
10659 match(Set src2 (SubD (MulD src0 src1) src2));
10660 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10661 "DMUL ST,$src1\n\t"
10662 "DSUBRp $src2,ST" %}
10663 ins_cost(250);
10664 ins_encode( Push_Reg_F(src0),
10665 FMul_ST_reg(src1),
10666 Opcode(0xDE), Opc_plus(0xE0,src2));
10667 ins_pipe( fpu_reg_reg_reg );
10668 %}
10671 instruct divD_reg(regD dst, regD src) %{
10672 predicate( UseSSE<=1 );
10673 match(Set dst (DivD dst src));
10675 format %{ "FLD $src\n\t"
10676 "FDIVp $dst,ST" %}
10677 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10678 ins_cost(150);
10679 ins_encode( Push_Reg_D(src),
10680 OpcP, RegOpc(dst) );
10681 ins_pipe( fpu_reg_reg );
10682 %}
10684 // Strict FP instruction biases argument before division then
10685 // biases result, to avoid double rounding of subnormals.
10686 //
10687 // scale dividend by multiplying dividend by 2^(-15360)
10688 // load divisor
10689 // divide scaled dividend by divisor
10690 // rescale quotient by 2^(15360)
10691 //
10692 instruct strictfp_divD_reg(regDPR1 dst, regnotDPR1 src) %{
10693 predicate (UseSSE<=1);
10694 match(Set dst (DivD dst src));
10695 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
10696 ins_cost(01);
10698 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
10699 "DMULp $dst,ST\n\t"
10700 "FLD $src\n\t"
10701 "FDIVp $dst,ST\n\t"
10702 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
10703 "DMULp $dst,ST\n\t" %}
10704 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10705 ins_encode( strictfp_bias1(dst),
10706 Push_Reg_D(src),
10707 OpcP, RegOpc(dst),
10708 strictfp_bias2(dst) );
10709 ins_pipe( fpu_reg_reg );
10710 %}
10712 instruct divD_reg_round(stackSlotD dst, regD src1, regD src2) %{
10713 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
10714 match(Set dst (RoundDouble (DivD src1 src2)));
10716 format %{ "FLD $src1\n\t"
10717 "FDIV ST,$src2\n\t"
10718 "FSTP_D $dst\t# D-round" %}
10719 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
10720 ins_encode( Push_Reg_D(src1),
10721 OpcP, RegOpc(src2), Pop_Mem_D(dst) );
10722 ins_pipe( fpu_mem_reg_reg );
10723 %}
10726 instruct modD_reg(regD dst, regD src, eAXRegI rax, eFlagsReg cr) %{
10727 predicate(UseSSE<=1);
10728 match(Set dst (ModD dst src));
10729 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
10731 format %{ "DMOD $dst,$src" %}
10732 ins_cost(250);
10733 ins_encode(Push_Reg_Mod_D(dst, src),
10734 emitModD(),
10735 Push_Result_Mod_D(src),
10736 Pop_Reg_D(dst));
10737 ins_pipe( pipe_slow );
10738 %}
10740 instruct modXD_reg(regXD dst, regXD src0, regXD src1, eAXRegI rax, eFlagsReg cr) %{
10741 predicate(UseSSE>=2);
10742 match(Set dst (ModD src0 src1));
10743 effect(KILL rax, KILL cr);
10745 format %{ "SUB ESP,8\t # DMOD\n"
10746 "\tMOVSD [ESP+0],$src1\n"
10747 "\tFLD_D [ESP+0]\n"
10748 "\tMOVSD [ESP+0],$src0\n"
10749 "\tFLD_D [ESP+0]\n"
10750 "loop:\tFPREM\n"
10751 "\tFWAIT\n"
10752 "\tFNSTSW AX\n"
10753 "\tSAHF\n"
10754 "\tJP loop\n"
10755 "\tFSTP_D [ESP+0]\n"
10756 "\tMOVSD $dst,[ESP+0]\n"
10757 "\tADD ESP,8\n"
10758 "\tFSTP ST0\t # Restore FPU Stack"
10759 %}
10760 ins_cost(250);
10761 ins_encode( Push_ModD_encoding(src0, src1), emitModD(), Push_ResultXD(dst), PopFPU);
10762 ins_pipe( pipe_slow );
10763 %}
10765 instruct sinD_reg(regDPR1 dst, regDPR1 src) %{
10766 predicate (UseSSE<=1);
10767 match(Set dst (SinD src));
10768 ins_cost(1800);
10769 format %{ "DSIN $dst" %}
10770 opcode(0xD9, 0xFE);
10771 ins_encode( OpcP, OpcS );
10772 ins_pipe( pipe_slow );
10773 %}
10775 instruct sinXD_reg(regXD dst, eFlagsReg cr) %{
10776 predicate (UseSSE>=2);
10777 match(Set dst (SinD dst));
10778 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10779 ins_cost(1800);
10780 format %{ "DSIN $dst" %}
10781 opcode(0xD9, 0xFE);
10782 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10783 ins_pipe( pipe_slow );
10784 %}
10786 instruct cosD_reg(regDPR1 dst, regDPR1 src) %{
10787 predicate (UseSSE<=1);
10788 match(Set dst (CosD src));
10789 ins_cost(1800);
10790 format %{ "DCOS $dst" %}
10791 opcode(0xD9, 0xFF);
10792 ins_encode( OpcP, OpcS );
10793 ins_pipe( pipe_slow );
10794 %}
10796 instruct cosXD_reg(regXD dst, eFlagsReg cr) %{
10797 predicate (UseSSE>=2);
10798 match(Set dst (CosD dst));
10799 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10800 ins_cost(1800);
10801 format %{ "DCOS $dst" %}
10802 opcode(0xD9, 0xFF);
10803 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10804 ins_pipe( pipe_slow );
10805 %}
10807 instruct tanD_reg(regDPR1 dst, regDPR1 src) %{
10808 predicate (UseSSE<=1);
10809 match(Set dst(TanD src));
10810 format %{ "DTAN $dst" %}
10811 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
10812 Opcode(0xDD), Opcode(0xD8)); // fstp st
10813 ins_pipe( pipe_slow );
10814 %}
10816 instruct tanXD_reg(regXD dst, eFlagsReg cr) %{
10817 predicate (UseSSE>=2);
10818 match(Set dst(TanD dst));
10819 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10820 format %{ "DTAN $dst" %}
10821 ins_encode( Push_SrcXD(dst),
10822 Opcode(0xD9), Opcode(0xF2), // fptan
10823 Opcode(0xDD), Opcode(0xD8), // fstp st
10824 Push_ResultXD(dst) );
10825 ins_pipe( pipe_slow );
10826 %}
10828 instruct atanD_reg(regD dst, regD src) %{
10829 predicate (UseSSE<=1);
10830 match(Set dst(AtanD dst src));
10831 format %{ "DATA $dst,$src" %}
10832 opcode(0xD9, 0xF3);
10833 ins_encode( Push_Reg_D(src),
10834 OpcP, OpcS, RegOpc(dst) );
10835 ins_pipe( pipe_slow );
10836 %}
10838 instruct atanXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10839 predicate (UseSSE>=2);
10840 match(Set dst(AtanD dst src));
10841 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10842 format %{ "DATA $dst,$src" %}
10843 opcode(0xD9, 0xF3);
10844 ins_encode( Push_SrcXD(src),
10845 OpcP, OpcS, Push_ResultXD(dst) );
10846 ins_pipe( pipe_slow );
10847 %}
10849 instruct sqrtD_reg(regD dst, regD src) %{
10850 predicate (UseSSE<=1);
10851 match(Set dst (SqrtD src));
10852 format %{ "DSQRT $dst,$src" %}
10853 opcode(0xFA, 0xD9);
10854 ins_encode( Push_Reg_D(src),
10855 OpcS, OpcP, Pop_Reg_D(dst) );
10856 ins_pipe( pipe_slow );
10857 %}
10859 instruct powD_reg(regD X, regDPR1 Y, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10860 predicate (UseSSE<=1);
10861 match(Set Y (PowD X Y)); // Raise X to the Yth power
10862 effect(KILL rax, KILL rbx, KILL rcx);
10863 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10864 "FLD_D $X\n\t"
10865 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10867 "FDUP \t\t\t# Q Q\n\t"
10868 "FRNDINT\t\t\t# int(Q) Q\n\t"
10869 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10870 "FISTP dword [ESP]\n\t"
10871 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10872 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10873 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10874 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10875 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10876 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10877 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10878 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10879 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10880 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10881 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10882 "MOV [ESP+0],0\n\t"
10883 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10885 "ADD ESP,8"
10886 %}
10887 ins_encode( push_stack_temp_qword,
10888 Push_Reg_D(X),
10889 Opcode(0xD9), Opcode(0xF1), // fyl2x
10890 pow_exp_core_encoding,
10891 pop_stack_temp_qword);
10892 ins_pipe( pipe_slow );
10893 %}
10895 instruct powXD_reg(regXD dst, regXD src0, regXD src1, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx ) %{
10896 predicate (UseSSE>=2);
10897 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
10898 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx );
10899 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10900 "MOVSD [ESP],$src1\n\t"
10901 "FLD FPR1,$src1\n\t"
10902 "MOVSD [ESP],$src0\n\t"
10903 "FLD FPR1,$src0\n\t"
10904 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10906 "FDUP \t\t\t# Q Q\n\t"
10907 "FRNDINT\t\t\t# int(Q) Q\n\t"
10908 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10909 "FISTP dword [ESP]\n\t"
10910 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10911 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10912 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10913 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10914 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10915 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10916 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10917 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10918 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10919 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10920 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10921 "MOV [ESP+0],0\n\t"
10922 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10924 "FST_D [ESP]\n\t"
10925 "MOVSD $dst,[ESP]\n\t"
10926 "ADD ESP,8"
10927 %}
10928 ins_encode( push_stack_temp_qword,
10929 push_xmm_to_fpr1(src1),
10930 push_xmm_to_fpr1(src0),
10931 Opcode(0xD9), Opcode(0xF1), // fyl2x
10932 pow_exp_core_encoding,
10933 Push_ResultXD(dst) );
10934 ins_pipe( pipe_slow );
10935 %}
10938 instruct expD_reg(regDPR1 dpr1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10939 predicate (UseSSE<=1);
10940 match(Set dpr1 (ExpD dpr1));
10941 effect(KILL rax, KILL rbx, KILL rcx);
10942 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding"
10943 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10944 "FMULP \t\t\t# Q=X*log2(e)\n\t"
10946 "FDUP \t\t\t# Q Q\n\t"
10947 "FRNDINT\t\t\t# int(Q) Q\n\t"
10948 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10949 "FISTP dword [ESP]\n\t"
10950 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10951 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10952 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10953 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10954 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10955 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10956 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10957 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10958 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10959 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10960 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10961 "MOV [ESP+0],0\n\t"
10962 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10964 "ADD ESP,8"
10965 %}
10966 ins_encode( push_stack_temp_qword,
10967 Opcode(0xD9), Opcode(0xEA), // fldl2e
10968 Opcode(0xDE), Opcode(0xC9), // fmulp
10969 pow_exp_core_encoding,
10970 pop_stack_temp_qword);
10971 ins_pipe( pipe_slow );
10972 %}
10974 instruct expXD_reg(regXD dst, regXD src, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10975 predicate (UseSSE>=2);
10976 match(Set dst (ExpD src));
10977 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx);
10978 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding\n\t"
10979 "MOVSD [ESP],$src\n\t"
10980 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10981 "FMULP \t\t\t# Q=X*log2(e) X\n\t"
10983 "FDUP \t\t\t# Q Q\n\t"
10984 "FRNDINT\t\t\t# int(Q) Q\n\t"
10985 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10986 "FISTP dword [ESP]\n\t"
10987 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10988 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10989 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10990 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10991 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10992 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10993 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10994 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10995 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10996 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10997 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10998 "MOV [ESP+0],0\n\t"
10999 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
11001 "FST_D [ESP]\n\t"
11002 "MOVSD $dst,[ESP]\n\t"
11003 "ADD ESP,8"
11004 %}
11005 ins_encode( Push_SrcXD(src),
11006 Opcode(0xD9), Opcode(0xEA), // fldl2e
11007 Opcode(0xDE), Opcode(0xC9), // fmulp
11008 pow_exp_core_encoding,
11009 Push_ResultXD(dst) );
11010 ins_pipe( pipe_slow );
11011 %}
11015 instruct log10D_reg(regDPR1 dst, regDPR1 src) %{
11016 predicate (UseSSE<=1);
11017 // The source Double operand on FPU stack
11018 match(Set dst (Log10D src));
11019 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
11020 // fxch ; swap ST(0) with ST(1)
11021 // fyl2x ; compute log_10(2) * log_2(x)
11022 format %{ "FLDLG2 \t\t\t#Log10\n\t"
11023 "FXCH \n\t"
11024 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
11025 %}
11026 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
11027 Opcode(0xD9), Opcode(0xC9), // fxch
11028 Opcode(0xD9), Opcode(0xF1)); // fyl2x
11030 ins_pipe( pipe_slow );
11031 %}
11033 instruct log10XD_reg(regXD dst, regXD src, eFlagsReg cr) %{
11034 predicate (UseSSE>=2);
11035 effect(KILL cr);
11036 match(Set dst (Log10D src));
11037 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
11038 // fyl2x ; compute log_10(2) * log_2(x)
11039 format %{ "FLDLG2 \t\t\t#Log10\n\t"
11040 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
11041 %}
11042 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
11043 Push_SrcXD(src),
11044 Opcode(0xD9), Opcode(0xF1), // fyl2x
11045 Push_ResultXD(dst));
11047 ins_pipe( pipe_slow );
11048 %}
11050 instruct logD_reg(regDPR1 dst, regDPR1 src) %{
11051 predicate (UseSSE<=1);
11052 // The source Double operand on FPU stack
11053 match(Set dst (LogD src));
11054 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
11055 // fxch ; swap ST(0) with ST(1)
11056 // fyl2x ; compute log_e(2) * log_2(x)
11057 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
11058 "FXCH \n\t"
11059 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
11060 %}
11061 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
11062 Opcode(0xD9), Opcode(0xC9), // fxch
11063 Opcode(0xD9), Opcode(0xF1)); // fyl2x
11065 ins_pipe( pipe_slow );
11066 %}
11068 instruct logXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
11069 predicate (UseSSE>=2);
11070 effect(KILL cr);
11071 // The source and result Double operands in XMM registers
11072 match(Set dst (LogD src));
11073 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
11074 // fyl2x ; compute log_e(2) * log_2(x)
11075 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
11076 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
11077 %}
11078 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
11079 Push_SrcXD(src),
11080 Opcode(0xD9), Opcode(0xF1), // fyl2x
11081 Push_ResultXD(dst));
11082 ins_pipe( pipe_slow );
11083 %}
11085 //-------------Float Instructions-------------------------------
11086 // Float Math
11088 // Code for float compare:
11089 // fcompp();
11090 // fwait(); fnstsw_ax();
11091 // sahf();
11092 // movl(dst, unordered_result);
11093 // jcc(Assembler::parity, exit);
11094 // movl(dst, less_result);
11095 // jcc(Assembler::below, exit);
11096 // movl(dst, equal_result);
11097 // jcc(Assembler::equal, exit);
11098 // movl(dst, greater_result);
11099 // exit:
11101 // P6 version of float compare, sets condition codes in EFLAGS
11102 instruct cmpF_cc_P6(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
11103 predicate(VM_Version::supports_cmov() && UseSSE == 0);
11104 match(Set cr (CmpF src1 src2));
11105 effect(KILL rax);
11106 ins_cost(150);
11107 format %{ "FLD $src1\n\t"
11108 "FUCOMIP ST,$src2 // P6 instruction\n\t"
11109 "JNP exit\n\t"
11110 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
11111 "SAHF\n"
11112 "exit:\tNOP // avoid branch to branch" %}
11113 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
11114 ins_encode( Push_Reg_D(src1),
11115 OpcP, RegOpc(src2),
11116 cmpF_P6_fixup );
11117 ins_pipe( pipe_slow );
11118 %}
11120 instruct cmpF_cc_P6CF(eFlagsRegUCF cr, regF src1, regF src2) %{
11121 predicate(VM_Version::supports_cmov() && UseSSE == 0);
11122 match(Set cr (CmpF src1 src2));
11123 ins_cost(100);
11124 format %{ "FLD $src1\n\t"
11125 "FUCOMIP ST,$src2 // P6 instruction" %}
11126 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
11127 ins_encode( Push_Reg_D(src1),
11128 OpcP, RegOpc(src2));
11129 ins_pipe( pipe_slow );
11130 %}
11133 // Compare & branch
11134 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
11135 predicate(UseSSE == 0);
11136 match(Set cr (CmpF src1 src2));
11137 effect(KILL rax);
11138 ins_cost(200);
11139 format %{ "FLD $src1\n\t"
11140 "FCOMp $src2\n\t"
11141 "FNSTSW AX\n\t"
11142 "TEST AX,0x400\n\t"
11143 "JZ,s flags\n\t"
11144 "MOV AH,1\t# unordered treat as LT\n"
11145 "flags:\tSAHF" %}
11146 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
11147 ins_encode( Push_Reg_D(src1),
11148 OpcP, RegOpc(src2),
11149 fpu_flags);
11150 ins_pipe( pipe_slow );
11151 %}
11153 // Compare vs zero into -1,0,1
11154 instruct cmpF_0(eRegI dst, regF src1, immF0 zero, eAXRegI rax, eFlagsReg cr) %{
11155 predicate(UseSSE == 0);
11156 match(Set dst (CmpF3 src1 zero));
11157 effect(KILL cr, KILL rax);
11158 ins_cost(280);
11159 format %{ "FTSTF $dst,$src1" %}
11160 opcode(0xE4, 0xD9);
11161 ins_encode( Push_Reg_D(src1),
11162 OpcS, OpcP, PopFPU,
11163 CmpF_Result(dst));
11164 ins_pipe( pipe_slow );
11165 %}
11167 // Compare into -1,0,1
11168 instruct cmpF_reg(eRegI dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
11169 predicate(UseSSE == 0);
11170 match(Set dst (CmpF3 src1 src2));
11171 effect(KILL cr, KILL rax);
11172 ins_cost(300);
11173 format %{ "FCMPF $dst,$src1,$src2" %}
11174 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
11175 ins_encode( Push_Reg_D(src1),
11176 OpcP, RegOpc(src2),
11177 CmpF_Result(dst));
11178 ins_pipe( pipe_slow );
11179 %}
11181 // float compare and set condition codes in EFLAGS by XMM regs
11182 instruct cmpX_cc(eFlagsRegU cr, regX dst, regX src, eAXRegI rax) %{
11183 predicate(UseSSE>=1);
11184 match(Set cr (CmpF dst src));
11185 effect(KILL rax);
11186 ins_cost(145);
11187 format %{ "COMISS $dst,$src\n"
11188 "\tJNP exit\n"
11189 "\tMOV ah,1 // saw a NaN, set CF\n"
11190 "\tSAHF\n"
11191 "exit:\tNOP // avoid branch to branch" %}
11192 opcode(0x0F, 0x2F);
11193 ins_encode(OpcP, OpcS, RegReg(dst, src), cmpF_P6_fixup);
11194 ins_pipe( pipe_slow );
11195 %}
11197 instruct cmpX_ccCF(eFlagsRegUCF cr, regX dst, regX src) %{
11198 predicate(UseSSE>=1);
11199 match(Set cr (CmpF dst src));
11200 ins_cost(100);
11201 format %{ "COMISS $dst,$src" %}
11202 opcode(0x0F, 0x2F);
11203 ins_encode(OpcP, OpcS, RegReg(dst, src));
11204 ins_pipe( pipe_slow );
11205 %}
11207 // float compare and set condition codes in EFLAGS by XMM regs
11208 instruct cmpX_ccmem(eFlagsRegU cr, regX dst, memory src, eAXRegI rax) %{
11209 predicate(UseSSE>=1);
11210 match(Set cr (CmpF dst (LoadF src)));
11211 effect(KILL rax);
11212 ins_cost(165);
11213 format %{ "COMISS $dst,$src\n"
11214 "\tJNP exit\n"
11215 "\tMOV ah,1 // saw a NaN, set CF\n"
11216 "\tSAHF\n"
11217 "exit:\tNOP // avoid branch to branch" %}
11218 opcode(0x0F, 0x2F);
11219 ins_encode(OpcP, OpcS, RegMem(dst, src), cmpF_P6_fixup);
11220 ins_pipe( pipe_slow );
11221 %}
11223 instruct cmpX_ccmemCF(eFlagsRegUCF cr, regX dst, memory src) %{
11224 predicate(UseSSE>=1);
11225 match(Set cr (CmpF dst (LoadF src)));
11226 ins_cost(100);
11227 format %{ "COMISS $dst,$src" %}
11228 opcode(0x0F, 0x2F);
11229 ins_encode(OpcP, OpcS, RegMem(dst, src));
11230 ins_pipe( pipe_slow );
11231 %}
11233 // Compare into -1,0,1 in XMM
11234 instruct cmpX_reg(eRegI dst, regX src1, regX src2, eFlagsReg cr) %{
11235 predicate(UseSSE>=1);
11236 match(Set dst (CmpF3 src1 src2));
11237 effect(KILL cr);
11238 ins_cost(255);
11239 format %{ "XOR $dst,$dst\n"
11240 "\tCOMISS $src1,$src2\n"
11241 "\tJP,s nan\n"
11242 "\tJEQ,s exit\n"
11243 "\tJA,s inc\n"
11244 "nan:\tDEC $dst\n"
11245 "\tJMP,s exit\n"
11246 "inc:\tINC $dst\n"
11247 "exit:"
11248 %}
11249 opcode(0x0F, 0x2F);
11250 ins_encode(Xor_Reg(dst), OpcP, OpcS, RegReg(src1, src2), CmpX_Result(dst));
11251 ins_pipe( pipe_slow );
11252 %}
11254 // Compare into -1,0,1 in XMM and memory
11255 instruct cmpX_regmem(eRegI dst, regX src1, memory mem, eFlagsReg cr) %{
11256 predicate(UseSSE>=1);
11257 match(Set dst (CmpF3 src1 (LoadF mem)));
11258 effect(KILL cr);
11259 ins_cost(275);
11260 format %{ "COMISS $src1,$mem\n"
11261 "\tMOV $dst,0\t\t# do not blow flags\n"
11262 "\tJP,s nan\n"
11263 "\tJEQ,s exit\n"
11264 "\tJA,s inc\n"
11265 "nan:\tDEC $dst\n"
11266 "\tJMP,s exit\n"
11267 "inc:\tINC $dst\n"
11268 "exit:"
11269 %}
11270 opcode(0x0F, 0x2F);
11271 ins_encode(OpcP, OpcS, RegMem(src1, mem), LdImmI(dst,0x0), CmpX_Result(dst));
11272 ins_pipe( pipe_slow );
11273 %}
11275 // Spill to obtain 24-bit precision
11276 instruct subF24_reg(stackSlotF dst, regF src1, regF src2) %{
11277 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11278 match(Set dst (SubF src1 src2));
11280 format %{ "FSUB $dst,$src1 - $src2" %}
11281 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
11282 ins_encode( Push_Reg_F(src1),
11283 OpcReg_F(src2),
11284 Pop_Mem_F(dst) );
11285 ins_pipe( fpu_mem_reg_reg );
11286 %}
11287 //
11288 // This instruction does not round to 24-bits
11289 instruct subF_reg(regF dst, regF src) %{
11290 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11291 match(Set dst (SubF dst src));
11293 format %{ "FSUB $dst,$src" %}
11294 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
11295 ins_encode( Push_Reg_F(src),
11296 OpcP, RegOpc(dst) );
11297 ins_pipe( fpu_reg_reg );
11298 %}
11300 // Spill to obtain 24-bit precision
11301 instruct addF24_reg(stackSlotF dst, regF src1, regF src2) %{
11302 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11303 match(Set dst (AddF src1 src2));
11305 format %{ "FADD $dst,$src1,$src2" %}
11306 opcode(0xD8, 0x0); /* D8 C0+i */
11307 ins_encode( Push_Reg_F(src2),
11308 OpcReg_F(src1),
11309 Pop_Mem_F(dst) );
11310 ins_pipe( fpu_mem_reg_reg );
11311 %}
11312 //
11313 // This instruction does not round to 24-bits
11314 instruct addF_reg(regF dst, regF src) %{
11315 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11316 match(Set dst (AddF dst src));
11318 format %{ "FLD $src\n\t"
11319 "FADDp $dst,ST" %}
11320 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
11321 ins_encode( Push_Reg_F(src),
11322 OpcP, RegOpc(dst) );
11323 ins_pipe( fpu_reg_reg );
11324 %}
11326 // Add two single precision floating point values in xmm
11327 instruct addX_reg(regX dst, regX src) %{
11328 predicate(UseSSE>=1);
11329 match(Set dst (AddF dst src));
11330 format %{ "ADDSS $dst,$src" %}
11331 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
11332 ins_pipe( pipe_slow );
11333 %}
11335 instruct addX_imm(regX dst, immXF con) %{
11336 predicate(UseSSE>=1);
11337 match(Set dst (AddF dst con));
11338 format %{ "ADDSS $dst,[$con]" %}
11339 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), LdImmX(dst, con) );
11340 ins_pipe( pipe_slow );
11341 %}
11343 instruct addX_mem(regX dst, memory mem) %{
11344 predicate(UseSSE>=1);
11345 match(Set dst (AddF dst (LoadF mem)));
11346 format %{ "ADDSS $dst,$mem" %}
11347 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegMem(dst, mem));
11348 ins_pipe( pipe_slow );
11349 %}
11351 // Subtract two single precision floating point values in xmm
11352 instruct subX_reg(regX dst, regX src) %{
11353 predicate(UseSSE>=1);
11354 match(Set dst (SubF dst src));
11355 format %{ "SUBSS $dst,$src" %}
11356 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
11357 ins_pipe( pipe_slow );
11358 %}
11360 instruct subX_imm(regX dst, immXF con) %{
11361 predicate(UseSSE>=1);
11362 match(Set dst (SubF dst con));
11363 format %{ "SUBSS $dst,[$con]" %}
11364 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), LdImmX(dst, con) );
11365 ins_pipe( pipe_slow );
11366 %}
11368 instruct subX_mem(regX dst, memory mem) %{
11369 predicate(UseSSE>=1);
11370 match(Set dst (SubF dst (LoadF mem)));
11371 format %{ "SUBSS $dst,$mem" %}
11372 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
11373 ins_pipe( pipe_slow );
11374 %}
11376 // Multiply two single precision floating point values in xmm
11377 instruct mulX_reg(regX dst, regX src) %{
11378 predicate(UseSSE>=1);
11379 match(Set dst (MulF dst src));
11380 format %{ "MULSS $dst,$src" %}
11381 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
11382 ins_pipe( pipe_slow );
11383 %}
11385 instruct mulX_imm(regX dst, immXF con) %{
11386 predicate(UseSSE>=1);
11387 match(Set dst (MulF dst con));
11388 format %{ "MULSS $dst,[$con]" %}
11389 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), LdImmX(dst, con) );
11390 ins_pipe( pipe_slow );
11391 %}
11393 instruct mulX_mem(regX dst, memory mem) %{
11394 predicate(UseSSE>=1);
11395 match(Set dst (MulF dst (LoadF mem)));
11396 format %{ "MULSS $dst,$mem" %}
11397 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
11398 ins_pipe( pipe_slow );
11399 %}
11401 // Divide two single precision floating point values in xmm
11402 instruct divX_reg(regX dst, regX src) %{
11403 predicate(UseSSE>=1);
11404 match(Set dst (DivF dst src));
11405 format %{ "DIVSS $dst,$src" %}
11406 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
11407 ins_pipe( pipe_slow );
11408 %}
11410 instruct divX_imm(regX dst, immXF con) %{
11411 predicate(UseSSE>=1);
11412 match(Set dst (DivF dst con));
11413 format %{ "DIVSS $dst,[$con]" %}
11414 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), LdImmX(dst, con) );
11415 ins_pipe( pipe_slow );
11416 %}
11418 instruct divX_mem(regX dst, memory mem) %{
11419 predicate(UseSSE>=1);
11420 match(Set dst (DivF dst (LoadF mem)));
11421 format %{ "DIVSS $dst,$mem" %}
11422 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
11423 ins_pipe( pipe_slow );
11424 %}
11426 // Get the square root of a single precision floating point values in xmm
11427 instruct sqrtX_reg(regX dst, regX src) %{
11428 predicate(UseSSE>=1);
11429 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
11430 format %{ "SQRTSS $dst,$src" %}
11431 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
11432 ins_pipe( pipe_slow );
11433 %}
11435 instruct sqrtX_mem(regX dst, memory mem) %{
11436 predicate(UseSSE>=1);
11437 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF mem)))));
11438 format %{ "SQRTSS $dst,$mem" %}
11439 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
11440 ins_pipe( pipe_slow );
11441 %}
11443 // Get the square root of a double precision floating point values in xmm
11444 instruct sqrtXD_reg(regXD dst, regXD src) %{
11445 predicate(UseSSE>=2);
11446 match(Set dst (SqrtD src));
11447 format %{ "SQRTSD $dst,$src" %}
11448 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
11449 ins_pipe( pipe_slow );
11450 %}
11452 instruct sqrtXD_mem(regXD dst, memory mem) %{
11453 predicate(UseSSE>=2);
11454 match(Set dst (SqrtD (LoadD mem)));
11455 format %{ "SQRTSD $dst,$mem" %}
11456 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
11457 ins_pipe( pipe_slow );
11458 %}
11460 instruct absF_reg(regFPR1 dst, regFPR1 src) %{
11461 predicate(UseSSE==0);
11462 match(Set dst (AbsF src));
11463 ins_cost(100);
11464 format %{ "FABS" %}
11465 opcode(0xE1, 0xD9);
11466 ins_encode( OpcS, OpcP );
11467 ins_pipe( fpu_reg_reg );
11468 %}
11470 instruct absX_reg(regX dst ) %{
11471 predicate(UseSSE>=1);
11472 match(Set dst (AbsF dst));
11473 format %{ "ANDPS $dst,[0x7FFFFFFF]\t# ABS F by sign masking" %}
11474 ins_encode( AbsXF_encoding(dst));
11475 ins_pipe( pipe_slow );
11476 %}
11478 instruct negF_reg(regFPR1 dst, regFPR1 src) %{
11479 predicate(UseSSE==0);
11480 match(Set dst (NegF src));
11481 ins_cost(100);
11482 format %{ "FCHS" %}
11483 opcode(0xE0, 0xD9);
11484 ins_encode( OpcS, OpcP );
11485 ins_pipe( fpu_reg_reg );
11486 %}
11488 instruct negX_reg( regX dst ) %{
11489 predicate(UseSSE>=1);
11490 match(Set dst (NegF dst));
11491 format %{ "XORPS $dst,[0x80000000]\t# CHS F by sign flipping" %}
11492 ins_encode( NegXF_encoding(dst));
11493 ins_pipe( pipe_slow );
11494 %}
11496 // Cisc-alternate to addF_reg
11497 // Spill to obtain 24-bit precision
11498 instruct addF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
11499 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11500 match(Set dst (AddF src1 (LoadF src2)));
11502 format %{ "FLD $src2\n\t"
11503 "FADD ST,$src1\n\t"
11504 "FSTP_S $dst" %}
11505 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11506 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11507 OpcReg_F(src1),
11508 Pop_Mem_F(dst) );
11509 ins_pipe( fpu_mem_reg_mem );
11510 %}
11511 //
11512 // Cisc-alternate to addF_reg
11513 // This instruction does not round to 24-bits
11514 instruct addF_reg_mem(regF dst, memory src) %{
11515 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11516 match(Set dst (AddF dst (LoadF src)));
11518 format %{ "FADD $dst,$src" %}
11519 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
11520 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
11521 OpcP, RegOpc(dst) );
11522 ins_pipe( fpu_reg_mem );
11523 %}
11525 // // Following two instructions for _222_mpegaudio
11526 // Spill to obtain 24-bit precision
11527 instruct addF24_mem_reg(stackSlotF dst, regF src2, memory src1 ) %{
11528 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11529 match(Set dst (AddF src1 src2));
11531 format %{ "FADD $dst,$src1,$src2" %}
11532 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11533 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
11534 OpcReg_F(src2),
11535 Pop_Mem_F(dst) );
11536 ins_pipe( fpu_mem_reg_mem );
11537 %}
11539 // Cisc-spill variant
11540 // Spill to obtain 24-bit precision
11541 instruct addF24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
11542 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11543 match(Set dst (AddF src1 (LoadF src2)));
11545 format %{ "FADD $dst,$src1,$src2 cisc" %}
11546 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11547 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11548 set_instruction_start,
11549 OpcP, RMopc_Mem(secondary,src1),
11550 Pop_Mem_F(dst) );
11551 ins_pipe( fpu_mem_mem_mem );
11552 %}
11554 // Spill to obtain 24-bit precision
11555 instruct addF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
11556 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11557 match(Set dst (AddF src1 src2));
11559 format %{ "FADD $dst,$src1,$src2" %}
11560 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
11561 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11562 set_instruction_start,
11563 OpcP, RMopc_Mem(secondary,src1),
11564 Pop_Mem_F(dst) );
11565 ins_pipe( fpu_mem_mem_mem );
11566 %}
11569 // Spill to obtain 24-bit precision
11570 instruct addF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
11571 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11572 match(Set dst (AddF src1 src2));
11573 format %{ "FLD $src1\n\t"
11574 "FADD $src2\n\t"
11575 "FSTP_S $dst" %}
11576 opcode(0xD8, 0x00); /* D8 /0 */
11577 ins_encode( Push_Reg_F(src1),
11578 Opc_MemImm_F(src2),
11579 Pop_Mem_F(dst));
11580 ins_pipe( fpu_mem_reg_con );
11581 %}
11582 //
11583 // This instruction does not round to 24-bits
11584 instruct addF_reg_imm(regF dst, regF src1, immF src2) %{
11585 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11586 match(Set dst (AddF src1 src2));
11587 format %{ "FLD $src1\n\t"
11588 "FADD $src2\n\t"
11589 "FSTP_S $dst" %}
11590 opcode(0xD8, 0x00); /* D8 /0 */
11591 ins_encode( Push_Reg_F(src1),
11592 Opc_MemImm_F(src2),
11593 Pop_Reg_F(dst));
11594 ins_pipe( fpu_reg_reg_con );
11595 %}
11597 // Spill to obtain 24-bit precision
11598 instruct mulF24_reg(stackSlotF dst, regF src1, regF src2) %{
11599 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11600 match(Set dst (MulF src1 src2));
11602 format %{ "FLD $src1\n\t"
11603 "FMUL $src2\n\t"
11604 "FSTP_S $dst" %}
11605 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
11606 ins_encode( Push_Reg_F(src1),
11607 OpcReg_F(src2),
11608 Pop_Mem_F(dst) );
11609 ins_pipe( fpu_mem_reg_reg );
11610 %}
11611 //
11612 // This instruction does not round to 24-bits
11613 instruct mulF_reg(regF dst, regF src1, regF src2) %{
11614 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11615 match(Set dst (MulF src1 src2));
11617 format %{ "FLD $src1\n\t"
11618 "FMUL $src2\n\t"
11619 "FSTP_S $dst" %}
11620 opcode(0xD8, 0x1); /* D8 C8+i */
11621 ins_encode( Push_Reg_F(src2),
11622 OpcReg_F(src1),
11623 Pop_Reg_F(dst) );
11624 ins_pipe( fpu_reg_reg_reg );
11625 %}
11628 // Spill to obtain 24-bit precision
11629 // Cisc-alternate to reg-reg multiply
11630 instruct mulF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
11631 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11632 match(Set dst (MulF src1 (LoadF src2)));
11634 format %{ "FLD_S $src2\n\t"
11635 "FMUL $src1\n\t"
11636 "FSTP_S $dst" %}
11637 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
11638 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11639 OpcReg_F(src1),
11640 Pop_Mem_F(dst) );
11641 ins_pipe( fpu_mem_reg_mem );
11642 %}
11643 //
11644 // This instruction does not round to 24-bits
11645 // Cisc-alternate to reg-reg multiply
11646 instruct mulF_reg_mem(regF dst, regF src1, memory src2) %{
11647 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11648 match(Set dst (MulF src1 (LoadF src2)));
11650 format %{ "FMUL $dst,$src1,$src2" %}
11651 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
11652 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11653 OpcReg_F(src1),
11654 Pop_Reg_F(dst) );
11655 ins_pipe( fpu_reg_reg_mem );
11656 %}
11658 // Spill to obtain 24-bit precision
11659 instruct mulF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
11660 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11661 match(Set dst (MulF src1 src2));
11663 format %{ "FMUL $dst,$src1,$src2" %}
11664 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
11665 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11666 set_instruction_start,
11667 OpcP, RMopc_Mem(secondary,src1),
11668 Pop_Mem_F(dst) );
11669 ins_pipe( fpu_mem_mem_mem );
11670 %}
11672 // Spill to obtain 24-bit precision
11673 instruct mulF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
11674 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11675 match(Set dst (MulF src1 src2));
11677 format %{ "FMULc $dst,$src1,$src2" %}
11678 opcode(0xD8, 0x1); /* D8 /1*/
11679 ins_encode( Push_Reg_F(src1),
11680 Opc_MemImm_F(src2),
11681 Pop_Mem_F(dst));
11682 ins_pipe( fpu_mem_reg_con );
11683 %}
11684 //
11685 // This instruction does not round to 24-bits
11686 instruct mulF_reg_imm(regF dst, regF src1, immF src2) %{
11687 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11688 match(Set dst (MulF src1 src2));
11690 format %{ "FMULc $dst. $src1, $src2" %}
11691 opcode(0xD8, 0x1); /* D8 /1*/
11692 ins_encode( Push_Reg_F(src1),
11693 Opc_MemImm_F(src2),
11694 Pop_Reg_F(dst));
11695 ins_pipe( fpu_reg_reg_con );
11696 %}
11699 //
11700 // MACRO1 -- subsume unshared load into mulF
11701 // This instruction does not round to 24-bits
11702 instruct mulF_reg_load1(regF dst, regF src, memory mem1 ) %{
11703 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11704 match(Set dst (MulF (LoadF mem1) src));
11706 format %{ "FLD $mem1 ===MACRO1===\n\t"
11707 "FMUL ST,$src\n\t"
11708 "FSTP $dst" %}
11709 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
11710 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
11711 OpcReg_F(src),
11712 Pop_Reg_F(dst) );
11713 ins_pipe( fpu_reg_reg_mem );
11714 %}
11715 //
11716 // MACRO2 -- addF a mulF which subsumed an unshared load
11717 // This instruction does not round to 24-bits
11718 instruct addF_mulF_reg_load1(regF dst, memory mem1, regF src1, regF src2) %{
11719 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11720 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
11721 ins_cost(95);
11723 format %{ "FLD $mem1 ===MACRO2===\n\t"
11724 "FMUL ST,$src1 subsume mulF left load\n\t"
11725 "FADD ST,$src2\n\t"
11726 "FSTP $dst" %}
11727 opcode(0xD9); /* LoadF D9 /0 */
11728 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
11729 FMul_ST_reg(src1),
11730 FAdd_ST_reg(src2),
11731 Pop_Reg_F(dst) );
11732 ins_pipe( fpu_reg_mem_reg_reg );
11733 %}
11735 // MACRO3 -- addF a mulF
11736 // This instruction does not round to 24-bits. It is a '2-address'
11737 // instruction in that the result goes back to src2. This eliminates
11738 // a move from the macro; possibly the register allocator will have
11739 // to add it back (and maybe not).
11740 instruct addF_mulF_reg(regF src2, regF src1, regF src0) %{
11741 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11742 match(Set src2 (AddF (MulF src0 src1) src2));
11744 format %{ "FLD $src0 ===MACRO3===\n\t"
11745 "FMUL ST,$src1\n\t"
11746 "FADDP $src2,ST" %}
11747 opcode(0xD9); /* LoadF D9 /0 */
11748 ins_encode( Push_Reg_F(src0),
11749 FMul_ST_reg(src1),
11750 FAddP_reg_ST(src2) );
11751 ins_pipe( fpu_reg_reg_reg );
11752 %}
11754 // MACRO4 -- divF subF
11755 // This instruction does not round to 24-bits
11756 instruct subF_divF_reg(regF dst, regF src1, regF src2, regF src3) %{
11757 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11758 match(Set dst (DivF (SubF src2 src1) src3));
11760 format %{ "FLD $src2 ===MACRO4===\n\t"
11761 "FSUB ST,$src1\n\t"
11762 "FDIV ST,$src3\n\t"
11763 "FSTP $dst" %}
11764 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11765 ins_encode( Push_Reg_F(src2),
11766 subF_divF_encode(src1,src3),
11767 Pop_Reg_F(dst) );
11768 ins_pipe( fpu_reg_reg_reg_reg );
11769 %}
11771 // Spill to obtain 24-bit precision
11772 instruct divF24_reg(stackSlotF dst, regF src1, regF src2) %{
11773 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11774 match(Set dst (DivF src1 src2));
11776 format %{ "FDIV $dst,$src1,$src2" %}
11777 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
11778 ins_encode( Push_Reg_F(src1),
11779 OpcReg_F(src2),
11780 Pop_Mem_F(dst) );
11781 ins_pipe( fpu_mem_reg_reg );
11782 %}
11783 //
11784 // This instruction does not round to 24-bits
11785 instruct divF_reg(regF dst, regF src) %{
11786 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11787 match(Set dst (DivF dst src));
11789 format %{ "FDIV $dst,$src" %}
11790 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11791 ins_encode( Push_Reg_F(src),
11792 OpcP, RegOpc(dst) );
11793 ins_pipe( fpu_reg_reg );
11794 %}
11797 // Spill to obtain 24-bit precision
11798 instruct modF24_reg(stackSlotF dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
11799 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11800 match(Set dst (ModF src1 src2));
11801 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
11803 format %{ "FMOD $dst,$src1,$src2" %}
11804 ins_encode( Push_Reg_Mod_D(src1, src2),
11805 emitModD(),
11806 Push_Result_Mod_D(src2),
11807 Pop_Mem_F(dst));
11808 ins_pipe( pipe_slow );
11809 %}
11810 //
11811 // This instruction does not round to 24-bits
11812 instruct modF_reg(regF dst, regF src, eAXRegI rax, eFlagsReg cr) %{
11813 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11814 match(Set dst (ModF dst src));
11815 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
11817 format %{ "FMOD $dst,$src" %}
11818 ins_encode(Push_Reg_Mod_D(dst, src),
11819 emitModD(),
11820 Push_Result_Mod_D(src),
11821 Pop_Reg_F(dst));
11822 ins_pipe( pipe_slow );
11823 %}
11825 instruct modX_reg(regX dst, regX src0, regX src1, eAXRegI rax, eFlagsReg cr) %{
11826 predicate(UseSSE>=1);
11827 match(Set dst (ModF src0 src1));
11828 effect(KILL rax, KILL cr);
11829 format %{ "SUB ESP,4\t # FMOD\n"
11830 "\tMOVSS [ESP+0],$src1\n"
11831 "\tFLD_S [ESP+0]\n"
11832 "\tMOVSS [ESP+0],$src0\n"
11833 "\tFLD_S [ESP+0]\n"
11834 "loop:\tFPREM\n"
11835 "\tFWAIT\n"
11836 "\tFNSTSW AX\n"
11837 "\tSAHF\n"
11838 "\tJP loop\n"
11839 "\tFSTP_S [ESP+0]\n"
11840 "\tMOVSS $dst,[ESP+0]\n"
11841 "\tADD ESP,4\n"
11842 "\tFSTP ST0\t # Restore FPU Stack"
11843 %}
11844 ins_cost(250);
11845 ins_encode( Push_ModX_encoding(src0, src1), emitModD(), Push_ResultX(dst,0x4), PopFPU);
11846 ins_pipe( pipe_slow );
11847 %}
11850 //----------Arithmetic Conversion Instructions---------------------------------
11851 // The conversions operations are all Alpha sorted. Please keep it that way!
11853 instruct roundFloat_mem_reg(stackSlotF dst, regF src) %{
11854 predicate(UseSSE==0);
11855 match(Set dst (RoundFloat src));
11856 ins_cost(125);
11857 format %{ "FST_S $dst,$src\t# F-round" %}
11858 ins_encode( Pop_Mem_Reg_F(dst, src) );
11859 ins_pipe( fpu_mem_reg );
11860 %}
11862 instruct roundDouble_mem_reg(stackSlotD dst, regD src) %{
11863 predicate(UseSSE<=1);
11864 match(Set dst (RoundDouble src));
11865 ins_cost(125);
11866 format %{ "FST_D $dst,$src\t# D-round" %}
11867 ins_encode( Pop_Mem_Reg_D(dst, src) );
11868 ins_pipe( fpu_mem_reg );
11869 %}
11871 // Force rounding to 24-bit precision and 6-bit exponent
11872 instruct convD2F_reg(stackSlotF dst, regD src) %{
11873 predicate(UseSSE==0);
11874 match(Set dst (ConvD2F src));
11875 format %{ "FST_S $dst,$src\t# F-round" %}
11876 expand %{
11877 roundFloat_mem_reg(dst,src);
11878 %}
11879 %}
11881 // Force rounding to 24-bit precision and 6-bit exponent
11882 instruct convD2X_reg(regX dst, regD src, eFlagsReg cr) %{
11883 predicate(UseSSE==1);
11884 match(Set dst (ConvD2F src));
11885 effect( KILL cr );
11886 format %{ "SUB ESP,4\n\t"
11887 "FST_S [ESP],$src\t# F-round\n\t"
11888 "MOVSS $dst,[ESP]\n\t"
11889 "ADD ESP,4" %}
11890 ins_encode( D2X_encoding(dst, src) );
11891 ins_pipe( pipe_slow );
11892 %}
11894 // Force rounding double precision to single precision
11895 instruct convXD2X_reg(regX dst, regXD src) %{
11896 predicate(UseSSE>=2);
11897 match(Set dst (ConvD2F src));
11898 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
11899 opcode(0xF2, 0x0F, 0x5A);
11900 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11901 ins_pipe( pipe_slow );
11902 %}
11904 instruct convF2D_reg_reg(regD dst, regF src) %{
11905 predicate(UseSSE==0);
11906 match(Set dst (ConvF2D src));
11907 format %{ "FST_S $dst,$src\t# D-round" %}
11908 ins_encode( Pop_Reg_Reg_D(dst, src));
11909 ins_pipe( fpu_reg_reg );
11910 %}
11912 instruct convF2D_reg(stackSlotD dst, regF src) %{
11913 predicate(UseSSE==1);
11914 match(Set dst (ConvF2D src));
11915 format %{ "FST_D $dst,$src\t# D-round" %}
11916 expand %{
11917 roundDouble_mem_reg(dst,src);
11918 %}
11919 %}
11921 instruct convX2D_reg(regD dst, regX src, eFlagsReg cr) %{
11922 predicate(UseSSE==1);
11923 match(Set dst (ConvF2D src));
11924 effect( KILL cr );
11925 format %{ "SUB ESP,4\n\t"
11926 "MOVSS [ESP] $src\n\t"
11927 "FLD_S [ESP]\n\t"
11928 "ADD ESP,4\n\t"
11929 "FSTP $dst\t# D-round" %}
11930 ins_encode( X2D_encoding(dst, src), Pop_Reg_D(dst));
11931 ins_pipe( pipe_slow );
11932 %}
11934 instruct convX2XD_reg(regXD dst, regX src) %{
11935 predicate(UseSSE>=2);
11936 match(Set dst (ConvF2D src));
11937 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
11938 opcode(0xF3, 0x0F, 0x5A);
11939 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11940 ins_pipe( pipe_slow );
11941 %}
11943 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11944 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
11945 predicate(UseSSE<=1);
11946 match(Set dst (ConvD2I src));
11947 effect( KILL tmp, KILL cr );
11948 format %{ "FLD $src\t# Convert double to int \n\t"
11949 "FLDCW trunc mode\n\t"
11950 "SUB ESP,4\n\t"
11951 "FISTp [ESP + #0]\n\t"
11952 "FLDCW std/24-bit mode\n\t"
11953 "POP EAX\n\t"
11954 "CMP EAX,0x80000000\n\t"
11955 "JNE,s fast\n\t"
11956 "FLD_D $src\n\t"
11957 "CALL d2i_wrapper\n"
11958 "fast:" %}
11959 ins_encode( Push_Reg_D(src), D2I_encoding(src) );
11960 ins_pipe( pipe_slow );
11961 %}
11963 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11964 instruct convXD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regXD src, eFlagsReg cr ) %{
11965 predicate(UseSSE>=2);
11966 match(Set dst (ConvD2I src));
11967 effect( KILL tmp, KILL cr );
11968 format %{ "CVTTSD2SI $dst, $src\n\t"
11969 "CMP $dst,0x80000000\n\t"
11970 "JNE,s fast\n\t"
11971 "SUB ESP, 8\n\t"
11972 "MOVSD [ESP], $src\n\t"
11973 "FLD_D [ESP]\n\t"
11974 "ADD ESP, 8\n\t"
11975 "CALL d2i_wrapper\n"
11976 "fast:" %}
11977 opcode(0x1); // double-precision conversion
11978 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
11979 ins_pipe( pipe_slow );
11980 %}
11982 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
11983 predicate(UseSSE<=1);
11984 match(Set dst (ConvD2L src));
11985 effect( KILL cr );
11986 format %{ "FLD $src\t# Convert double to long\n\t"
11987 "FLDCW trunc mode\n\t"
11988 "SUB ESP,8\n\t"
11989 "FISTp [ESP + #0]\n\t"
11990 "FLDCW std/24-bit mode\n\t"
11991 "POP EAX\n\t"
11992 "POP EDX\n\t"
11993 "CMP EDX,0x80000000\n\t"
11994 "JNE,s fast\n\t"
11995 "TEST EAX,EAX\n\t"
11996 "JNE,s fast\n\t"
11997 "FLD $src\n\t"
11998 "CALL d2l_wrapper\n"
11999 "fast:" %}
12000 ins_encode( Push_Reg_D(src), D2L_encoding(src) );
12001 ins_pipe( pipe_slow );
12002 %}
12004 // XMM lacks a float/double->long conversion, so use the old FPU stack.
12005 instruct convXD2L_reg_reg( eADXRegL dst, regXD src, eFlagsReg cr ) %{
12006 predicate (UseSSE>=2);
12007 match(Set dst (ConvD2L src));
12008 effect( KILL cr );
12009 format %{ "SUB ESP,8\t# Convert double to long\n\t"
12010 "MOVSD [ESP],$src\n\t"
12011 "FLD_D [ESP]\n\t"
12012 "FLDCW trunc mode\n\t"
12013 "FISTp [ESP + #0]\n\t"
12014 "FLDCW std/24-bit mode\n\t"
12015 "POP EAX\n\t"
12016 "POP EDX\n\t"
12017 "CMP EDX,0x80000000\n\t"
12018 "JNE,s fast\n\t"
12019 "TEST EAX,EAX\n\t"
12020 "JNE,s fast\n\t"
12021 "SUB ESP,8\n\t"
12022 "MOVSD [ESP],$src\n\t"
12023 "FLD_D [ESP]\n\t"
12024 "CALL d2l_wrapper\n"
12025 "fast:" %}
12026 ins_encode( XD2L_encoding(src) );
12027 ins_pipe( pipe_slow );
12028 %}
12030 // Convert a double to an int. Java semantics require we do complex
12031 // manglations in the corner cases. So we set the rounding mode to
12032 // 'zero', store the darned double down as an int, and reset the
12033 // rounding mode to 'nearest'. The hardware stores a flag value down
12034 // if we would overflow or converted a NAN; we check for this and
12035 // and go the slow path if needed.
12036 instruct convF2I_reg_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
12037 predicate(UseSSE==0);
12038 match(Set dst (ConvF2I src));
12039 effect( KILL tmp, KILL cr );
12040 format %{ "FLD $src\t# Convert float to int \n\t"
12041 "FLDCW trunc mode\n\t"
12042 "SUB ESP,4\n\t"
12043 "FISTp [ESP + #0]\n\t"
12044 "FLDCW std/24-bit mode\n\t"
12045 "POP EAX\n\t"
12046 "CMP EAX,0x80000000\n\t"
12047 "JNE,s fast\n\t"
12048 "FLD $src\n\t"
12049 "CALL d2i_wrapper\n"
12050 "fast:" %}
12051 // D2I_encoding works for F2I
12052 ins_encode( Push_Reg_F(src), D2I_encoding(src) );
12053 ins_pipe( pipe_slow );
12054 %}
12056 // Convert a float in xmm to an int reg.
12057 instruct convX2I_reg(eAXRegI dst, eDXRegI tmp, regX src, eFlagsReg cr ) %{
12058 predicate(UseSSE>=1);
12059 match(Set dst (ConvF2I src));
12060 effect( KILL tmp, KILL cr );
12061 format %{ "CVTTSS2SI $dst, $src\n\t"
12062 "CMP $dst,0x80000000\n\t"
12063 "JNE,s fast\n\t"
12064 "SUB ESP, 4\n\t"
12065 "MOVSS [ESP], $src\n\t"
12066 "FLD [ESP]\n\t"
12067 "ADD ESP, 4\n\t"
12068 "CALL d2i_wrapper\n"
12069 "fast:" %}
12070 opcode(0x0); // single-precision conversion
12071 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
12072 ins_pipe( pipe_slow );
12073 %}
12075 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
12076 predicate(UseSSE==0);
12077 match(Set dst (ConvF2L src));
12078 effect( KILL cr );
12079 format %{ "FLD $src\t# Convert float to long\n\t"
12080 "FLDCW trunc mode\n\t"
12081 "SUB ESP,8\n\t"
12082 "FISTp [ESP + #0]\n\t"
12083 "FLDCW std/24-bit mode\n\t"
12084 "POP EAX\n\t"
12085 "POP EDX\n\t"
12086 "CMP EDX,0x80000000\n\t"
12087 "JNE,s fast\n\t"
12088 "TEST EAX,EAX\n\t"
12089 "JNE,s fast\n\t"
12090 "FLD $src\n\t"
12091 "CALL d2l_wrapper\n"
12092 "fast:" %}
12093 // D2L_encoding works for F2L
12094 ins_encode( Push_Reg_F(src), D2L_encoding(src) );
12095 ins_pipe( pipe_slow );
12096 %}
12098 // XMM lacks a float/double->long conversion, so use the old FPU stack.
12099 instruct convX2L_reg_reg( eADXRegL dst, regX src, eFlagsReg cr ) %{
12100 predicate (UseSSE>=1);
12101 match(Set dst (ConvF2L src));
12102 effect( KILL cr );
12103 format %{ "SUB ESP,8\t# Convert float to long\n\t"
12104 "MOVSS [ESP],$src\n\t"
12105 "FLD_S [ESP]\n\t"
12106 "FLDCW trunc mode\n\t"
12107 "FISTp [ESP + #0]\n\t"
12108 "FLDCW std/24-bit mode\n\t"
12109 "POP EAX\n\t"
12110 "POP EDX\n\t"
12111 "CMP EDX,0x80000000\n\t"
12112 "JNE,s fast\n\t"
12113 "TEST EAX,EAX\n\t"
12114 "JNE,s fast\n\t"
12115 "SUB ESP,4\t# Convert float to long\n\t"
12116 "MOVSS [ESP],$src\n\t"
12117 "FLD_S [ESP]\n\t"
12118 "ADD ESP,4\n\t"
12119 "CALL d2l_wrapper\n"
12120 "fast:" %}
12121 ins_encode( X2L_encoding(src) );
12122 ins_pipe( pipe_slow );
12123 %}
12125 instruct convI2D_reg(regD dst, stackSlotI src) %{
12126 predicate( UseSSE<=1 );
12127 match(Set dst (ConvI2D src));
12128 format %{ "FILD $src\n\t"
12129 "FSTP $dst" %}
12130 opcode(0xDB, 0x0); /* DB /0 */
12131 ins_encode(Push_Mem_I(src), Pop_Reg_D(dst));
12132 ins_pipe( fpu_reg_mem );
12133 %}
12135 instruct convI2XD_reg(regXD dst, eRegI src) %{
12136 predicate( UseSSE>=2 && !UseXmmI2D );
12137 match(Set dst (ConvI2D src));
12138 format %{ "CVTSI2SD $dst,$src" %}
12139 opcode(0xF2, 0x0F, 0x2A);
12140 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
12141 ins_pipe( pipe_slow );
12142 %}
12144 instruct convI2XD_mem(regXD dst, memory mem) %{
12145 predicate( UseSSE>=2 );
12146 match(Set dst (ConvI2D (LoadI mem)));
12147 format %{ "CVTSI2SD $dst,$mem" %}
12148 opcode(0xF2, 0x0F, 0x2A);
12149 ins_encode( OpcP, OpcS, Opcode(tertiary), RegMem(dst, mem));
12150 ins_pipe( pipe_slow );
12151 %}
12153 instruct convXI2XD_reg(regXD dst, eRegI src)
12154 %{
12155 predicate( UseSSE>=2 && UseXmmI2D );
12156 match(Set dst (ConvI2D src));
12158 format %{ "MOVD $dst,$src\n\t"
12159 "CVTDQ2PD $dst,$dst\t# i2d" %}
12160 ins_encode %{
12161 __ movdl($dst$$XMMRegister, $src$$Register);
12162 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
12163 %}
12164 ins_pipe(pipe_slow); // XXX
12165 %}
12167 instruct convI2D_mem(regD dst, memory mem) %{
12168 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
12169 match(Set dst (ConvI2D (LoadI mem)));
12170 format %{ "FILD $mem\n\t"
12171 "FSTP $dst" %}
12172 opcode(0xDB); /* DB /0 */
12173 ins_encode( OpcP, RMopc_Mem(0x00,mem),
12174 Pop_Reg_D(dst));
12175 ins_pipe( fpu_reg_mem );
12176 %}
12178 // Convert a byte to a float; no rounding step needed.
12179 instruct conv24I2F_reg(regF dst, stackSlotI src) %{
12180 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
12181 match(Set dst (ConvI2F src));
12182 format %{ "FILD $src\n\t"
12183 "FSTP $dst" %}
12185 opcode(0xDB, 0x0); /* DB /0 */
12186 ins_encode(Push_Mem_I(src), Pop_Reg_F(dst));
12187 ins_pipe( fpu_reg_mem );
12188 %}
12190 // In 24-bit mode, force exponent rounding by storing back out
12191 instruct convI2F_SSF(stackSlotF dst, stackSlotI src) %{
12192 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
12193 match(Set dst (ConvI2F src));
12194 ins_cost(200);
12195 format %{ "FILD $src\n\t"
12196 "FSTP_S $dst" %}
12197 opcode(0xDB, 0x0); /* DB /0 */
12198 ins_encode( Push_Mem_I(src),
12199 Pop_Mem_F(dst));
12200 ins_pipe( fpu_mem_mem );
12201 %}
12203 // In 24-bit mode, force exponent rounding by storing back out
12204 instruct convI2F_SSF_mem(stackSlotF dst, memory mem) %{
12205 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
12206 match(Set dst (ConvI2F (LoadI mem)));
12207 ins_cost(200);
12208 format %{ "FILD $mem\n\t"
12209 "FSTP_S $dst" %}
12210 opcode(0xDB); /* DB /0 */
12211 ins_encode( OpcP, RMopc_Mem(0x00,mem),
12212 Pop_Mem_F(dst));
12213 ins_pipe( fpu_mem_mem );
12214 %}
12216 // This instruction does not round to 24-bits
12217 instruct convI2F_reg(regF dst, stackSlotI src) %{
12218 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
12219 match(Set dst (ConvI2F src));
12220 format %{ "FILD $src\n\t"
12221 "FSTP $dst" %}
12222 opcode(0xDB, 0x0); /* DB /0 */
12223 ins_encode( Push_Mem_I(src),
12224 Pop_Reg_F(dst));
12225 ins_pipe( fpu_reg_mem );
12226 %}
12228 // This instruction does not round to 24-bits
12229 instruct convI2F_mem(regF dst, memory mem) %{
12230 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
12231 match(Set dst (ConvI2F (LoadI mem)));
12232 format %{ "FILD $mem\n\t"
12233 "FSTP $dst" %}
12234 opcode(0xDB); /* DB /0 */
12235 ins_encode( OpcP, RMopc_Mem(0x00,mem),
12236 Pop_Reg_F(dst));
12237 ins_pipe( fpu_reg_mem );
12238 %}
12240 // Convert an int to a float in xmm; no rounding step needed.
12241 instruct convI2X_reg(regX dst, eRegI src) %{
12242 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
12243 match(Set dst (ConvI2F src));
12244 format %{ "CVTSI2SS $dst, $src" %}
12246 opcode(0xF3, 0x0F, 0x2A); /* F3 0F 2A /r */
12247 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
12248 ins_pipe( pipe_slow );
12249 %}
12251 instruct convXI2X_reg(regX dst, eRegI src)
12252 %{
12253 predicate( UseSSE>=2 && UseXmmI2F );
12254 match(Set dst (ConvI2F src));
12256 format %{ "MOVD $dst,$src\n\t"
12257 "CVTDQ2PS $dst,$dst\t# i2f" %}
12258 ins_encode %{
12259 __ movdl($dst$$XMMRegister, $src$$Register);
12260 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
12261 %}
12262 ins_pipe(pipe_slow); // XXX
12263 %}
12265 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{
12266 match(Set dst (ConvI2L src));
12267 effect(KILL cr);
12268 ins_cost(375);
12269 format %{ "MOV $dst.lo,$src\n\t"
12270 "MOV $dst.hi,$src\n\t"
12271 "SAR $dst.hi,31" %}
12272 ins_encode(convert_int_long(dst,src));
12273 ins_pipe( ialu_reg_reg_long );
12274 %}
12276 // Zero-extend convert int to long
12277 instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{
12278 match(Set dst (AndL (ConvI2L src) mask) );
12279 effect( KILL flags );
12280 ins_cost(250);
12281 format %{ "MOV $dst.lo,$src\n\t"
12282 "XOR $dst.hi,$dst.hi" %}
12283 opcode(0x33); // XOR
12284 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
12285 ins_pipe( ialu_reg_reg_long );
12286 %}
12288 // Zero-extend long
12289 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
12290 match(Set dst (AndL src mask) );
12291 effect( KILL flags );
12292 ins_cost(250);
12293 format %{ "MOV $dst.lo,$src.lo\n\t"
12294 "XOR $dst.hi,$dst.hi\n\t" %}
12295 opcode(0x33); // XOR
12296 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
12297 ins_pipe( ialu_reg_reg_long );
12298 %}
12300 instruct convL2D_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
12301 predicate (UseSSE<=1);
12302 match(Set dst (ConvL2D src));
12303 effect( KILL cr );
12304 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
12305 "PUSH $src.lo\n\t"
12306 "FILD ST,[ESP + #0]\n\t"
12307 "ADD ESP,8\n\t"
12308 "FSTP_D $dst\t# D-round" %}
12309 opcode(0xDF, 0x5); /* DF /5 */
12310 ins_encode(convert_long_double(src), Pop_Mem_D(dst));
12311 ins_pipe( pipe_slow );
12312 %}
12314 instruct convL2XD_reg( regXD dst, eRegL src, eFlagsReg cr) %{
12315 predicate (UseSSE>=2);
12316 match(Set dst (ConvL2D src));
12317 effect( KILL cr );
12318 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
12319 "PUSH $src.lo\n\t"
12320 "FILD_D [ESP]\n\t"
12321 "FSTP_D [ESP]\n\t"
12322 "MOVSD $dst,[ESP]\n\t"
12323 "ADD ESP,8" %}
12324 opcode(0xDF, 0x5); /* DF /5 */
12325 ins_encode(convert_long_double2(src), Push_ResultXD(dst));
12326 ins_pipe( pipe_slow );
12327 %}
12329 instruct convL2X_reg( regX dst, eRegL src, eFlagsReg cr) %{
12330 predicate (UseSSE>=1);
12331 match(Set dst (ConvL2F src));
12332 effect( KILL cr );
12333 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
12334 "PUSH $src.lo\n\t"
12335 "FILD_D [ESP]\n\t"
12336 "FSTP_S [ESP]\n\t"
12337 "MOVSS $dst,[ESP]\n\t"
12338 "ADD ESP,8" %}
12339 opcode(0xDF, 0x5); /* DF /5 */
12340 ins_encode(convert_long_double2(src), Push_ResultX(dst,0x8));
12341 ins_pipe( pipe_slow );
12342 %}
12344 instruct convL2F_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
12345 match(Set dst (ConvL2F src));
12346 effect( KILL cr );
12347 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
12348 "PUSH $src.lo\n\t"
12349 "FILD ST,[ESP + #0]\n\t"
12350 "ADD ESP,8\n\t"
12351 "FSTP_S $dst\t# F-round" %}
12352 opcode(0xDF, 0x5); /* DF /5 */
12353 ins_encode(convert_long_double(src), Pop_Mem_F(dst));
12354 ins_pipe( pipe_slow );
12355 %}
12357 instruct convL2I_reg( eRegI dst, eRegL src ) %{
12358 match(Set dst (ConvL2I src));
12359 effect( DEF dst, USE src );
12360 format %{ "MOV $dst,$src.lo" %}
12361 ins_encode(enc_CopyL_Lo(dst,src));
12362 ins_pipe( ialu_reg_reg );
12363 %}
12366 instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{
12367 match(Set dst (MoveF2I src));
12368 effect( DEF dst, USE src );
12369 ins_cost(100);
12370 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
12371 opcode(0x8B);
12372 ins_encode( OpcP, RegMem(dst,src));
12373 ins_pipe( ialu_reg_mem );
12374 %}
12376 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
12377 predicate(UseSSE==0);
12378 match(Set dst (MoveF2I src));
12379 effect( DEF dst, USE src );
12381 ins_cost(125);
12382 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
12383 ins_encode( Pop_Mem_Reg_F(dst, src) );
12384 ins_pipe( fpu_mem_reg );
12385 %}
12387 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regX src) %{
12388 predicate(UseSSE>=1);
12389 match(Set dst (MoveF2I src));
12390 effect( DEF dst, USE src );
12392 ins_cost(95);
12393 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
12394 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, dst));
12395 ins_pipe( pipe_slow );
12396 %}
12398 instruct MoveF2I_reg_reg_sse(eRegI dst, regX src) %{
12399 predicate(UseSSE>=2);
12400 match(Set dst (MoveF2I src));
12401 effect( DEF dst, USE src );
12402 ins_cost(85);
12403 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
12404 ins_encode( MovX2I_reg(dst, src));
12405 ins_pipe( pipe_slow );
12406 %}
12408 instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{
12409 match(Set dst (MoveI2F src));
12410 effect( DEF dst, USE src );
12412 ins_cost(100);
12413 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
12414 opcode(0x89);
12415 ins_encode( OpcPRegSS( dst, src ) );
12416 ins_pipe( ialu_mem_reg );
12417 %}
12420 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
12421 predicate(UseSSE==0);
12422 match(Set dst (MoveI2F src));
12423 effect(DEF dst, USE src);
12425 ins_cost(125);
12426 format %{ "FLD_S $src\n\t"
12427 "FSTP $dst\t# MoveI2F_stack_reg" %}
12428 opcode(0xD9); /* D9 /0, FLD m32real */
12429 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
12430 Pop_Reg_F(dst) );
12431 ins_pipe( fpu_reg_mem );
12432 %}
12434 instruct MoveI2F_stack_reg_sse(regX dst, stackSlotI src) %{
12435 predicate(UseSSE>=1);
12436 match(Set dst (MoveI2F src));
12437 effect( DEF dst, USE src );
12439 ins_cost(95);
12440 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
12441 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
12442 ins_pipe( pipe_slow );
12443 %}
12445 instruct MoveI2F_reg_reg_sse(regX dst, eRegI src) %{
12446 predicate(UseSSE>=2);
12447 match(Set dst (MoveI2F src));
12448 effect( DEF dst, USE src );
12450 ins_cost(85);
12451 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
12452 ins_encode( MovI2X_reg(dst, src) );
12453 ins_pipe( pipe_slow );
12454 %}
12456 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
12457 match(Set dst (MoveD2L src));
12458 effect(DEF dst, USE src);
12460 ins_cost(250);
12461 format %{ "MOV $dst.lo,$src\n\t"
12462 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
12463 opcode(0x8B, 0x8B);
12464 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
12465 ins_pipe( ialu_mem_long_reg );
12466 %}
12468 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
12469 predicate(UseSSE<=1);
12470 match(Set dst (MoveD2L src));
12471 effect(DEF dst, USE src);
12473 ins_cost(125);
12474 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
12475 ins_encode( Pop_Mem_Reg_D(dst, src) );
12476 ins_pipe( fpu_mem_reg );
12477 %}
12479 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regXD src) %{
12480 predicate(UseSSE>=2);
12481 match(Set dst (MoveD2L src));
12482 effect(DEF dst, USE src);
12483 ins_cost(95);
12485 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
12486 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src,dst));
12487 ins_pipe( pipe_slow );
12488 %}
12490 instruct MoveD2L_reg_reg_sse(eRegL dst, regXD src, regXD tmp) %{
12491 predicate(UseSSE>=2);
12492 match(Set dst (MoveD2L src));
12493 effect(DEF dst, USE src, TEMP tmp);
12494 ins_cost(85);
12495 format %{ "MOVD $dst.lo,$src\n\t"
12496 "PSHUFLW $tmp,$src,0x4E\n\t"
12497 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
12498 ins_encode( MovXD2L_reg(dst, src, tmp) );
12499 ins_pipe( pipe_slow );
12500 %}
12502 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
12503 match(Set dst (MoveL2D src));
12504 effect(DEF dst, USE src);
12506 ins_cost(200);
12507 format %{ "MOV $dst,$src.lo\n\t"
12508 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
12509 opcode(0x89, 0x89);
12510 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
12511 ins_pipe( ialu_mem_long_reg );
12512 %}
12515 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
12516 predicate(UseSSE<=1);
12517 match(Set dst (MoveL2D src));
12518 effect(DEF dst, USE src);
12519 ins_cost(125);
12521 format %{ "FLD_D $src\n\t"
12522 "FSTP $dst\t# MoveL2D_stack_reg" %}
12523 opcode(0xDD); /* DD /0, FLD m64real */
12524 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
12525 Pop_Reg_D(dst) );
12526 ins_pipe( fpu_reg_mem );
12527 %}
12530 instruct MoveL2D_stack_reg_sse(regXD dst, stackSlotL src) %{
12531 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
12532 match(Set dst (MoveL2D src));
12533 effect(DEF dst, USE src);
12535 ins_cost(95);
12536 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
12537 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
12538 ins_pipe( pipe_slow );
12539 %}
12541 instruct MoveL2D_stack_reg_sse_partial(regXD dst, stackSlotL src) %{
12542 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
12543 match(Set dst (MoveL2D src));
12544 effect(DEF dst, USE src);
12546 ins_cost(95);
12547 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
12548 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,src));
12549 ins_pipe( pipe_slow );
12550 %}
12552 instruct MoveL2D_reg_reg_sse(regXD dst, eRegL src, regXD tmp) %{
12553 predicate(UseSSE>=2);
12554 match(Set dst (MoveL2D src));
12555 effect(TEMP dst, USE src, TEMP tmp);
12556 ins_cost(85);
12557 format %{ "MOVD $dst,$src.lo\n\t"
12558 "MOVD $tmp,$src.hi\n\t"
12559 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
12560 ins_encode( MovL2XD_reg(dst, src, tmp) );
12561 ins_pipe( pipe_slow );
12562 %}
12564 // Replicate scalar to packed byte (1 byte) values in xmm
12565 instruct Repl8B_reg(regXD dst, regXD src) %{
12566 predicate(UseSSE>=2);
12567 match(Set dst (Replicate8B src));
12568 format %{ "MOVDQA $dst,$src\n\t"
12569 "PUNPCKLBW $dst,$dst\n\t"
12570 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
12571 ins_encode( pshufd_8x8(dst, src));
12572 ins_pipe( pipe_slow );
12573 %}
12575 // Replicate scalar to packed byte (1 byte) values in xmm
12576 instruct Repl8B_eRegI(regXD dst, eRegI src) %{
12577 predicate(UseSSE>=2);
12578 match(Set dst (Replicate8B src));
12579 format %{ "MOVD $dst,$src\n\t"
12580 "PUNPCKLBW $dst,$dst\n\t"
12581 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
12582 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst));
12583 ins_pipe( pipe_slow );
12584 %}
12586 // Replicate scalar zero to packed byte (1 byte) values in xmm
12587 instruct Repl8B_immI0(regXD dst, immI0 zero) %{
12588 predicate(UseSSE>=2);
12589 match(Set dst (Replicate8B zero));
12590 format %{ "PXOR $dst,$dst\t! replicate8B" %}
12591 ins_encode( pxor(dst, dst));
12592 ins_pipe( fpu_reg_reg );
12593 %}
12595 // Replicate scalar to packed shore (2 byte) values in xmm
12596 instruct Repl4S_reg(regXD dst, regXD src) %{
12597 predicate(UseSSE>=2);
12598 match(Set dst (Replicate4S src));
12599 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
12600 ins_encode( pshufd_4x16(dst, src));
12601 ins_pipe( fpu_reg_reg );
12602 %}
12604 // Replicate scalar to packed shore (2 byte) values in xmm
12605 instruct Repl4S_eRegI(regXD dst, eRegI src) %{
12606 predicate(UseSSE>=2);
12607 match(Set dst (Replicate4S src));
12608 format %{ "MOVD $dst,$src\n\t"
12609 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
12610 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
12611 ins_pipe( fpu_reg_reg );
12612 %}
12614 // Replicate scalar zero to packed short (2 byte) values in xmm
12615 instruct Repl4S_immI0(regXD dst, immI0 zero) %{
12616 predicate(UseSSE>=2);
12617 match(Set dst (Replicate4S zero));
12618 format %{ "PXOR $dst,$dst\t! replicate4S" %}
12619 ins_encode( pxor(dst, dst));
12620 ins_pipe( fpu_reg_reg );
12621 %}
12623 // Replicate scalar to packed char (2 byte) values in xmm
12624 instruct Repl4C_reg(regXD dst, regXD src) %{
12625 predicate(UseSSE>=2);
12626 match(Set dst (Replicate4C src));
12627 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
12628 ins_encode( pshufd_4x16(dst, src));
12629 ins_pipe( fpu_reg_reg );
12630 %}
12632 // Replicate scalar to packed char (2 byte) values in xmm
12633 instruct Repl4C_eRegI(regXD dst, eRegI src) %{
12634 predicate(UseSSE>=2);
12635 match(Set dst (Replicate4C src));
12636 format %{ "MOVD $dst,$src\n\t"
12637 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
12638 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
12639 ins_pipe( fpu_reg_reg );
12640 %}
12642 // Replicate scalar zero to packed char (2 byte) values in xmm
12643 instruct Repl4C_immI0(regXD dst, immI0 zero) %{
12644 predicate(UseSSE>=2);
12645 match(Set dst (Replicate4C zero));
12646 format %{ "PXOR $dst,$dst\t! replicate4C" %}
12647 ins_encode( pxor(dst, dst));
12648 ins_pipe( fpu_reg_reg );
12649 %}
12651 // Replicate scalar to packed integer (4 byte) values in xmm
12652 instruct Repl2I_reg(regXD dst, regXD src) %{
12653 predicate(UseSSE>=2);
12654 match(Set dst (Replicate2I src));
12655 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
12656 ins_encode( pshufd(dst, src, 0x00));
12657 ins_pipe( fpu_reg_reg );
12658 %}
12660 // Replicate scalar to packed integer (4 byte) values in xmm
12661 instruct Repl2I_eRegI(regXD dst, eRegI src) %{
12662 predicate(UseSSE>=2);
12663 match(Set dst (Replicate2I src));
12664 format %{ "MOVD $dst,$src\n\t"
12665 "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
12666 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00));
12667 ins_pipe( fpu_reg_reg );
12668 %}
12670 // Replicate scalar zero to packed integer (2 byte) values in xmm
12671 instruct Repl2I_immI0(regXD dst, immI0 zero) %{
12672 predicate(UseSSE>=2);
12673 match(Set dst (Replicate2I zero));
12674 format %{ "PXOR $dst,$dst\t! replicate2I" %}
12675 ins_encode( pxor(dst, dst));
12676 ins_pipe( fpu_reg_reg );
12677 %}
12679 // Replicate scalar to packed single precision floating point values in xmm
12680 instruct Repl2F_reg(regXD dst, regXD src) %{
12681 predicate(UseSSE>=2);
12682 match(Set dst (Replicate2F src));
12683 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
12684 ins_encode( pshufd(dst, src, 0xe0));
12685 ins_pipe( fpu_reg_reg );
12686 %}
12688 // Replicate scalar to packed single precision floating point values in xmm
12689 instruct Repl2F_regX(regXD dst, regX src) %{
12690 predicate(UseSSE>=2);
12691 match(Set dst (Replicate2F src));
12692 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
12693 ins_encode( pshufd(dst, src, 0xe0));
12694 ins_pipe( fpu_reg_reg );
12695 %}
12697 // Replicate scalar to packed single precision floating point values in xmm
12698 instruct Repl2F_immXF0(regXD dst, immXF0 zero) %{
12699 predicate(UseSSE>=2);
12700 match(Set dst (Replicate2F zero));
12701 format %{ "PXOR $dst,$dst\t! replicate2F" %}
12702 ins_encode( pxor(dst, dst));
12703 ins_pipe( fpu_reg_reg );
12704 %}
12706 // =======================================================================
12707 // fast clearing of an array
12708 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
12709 match(Set dummy (ClearArray cnt base));
12710 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
12711 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t"
12712 "XOR EAX,EAX\n\t"
12713 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
12714 opcode(0,0x4);
12715 ins_encode( Opcode(0xD1), RegOpc(ECX),
12716 OpcRegReg(0x33,EAX,EAX),
12717 Opcode(0xF3), Opcode(0xAB) );
12718 ins_pipe( pipe_slow );
12719 %}
12721 instruct string_compare(eDIRegP str1, eSIRegP str2, regXD tmp1, regXD tmp2,
12722 eAXRegI tmp3, eBXRegI tmp4, eCXRegI result, eFlagsReg cr) %{
12723 match(Set result (StrComp str1 str2));
12724 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, KILL tmp3, KILL tmp4, KILL cr);
12725 //ins_cost(300);
12727 format %{ "String Compare $str1,$str2 -> $result // KILL EAX, EBX" %}
12728 ins_encode( enc_String_Compare(str1, str2, tmp1, tmp2, tmp3, tmp4, result) );
12729 ins_pipe( pipe_slow );
12730 %}
12732 // fast string equals
12733 instruct string_equals(eDIRegP str1, eSIRegP str2, regXD tmp1, regXD tmp2,
12734 eBXRegI tmp3, eCXRegI tmp4, eAXRegI result, eFlagsReg cr) %{
12735 match(Set result (StrEquals str1 str2));
12736 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, KILL tmp3, KILL tmp4, KILL cr);
12738 format %{ "String Equals $str1,$str2 -> $result // KILL EBX, ECX" %}
12739 ins_encode( enc_String_Equals(tmp1, tmp2, str1, str2, tmp3, tmp4, result) );
12740 ins_pipe( pipe_slow );
12741 %}
12743 instruct string_indexof(eSIRegP str1, eDIRegP str2, regXD tmp1, eAXRegI tmp2,
12744 eCXRegI tmp3, eDXRegI tmp4, eBXRegI result, eFlagsReg cr) %{
12745 predicate(UseSSE42Intrinsics);
12746 match(Set result (StrIndexOf str1 str2));
12747 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, KILL tmp2, KILL tmp3, KILL tmp4, KILL cr);
12749 format %{ "String IndexOf $str1,$str2 -> $result // KILL EAX, ECX, EDX" %}
12750 ins_encode( enc_String_IndexOf(str1, str2, tmp1, tmp2, tmp3, tmp4, result) );
12751 ins_pipe( pipe_slow );
12752 %}
12754 // fast array equals
12755 instruct array_equals(eDIRegP ary1, eSIRegP ary2, regXD tmp1, regXD tmp2, eBXRegI tmp3,
12756 eDXRegI tmp4, eAXRegI result, eFlagsReg cr) %{
12757 match(Set result (AryEq ary1 ary2));
12758 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
12759 //ins_cost(300);
12761 format %{ "Array Equals $ary1,$ary2 -> $result // KILL EBX, EDX" %}
12762 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, tmp2, tmp3, tmp4, result) );
12763 ins_pipe( pipe_slow );
12764 %}
12766 //----------Control Flow Instructions------------------------------------------
12767 // Signed compare Instructions
12768 instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{
12769 match(Set cr (CmpI op1 op2));
12770 effect( DEF cr, USE op1, USE op2 );
12771 format %{ "CMP $op1,$op2" %}
12772 opcode(0x3B); /* Opcode 3B /r */
12773 ins_encode( OpcP, RegReg( op1, op2) );
12774 ins_pipe( ialu_cr_reg_reg );
12775 %}
12777 instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{
12778 match(Set cr (CmpI op1 op2));
12779 effect( DEF cr, USE op1 );
12780 format %{ "CMP $op1,$op2" %}
12781 opcode(0x81,0x07); /* Opcode 81 /7 */
12782 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
12783 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12784 ins_pipe( ialu_cr_reg_imm );
12785 %}
12787 // Cisc-spilled version of cmpI_eReg
12788 instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{
12789 match(Set cr (CmpI op1 (LoadI op2)));
12791 format %{ "CMP $op1,$op2" %}
12792 ins_cost(500);
12793 opcode(0x3B); /* Opcode 3B /r */
12794 ins_encode( OpcP, RegMem( op1, op2) );
12795 ins_pipe( ialu_cr_reg_mem );
12796 %}
12798 instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{
12799 match(Set cr (CmpI src zero));
12800 effect( DEF cr, USE src );
12802 format %{ "TEST $src,$src" %}
12803 opcode(0x85);
12804 ins_encode( OpcP, RegReg( src, src ) );
12805 ins_pipe( ialu_cr_reg_imm );
12806 %}
12808 instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{
12809 match(Set cr (CmpI (AndI src con) zero));
12811 format %{ "TEST $src,$con" %}
12812 opcode(0xF7,0x00);
12813 ins_encode( OpcP, RegOpc(src), Con32(con) );
12814 ins_pipe( ialu_cr_reg_imm );
12815 %}
12817 instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{
12818 match(Set cr (CmpI (AndI src mem) zero));
12820 format %{ "TEST $src,$mem" %}
12821 opcode(0x85);
12822 ins_encode( OpcP, RegMem( src, mem ) );
12823 ins_pipe( ialu_cr_reg_mem );
12824 %}
12826 // Unsigned compare Instructions; really, same as signed except they
12827 // produce an eFlagsRegU instead of eFlagsReg.
12828 instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{
12829 match(Set cr (CmpU op1 op2));
12831 format %{ "CMPu $op1,$op2" %}
12832 opcode(0x3B); /* Opcode 3B /r */
12833 ins_encode( OpcP, RegReg( op1, op2) );
12834 ins_pipe( ialu_cr_reg_reg );
12835 %}
12837 instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{
12838 match(Set cr (CmpU op1 op2));
12840 format %{ "CMPu $op1,$op2" %}
12841 opcode(0x81,0x07); /* Opcode 81 /7 */
12842 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12843 ins_pipe( ialu_cr_reg_imm );
12844 %}
12846 // // Cisc-spilled version of cmpU_eReg
12847 instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{
12848 match(Set cr (CmpU op1 (LoadI op2)));
12850 format %{ "CMPu $op1,$op2" %}
12851 ins_cost(500);
12852 opcode(0x3B); /* Opcode 3B /r */
12853 ins_encode( OpcP, RegMem( op1, op2) );
12854 ins_pipe( ialu_cr_reg_mem );
12855 %}
12857 // // Cisc-spilled version of cmpU_eReg
12858 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{
12859 // match(Set cr (CmpU (LoadI op1) op2));
12860 //
12861 // format %{ "CMPu $op1,$op2" %}
12862 // ins_cost(500);
12863 // opcode(0x39); /* Opcode 39 /r */
12864 // ins_encode( OpcP, RegMem( op1, op2) );
12865 //%}
12867 instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{
12868 match(Set cr (CmpU src zero));
12870 format %{ "TESTu $src,$src" %}
12871 opcode(0x85);
12872 ins_encode( OpcP, RegReg( src, src ) );
12873 ins_pipe( ialu_cr_reg_imm );
12874 %}
12876 // Unsigned pointer compare Instructions
12877 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
12878 match(Set cr (CmpP op1 op2));
12880 format %{ "CMPu $op1,$op2" %}
12881 opcode(0x3B); /* Opcode 3B /r */
12882 ins_encode( OpcP, RegReg( op1, op2) );
12883 ins_pipe( ialu_cr_reg_reg );
12884 %}
12886 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
12887 match(Set cr (CmpP op1 op2));
12889 format %{ "CMPu $op1,$op2" %}
12890 opcode(0x81,0x07); /* Opcode 81 /7 */
12891 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12892 ins_pipe( ialu_cr_reg_imm );
12893 %}
12895 // // Cisc-spilled version of cmpP_eReg
12896 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
12897 match(Set cr (CmpP op1 (LoadP op2)));
12899 format %{ "CMPu $op1,$op2" %}
12900 ins_cost(500);
12901 opcode(0x3B); /* Opcode 3B /r */
12902 ins_encode( OpcP, RegMem( op1, op2) );
12903 ins_pipe( ialu_cr_reg_mem );
12904 %}
12906 // // Cisc-spilled version of cmpP_eReg
12907 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
12908 // match(Set cr (CmpP (LoadP op1) op2));
12909 //
12910 // format %{ "CMPu $op1,$op2" %}
12911 // ins_cost(500);
12912 // opcode(0x39); /* Opcode 39 /r */
12913 // ins_encode( OpcP, RegMem( op1, op2) );
12914 //%}
12916 // Compare raw pointer (used in out-of-heap check).
12917 // Only works because non-oop pointers must be raw pointers
12918 // and raw pointers have no anti-dependencies.
12919 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
12920 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() );
12921 match(Set cr (CmpP op1 (LoadP op2)));
12923 format %{ "CMPu $op1,$op2" %}
12924 opcode(0x3B); /* Opcode 3B /r */
12925 ins_encode( OpcP, RegMem( op1, op2) );
12926 ins_pipe( ialu_cr_reg_mem );
12927 %}
12929 //
12930 // This will generate a signed flags result. This should be ok
12931 // since any compare to a zero should be eq/neq.
12932 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
12933 match(Set cr (CmpP src zero));
12935 format %{ "TEST $src,$src" %}
12936 opcode(0x85);
12937 ins_encode( OpcP, RegReg( src, src ) );
12938 ins_pipe( ialu_cr_reg_imm );
12939 %}
12941 // Cisc-spilled version of testP_reg
12942 // This will generate a signed flags result. This should be ok
12943 // since any compare to a zero should be eq/neq.
12944 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
12945 match(Set cr (CmpP (LoadP op) zero));
12947 format %{ "TEST $op,0xFFFFFFFF" %}
12948 ins_cost(500);
12949 opcode(0xF7); /* Opcode F7 /0 */
12950 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
12951 ins_pipe( ialu_cr_reg_imm );
12952 %}
12954 // Yanked all unsigned pointer compare operations.
12955 // Pointer compares are done with CmpP which is already unsigned.
12957 //----------Max and Min--------------------------------------------------------
12958 // Min Instructions
12959 ////
12960 // *** Min and Max using the conditional move are slower than the
12961 // *** branch version on a Pentium III.
12962 // // Conditional move for min
12963 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12964 // effect( USE_DEF op2, USE op1, USE cr );
12965 // format %{ "CMOVlt $op2,$op1\t! min" %}
12966 // opcode(0x4C,0x0F);
12967 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12968 // ins_pipe( pipe_cmov_reg );
12969 //%}
12970 //
12971 //// Min Register with Register (P6 version)
12972 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{
12973 // predicate(VM_Version::supports_cmov() );
12974 // match(Set op2 (MinI op1 op2));
12975 // ins_cost(200);
12976 // expand %{
12977 // eFlagsReg cr;
12978 // compI_eReg(cr,op1,op2);
12979 // cmovI_reg_lt(op2,op1,cr);
12980 // %}
12981 //%}
12983 // Min Register with Register (generic version)
12984 instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12985 match(Set dst (MinI dst src));
12986 effect(KILL flags);
12987 ins_cost(300);
12989 format %{ "MIN $dst,$src" %}
12990 opcode(0xCC);
12991 ins_encode( min_enc(dst,src) );
12992 ins_pipe( pipe_slow );
12993 %}
12995 // Max Register with Register
12996 // *** Min and Max using the conditional move are slower than the
12997 // *** branch version on a Pentium III.
12998 // // Conditional move for max
12999 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
13000 // effect( USE_DEF op2, USE op1, USE cr );
13001 // format %{ "CMOVgt $op2,$op1\t! max" %}
13002 // opcode(0x4F,0x0F);
13003 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
13004 // ins_pipe( pipe_cmov_reg );
13005 //%}
13006 //
13007 // // Max Register with Register (P6 version)
13008 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{
13009 // predicate(VM_Version::supports_cmov() );
13010 // match(Set op2 (MaxI op1 op2));
13011 // ins_cost(200);
13012 // expand %{
13013 // eFlagsReg cr;
13014 // compI_eReg(cr,op1,op2);
13015 // cmovI_reg_gt(op2,op1,cr);
13016 // %}
13017 //%}
13019 // Max Register with Register (generic version)
13020 instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
13021 match(Set dst (MaxI dst src));
13022 effect(KILL flags);
13023 ins_cost(300);
13025 format %{ "MAX $dst,$src" %}
13026 opcode(0xCC);
13027 ins_encode( max_enc(dst,src) );
13028 ins_pipe( pipe_slow );
13029 %}
13031 // ============================================================================
13032 // Branch Instructions
13033 // Jump Table
13034 instruct jumpXtnd(eRegI switch_val) %{
13035 match(Jump switch_val);
13036 ins_cost(350);
13038 format %{ "JMP [table_base](,$switch_val,1)\n\t" %}
13040 ins_encode %{
13041 address table_base = __ address_table_constant(_index2label);
13043 // Jump to Address(table_base + switch_reg)
13044 InternalAddress table(table_base);
13045 Address index(noreg, $switch_val$$Register, Address::times_1);
13046 __ jump(ArrayAddress(table, index));
13047 %}
13048 ins_pc_relative(1);
13049 ins_pipe(pipe_jmp);
13050 %}
13052 // Jump Direct - Label defines a relative address from JMP+1
13053 instruct jmpDir(label labl) %{
13054 match(Goto);
13055 effect(USE labl);
13057 ins_cost(300);
13058 format %{ "JMP $labl" %}
13059 size(5);
13060 opcode(0xE9);
13061 ins_encode( OpcP, Lbl( labl ) );
13062 ins_pipe( pipe_jmp );
13063 ins_pc_relative(1);
13064 %}
13066 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13067 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
13068 match(If cop cr);
13069 effect(USE labl);
13071 ins_cost(300);
13072 format %{ "J$cop $labl" %}
13073 size(6);
13074 opcode(0x0F, 0x80);
13075 ins_encode( Jcc( cop, labl) );
13076 ins_pipe( pipe_jcc );
13077 ins_pc_relative(1);
13078 %}
13080 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13081 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
13082 match(CountedLoopEnd cop cr);
13083 effect(USE labl);
13085 ins_cost(300);
13086 format %{ "J$cop $labl\t# Loop end" %}
13087 size(6);
13088 opcode(0x0F, 0x80);
13089 ins_encode( Jcc( cop, labl) );
13090 ins_pipe( pipe_jcc );
13091 ins_pc_relative(1);
13092 %}
13094 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13095 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
13096 match(CountedLoopEnd cop cmp);
13097 effect(USE labl);
13099 ins_cost(300);
13100 format %{ "J$cop,u $labl\t# Loop end" %}
13101 size(6);
13102 opcode(0x0F, 0x80);
13103 ins_encode( Jcc( cop, labl) );
13104 ins_pipe( pipe_jcc );
13105 ins_pc_relative(1);
13106 %}
13108 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
13109 match(CountedLoopEnd cop cmp);
13110 effect(USE labl);
13112 ins_cost(200);
13113 format %{ "J$cop,u $labl\t# Loop end" %}
13114 size(6);
13115 opcode(0x0F, 0x80);
13116 ins_encode( Jcc( cop, labl) );
13117 ins_pipe( pipe_jcc );
13118 ins_pc_relative(1);
13119 %}
13121 // Jump Direct Conditional - using unsigned comparison
13122 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
13123 match(If cop cmp);
13124 effect(USE labl);
13126 ins_cost(300);
13127 format %{ "J$cop,u $labl" %}
13128 size(6);
13129 opcode(0x0F, 0x80);
13130 ins_encode(Jcc(cop, labl));
13131 ins_pipe(pipe_jcc);
13132 ins_pc_relative(1);
13133 %}
13135 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
13136 match(If cop cmp);
13137 effect(USE labl);
13139 ins_cost(200);
13140 format %{ "J$cop,u $labl" %}
13141 size(6);
13142 opcode(0x0F, 0x80);
13143 ins_encode(Jcc(cop, labl));
13144 ins_pipe(pipe_jcc);
13145 ins_pc_relative(1);
13146 %}
13148 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
13149 match(If cop cmp);
13150 effect(USE labl);
13152 ins_cost(200);
13153 format %{ $$template
13154 if ($cop$$cmpcode == Assembler::notEqual) {
13155 $$emit$$"JP,u $labl\n\t"
13156 $$emit$$"J$cop,u $labl"
13157 } else {
13158 $$emit$$"JP,u done\n\t"
13159 $$emit$$"J$cop,u $labl\n\t"
13160 $$emit$$"done:"
13161 }
13162 %}
13163 size(12);
13164 opcode(0x0F, 0x80);
13165 ins_encode %{
13166 Label* l = $labl$$label;
13167 $$$emit8$primary;
13168 emit_cc(cbuf, $secondary, Assembler::parity);
13169 int parity_disp = -1;
13170 bool ok = false;
13171 if ($cop$$cmpcode == Assembler::notEqual) {
13172 // the two jumps 6 bytes apart so the jump distances are too
13173 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0;
13174 } else if ($cop$$cmpcode == Assembler::equal) {
13175 parity_disp = 6;
13176 ok = true;
13177 } else {
13178 ShouldNotReachHere();
13179 }
13180 emit_d32(cbuf, parity_disp);
13181 $$$emit8$primary;
13182 emit_cc(cbuf, $secondary, $cop$$cmpcode);
13183 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0;
13184 emit_d32(cbuf, disp);
13185 %}
13186 ins_pipe(pipe_jcc);
13187 ins_pc_relative(1);
13188 %}
13190 // ============================================================================
13191 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
13192 // array for an instance of the superklass. Set a hidden internal cache on a
13193 // hit (cache is checked with exposed code in gen_subtype_check()). Return
13194 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
13195 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
13196 match(Set result (PartialSubtypeCheck sub super));
13197 effect( KILL rcx, KILL cr );
13199 ins_cost(1100); // slightly larger than the next version
13200 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
13201 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
13202 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
13203 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
13204 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
13205 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
13206 "XOR $result,$result\t\t Hit: EDI zero\n\t"
13207 "miss:\t" %}
13209 opcode(0x1); // Force a XOR of EDI
13210 ins_encode( enc_PartialSubtypeCheck() );
13211 ins_pipe( pipe_slow );
13212 %}
13214 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
13215 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
13216 effect( KILL rcx, KILL result );
13218 ins_cost(1000);
13219 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
13220 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
13221 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
13222 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
13223 "JNE,s miss\t\t# Missed: flags NZ\n\t"
13224 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
13225 "miss:\t" %}
13227 opcode(0x0); // No need to XOR EDI
13228 ins_encode( enc_PartialSubtypeCheck() );
13229 ins_pipe( pipe_slow );
13230 %}
13232 // ============================================================================
13233 // Branch Instructions -- short offset versions
13234 //
13235 // These instructions are used to replace jumps of a long offset (the default
13236 // match) with jumps of a shorter offset. These instructions are all tagged
13237 // with the ins_short_branch attribute, which causes the ADLC to suppress the
13238 // match rules in general matching. Instead, the ADLC generates a conversion
13239 // method in the MachNode which can be used to do in-place replacement of the
13240 // long variant with the shorter variant. The compiler will determine if a
13241 // branch can be taken by the is_short_branch_offset() predicate in the machine
13242 // specific code section of the file.
13244 // Jump Direct - Label defines a relative address from JMP+1
13245 instruct jmpDir_short(label labl) %{
13246 match(Goto);
13247 effect(USE labl);
13249 ins_cost(300);
13250 format %{ "JMP,s $labl" %}
13251 size(2);
13252 opcode(0xEB);
13253 ins_encode( OpcP, LblShort( labl ) );
13254 ins_pipe( pipe_jmp );
13255 ins_pc_relative(1);
13256 ins_short_branch(1);
13257 %}
13259 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13260 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
13261 match(If cop cr);
13262 effect(USE labl);
13264 ins_cost(300);
13265 format %{ "J$cop,s $labl" %}
13266 size(2);
13267 opcode(0x70);
13268 ins_encode( JccShort( cop, labl) );
13269 ins_pipe( pipe_jcc );
13270 ins_pc_relative(1);
13271 ins_short_branch(1);
13272 %}
13274 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13275 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
13276 match(CountedLoopEnd cop cr);
13277 effect(USE labl);
13279 ins_cost(300);
13280 format %{ "J$cop,s $labl\t# Loop end" %}
13281 size(2);
13282 opcode(0x70);
13283 ins_encode( JccShort( cop, labl) );
13284 ins_pipe( pipe_jcc );
13285 ins_pc_relative(1);
13286 ins_short_branch(1);
13287 %}
13289 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13290 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
13291 match(CountedLoopEnd cop cmp);
13292 effect(USE labl);
13294 ins_cost(300);
13295 format %{ "J$cop,us $labl\t# Loop end" %}
13296 size(2);
13297 opcode(0x70);
13298 ins_encode( JccShort( cop, labl) );
13299 ins_pipe( pipe_jcc );
13300 ins_pc_relative(1);
13301 ins_short_branch(1);
13302 %}
13304 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
13305 match(CountedLoopEnd cop cmp);
13306 effect(USE labl);
13308 ins_cost(300);
13309 format %{ "J$cop,us $labl\t# Loop end" %}
13310 size(2);
13311 opcode(0x70);
13312 ins_encode( JccShort( cop, labl) );
13313 ins_pipe( pipe_jcc );
13314 ins_pc_relative(1);
13315 ins_short_branch(1);
13316 %}
13318 // Jump Direct Conditional - using unsigned comparison
13319 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
13320 match(If cop cmp);
13321 effect(USE labl);
13323 ins_cost(300);
13324 format %{ "J$cop,us $labl" %}
13325 size(2);
13326 opcode(0x70);
13327 ins_encode( JccShort( cop, labl) );
13328 ins_pipe( pipe_jcc );
13329 ins_pc_relative(1);
13330 ins_short_branch(1);
13331 %}
13333 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
13334 match(If cop cmp);
13335 effect(USE labl);
13337 ins_cost(300);
13338 format %{ "J$cop,us $labl" %}
13339 size(2);
13340 opcode(0x70);
13341 ins_encode( JccShort( cop, labl) );
13342 ins_pipe( pipe_jcc );
13343 ins_pc_relative(1);
13344 ins_short_branch(1);
13345 %}
13347 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
13348 match(If cop cmp);
13349 effect(USE labl);
13351 ins_cost(300);
13352 format %{ $$template
13353 if ($cop$$cmpcode == Assembler::notEqual) {
13354 $$emit$$"JP,u,s $labl\n\t"
13355 $$emit$$"J$cop,u,s $labl"
13356 } else {
13357 $$emit$$"JP,u,s done\n\t"
13358 $$emit$$"J$cop,u,s $labl\n\t"
13359 $$emit$$"done:"
13360 }
13361 %}
13362 size(4);
13363 opcode(0x70);
13364 ins_encode %{
13365 Label* l = $labl$$label;
13366 emit_cc(cbuf, $primary, Assembler::parity);
13367 int parity_disp = -1;
13368 if ($cop$$cmpcode == Assembler::notEqual) {
13369 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
13370 } else if ($cop$$cmpcode == Assembler::equal) {
13371 parity_disp = 2;
13372 } else {
13373 ShouldNotReachHere();
13374 }
13375 emit_d8(cbuf, parity_disp);
13376 emit_cc(cbuf, $primary, $cop$$cmpcode);
13377 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
13378 emit_d8(cbuf, disp);
13379 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
13380 assert(-128 <= parity_disp && parity_disp <= 127, "Displacement too large for short jmp");
13381 %}
13382 ins_pipe(pipe_jcc);
13383 ins_pc_relative(1);
13384 ins_short_branch(1);
13385 %}
13387 // ============================================================================
13388 // Long Compare
13389 //
13390 // Currently we hold longs in 2 registers. Comparing such values efficiently
13391 // is tricky. The flavor of compare used depends on whether we are testing
13392 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
13393 // The GE test is the negated LT test. The LE test can be had by commuting
13394 // the operands (yielding a GE test) and then negating; negate again for the
13395 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
13396 // NE test is negated from that.
13398 // Due to a shortcoming in the ADLC, it mixes up expressions like:
13399 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
13400 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
13401 // are collapsed internally in the ADLC's dfa-gen code. The match for
13402 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
13403 // foo match ends up with the wrong leaf. One fix is to not match both
13404 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
13405 // both forms beat the trinary form of long-compare and both are very useful
13406 // on Intel which has so few registers.
13408 // Manifest a CmpL result in an integer register. Very painful.
13409 // This is the test to avoid.
13410 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
13411 match(Set dst (CmpL3 src1 src2));
13412 effect( KILL flags );
13413 ins_cost(1000);
13414 format %{ "XOR $dst,$dst\n\t"
13415 "CMP $src1.hi,$src2.hi\n\t"
13416 "JLT,s m_one\n\t"
13417 "JGT,s p_one\n\t"
13418 "CMP $src1.lo,$src2.lo\n\t"
13419 "JB,s m_one\n\t"
13420 "JEQ,s done\n"
13421 "p_one:\tINC $dst\n\t"
13422 "JMP,s done\n"
13423 "m_one:\tDEC $dst\n"
13424 "done:" %}
13425 ins_encode %{
13426 Label p_one, m_one, done;
13427 __ xorptr($dst$$Register, $dst$$Register);
13428 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
13429 __ jccb(Assembler::less, m_one);
13430 __ jccb(Assembler::greater, p_one);
13431 __ cmpl($src1$$Register, $src2$$Register);
13432 __ jccb(Assembler::below, m_one);
13433 __ jccb(Assembler::equal, done);
13434 __ bind(p_one);
13435 __ incrementl($dst$$Register);
13436 __ jmpb(done);
13437 __ bind(m_one);
13438 __ decrementl($dst$$Register);
13439 __ bind(done);
13440 %}
13441 ins_pipe( pipe_slow );
13442 %}
13444 //======
13445 // Manifest a CmpL result in the normal flags. Only good for LT or GE
13446 // compares. Can be used for LE or GT compares by reversing arguments.
13447 // NOT GOOD FOR EQ/NE tests.
13448 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
13449 match( Set flags (CmpL src zero ));
13450 ins_cost(100);
13451 format %{ "TEST $src.hi,$src.hi" %}
13452 opcode(0x85);
13453 ins_encode( OpcP, RegReg_Hi2( src, src ) );
13454 ins_pipe( ialu_cr_reg_reg );
13455 %}
13457 // Manifest a CmpL result in the normal flags. Only good for LT or GE
13458 // compares. Can be used for LE or GT compares by reversing arguments.
13459 // NOT GOOD FOR EQ/NE tests.
13460 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{
13461 match( Set flags (CmpL src1 src2 ));
13462 effect( TEMP tmp );
13463 ins_cost(300);
13464 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
13465 "MOV $tmp,$src1.hi\n\t"
13466 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
13467 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
13468 ins_pipe( ialu_cr_reg_reg );
13469 %}
13471 // Long compares reg < zero/req OR reg >= zero/req.
13472 // Just a wrapper for a normal branch, plus the predicate test.
13473 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
13474 match(If cmp flags);
13475 effect(USE labl);
13476 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13477 expand %{
13478 jmpCon(cmp,flags,labl); // JLT or JGE...
13479 %}
13480 %}
13482 // Compare 2 longs and CMOVE longs.
13483 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
13484 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13485 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13486 ins_cost(400);
13487 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13488 "CMOV$cmp $dst.hi,$src.hi" %}
13489 opcode(0x0F,0x40);
13490 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13491 ins_pipe( pipe_cmov_reg_long );
13492 %}
13494 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
13495 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13496 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13497 ins_cost(500);
13498 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13499 "CMOV$cmp $dst.hi,$src.hi" %}
13500 opcode(0x0F,0x40);
13501 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13502 ins_pipe( pipe_cmov_reg_long );
13503 %}
13505 // Compare 2 longs and CMOVE ints.
13506 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{
13507 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13508 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13509 ins_cost(200);
13510 format %{ "CMOV$cmp $dst,$src" %}
13511 opcode(0x0F,0x40);
13512 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13513 ins_pipe( pipe_cmov_reg );
13514 %}
13516 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{
13517 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13518 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13519 ins_cost(250);
13520 format %{ "CMOV$cmp $dst,$src" %}
13521 opcode(0x0F,0x40);
13522 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13523 ins_pipe( pipe_cmov_mem );
13524 %}
13526 // Compare 2 longs and CMOVE ints.
13527 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
13528 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13529 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13530 ins_cost(200);
13531 format %{ "CMOV$cmp $dst,$src" %}
13532 opcode(0x0F,0x40);
13533 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13534 ins_pipe( pipe_cmov_reg );
13535 %}
13537 // Compare 2 longs and CMOVE doubles
13538 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
13539 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13540 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13541 ins_cost(200);
13542 expand %{
13543 fcmovD_regS(cmp,flags,dst,src);
13544 %}
13545 %}
13547 // Compare 2 longs and CMOVE doubles
13548 instruct cmovXDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regXD dst, regXD src) %{
13549 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13550 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13551 ins_cost(200);
13552 expand %{
13553 fcmovXD_regS(cmp,flags,dst,src);
13554 %}
13555 %}
13557 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
13558 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13559 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13560 ins_cost(200);
13561 expand %{
13562 fcmovF_regS(cmp,flags,dst,src);
13563 %}
13564 %}
13566 instruct cmovXX_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regX dst, regX src) %{
13567 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13568 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13569 ins_cost(200);
13570 expand %{
13571 fcmovX_regS(cmp,flags,dst,src);
13572 %}
13573 %}
13575 //======
13576 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
13577 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{
13578 match( Set flags (CmpL src zero ));
13579 effect(TEMP tmp);
13580 ins_cost(200);
13581 format %{ "MOV $tmp,$src.lo\n\t"
13582 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
13583 ins_encode( long_cmp_flags0( src, tmp ) );
13584 ins_pipe( ialu_reg_reg_long );
13585 %}
13587 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
13588 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
13589 match( Set flags (CmpL src1 src2 ));
13590 ins_cost(200+300);
13591 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
13592 "JNE,s skip\n\t"
13593 "CMP $src1.hi,$src2.hi\n\t"
13594 "skip:\t" %}
13595 ins_encode( long_cmp_flags1( src1, src2 ) );
13596 ins_pipe( ialu_cr_reg_reg );
13597 %}
13599 // Long compare reg == zero/reg OR reg != zero/reg
13600 // Just a wrapper for a normal branch, plus the predicate test.
13601 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
13602 match(If cmp flags);
13603 effect(USE labl);
13604 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13605 expand %{
13606 jmpCon(cmp,flags,labl); // JEQ or JNE...
13607 %}
13608 %}
13610 // Compare 2 longs and CMOVE longs.
13611 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
13612 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13613 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13614 ins_cost(400);
13615 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13616 "CMOV$cmp $dst.hi,$src.hi" %}
13617 opcode(0x0F,0x40);
13618 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13619 ins_pipe( pipe_cmov_reg_long );
13620 %}
13622 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
13623 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13624 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13625 ins_cost(500);
13626 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13627 "CMOV$cmp $dst.hi,$src.hi" %}
13628 opcode(0x0F,0x40);
13629 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13630 ins_pipe( pipe_cmov_reg_long );
13631 %}
13633 // Compare 2 longs and CMOVE ints.
13634 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{
13635 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13636 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13637 ins_cost(200);
13638 format %{ "CMOV$cmp $dst,$src" %}
13639 opcode(0x0F,0x40);
13640 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13641 ins_pipe( pipe_cmov_reg );
13642 %}
13644 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{
13645 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13646 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13647 ins_cost(250);
13648 format %{ "CMOV$cmp $dst,$src" %}
13649 opcode(0x0F,0x40);
13650 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13651 ins_pipe( pipe_cmov_mem );
13652 %}
13654 // Compare 2 longs and CMOVE ints.
13655 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
13656 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13657 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13658 ins_cost(200);
13659 format %{ "CMOV$cmp $dst,$src" %}
13660 opcode(0x0F,0x40);
13661 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13662 ins_pipe( pipe_cmov_reg );
13663 %}
13665 // Compare 2 longs and CMOVE doubles
13666 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
13667 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13668 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13669 ins_cost(200);
13670 expand %{
13671 fcmovD_regS(cmp,flags,dst,src);
13672 %}
13673 %}
13675 // Compare 2 longs and CMOVE doubles
13676 instruct cmovXDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regXD dst, regXD src) %{
13677 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13678 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13679 ins_cost(200);
13680 expand %{
13681 fcmovXD_regS(cmp,flags,dst,src);
13682 %}
13683 %}
13685 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
13686 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13687 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13688 ins_cost(200);
13689 expand %{
13690 fcmovF_regS(cmp,flags,dst,src);
13691 %}
13692 %}
13694 instruct cmovXX_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regX dst, regX src) %{
13695 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13696 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13697 ins_cost(200);
13698 expand %{
13699 fcmovX_regS(cmp,flags,dst,src);
13700 %}
13701 %}
13703 //======
13704 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13705 // Same as cmpL_reg_flags_LEGT except must negate src
13706 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{
13707 match( Set flags (CmpL src zero ));
13708 effect( TEMP tmp );
13709 ins_cost(300);
13710 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
13711 "CMP $tmp,$src.lo\n\t"
13712 "SBB $tmp,$src.hi\n\t" %}
13713 ins_encode( long_cmp_flags3(src, tmp) );
13714 ins_pipe( ialu_reg_reg_long );
13715 %}
13717 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13718 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
13719 // requires a commuted test to get the same result.
13720 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{
13721 match( Set flags (CmpL src1 src2 ));
13722 effect( TEMP tmp );
13723 ins_cost(300);
13724 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
13725 "MOV $tmp,$src2.hi\n\t"
13726 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
13727 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
13728 ins_pipe( ialu_cr_reg_reg );
13729 %}
13731 // Long compares reg < zero/req OR reg >= zero/req.
13732 // Just a wrapper for a normal branch, plus the predicate test
13733 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
13734 match(If cmp flags);
13735 effect(USE labl);
13736 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
13737 ins_cost(300);
13738 expand %{
13739 jmpCon(cmp,flags,labl); // JGT or JLE...
13740 %}
13741 %}
13743 // Compare 2 longs and CMOVE longs.
13744 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
13745 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13746 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13747 ins_cost(400);
13748 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13749 "CMOV$cmp $dst.hi,$src.hi" %}
13750 opcode(0x0F,0x40);
13751 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13752 ins_pipe( pipe_cmov_reg_long );
13753 %}
13755 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
13756 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13757 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13758 ins_cost(500);
13759 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13760 "CMOV$cmp $dst.hi,$src.hi+4" %}
13761 opcode(0x0F,0x40);
13762 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13763 ins_pipe( pipe_cmov_reg_long );
13764 %}
13766 // Compare 2 longs and CMOVE ints.
13767 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{
13768 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13769 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13770 ins_cost(200);
13771 format %{ "CMOV$cmp $dst,$src" %}
13772 opcode(0x0F,0x40);
13773 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13774 ins_pipe( pipe_cmov_reg );
13775 %}
13777 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{
13778 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13779 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13780 ins_cost(250);
13781 format %{ "CMOV$cmp $dst,$src" %}
13782 opcode(0x0F,0x40);
13783 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13784 ins_pipe( pipe_cmov_mem );
13785 %}
13787 // Compare 2 longs and CMOVE ptrs.
13788 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
13789 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13790 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13791 ins_cost(200);
13792 format %{ "CMOV$cmp $dst,$src" %}
13793 opcode(0x0F,0x40);
13794 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13795 ins_pipe( pipe_cmov_reg );
13796 %}
13798 // Compare 2 longs and CMOVE doubles
13799 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
13800 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13801 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13802 ins_cost(200);
13803 expand %{
13804 fcmovD_regS(cmp,flags,dst,src);
13805 %}
13806 %}
13808 // Compare 2 longs and CMOVE doubles
13809 instruct cmovXDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regXD dst, regXD src) %{
13810 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13811 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13812 ins_cost(200);
13813 expand %{
13814 fcmovXD_regS(cmp,flags,dst,src);
13815 %}
13816 %}
13818 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
13819 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13820 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13821 ins_cost(200);
13822 expand %{
13823 fcmovF_regS(cmp,flags,dst,src);
13824 %}
13825 %}
13828 instruct cmovXX_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regX dst, regX src) %{
13829 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13830 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13831 ins_cost(200);
13832 expand %{
13833 fcmovX_regS(cmp,flags,dst,src);
13834 %}
13835 %}
13838 // ============================================================================
13839 // Procedure Call/Return Instructions
13840 // Call Java Static Instruction
13841 // Note: If this code changes, the corresponding ret_addr_offset() and
13842 // compute_padding() functions will have to be adjusted.
13843 instruct CallStaticJavaDirect(method meth) %{
13844 match(CallStaticJava);
13845 effect(USE meth);
13847 ins_cost(300);
13848 format %{ "CALL,static " %}
13849 opcode(0xE8); /* E8 cd */
13850 ins_encode( pre_call_FPU,
13851 Java_Static_Call( meth ),
13852 call_epilog,
13853 post_call_FPU );
13854 ins_pipe( pipe_slow );
13855 ins_pc_relative(1);
13856 ins_alignment(4);
13857 %}
13859 // Call Java Dynamic Instruction
13860 // Note: If this code changes, the corresponding ret_addr_offset() and
13861 // compute_padding() functions will have to be adjusted.
13862 instruct CallDynamicJavaDirect(method meth) %{
13863 match(CallDynamicJava);
13864 effect(USE meth);
13866 ins_cost(300);
13867 format %{ "MOV EAX,(oop)-1\n\t"
13868 "CALL,dynamic" %}
13869 opcode(0xE8); /* E8 cd */
13870 ins_encode( pre_call_FPU,
13871 Java_Dynamic_Call( meth ),
13872 call_epilog,
13873 post_call_FPU );
13874 ins_pipe( pipe_slow );
13875 ins_pc_relative(1);
13876 ins_alignment(4);
13877 %}
13879 // Call Runtime Instruction
13880 instruct CallRuntimeDirect(method meth) %{
13881 match(CallRuntime );
13882 effect(USE meth);
13884 ins_cost(300);
13885 format %{ "CALL,runtime " %}
13886 opcode(0xE8); /* E8 cd */
13887 // Use FFREEs to clear entries in float stack
13888 ins_encode( pre_call_FPU,
13889 FFree_Float_Stack_All,
13890 Java_To_Runtime( meth ),
13891 post_call_FPU );
13892 ins_pipe( pipe_slow );
13893 ins_pc_relative(1);
13894 %}
13896 // Call runtime without safepoint
13897 instruct CallLeafDirect(method meth) %{
13898 match(CallLeaf);
13899 effect(USE meth);
13901 ins_cost(300);
13902 format %{ "CALL_LEAF,runtime " %}
13903 opcode(0xE8); /* E8 cd */
13904 ins_encode( pre_call_FPU,
13905 FFree_Float_Stack_All,
13906 Java_To_Runtime( meth ),
13907 Verify_FPU_For_Leaf, post_call_FPU );
13908 ins_pipe( pipe_slow );
13909 ins_pc_relative(1);
13910 %}
13912 instruct CallLeafNoFPDirect(method meth) %{
13913 match(CallLeafNoFP);
13914 effect(USE meth);
13916 ins_cost(300);
13917 format %{ "CALL_LEAF_NOFP,runtime " %}
13918 opcode(0xE8); /* E8 cd */
13919 ins_encode(Java_To_Runtime(meth));
13920 ins_pipe( pipe_slow );
13921 ins_pc_relative(1);
13922 %}
13925 // Return Instruction
13926 // Remove the return address & jump to it.
13927 instruct Ret() %{
13928 match(Return);
13929 format %{ "RET" %}
13930 opcode(0xC3);
13931 ins_encode(OpcP);
13932 ins_pipe( pipe_jmp );
13933 %}
13935 // Tail Call; Jump from runtime stub to Java code.
13936 // Also known as an 'interprocedural jump'.
13937 // Target of jump will eventually return to caller.
13938 // TailJump below removes the return address.
13939 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
13940 match(TailCall jump_target method_oop );
13941 ins_cost(300);
13942 format %{ "JMP $jump_target \t# EBX holds method oop" %}
13943 opcode(0xFF, 0x4); /* Opcode FF /4 */
13944 ins_encode( OpcP, RegOpc(jump_target) );
13945 ins_pipe( pipe_jmp );
13946 %}
13949 // Tail Jump; remove the return address; jump to target.
13950 // TailCall above leaves the return address around.
13951 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
13952 match( TailJump jump_target ex_oop );
13953 ins_cost(300);
13954 format %{ "POP EDX\t# pop return address into dummy\n\t"
13955 "JMP $jump_target " %}
13956 opcode(0xFF, 0x4); /* Opcode FF /4 */
13957 ins_encode( enc_pop_rdx,
13958 OpcP, RegOpc(jump_target) );
13959 ins_pipe( pipe_jmp );
13960 %}
13962 // Create exception oop: created by stack-crawling runtime code.
13963 // Created exception is now available to this handler, and is setup
13964 // just prior to jumping to this handler. No code emitted.
13965 instruct CreateException( eAXRegP ex_oop )
13966 %{
13967 match(Set ex_oop (CreateEx));
13969 size(0);
13970 // use the following format syntax
13971 format %{ "# exception oop is in EAX; no code emitted" %}
13972 ins_encode();
13973 ins_pipe( empty );
13974 %}
13977 // Rethrow exception:
13978 // The exception oop will come in the first argument position.
13979 // Then JUMP (not call) to the rethrow stub code.
13980 instruct RethrowException()
13981 %{
13982 match(Rethrow);
13984 // use the following format syntax
13985 format %{ "JMP rethrow_stub" %}
13986 ins_encode(enc_rethrow);
13987 ins_pipe( pipe_jmp );
13988 %}
13990 // inlined locking and unlocking
13993 instruct cmpFastLock( eFlagsReg cr, eRegP object, eRegP box, eAXRegI tmp, eRegP scr) %{
13994 match( Set cr (FastLock object box) );
13995 effect( TEMP tmp, TEMP scr );
13996 ins_cost(300);
13997 format %{ "FASTLOCK $object, $box KILLS $tmp,$scr" %}
13998 ins_encode( Fast_Lock(object,box,tmp,scr) );
13999 ins_pipe( pipe_slow );
14000 ins_pc_relative(1);
14001 %}
14003 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
14004 match( Set cr (FastUnlock object box) );
14005 effect( TEMP tmp );
14006 ins_cost(300);
14007 format %{ "FASTUNLOCK $object, $box, $tmp" %}
14008 ins_encode( Fast_Unlock(object,box,tmp) );
14009 ins_pipe( pipe_slow );
14010 ins_pc_relative(1);
14011 %}
14015 // ============================================================================
14016 // Safepoint Instruction
14017 instruct safePoint_poll(eFlagsReg cr) %{
14018 match(SafePoint);
14019 effect(KILL cr);
14021 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
14022 // On SPARC that might be acceptable as we can generate the address with
14023 // just a sethi, saving an or. By polling at offset 0 we can end up
14024 // putting additional pressure on the index-0 in the D$. Because of
14025 // alignment (just like the situation at hand) the lower indices tend
14026 // to see more traffic. It'd be better to change the polling address
14027 // to offset 0 of the last $line in the polling page.
14029 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
14030 ins_cost(125);
14031 size(6) ;
14032 ins_encode( Safepoint_Poll() );
14033 ins_pipe( ialu_reg_mem );
14034 %}
14036 //----------PEEPHOLE RULES-----------------------------------------------------
14037 // These must follow all instruction definitions as they use the names
14038 // defined in the instructions definitions.
14039 //
14040 // peepmatch ( root_instr_name [preceding_instruction]* );
14041 //
14042 // peepconstraint %{
14043 // (instruction_number.operand_name relational_op instruction_number.operand_name
14044 // [, ...] );
14045 // // instruction numbers are zero-based using left to right order in peepmatch
14046 //
14047 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
14048 // // provide an instruction_number.operand_name for each operand that appears
14049 // // in the replacement instruction's match rule
14050 //
14051 // ---------VM FLAGS---------------------------------------------------------
14052 //
14053 // All peephole optimizations can be turned off using -XX:-OptoPeephole
14054 //
14055 // Each peephole rule is given an identifying number starting with zero and
14056 // increasing by one in the order seen by the parser. An individual peephole
14057 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
14058 // on the command-line.
14059 //
14060 // ---------CURRENT LIMITATIONS----------------------------------------------
14061 //
14062 // Only match adjacent instructions in same basic block
14063 // Only equality constraints
14064 // Only constraints between operands, not (0.dest_reg == EAX_enc)
14065 // Only one replacement instruction
14066 //
14067 // ---------EXAMPLE----------------------------------------------------------
14068 //
14069 // // pertinent parts of existing instructions in architecture description
14070 // instruct movI(eRegI dst, eRegI src) %{
14071 // match(Set dst (CopyI src));
14072 // %}
14073 //
14074 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
14075 // match(Set dst (AddI dst src));
14076 // effect(KILL cr);
14077 // %}
14078 //
14079 // // Change (inc mov) to lea
14080 // peephole %{
14081 // // increment preceeded by register-register move
14082 // peepmatch ( incI_eReg movI );
14083 // // require that the destination register of the increment
14084 // // match the destination register of the move
14085 // peepconstraint ( 0.dst == 1.dst );
14086 // // construct a replacement instruction that sets
14087 // // the destination to ( move's source register + one )
14088 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
14089 // %}
14090 //
14091 // Implementation no longer uses movX instructions since
14092 // machine-independent system no longer uses CopyX nodes.
14093 //
14094 // peephole %{
14095 // peepmatch ( incI_eReg movI );
14096 // peepconstraint ( 0.dst == 1.dst );
14097 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
14098 // %}
14099 //
14100 // peephole %{
14101 // peepmatch ( decI_eReg movI );
14102 // peepconstraint ( 0.dst == 1.dst );
14103 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
14104 // %}
14105 //
14106 // peephole %{
14107 // peepmatch ( addI_eReg_imm movI );
14108 // peepconstraint ( 0.dst == 1.dst );
14109 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
14110 // %}
14111 //
14112 // peephole %{
14113 // peepmatch ( addP_eReg_imm movP );
14114 // peepconstraint ( 0.dst == 1.dst );
14115 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
14116 // %}
14118 // // Change load of spilled value to only a spill
14119 // instruct storeI(memory mem, eRegI src) %{
14120 // match(Set mem (StoreI mem src));
14121 // %}
14122 //
14123 // instruct loadI(eRegI dst, memory mem) %{
14124 // match(Set dst (LoadI mem));
14125 // %}
14126 //
14127 peephole %{
14128 peepmatch ( loadI storeI );
14129 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
14130 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
14131 %}
14133 //----------SMARTSPILL RULES---------------------------------------------------
14134 // These must follow all instruction definitions as they use the names
14135 // defined in the instructions definitions.