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src/cpu/mips/vm/mips_64.ad@0797c3ebbee4
src/cpu/mips/vm/mips_64.ad
Mon, 20 Feb 2017 12:23:10 -0500
- author
- fujie
- date
- Mon, 20 Feb 2017 12:23:10 -0500
- changeset 327
- 0797c3ebbee4
- parent 326
- 82d0812bdc67
- child 328
- 245bd118e64c
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- -rw-r--r--
[C2] Add instruct rotI_shr_logical_Reg in mips_64.ad
1 //
2 // Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24 //
26 // GodSon3 Architecture Description File
28 //----------REGISTER DEFINITION BLOCK------------------------------------------
29 // This information is used by the matcher and the register allocator to
30 // describe individual registers and classes of registers within the target
31 // archtecture.
33 // format:
34 // reg_def name (call convention, c-call convention, ideal type, encoding);
35 // call convention :
36 // NS = No-Save
37 // SOC = Save-On-Call
38 // SOE = Save-On-Entry
39 // AS = Always-Save
40 // ideal type :
41 // see opto/opcodes.hpp for more info
42 // reg_class name (reg, ...);
43 // alloc_class name (reg, ...);
44 register %{
46 // General Registers
47 // Integer Registers
48 reg_def R0 ( NS, NS, Op_RegI, 0, VMRegImpl::Bad());
49 reg_def AT ( NS, NS, Op_RegI, 1, AT->as_VMReg());
50 reg_def AT_H ( NS, NS, Op_RegI, 1, AT->as_VMReg()->next());
51 reg_def V0 (SOC, SOC, Op_RegI, 2, V0->as_VMReg());
52 reg_def V0_H (SOC, SOC, Op_RegI, 2, V0->as_VMReg()->next());
53 reg_def V1 (SOC, SOC, Op_RegI, 3, V1->as_VMReg());
54 reg_def V1_H (SOC, SOC, Op_RegI, 3, V1->as_VMReg()->next());
55 reg_def A0 (SOC, SOC, Op_RegI, 4, A0->as_VMReg());
56 reg_def A0_H (SOC, SOC, Op_RegI, 4, A0->as_VMReg()->next());
57 reg_def A1 (SOC, SOC, Op_RegI, 5, A1->as_VMReg());
58 reg_def A1_H (SOC, SOC, Op_RegI, 5, A1->as_VMReg()->next());
59 reg_def A2 (SOC, SOC, Op_RegI, 6, A2->as_VMReg());
60 reg_def A2_H (SOC, SOC, Op_RegI, 6, A2->as_VMReg()->next());
61 reg_def A3 (SOC, SOC, Op_RegI, 7, A3->as_VMReg());
62 reg_def A3_H (SOC, SOC, Op_RegI, 7, A3->as_VMReg()->next());
63 reg_def A4 (SOC, SOC, Op_RegI, 8, A4->as_VMReg());
64 reg_def A4_H (SOC, SOC, Op_RegI, 8, A4->as_VMReg()->next());
65 reg_def A5 (SOC, SOC, Op_RegI, 9, A5->as_VMReg());
66 reg_def A5_H (SOC, SOC, Op_RegI, 9, A5->as_VMReg()->next());
67 reg_def A6 (SOC, SOC, Op_RegI, 10, A6->as_VMReg());
68 reg_def A6_H (SOC, SOC, Op_RegI, 10, A6->as_VMReg()->next());
69 reg_def A7 (SOC, SOC, Op_RegI, 11, A7->as_VMReg());
70 reg_def A7_H (SOC, SOC, Op_RegI, 11, A7->as_VMReg()->next());
71 reg_def T0 (SOC, SOC, Op_RegI, 12, T0->as_VMReg());
72 reg_def T0_H (SOC, SOC, Op_RegI, 12, T0->as_VMReg()->next());
73 reg_def T1 (SOC, SOC, Op_RegI, 13, T1->as_VMReg());
74 reg_def T1_H (SOC, SOC, Op_RegI, 13, T1->as_VMReg()->next());
75 reg_def T2 (SOC, SOC, Op_RegI, 14, T2->as_VMReg());
76 reg_def T2_H (SOC, SOC, Op_RegI, 14, T2->as_VMReg()->next());
77 reg_def T3 (SOC, SOC, Op_RegI, 15, T3->as_VMReg());
78 reg_def T3_H (SOC, SOC, Op_RegI, 15, T3->as_VMReg()->next());
79 reg_def S0 (SOC, SOE, Op_RegI, 16, S0->as_VMReg());
80 reg_def S0_H (SOC, SOE, Op_RegI, 16, S0->as_VMReg()->next());
81 reg_def S1 (SOC, SOE, Op_RegI, 17, S1->as_VMReg());
82 reg_def S1_H (SOC, SOE, Op_RegI, 17, S1->as_VMReg()->next());
83 reg_def S2 (SOC, SOE, Op_RegI, 18, S2->as_VMReg());
84 reg_def S2_H (SOC, SOE, Op_RegI, 18, S2->as_VMReg()->next());
85 reg_def S3 (SOC, SOE, Op_RegI, 19, S3->as_VMReg());
86 reg_def S3_H (SOC, SOE, Op_RegI, 19, S3->as_VMReg()->next());
87 reg_def S4 (SOC, SOE, Op_RegI, 20, S4->as_VMReg());
88 reg_def S4_H (SOC, SOE, Op_RegI, 20, S4->as_VMReg()->next());
89 reg_def S5 (SOC, SOE, Op_RegI, 21, S5->as_VMReg());
90 reg_def S5_H (SOC, SOE, Op_RegI, 21, S5->as_VMReg()->next());
91 reg_def S6 (SOC, SOE, Op_RegI, 22, S6->as_VMReg());
92 reg_def S6_H (SOC, SOE, Op_RegI, 22, S6->as_VMReg()->next());
93 reg_def S7 (SOC, SOE, Op_RegI, 23, S7->as_VMReg());
94 reg_def S7_H (SOC, SOE, Op_RegI, 23, S7->as_VMReg()->next());
95 reg_def T8 (SOC, SOC, Op_RegI, 24, T8->as_VMReg());
96 reg_def T8_H (SOC, SOC, Op_RegI, 24, T8->as_VMReg()->next());
97 reg_def T9 (SOC, SOC, Op_RegI, 25, T9->as_VMReg());
98 reg_def T9_H (SOC, SOC, Op_RegI, 25, T9->as_VMReg()->next());
100 // Special Registers
101 reg_def K0 ( NS, NS, Op_RegI, 26, K0->as_VMReg());
102 reg_def K1 ( NS, NS, Op_RegI, 27, K1->as_VMReg());
103 reg_def GP ( NS, NS, Op_RegI, 28, GP->as_VMReg());
104 reg_def GP_H ( NS, NS, Op_RegI, 28, GP->as_VMReg()->next());
105 reg_def SP ( NS, NS, Op_RegI, 29, SP->as_VMReg());
106 reg_def SP_H ( NS, NS, Op_RegI, 29, SP->as_VMReg()->next());
107 reg_def FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
108 reg_def FP_H ( NS, NS, Op_RegI, 30, FP->as_VMReg()->next());
109 reg_def RA ( NS, NS, Op_RegI, 31, RA->as_VMReg());
110 reg_def RA_H ( NS, NS, Op_RegI, 31, RA->as_VMReg()->next());
112 // Floating registers.
113 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
114 reg_def F0_H ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()->next());
115 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
116 reg_def F1_H ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()->next());
117 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
118 reg_def F2_H ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()->next());
119 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
120 reg_def F3_H ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()->next());
121 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
122 reg_def F4_H ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()->next());
123 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
124 reg_def F5_H ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()->next());
125 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
126 reg_def F6_H ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()->next());
127 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
128 reg_def F7_H ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()->next());
129 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
130 reg_def F8_H ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()->next());
131 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
132 reg_def F9_H ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()->next());
133 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
134 reg_def F10_H ( SOC, SOC, Op_RegF, 10, F10->as_VMReg()->next());
135 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
136 reg_def F11_H ( SOC, SOC, Op_RegF, 11, F11->as_VMReg()->next());
137 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
138 reg_def F12_H ( SOC, SOC, Op_RegF, 12, F12->as_VMReg()->next());
139 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
140 reg_def F13_H ( SOC, SOC, Op_RegF, 13, F13->as_VMReg()->next());
141 reg_def F14 ( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
142 reg_def F14_H ( SOC, SOC, Op_RegF, 14, F14->as_VMReg()->next());
143 reg_def F15 ( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
144 reg_def F15_H ( SOC, SOC, Op_RegF, 15, F15->as_VMReg()->next());
145 reg_def F16 ( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
146 reg_def F16_H ( SOC, SOC, Op_RegF, 16, F16->as_VMReg()->next());
147 reg_def F17 ( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
148 reg_def F17_H ( SOC, SOC, Op_RegF, 17, F17->as_VMReg()->next());
149 reg_def F18 ( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
150 reg_def F18_H ( SOC, SOC, Op_RegF, 18, F18->as_VMReg()->next());
151 reg_def F19 ( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
152 reg_def F19_H ( SOC, SOC, Op_RegF, 19, F19->as_VMReg()->next());
153 reg_def F20 ( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
154 reg_def F20_H ( SOC, SOC, Op_RegF, 20, F20->as_VMReg()->next());
155 reg_def F21 ( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
156 reg_def F21_H ( SOC, SOC, Op_RegF, 21, F21->as_VMReg()->next());
157 reg_def F22 ( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
158 reg_def F22_H ( SOC, SOC, Op_RegF, 22, F22->as_VMReg()->next());
159 reg_def F23 ( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
160 reg_def F23_H ( SOC, SOC, Op_RegF, 23, F23->as_VMReg()->next());
161 reg_def F24 ( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
162 reg_def F24_H ( SOC, SOC, Op_RegF, 24, F24->as_VMReg()->next());
163 reg_def F25 ( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
164 reg_def F25_H ( SOC, SOC, Op_RegF, 25, F25->as_VMReg()->next());
165 reg_def F26 ( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
166 reg_def F26_H ( SOC, SOC, Op_RegF, 26, F26->as_VMReg()->next());
167 reg_def F27 ( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
168 reg_def F27_H ( SOC, SOC, Op_RegF, 27, F27->as_VMReg()->next());
169 reg_def F28 ( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
170 reg_def F28_H ( SOC, SOC, Op_RegF, 28, F28->as_VMReg()->next());
171 reg_def F29 ( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
172 reg_def F29_H ( SOC, SOC, Op_RegF, 29, F29->as_VMReg()->next());
173 reg_def F30 ( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
174 reg_def F30_H ( SOC, SOC, Op_RegF, 30, F30->as_VMReg()->next());
175 reg_def F31 ( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
176 reg_def F31_H ( SOC, SOC, Op_RegF, 31, F31->as_VMReg()->next());
179 // ----------------------------
180 // Special Registers
181 // Condition Codes Flag Registers
182 reg_def MIPS_FLAG (SOC, SOC, Op_RegFlags, 1, as_Register(1)->as_VMReg());
183 //S6 is used for get_thread(S6)
184 //S5 is uesd for heapbase of compressed oop
185 alloc_class chunk0(
186 S7, S7_H,
187 S0, S0_H,
188 S1, S1_H,
189 S2, S2_H,
190 S4, S4_H,
191 S5, S5_H,
192 S6, S6_H,
193 S3, S3_H,
194 T2, T2_H,
195 T3, T3_H,
196 T8, T8_H,
197 T9, T9_H,
198 T1, T1_H, // inline_cache_reg
199 V1, V1_H,
200 A7, A7_H,
201 A6, A6_H,
202 A5, A5_H,
203 A4, A4_H,
204 V0, V0_H,
205 A3, A3_H,
206 A2, A2_H,
207 A1, A1_H,
208 A0, A0_H,
209 T0, T0_H,
210 GP, GP_H
211 RA, RA_H,
212 SP, SP_H, // stack_pointer
213 FP, FP_H // frame_pointer
214 );
216 alloc_class chunk1( F0, F0_H,
217 F1, F1_H,
218 F2, F2_H,
219 F3, F3_H,
220 F4, F4_H,
221 F5, F5_H,
222 F6, F6_H,
223 F7, F7_H,
224 F8, F8_H,
225 F9, F9_H,
226 F10, F10_H,
227 F11, F11_H,
228 F20, F20_H,
229 F21, F21_H,
230 F22, F22_H,
231 F23, F23_H,
232 F24, F24_H,
233 F25, F25_H,
234 F26, F26_H,
235 F27, F27_H,
236 F28, F28_H,
237 F19, F19_H,
238 F18, F18_H,
239 F17, F17_H,
240 F16, F16_H,
241 F15, F15_H,
242 F14, F14_H,
243 F13, F13_H,
244 F12, F12_H,
245 F29, F29_H,
246 F30, F30_H,
247 F31, F31_H);
249 alloc_class chunk2(MIPS_FLAG);
251 reg_class s_reg( S0, S1, S2, S3, S4, S5, S6, S7 );
252 reg_class s0_reg( S0 );
253 reg_class s1_reg( S1 );
254 reg_class s2_reg( S2 );
255 reg_class s3_reg( S3 );
256 reg_class s4_reg( S4 );
257 reg_class s5_reg( S5 );
258 reg_class s6_reg( S6 );
259 reg_class s7_reg( S7 );
261 reg_class t_reg( T0, T1, T2, T3, T8, T9 );
262 reg_class t0_reg( T0 );
263 reg_class t1_reg( T1 );
264 reg_class t2_reg( T2 );
265 reg_class t3_reg( T3 );
266 reg_class t8_reg( T8 );
267 reg_class t9_reg( T9 );
269 reg_class a_reg( A0, A1, A2, A3, A4, A5, A6, A7 );
270 reg_class a0_reg( A0 );
271 reg_class a1_reg( A1 );
272 reg_class a2_reg( A2 );
273 reg_class a3_reg( A3 );
274 reg_class a4_reg( A4 );
275 reg_class a5_reg( A5 );
276 reg_class a6_reg( A6 );
277 reg_class a7_reg( A7 );
279 reg_class v0_reg( V0 );
280 reg_class v1_reg( V1 );
282 reg_class sp_reg( SP, SP_H );
283 reg_class fp_reg( FP, FP_H );
285 reg_class mips_flags(MIPS_FLAG);
287 reg_class v0_long_reg( V0, V0_H );
288 reg_class v1_long_reg( V1, V1_H );
289 reg_class a0_long_reg( A0, A0_H );
290 reg_class a1_long_reg( A1, A1_H );
291 reg_class a2_long_reg( A2, A2_H );
292 reg_class a3_long_reg( A3, A3_H );
293 reg_class a4_long_reg( A4, A4_H );
294 reg_class a5_long_reg( A5, A5_H );
295 reg_class a6_long_reg( A6, A6_H );
296 reg_class a7_long_reg( A7, A7_H );
297 reg_class t0_long_reg( T0, T0_H );
298 reg_class t1_long_reg( T1, T1_H );
299 reg_class t2_long_reg( T2, T2_H );
300 reg_class t3_long_reg( T3, T3_H );
301 reg_class t8_long_reg( T8, T8_H );
302 reg_class t9_long_reg( T9, T9_H );
303 reg_class s0_long_reg( S0, S0_H );
304 reg_class s1_long_reg( S1, S1_H );
305 reg_class s2_long_reg( S2, S2_H );
306 reg_class s3_long_reg( S3, S3_H );
307 reg_class s4_long_reg( S4, S4_H );
308 reg_class s5_long_reg( S5, S5_H );
309 reg_class s6_long_reg( S6, S6_H );
310 reg_class s7_long_reg( S7, S7_H );
312 reg_class int_reg( S7, S0, S1, S2, S4, S3, T8, T2, T3, T1, V1, A7, A6, A5, A4, V0, A3, A2, A1, A0, T0 );
314 reg_class no_Ax_int_reg( S7, S0, S1, S2, S4, S3, T8, T2, T3, T1, V1, V0, T0 );
316 reg_class p_reg(
317 S7, S7_H,
318 S0, S0_H,
319 S1, S1_H,
320 S2, S2_H,
321 S4, S4_H,
322 S3, S3_H,
323 T8, T8_H,
324 T2, T2_H,
325 T3, T3_H,
326 T1, T1_H,
327 A7, A7_H,
328 A6, A6_H,
329 A5, A5_H,
330 A4, A4_H,
331 A3, A3_H,
332 A2, A2_H,
333 A1, A1_H,
334 A0, A0_H,
335 T0, T0_H
336 );
338 reg_class no_T8_p_reg(
339 S7, S7_H,
340 S0, S0_H,
341 S1, S1_H,
342 S2, S2_H,
343 S4, S4_H,
344 S3, S3_H,
345 T2, T2_H,
346 T3, T3_H,
347 T1, T1_H,
348 A7, A7_H,
349 A6, A6_H,
350 A5, A5_H,
351 A4, A4_H,
352 A3, A3_H,
353 A2, A2_H,
354 A1, A1_H,
355 A0, A0_H,
356 T0, T0_H
357 );
359 reg_class long_reg(
360 S7, S7_H,
361 S0, S0_H,
362 S1, S1_H,
363 S2, S2_H,
364 S4, S4_H,
365 S3, S3_H,
366 T8, T8_H,
367 T2, T2_H,
368 T3, T3_H,
369 T1, T1_H,
370 A7, A7_H,
371 A6, A6_H,
372 A5, A5_H,
373 A4, A4_H,
374 A3, A3_H,
375 A2, A2_H,
376 A1, A1_H,
377 A0, A0_H,
378 T0, T0_H
379 );
382 // Floating point registers.
383 // 2012/8/23 Fu: F30/F31 are used as temporary registers in D2I
384 // 2016/12/1 aoqi: F31 are not used as temporary registers in D2I
385 reg_class flt_reg( F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17 F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F31);
386 reg_class dbl_reg( F0, F0_H,
387 F1, F1_H,
388 F2, F2_H,
389 F3, F3_H,
390 F4, F4_H,
391 F5, F5_H,
392 F6, F6_H,
393 F7, F7_H,
394 F8, F8_H,
395 F9, F9_H,
396 F10, F10_H,
397 F11, F11_H,
398 F12, F12_H,
399 F13, F13_H,
400 F14, F14_H,
401 F15, F15_H,
402 F16, F16_H,
403 F17, F17_H,
404 F18, F18_H,
405 F19, F19_H,
406 F20, F20_H,
407 F21, F21_H,
408 F22, F22_H,
409 F23, F23_H,
410 F24, F24_H,
411 F25, F25_H,
412 F26, F26_H,
413 F27, F27_H,
414 F28, F28_H,
415 F29, F29_H,
416 F31, F31_H);
418 reg_class flt_arg0( F12 );
419 reg_class dbl_arg0( F12, F12_H );
420 reg_class dbl_arg1( F14, F14_H );
422 %}
424 //----------DEFINITION BLOCK---------------------------------------------------
425 // Define name --> value mappings to inform the ADLC of an integer valued name
426 // Current support includes integer values in the range [0, 0x7FFFFFFF]
427 // Format:
428 // int_def <name> ( <int_value>, <expression>);
429 // Generated Code in ad_<arch>.hpp
430 // #define <name> (<expression>)
431 // // value == <int_value>
432 // Generated code in ad_<arch>.cpp adlc_verification()
433 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
434 //
435 definitions %{
436 int_def DEFAULT_COST ( 100, 100);
437 int_def HUGE_COST (1000000, 1000000);
439 // Memory refs are twice as expensive as run-of-the-mill.
440 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
442 // Branches are even more expensive.
443 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
444 // we use jr instruction to construct call, so more expensive
445 // by yjl 2/28/2006
446 int_def CALL_COST ( 500, DEFAULT_COST * 5);
447 /*
448 int_def EQUAL ( 1, 1 );
449 int_def NOT_EQUAL ( 2, 2 );
450 int_def GREATER ( 3, 3 );
451 int_def GREATER_EQUAL ( 4, 4 );
452 int_def LESS ( 5, 5 );
453 int_def LESS_EQUAL ( 6, 6 );
454 */
455 %}
459 //----------SOURCE BLOCK-------------------------------------------------------
460 // This is a block of C++ code which provides values, functions, and
461 // definitions necessary in the rest of the architecture description
463 source_hpp %{
464 // Header information of the source block.
465 // Method declarations/definitions which are used outside
466 // the ad-scope can conveniently be defined here.
467 //
468 // To keep related declarations/definitions/uses close together,
469 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
471 class CallStubImpl {
473 //--------------------------------------------------------------
474 //---< Used for optimization in Compile::shorten_branches >---
475 //--------------------------------------------------------------
477 public:
478 // Size of call trampoline stub.
479 static uint size_call_trampoline() {
480 return 0; // no call trampolines on this platform
481 }
483 // number of relocations needed by a call trampoline stub
484 static uint reloc_call_trampoline() {
485 return 0; // no call trampolines on this platform
486 }
487 };
489 class HandlerImpl {
491 public:
493 static int emit_exception_handler(CodeBuffer &cbuf);
494 static int emit_deopt_handler(CodeBuffer& cbuf);
496 static uint size_exception_handler() {
497 // NativeCall instruction size is the same as NativeJump.
498 // exception handler starts out as jump and can be patched to
499 // a call be deoptimization. (4932387)
500 // Note that this value is also credited (in output.cpp) to
501 // the size of the code section.
502 // return NativeJump::instruction_size;
503 int size = NativeCall::instruction_size;
504 return round_to(size, 16);
505 }
507 #ifdef _LP64
508 static uint size_deopt_handler() {
509 int size = NativeCall::instruction_size;
510 return round_to(size, 16);
511 }
512 #else
513 static uint size_deopt_handler() {
514 // NativeCall instruction size is the same as NativeJump.
515 // exception handler starts out as jump and can be patched to
516 // a call be deoptimization. (4932387)
517 // Note that this value is also credited (in output.cpp) to
518 // the size of the code section.
519 return 5 + NativeJump::instruction_size; // pushl(); jmp;
520 }
521 #endif
522 };
524 %} // end source_hpp
526 source %{
528 #define NO_INDEX 0
529 #define RELOC_IMM64 Assembler::imm_operand
530 #define RELOC_DISP32 Assembler::disp32_operand
533 #define __ _masm.
536 // Emit exception handler code.
537 // Stuff framesize into a register and call a VM stub routine.
538 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) {
539 /*
540 // Note that the code buffer's insts_mark is always relative to insts.
541 // That's why we must use the macroassembler to generate a handler.
542 MacroAssembler _masm(&cbuf);
543 address base = __ start_a_stub(size_exception_handler());
544 if (base == NULL) return 0; // CodeBuffer::expand failed
545 int offset = __ offset();
546 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
547 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
548 __ end_a_stub();
549 return offset;
550 */
551 // Note that the code buffer's insts_mark is always relative to insts.
552 // That's why we must use the macroassembler to generate a handler.
553 MacroAssembler _masm(&cbuf);
554 address base =
555 __ start_a_stub(size_exception_handler());
556 if (base == NULL) return 0; // CodeBuffer::expand failed
557 int offset = __ offset();
559 __ block_comment("; emit_exception_handler");
561 /* 2012/9/25 FIXME Jin: According to X86, we should use direct jumpt.
562 * * However, this will trigger an assert after the 40th method:
563 * *
564 * * 39 b java.lang.Throwable::<init> (25 bytes)
565 * * --- ns java.lang.Throwable::fillInStackTrace
566 * * 40 !b java.net.URLClassLoader::findClass (29 bytes)
567 * * /vm/opto/runtime.cpp, 900 , assert(caller.is_compiled_frame(),"must be")
568 * * 40 made not entrant (2) java.net.URLClassLoader::findClass (29 bytes)
569 * *
570 * * If we change from JR to JALR, the assert will disappear, but WebClient will
571 * * fail after the 403th method with unknown reason.
572 * */
573 __ li48(T9, (long)OptoRuntime::exception_blob()->entry_point());
574 __ jr(T9);
575 __ delayed()->nop();
576 __ align(16);
577 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
578 __ end_a_stub();
579 return offset;
580 }
582 // Emit deopt handler code.
583 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
584 /*
585 // Note that the code buffer's insts_mark is always relative to insts.
586 // That's why we must use the macroassembler to generate a handler.
587 MacroAssembler _masm(&cbuf);
588 address base = __ start_a_stub(size_deopt_handler());
589 if (base == NULL) return 0; // CodeBuffer::expand failed
590 int offset = __ offset();
592 #ifdef _LP64
593 address the_pc = (address) __ pc();
594 Label next;
595 // push a "the_pc" on the stack without destroying any registers
596 // as they all may be live.
598 // push address of "next"
599 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32
600 __ bind(next);
601 // adjust it so it matches "the_pc"
602 __ subptr(Address(rsp, 0), __ offset() - offset);
603 #else
604 InternalAddress here(__ pc());
605 __ pushptr(here.addr());
606 #endif
608 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
609 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
610 __ end_a_stub();
611 return offset;
612 */
613 // Note that the code buffer's insts_mark is always relative to insts.
614 // That's why we must use the macroassembler to generate a handler.
615 MacroAssembler _masm(&cbuf);
616 address base =
617 __ start_a_stub(size_deopt_handler());
619 // FIXME
620 if (base == NULL) return 0; // CodeBuffer::expand failed
621 int offset = __ offset();
623 __ block_comment("; emit_deopt_handler");
625 cbuf.set_insts_mark();
626 __ relocate(relocInfo::runtime_call_type);
628 __ li48(T9, (long)SharedRuntime::deopt_blob()->unpack());
629 __ jalr(T9);
630 __ delayed()->nop();
631 __ align(16);
632 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
633 __ end_a_stub();
634 return offset;
635 }
638 const bool Matcher::match_rule_supported(int opcode) {
639 if (!has_match_rule(opcode))
640 return false;
642 switch (opcode) {
643 //Op_CountLeadingZerosI Op_CountLeadingZerosL can be deleted, all MIPS CPUs support clz & dclz.
644 case Op_CountLeadingZerosI:
645 case Op_CountLeadingZerosL:
646 if (!UseCountLeadingZerosInstruction)
647 return false;
648 break;
649 case Op_CountTrailingZerosI:
650 case Op_CountTrailingZerosL:
651 if (!UseCountTrailingZerosInstruction)
652 return false;
653 break;
654 }
656 return true; // Per default match rules are supported.
657 }
659 //FIXME
660 // emit call stub, compiled java to interpreter
661 void emit_java_to_interp(CodeBuffer &cbuf ) {
662 // Stub is fixed up when the corresponding call is converted from calling
663 // compiled code to calling interpreted code.
664 // mov rbx,0
665 // jmp -1
667 address mark = cbuf.insts_mark(); // get mark within main instrs section
669 // Note that the code buffer's insts_mark is always relative to insts.
670 // That's why we must use the macroassembler to generate a stub.
671 MacroAssembler _masm(&cbuf);
673 address base =
674 __ start_a_stub(Compile::MAX_stubs_size);
675 if (base == NULL) return; // CodeBuffer::expand failed
676 // static stub relocation stores the instruction address of the call
678 __ relocate(static_stub_Relocation::spec(mark), 0);
680 /* 2012/10/29 Jin: Rmethod contains methodOop, it should be relocated for GC */
681 /*
682 int oop_index = __ oop_recorder()->allocate_index(NULL);
683 RelocationHolder rspec = oop_Relocation::spec(oop_index);
684 __ relocate(rspec);
685 */
687 // static stub relocation also tags the methodOop in the code-stream.
688 __ li48(S3, (long)0);
689 // This is recognized as unresolved by relocs/nativeInst/ic code
691 __ relocate(relocInfo::runtime_call_type);
693 cbuf.set_insts_mark();
694 address call_pc = (address)-1;
695 __ li48(AT, (long)call_pc);
696 __ jr(AT);
697 __ nop();
698 __ align(16);
699 __ end_a_stub();
700 // Update current stubs pointer and restore code_end.
701 }
703 // size of call stub, compiled java to interpretor
704 uint size_java_to_interp() {
705 int size = 4 * 4 + NativeCall::instruction_size; // sizeof(li48) + NativeCall::instruction_size
706 return round_to(size, 16);
707 }
709 // relocation entries for call stub, compiled java to interpreter
710 uint reloc_java_to_interp() {
711 return 16; // in emit_java_to_interp + in Java_Static_Call
712 }
714 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
715 if( Assembler::is_simm16(offset) ) return true;
716 else
717 {
718 assert(false, "Not implemented yet !" );
719 Unimplemented();
720 }
721 }
724 // No additional cost for CMOVL.
725 const int Matcher::long_cmove_cost() { return 0; }
727 // No CMOVF/CMOVD with SSE2
728 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
730 // Does the CPU require late expand (see block.cpp for description of late expand)?
731 const bool Matcher::require_postalloc_expand = false;
733 // Should the Matcher clone shifts on addressing modes, expecting them
734 // to be subsumed into complex addressing expressions or compute them
735 // into registers? True for Intel but false for most RISCs
736 const bool Matcher::clone_shift_expressions = false;
738 // Do we need to mask the count passed to shift instructions or does
739 // the cpu only look at the lower 5/6 bits anyway?
740 const bool Matcher::need_masked_shift_count = false;
742 bool Matcher::narrow_oop_use_complex_address() {
743 NOT_LP64(ShouldNotCallThis());
744 assert(UseCompressedOops, "only for compressed oops code");
745 return false;
746 }
748 bool Matcher::narrow_klass_use_complex_address() {
749 NOT_LP64(ShouldNotCallThis());
750 assert(UseCompressedClassPointers, "only for compressed klass code");
751 return false;
752 }
754 // This is UltraSparc specific, true just means we have fast l2f conversion
755 const bool Matcher::convL2FSupported(void) {
756 return true;
757 }
759 // Max vector size in bytes. 0 if not supported.
760 const int Matcher::vector_width_in_bytes(BasicType bt) {
761 assert(MaxVectorSize == 8, "");
762 return 8;
763 }
765 // Vector ideal reg
766 const int Matcher::vector_ideal_reg(int size) {
767 assert(MaxVectorSize == 8, "");
768 switch(size) {
769 case 8: return Op_VecD;
770 }
771 ShouldNotReachHere();
772 return 0;
773 }
775 // Only lowest bits of xmm reg are used for vector shift count.
776 const int Matcher::vector_shift_count_ideal_reg(int size) {
777 fatal("vector shift is not supported");
778 return Node::NotAMachineReg;
779 }
781 // Limits on vector size (number of elements) loaded into vector.
782 const int Matcher::max_vector_size(const BasicType bt) {
783 assert(is_java_primitive(bt), "only primitive type vectors");
784 return vector_width_in_bytes(bt)/type2aelembytes(bt);
785 }
787 const int Matcher::min_vector_size(const BasicType bt) {
788 return max_vector_size(bt); // Same as max.
789 }
791 // MIPS supports misaligned vectors store/load? FIXME
792 const bool Matcher::misaligned_vectors_ok() {
793 return false;
794 //return !AlignVector; // can be changed by flag
795 }
797 // Register for DIVI projection of divmodI
798 RegMask Matcher::divI_proj_mask() {
799 ShouldNotReachHere();
800 return RegMask();
801 }
803 // Register for MODI projection of divmodI
804 RegMask Matcher::modI_proj_mask() {
805 ShouldNotReachHere();
806 return RegMask();
807 }
809 // Register for DIVL projection of divmodL
810 RegMask Matcher::divL_proj_mask() {
811 ShouldNotReachHere();
812 return RegMask();
813 }
815 int Matcher::regnum_to_fpu_offset(int regnum) {
816 return regnum - 32; // The FP registers are in the second chunk
817 }
820 const bool Matcher::isSimpleConstant64(jlong value) {
821 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
822 return true;
823 }
826 // Return whether or not this register is ever used as an argument. This
827 // function is used on startup to build the trampoline stubs in generateOptoStub.
828 // Registers not mentioned will be killed by the VM call in the trampoline, and
829 // arguments in those registers not be available to the callee.
830 bool Matcher::can_be_java_arg( int reg ) {
831 /* Refer to: [sharedRuntime_mips_64.cpp] SharedRuntime::java_calling_convention() */
832 if ( reg == T0_num || reg == T0_H_num
833 || reg == A0_num || reg == A0_H_num
834 || reg == A1_num || reg == A1_H_num
835 || reg == A2_num || reg == A2_H_num
836 || reg == A3_num || reg == A3_H_num
837 || reg == A4_num || reg == A4_H_num
838 || reg == A5_num || reg == A5_H_num
839 || reg == A6_num || reg == A6_H_num
840 || reg == A7_num || reg == A7_H_num )
841 return true;
843 if ( reg == F12_num || reg == F12_H_num
844 || reg == F13_num || reg == F13_H_num
845 || reg == F14_num || reg == F14_H_num
846 || reg == F15_num || reg == F15_H_num
847 || reg == F16_num || reg == F16_H_num
848 || reg == F17_num || reg == F17_H_num
849 || reg == F18_num || reg == F18_H_num
850 || reg == F19_num || reg == F19_H_num )
851 return true;
853 return false;
854 }
856 bool Matcher::is_spillable_arg( int reg ) {
857 return can_be_java_arg(reg);
858 }
860 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
861 return false;
862 }
864 // Register for MODL projection of divmodL
865 RegMask Matcher::modL_proj_mask() {
866 ShouldNotReachHere();
867 return RegMask();
868 }
870 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
871 return FP_REG_mask();
872 }
874 // MIPS doesn't support AES intrinsics
875 const bool Matcher::pass_original_key_for_aes() {
876 return false;
877 }
879 // The address of the call instruction needs to be 16-byte aligned to
880 // ensure that it does not span a cache line so that it can be patched.
882 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
883 //lui
884 //ori
885 //dsll
886 //ori
888 //jalr
889 //nop
891 return round_to(current_offset, alignment_required()) - current_offset;
892 }
894 // The address of the call instruction needs to be 16-byte aligned to
895 // ensure that it does not span a cache line so that it can be patched.
896 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
897 //li64 <--- skip
899 //lui
900 //ori
901 //dsll
902 //ori
904 //jalr
905 //nop
907 current_offset += 4 * 6; // skip li64
908 return round_to(current_offset, alignment_required()) - current_offset;
909 }
911 int CallLeafNoFPDirectNode::compute_padding(int current_offset) const {
912 //lui
913 //ori
914 //dsll
915 //ori
917 //jalr
918 //nop
920 return round_to(current_offset, alignment_required()) - current_offset;
921 }
923 int CallLeafDirectNode::compute_padding(int current_offset) const {
924 //lui
925 //ori
926 //dsll
927 //ori
929 //jalr
930 //nop
932 return round_to(current_offset, alignment_required()) - current_offset;
933 }
935 int CallRuntimeDirectNode::compute_padding(int current_offset) const {
936 //lui
937 //ori
938 //dsll
939 //ori
941 //jalr
942 //nop
944 return round_to(current_offset, alignment_required()) - current_offset;
945 }
947 // If CPU can load and store mis-aligned doubles directly then no fixup is
948 // needed. Else we split the double into 2 integer pieces and move it
949 // piece-by-piece. Only happens when passing doubles into C code as the
950 // Java calling convention forces doubles to be aligned.
951 const bool Matcher::misaligned_doubles_ok = false;
952 // Do floats take an entire double register or just half?
953 //const bool Matcher::float_in_double = true;
954 bool Matcher::float_in_double() { return false; }
955 // Threshold size for cleararray.
956 const int Matcher::init_array_short_size = 8 * BytesPerLong;
957 // Do ints take an entire long register or just half?
958 const bool Matcher::int_in_long = true;
959 // Is it better to copy float constants, or load them directly from memory?
960 // Intel can load a float constant from a direct address, requiring no
961 // extra registers. Most RISCs will have to materialize an address into a
962 // register first, so they would do better to copy the constant from stack.
963 const bool Matcher::rematerialize_float_constants = false;
964 // Advertise here if the CPU requires explicit rounding operations
965 // to implement the UseStrictFP mode.
966 const bool Matcher::strict_fp_requires_explicit_rounding = false;
967 // The ecx parameter to rep stos for the ClearArray node is in dwords.
968 const bool Matcher::init_array_count_is_in_bytes = false;
971 // Indicate if the safepoint node needs the polling page as an input.
972 // Since MIPS doesn't have absolute addressing, it needs.
973 bool SafePointNode::needs_polling_address_input() {
974 return true;
975 }
977 // !!!!! Special hack to get all type of calls to specify the byte offset
978 // from the start of the call to the point where the return address
979 // will point.
980 int MachCallStaticJavaNode::ret_addr_offset() {
981 assert(NativeCall::instruction_size == 24, "in MachCallStaticJavaNode::ret_addr_offset");
982 //The value ought to be 16 bytes.
983 //lui
984 //ori
985 //dsll
986 //ori
987 //jalr
988 //nop
989 return NativeCall::instruction_size;
990 }
992 int MachCallDynamicJavaNode::ret_addr_offset() {
993 /* 2012/9/10 Jin: must be kept in sync with Java_Dynamic_Call */
995 // return NativeCall::instruction_size;
996 assert(NativeCall::instruction_size == 24, "in MachCallDynamicJavaNode::ret_addr_offset");
997 //The value ought to be 4 + 16 bytes.
998 //lui IC_Klass,
999 //ori IC_Klass,
1000 //dsll IC_Klass
1001 //ori IC_Klass
1002 //lui T9
1003 //ori T9
1004 //dsll T9
1005 //ori T9
1006 //jalr T9
1007 //nop
1008 return 6 * 4 + NativeCall::instruction_size;
1010 }
1012 /*
1013 // EMIT_OPCODE()
1014 void emit_opcode(CodeBuffer &cbuf, int code) {
1015 *(cbuf.code_end()) = (unsigned char)code;
1016 cbuf.set_code_end(cbuf.code_end() + 1);
1017 }
1018 */
1020 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
1021 int format) {
1022 cbuf.relocate(cbuf.insts_mark(), reloc, format);
1023 cbuf.insts()->emit_int32(d32);
1024 }
1026 //=============================================================================
1028 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1029 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1030 static enum RC rc_class( OptoReg::Name reg ) {
1031 if( !OptoReg::is_valid(reg) ) return rc_bad;
1032 if (OptoReg::is_stack(reg)) return rc_stack;
1033 VMReg r = OptoReg::as_VMReg(reg);
1034 if (r->is_Register()) return rc_int;
1035 assert(r->is_FloatRegister(), "must be");
1036 return rc_float;
1037 }
1039 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
1040 // Get registers to move
1041 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1042 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1043 OptoReg::Name dst_second = ra_->get_reg_second(this );
1044 OptoReg::Name dst_first = ra_->get_reg_first(this );
1046 enum RC src_second_rc = rc_class(src_second);
1047 enum RC src_first_rc = rc_class(src_first);
1048 enum RC dst_second_rc = rc_class(dst_second);
1049 enum RC dst_first_rc = rc_class(dst_first);
1051 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1053 // Generate spill code!
1054 int size = 0;
1056 if( src_first == dst_first && src_second == dst_second )
1057 return 0; // Self copy, no move
1059 if (src_first_rc == rc_stack) {
1060 // mem ->
1061 if (dst_first_rc == rc_stack) {
1062 // mem -> mem
1063 assert(src_second != dst_first, "overlap");
1064 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1065 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1066 // 64-bit
1067 int src_offset = ra_->reg2offset(src_first);
1068 int dst_offset = ra_->reg2offset(dst_first);
1069 if (cbuf) {
1070 MacroAssembler _masm(cbuf);
1071 __ ld(AT, Address(SP, src_offset));
1072 __ sd(AT, Address(SP, dst_offset));
1073 #ifndef PRODUCT
1074 } else {
1075 if(!do_size){
1076 if (size != 0) st->print("\n\t");
1077 st->print("ld AT, [SP + #%d]\t# 64-bit mem-mem spill 1\n\t"
1078 "sd AT, [SP + #%d]",
1079 src_offset, dst_offset);
1080 }
1081 #endif
1082 }
1083 size += 8;
1084 } else {
1085 // 32-bit
1086 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1087 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1088 // No pushl/popl, so:
1089 int src_offset = ra_->reg2offset(src_first);
1090 int dst_offset = ra_->reg2offset(dst_first);
1091 if (cbuf) {
1092 MacroAssembler _masm(cbuf);
1093 __ lw(AT, Address(SP, src_offset));
1094 __ sw(AT, Address(SP, dst_offset));
1095 #ifndef PRODUCT
1096 } else {
1097 if(!do_size){
1098 if (size != 0) st->print("\n\t");
1099 st->print("lw AT, [SP + #%d] spill 2\n\t"
1100 "sw AT, [SP + #%d]\n\t",
1101 src_offset, dst_offset);
1102 }
1103 #endif
1104 }
1105 size += 8;
1106 }
1107 return size;
1108 } else if (dst_first_rc == rc_int) {
1109 // mem -> gpr
1110 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1111 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1112 // 64-bit
1113 int offset = ra_->reg2offset(src_first);
1114 if (cbuf) {
1115 MacroAssembler _masm(cbuf);
1116 __ ld(as_Register(Matcher::_regEncode[dst_first]), Address(SP, offset));
1117 #ifndef PRODUCT
1118 } else {
1119 if(!do_size){
1120 if (size != 0) st->print("\n\t");
1121 st->print("ld %s, [SP + #%d]\t# spill 3",
1122 Matcher::regName[dst_first],
1123 offset);
1124 }
1125 #endif
1126 }
1127 size += 4;
1128 } else {
1129 // 32-bit
1130 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1131 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1132 int offset = ra_->reg2offset(src_first);
1133 if (cbuf) {
1134 MacroAssembler _masm(cbuf);
1135 if (this->ideal_reg() == Op_RegI)
1136 __ lw(as_Register(Matcher::_regEncode[dst_first]), Address(SP, offset));
1137 else
1138 __ lwu(as_Register(Matcher::_regEncode[dst_first]), Address(SP, offset));
1139 #ifndef PRODUCT
1140 } else {
1141 if(!do_size){
1142 if (size != 0) st->print("\n\t");
1143 if (this->ideal_reg() == Op_RegI)
1144 st->print("lw %s, [SP + #%d]\t# spill 4",
1145 Matcher::regName[dst_first],
1146 offset);
1147 else
1148 st->print("lwu %s, [SP + #%d]\t# spill 5",
1149 Matcher::regName[dst_first],
1150 offset);
1151 }
1152 #endif
1153 }
1154 size += 4;
1155 }
1156 return size;
1157 } else if (dst_first_rc == rc_float) {
1158 // mem-> xmm
1159 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1160 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1161 // 64-bit
1162 int offset = ra_->reg2offset(src_first);
1163 if (cbuf) {
1164 MacroAssembler _masm(cbuf);
1165 __ ldc1( as_FloatRegister(Matcher::_regEncode[dst_first]), Address(SP, offset));
1166 #ifndef PRODUCT
1167 } else {
1168 if(!do_size){
1169 if (size != 0) st->print("\n\t");
1170 st->print("ldc1 %s, [SP + #%d]\t# spill 6",
1171 Matcher::regName[dst_first],
1172 offset);
1173 }
1174 #endif
1175 }
1176 size += 4;
1177 } else {
1178 // 32-bit
1179 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1180 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1181 int offset = ra_->reg2offset(src_first);
1182 if (cbuf) {
1183 MacroAssembler _masm(cbuf);
1184 __ lwc1( as_FloatRegister(Matcher::_regEncode[dst_first]), Address(SP, offset));
1185 #ifndef PRODUCT
1186 } else {
1187 if(!do_size){
1188 if (size != 0) st->print("\n\t");
1189 st->print("lwc1 %s, [SP + #%d]\t# spill 7",
1190 Matcher::regName[dst_first],
1191 offset);
1192 }
1193 #endif
1194 }
1195 size += 4;
1196 }
1197 return size;
1198 }
1199 } else if (src_first_rc == rc_int) {
1200 // gpr ->
1201 if (dst_first_rc == rc_stack) {
1202 // gpr -> mem
1203 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1204 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1205 // 64-bit
1206 int offset = ra_->reg2offset(dst_first);
1207 if (cbuf) {
1208 MacroAssembler _masm(cbuf);
1209 __ sd(as_Register(Matcher::_regEncode[src_first]), Address(SP, offset));
1210 #ifndef PRODUCT
1211 } else {
1212 if(!do_size){
1213 if (size != 0) st->print("\n\t");
1214 st->print("sd %s, [SP + #%d] # spill 8",
1215 Matcher::regName[src_first],
1216 offset);
1217 }
1218 #endif
1219 }
1220 size += 4;
1221 } else {
1222 // 32-bit
1223 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1224 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1225 int offset = ra_->reg2offset(dst_first);
1226 if (cbuf) {
1227 MacroAssembler _masm(cbuf);
1228 __ sw(as_Register(Matcher::_regEncode[src_first]), Address(SP, offset));
1229 #ifndef PRODUCT
1230 } else {
1231 if(!do_size){
1232 if (size != 0) st->print("\n\t");
1233 st->print("sw %s, [SP + #%d]\t# spill 9",
1234 Matcher::regName[src_first], offset);
1235 }
1236 #endif
1237 }
1238 size += 4;
1239 }
1240 return size;
1241 } else if (dst_first_rc == rc_int) {
1242 // gpr -> gpr
1243 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1244 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1245 // 64-bit
1246 if (cbuf) {
1247 MacroAssembler _masm(cbuf);
1248 __ move(as_Register(Matcher::_regEncode[dst_first]),
1249 as_Register(Matcher::_regEncode[src_first]));
1250 #ifndef PRODUCT
1251 } else {
1252 if(!do_size){
1253 if (size != 0) st->print("\n\t");
1254 st->print("move(64bit) %s <-- %s\t# spill 10",
1255 Matcher::regName[dst_first],
1256 Matcher::regName[src_first]);
1257 }
1258 #endif
1259 }
1260 size += 4;
1261 return size;
1262 } else {
1263 // 32-bit
1264 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1265 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1266 if (cbuf) {
1267 MacroAssembler _masm(cbuf);
1268 if (this->ideal_reg() == Op_RegI)
1269 __ move_u32(as_Register(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1270 else
1271 __ daddu(as_Register(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]), R0);
1273 #ifndef PRODUCT
1274 } else {
1275 if(!do_size){
1276 if (size != 0) st->print("\n\t");
1277 st->print("move(32-bit) %s <-- %s\t# spill 11",
1278 Matcher::regName[dst_first],
1279 Matcher::regName[src_first]);
1280 }
1281 #endif
1282 }
1283 size += 4;
1284 return size;
1285 }
1286 } else if (dst_first_rc == rc_float) {
1287 // gpr -> xmm
1288 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1289 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1290 // 64-bit
1291 if (cbuf) {
1292 MacroAssembler _masm(cbuf);
1293 __ dmtc1(as_Register(Matcher::_regEncode[src_first]), as_FloatRegister(Matcher::_regEncode[dst_first]));
1294 #ifndef PRODUCT
1295 } else {
1296 if(!do_size){
1297 if (size != 0) st->print("\n\t");
1298 st->print("dmtc1 %s, %s\t# spill 12",
1299 Matcher::regName[dst_first],
1300 Matcher::regName[src_first]);
1301 }
1302 #endif
1303 }
1304 size += 4;
1305 } else {
1306 // 32-bit
1307 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1308 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1309 if (cbuf) {
1310 MacroAssembler _masm(cbuf);
1311 __ mtc1( as_Register(Matcher::_regEncode[src_first]), as_FloatRegister(Matcher::_regEncode[dst_first]) );
1312 #ifndef PRODUCT
1313 } else {
1314 if(!do_size){
1315 if (size != 0) st->print("\n\t");
1316 st->print("mtc1 %s, %s\t# spill 13",
1317 Matcher::regName[dst_first],
1318 Matcher::regName[src_first]);
1319 }
1320 #endif
1321 }
1322 size += 4;
1323 }
1324 return size;
1325 }
1326 } else if (src_first_rc == rc_float) {
1327 // xmm ->
1328 if (dst_first_rc == rc_stack) {
1329 // xmm -> mem
1330 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1331 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1332 // 64-bit
1333 int offset = ra_->reg2offset(dst_first);
1334 if (cbuf) {
1335 MacroAssembler _masm(cbuf);
1336 __ sdc1( as_FloatRegister(Matcher::_regEncode[src_first]), Address(SP, offset) );
1337 #ifndef PRODUCT
1338 } else {
1339 if(!do_size){
1340 if (size != 0) st->print("\n\t");
1341 st->print("sdc1 %s, [SP + #%d]\t# spill 14",
1342 Matcher::regName[src_first],
1343 offset);
1344 }
1345 #endif
1346 }
1347 size += 4;
1348 } else {
1349 // 32-bit
1350 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1351 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1352 int offset = ra_->reg2offset(dst_first);
1353 if (cbuf) {
1354 MacroAssembler _masm(cbuf);
1355 __ swc1(as_FloatRegister(Matcher::_regEncode[src_first]), Address(SP, offset));
1356 #ifndef PRODUCT
1357 } else {
1358 if(!do_size){
1359 if (size != 0) st->print("\n\t");
1360 st->print("swc1 %s, [SP + #%d]\t# spill 15",
1361 Matcher::regName[src_first],
1362 offset);
1363 }
1364 #endif
1365 }
1366 size += 4;
1367 }
1368 return size;
1369 } else if (dst_first_rc == rc_int) {
1370 // xmm -> gpr
1371 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1372 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1373 // 64-bit
1374 if (cbuf) {
1375 MacroAssembler _masm(cbuf);
1376 __ dmfc1( as_Register(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
1377 #ifndef PRODUCT
1378 } else {
1379 if(!do_size){
1380 if (size != 0) st->print("\n\t");
1381 st->print("dmfc1 %s, %s\t# spill 16",
1382 Matcher::regName[dst_first],
1383 Matcher::regName[src_first]);
1384 }
1385 #endif
1386 }
1387 size += 4;
1388 } else {
1389 // 32-bit
1390 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1391 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1392 if (cbuf) {
1393 MacroAssembler _masm(cbuf);
1394 __ mfc1( as_Register(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
1395 #ifndef PRODUCT
1396 } else {
1397 if(!do_size){
1398 if (size != 0) st->print("\n\t");
1399 st->print("mfc1 %s, %s\t# spill 17",
1400 Matcher::regName[dst_first],
1401 Matcher::regName[src_first]);
1402 }
1403 #endif
1404 }
1405 size += 4;
1406 }
1407 return size;
1408 } else if (dst_first_rc == rc_float) {
1409 // xmm -> xmm
1410 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1411 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1412 // 64-bit
1413 if (cbuf) {
1414 MacroAssembler _masm(cbuf);
1415 __ mov_d( as_FloatRegister(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
1416 #ifndef PRODUCT
1417 } else {
1418 if(!do_size){
1419 if (size != 0) st->print("\n\t");
1420 st->print("mov_d %s <-- %s\t# spill 18",
1421 Matcher::regName[dst_first],
1422 Matcher::regName[src_first]);
1423 }
1424 #endif
1425 }
1426 size += 4;
1427 } else {
1428 // 32-bit
1429 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1430 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1431 if (cbuf) {
1432 MacroAssembler _masm(cbuf);
1433 __ mov_s( as_FloatRegister(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
1434 #ifndef PRODUCT
1435 } else {
1436 if(!do_size){
1437 if (size != 0) st->print("\n\t");
1438 st->print("mov_s %s <-- %s\t# spill 19",
1439 Matcher::regName[dst_first],
1440 Matcher::regName[src_first]);
1441 }
1442 #endif
1443 }
1444 size += 4;
1445 }
1446 return size;
1447 }
1448 }
1450 assert(0," foo ");
1451 Unimplemented();
1452 return size;
1454 }
1456 #ifndef PRODUCT
1457 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1458 implementation( NULL, ra_, false, st );
1459 }
1460 #endif
1462 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1463 implementation( &cbuf, ra_, false, NULL );
1464 }
1466 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1467 return implementation( NULL, ra_, true, NULL );
1468 }
1470 //=============================================================================
1471 #
1473 #ifndef PRODUCT
1474 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const {
1475 st->print("INT3");
1476 }
1477 #endif
1479 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc* ra_) const {
1480 MacroAssembler _masm(&cbuf);
1481 __ int3();
1482 }
1484 uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const {
1485 return MachNode::size(ra_);
1486 }
1489 //=============================================================================
1490 #ifndef PRODUCT
1491 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1492 Compile *C = ra_->C;
1493 int framesize = C->frame_size_in_bytes();
1495 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1497 st->print("daddiu SP, SP, %d # Rlease stack @ MachEpilogNode",framesize);
1498 st->cr(); st->print("\t");
1499 if (UseLoongsonISA) {
1500 st->print("gslq RA, FP, SP, %d # Restore FP & RA @ MachEpilogNode", -wordSize*2);
1501 } else {
1502 st->print("ld RA, SP, %d # Restore RA @ MachEpilogNode", -wordSize);
1503 st->cr(); st->print("\t");
1504 st->print("ld FP, SP, %d # Restore FP @ MachEpilogNode", -wordSize*2);
1505 }
1507 if( do_polling() && C->is_method_compilation() ) {
1508 st->print("Poll Safepoint # MachEpilogNode");
1509 }
1510 }
1511 #endif
1513 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1514 Compile *C = ra_->C;
1515 MacroAssembler _masm(&cbuf);
1516 int framesize = C->frame_size_in_bytes();
1518 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1520 __ daddiu(SP, SP, framesize);
1522 if (UseLoongsonISA) {
1523 __ gslq(RA, FP, SP, -wordSize*2);
1524 } else {
1525 __ ld(RA, SP, -wordSize );
1526 __ ld(FP, SP, -wordSize*2 );
1527 }
1529 /* 2012/11/19 Jin: The epilog in a RuntimeStub should not contain a safepoint */
1530 if( do_polling() && C->is_method_compilation() ) {
1531 #ifndef OPT_SAFEPOINT
1532 __ set64(AT, (long)os::get_polling_page());
1533 __ relocate(relocInfo::poll_return_type);
1534 __ lw(AT, AT, 0);
1535 #else
1536 __ lui(AT, Assembler::split_high((intptr_t)os::get_polling_page()));
1537 __ relocate(relocInfo::poll_return_type);
1538 __ lw(AT, AT, Assembler::split_low((intptr_t)os::get_polling_page()));
1539 #endif
1540 }
1541 }
1543 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1544 return MachNode::size(ra_); // too many variables; just compute it the hard way fujie debug
1545 }
1547 int MachEpilogNode::reloc() const {
1548 return 0; // a large enough number
1549 }
1551 const Pipeline * MachEpilogNode::pipeline() const {
1552 return MachNode::pipeline_class();
1553 }
1555 int MachEpilogNode::safepoint_offset() const { return 0; }
1557 //=============================================================================
1559 #ifndef PRODUCT
1560 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1561 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1562 int reg = ra_->get_reg_first(this);
1563 st->print("ADDI %s, SP, %d @BoxLockNode",Matcher::regName[reg],offset);
1564 }
1565 #endif
1568 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1569 return 4;
1570 }
1572 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1573 MacroAssembler _masm(&cbuf);
1574 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1575 int reg = ra_->get_encode(this);
1577 __ addi(as_Register(reg), SP, offset);
1578 /*
1579 if( offset >= 128 ) {
1580 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1581 emit_rm(cbuf, 0x2, reg, 0x04);
1582 emit_rm(cbuf, 0x0, 0x04, SP_enc);
1583 emit_d32(cbuf, offset);
1584 }
1585 else {
1586 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1587 emit_rm(cbuf, 0x1, reg, 0x04);
1588 emit_rm(cbuf, 0x0, 0x04, SP_enc);
1589 emit_d8(cbuf, offset);
1590 }
1591 */
1592 }
1595 //static int sizeof_FFree_Float_Stack_All = -1;
1597 int MachCallRuntimeNode::ret_addr_offset() {
1598 //lui
1599 //ori
1600 //dsll
1601 //ori
1602 //jalr
1603 //nop
1604 assert(NativeCall::instruction_size == 24, "in MachCallRuntimeNode::ret_addr_offset()");
1605 return NativeCall::instruction_size;
1606 // return 16;
1607 }
1613 //=============================================================================
1614 #ifndef PRODUCT
1615 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const {
1616 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1617 }
1618 #endif
1620 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1621 MacroAssembler _masm(&cbuf);
1622 int i = 0;
1623 for(i = 0; i < _count; i++)
1624 __ nop();
1625 }
1627 uint MachNopNode::size(PhaseRegAlloc *) const {
1628 return 4 * _count;
1629 }
1630 const Pipeline* MachNopNode::pipeline() const {
1631 return MachNode::pipeline_class();
1632 }
1634 //=============================================================================
1636 //=============================================================================
1637 #ifndef PRODUCT
1638 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1639 st->print_cr("load_klass(AT, T0)");
1640 st->print_cr("\tbeq(AT, iCache, L)");
1641 st->print_cr("\tnop");
1642 st->print_cr("\tjmp(SharedRuntime::get_ic_miss_stub(), relocInfo::runtime_call_type)");
1643 st->print_cr("\tnop");
1644 st->print_cr("\tnop");
1645 st->print_cr(" L:");
1646 }
1647 #endif
1650 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1651 MacroAssembler _masm(&cbuf);
1652 #ifdef ASSERT
1653 //uint code_size = cbuf.code_size();
1654 #endif
1655 int ic_reg = Matcher::inline_cache_reg_encode();
1656 Label L;
1657 Register receiver = T0;
1658 Register iCache = as_Register(ic_reg);
1659 __ load_klass(AT, receiver);
1660 __ beq(AT, iCache, L);
1661 __ nop();
1663 __ relocate(relocInfo::runtime_call_type);
1664 __ li48(T9, (long)SharedRuntime::get_ic_miss_stub());
1665 __ jr(T9);
1666 __ nop();
1668 /* WARNING these NOPs are critical so that verified entry point is properly
1669 * 8 bytes aligned for patching by NativeJump::patch_verified_entry() */
1670 __ align(CodeEntryAlignment);
1671 __ bind(L);
1672 }
1674 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1675 return MachNode::size(ra_);
1676 }
1680 //=============================================================================
1682 const RegMask& MachConstantBaseNode::_out_RegMask = P_REG_mask();
1684 int Compile::ConstantTable::calculate_table_base_offset() const {
1685 return 0; // absolute addressing, no offset
1686 }
1688 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1689 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1690 ShouldNotReachHere();
1691 }
1693 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1694 Compile* C = ra_->C;
1695 Compile::ConstantTable& constant_table = C->constant_table();
1696 MacroAssembler _masm(&cbuf);
1698 Register Rtoc = as_Register(ra_->get_encode(this));
1699 CodeSection* consts_section = __ code()->consts();
1700 int consts_size = consts_section->align_at_start(consts_section->size());
1701 assert(constant_table.size() == consts_size, "must be equal");
1703 if (consts_section->size()) {
1704 // Materialize the constant table base.
1705 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1706 // RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1707 __ relocate(relocInfo::internal_pc_type);
1708 __ li48(Rtoc, (long)baseaddr);
1709 }
1710 }
1712 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1713 // li48 (4 insts)
1714 return 4 * 4;
1715 }
1717 #ifndef PRODUCT
1718 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1719 Register r = as_Register(ra_->get_encode(this));
1720 st->print("li48 %s, &constanttable (constant table base) @ MachConstantBaseNode", r->name());
1721 }
1722 #endif
1725 //=============================================================================
1726 #ifndef PRODUCT
1727 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1728 Compile* C = ra_->C;
1730 int framesize = C->frame_size_in_bytes();
1731 int bangsize = C->bang_size_in_bytes();
1732 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1734 // Calls to C2R adapters often do not accept exceptional returns.
1735 // We require that their callers must bang for them. But be careful, because
1736 // some VM calls (such as call site linkage) can use several kilobytes of
1737 // stack. But the stack safety zone should account for that.
1738 // See bugs 4446381, 4468289, 4497237.
1739 if (C->need_stack_bang(bangsize)) {
1740 st->print_cr("# stack bang"); st->print("\t");
1741 }
1742 if (UseLoongsonISA) {
1743 st->print("gssq RA, FP, %d(SP) @ MachPrologNode\n\t", -wordSize*2);
1744 } else {
1745 st->print("sd RA, %d(SP) @ MachPrologNode\n\t", -wordSize);
1746 st->print("sd FP, %d(SP) @ MachPrologNode\n\t", -wordSize*2);
1747 }
1748 st->print("daddiu FP, SP, -%d \n\t", wordSize*2);
1749 st->print("daddiu SP, SP, -%d \t",framesize);
1750 }
1751 #endif
1754 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1755 Compile* C = ra_->C;
1756 MacroAssembler _masm(&cbuf);
1758 int framesize = C->frame_size_in_bytes();
1759 int bangsize = C->bang_size_in_bytes();
1761 // __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false);
1763 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1765 if (C->need_stack_bang(framesize)) {
1766 __ generate_stack_overflow_check(framesize);
1767 }
1769 if (UseLoongsonISA) {
1770 __ gssq(RA, FP, SP, -wordSize*2);
1771 } else {
1772 __ sd(RA, SP, -wordSize);
1773 __ sd(FP, SP, -wordSize*2);
1774 }
1775 __ daddiu(FP, SP, -wordSize*2);
1776 __ daddiu(SP, SP, -framesize);
1777 __ nop(); /* 2013.10.22 Jin: Make enough room for patch_verified_entry() */
1778 __ nop();
1780 C->set_frame_complete(cbuf.insts_size());
1781 if (C->has_mach_constant_base_node()) {
1782 // NOTE: We set the table base offset here because users might be
1783 // emitted before MachConstantBaseNode.
1784 Compile::ConstantTable& constant_table = C->constant_table();
1785 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1786 }
1788 }
1791 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1792 //fprintf(stderr, "\nPrologNode::size(ra_)= %d \n", MachNode::size(ra_));//fujie debug
1793 return MachNode::size(ra_); // too many variables; just compute it the hard way
1794 }
1796 int MachPrologNode::reloc() const {
1797 return 0; // a large enough number
1798 }
1800 %}
1802 //----------ENCODING BLOCK-----------------------------------------------------
1803 // This block specifies the encoding classes used by the compiler to output
1804 // byte streams. Encoding classes generate functions which are called by
1805 // Machine Instruction Nodes in order to generate the bit encoding of the
1806 // instruction. Operands specify their base encoding interface with the
1807 // interface keyword. There are currently supported four interfaces,
1808 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1809 // operand to generate a function which returns its register number when
1810 // queried. CONST_INTER causes an operand to generate a function which
1811 // returns the value of the constant when queried. MEMORY_INTER causes an
1812 // operand to generate four functions which return the Base Register, the
1813 // Index Register, the Scale Value, and the Offset Value of the operand when
1814 // queried. COND_INTER causes an operand to generate six functions which
1815 // return the encoding code (ie - encoding bits for the instruction)
1816 // associated with each basic boolean condition for a conditional instruction.
1817 // Instructions specify two basic values for encoding. They use the
1818 // ins_encode keyword to specify their encoding class (which must be one of
1819 // the class names specified in the encoding block), and they use the
1820 // opcode keyword to specify, in order, their primary, secondary, and
1821 // tertiary opcode. Only the opcode sections which a particular instruction
1822 // needs for encoding need to be specified.
1823 encode %{
1824 /*
1825 Alias:
1826 1044 b java.io.ObjectInputStream::readHandle (130 bytes)
1827 118 B14: # B19 B15 <- B13 Freq: 0.899955
1828 118 add S1, S2, V0 #@addP_reg_reg
1829 11c lb S0, [S1 + #-8257524] #@loadB
1830 120 BReq S0, #3, B19 #@branchConI_reg_imm P=0.100000 C=-1.000000
1831 */
1832 //Load byte signed
1833 enc_class load_B_enc (mRegI dst, memory mem) %{
1834 MacroAssembler _masm(&cbuf);
1835 int dst = $dst$$reg;
1836 int base = $mem$$base;
1837 int index = $mem$$index;
1838 int scale = $mem$$scale;
1839 int disp = $mem$$disp;
1841 if( index != 0 ) {
1842 if( Assembler::is_simm16(disp) ) {
1843 if( UseLoongsonISA ) {
1844 if (scale == 0) {
1845 __ gslbx(as_Register(dst), as_Register(base), as_Register(index), disp);
1846 } else {
1847 __ dsll(AT, as_Register(index), scale);
1848 __ gslbx(as_Register(dst), as_Register(base), AT, disp);
1849 }
1850 } else {
1851 if (scale == 0) {
1852 __ addu(AT, as_Register(base), as_Register(index));
1853 } else {
1854 __ dsll(AT, as_Register(index), scale);
1855 __ addu(AT, as_Register(base), AT);
1856 }
1857 __ lb(as_Register(dst), AT, disp);
1858 }
1859 } else {
1860 if (scale == 0) {
1861 __ addu(AT, as_Register(base), as_Register(index));
1862 } else {
1863 __ dsll(AT, as_Register(index), scale);
1864 __ addu(AT, as_Register(base), AT);
1865 }
1866 __ move(T9, disp);
1867 if( UseLoongsonISA ) {
1868 __ gslbx(as_Register(dst), AT, T9, 0);
1869 } else {
1870 __ addu(AT, AT, T9);
1871 __ lb(as_Register(dst), AT, 0);
1872 }
1873 }
1874 } else {
1875 if( Assembler::is_simm16(disp) ) {
1876 __ lb(as_Register(dst), as_Register(base), disp);
1877 } else {
1878 __ move(T9, disp);
1879 if( UseLoongsonISA ) {
1880 __ gslbx(as_Register(dst), as_Register(base), T9, 0);
1881 } else {
1882 __ addu(AT, as_Register(base), T9);
1883 __ lb(as_Register(dst), AT, 0);
1884 }
1885 }
1886 }
1887 %}
1889 //Load byte unsigned
1890 enc_class load_UB_enc (mRegI dst, memory mem) %{
1891 MacroAssembler _masm(&cbuf);
1892 int dst = $dst$$reg;
1893 int base = $mem$$base;
1894 int index = $mem$$index;
1895 int scale = $mem$$scale;
1896 int disp = $mem$$disp;
1898 if( index != 0 ) {
1899 if (scale == 0) {
1900 __ daddu(AT, as_Register(base), as_Register(index));
1901 } else {
1902 __ dsll(AT, as_Register(index), scale);
1903 __ daddu(AT, as_Register(base), AT);
1904 }
1905 if( Assembler::is_simm16(disp) ) {
1906 __ lbu(as_Register(dst), AT, disp);
1907 } else {
1908 __ move(T9, disp);
1909 __ daddu(AT, AT, T9);
1910 __ lbu(as_Register(dst), AT, 0);
1911 }
1912 } else {
1913 if( Assembler::is_simm16(disp) ) {
1914 __ lbu(as_Register(dst), as_Register(base), disp);
1915 } else {
1916 __ move(T9, disp);
1917 __ daddu(AT, as_Register(base), T9);
1918 __ lbu(as_Register(dst), AT, 0);
1919 }
1920 }
1921 %}
1923 enc_class store_B_reg_enc (memory mem, mRegI src) %{
1924 MacroAssembler _masm(&cbuf);
1925 int src = $src$$reg;
1926 int base = $mem$$base;
1927 int index = $mem$$index;
1928 int scale = $mem$$scale;
1929 int disp = $mem$$disp;
1931 if( index != 0 ) {
1932 if (scale == 0) {
1933 if( Assembler::is_simm(disp, 8) ) {
1934 if (UseLoongsonISA) {
1935 __ gssbx(as_Register(src), as_Register(base), as_Register(index), disp);
1936 } else {
1937 __ addu(AT, as_Register(base), as_Register(index));
1938 __ sb(as_Register(src), AT, disp);
1939 }
1940 } else if( Assembler::is_simm16(disp) ) {
1941 __ addu(AT, as_Register(base), as_Register(index));
1942 __ sb(as_Register(src), AT, disp);
1943 } else {
1944 __ addu(AT, as_Register(base), as_Register(index));
1945 __ move(T9, disp);
1946 if (UseLoongsonISA) {
1947 __ gssbx(as_Register(src), AT, T9, 0);
1948 } else {
1949 __ addu(AT, AT, T9);
1950 __ sb(as_Register(src), AT, 0);
1951 }
1952 }
1953 } else {
1954 __ dsll(AT, as_Register(index), scale);
1955 if( Assembler::is_simm(disp, 8) ) {
1956 if (UseLoongsonISA) {
1957 __ gssbx(as_Register(src), AT, as_Register(base), disp);
1958 } else {
1959 __ addu(AT, as_Register(base), AT);
1960 __ sb(as_Register(src), AT, disp);
1961 }
1962 } else if( Assembler::is_simm16(disp) ) {
1963 __ addu(AT, as_Register(base), AT);
1964 __ sb(as_Register(src), AT, disp);
1965 } else {
1966 __ addu(AT, as_Register(base), AT);
1967 __ move(T9, disp);
1968 if (UseLoongsonISA) {
1969 __ gssbx(as_Register(src), AT, T9, 0);
1970 } else {
1971 __ addu(AT, AT, T9);
1972 __ sb(as_Register(src), AT, 0);
1973 }
1974 }
1975 }
1976 } else {
1977 if( Assembler::is_simm16(disp) ) {
1978 __ sb(as_Register(src), as_Register(base), disp);
1979 } else {
1980 __ move(T9, disp);
1981 if (UseLoongsonISA) {
1982 __ gssbx(as_Register(src), as_Register(base), T9, 0);
1983 } else {
1984 __ addu(AT, as_Register(base), T9);
1985 __ sb(as_Register(src), AT, 0);
1986 }
1987 }
1988 }
1989 %}
1991 enc_class store_B_immI_enc (memory mem, immI8 src) %{
1992 MacroAssembler _masm(&cbuf);
1993 int base = $mem$$base;
1994 int index = $mem$$index;
1995 int scale = $mem$$scale;
1996 int disp = $mem$$disp;
1997 int value = $src$$constant;
1999 if( index != 0 ) {
2000 if (!UseLoongsonISA) {
2001 if (scale == 0) {
2002 __ daddu(AT, as_Register(base), as_Register(index));
2003 } else {
2004 __ dsll(AT, as_Register(index), scale);
2005 __ daddu(AT, as_Register(base), AT);
2006 }
2007 if( Assembler::is_simm16(disp) ) {
2008 if (value == 0) {
2009 __ sb(R0, AT, disp);
2010 } else {
2011 __ move(T9, value);
2012 __ sb(T9, AT, disp);
2013 }
2014 } else {
2015 if (value == 0) {
2016 __ move(T9, disp);
2017 __ daddu(AT, AT, T9);
2018 __ sb(R0, AT, 0);
2019 } else {
2020 __ move(T9, disp);
2021 __ daddu(AT, AT, T9);
2022 __ move(T9, value);
2023 __ sb(T9, AT, 0);
2024 }
2025 }
2026 } else {
2028 if (scale == 0) {
2029 if( Assembler::is_simm(disp, 8) ) {
2030 if (value == 0) {
2031 __ gssbx(R0, as_Register(base), as_Register(index), disp);
2032 } else {
2033 __ move(T9, value);
2034 __ gssbx(T9, as_Register(base), as_Register(index), disp);
2035 }
2036 } else if( Assembler::is_simm16(disp) ) {
2037 __ daddu(AT, as_Register(base), as_Register(index));
2038 if (value == 0) {
2039 __ sb(R0, AT, disp);
2040 } else {
2041 __ move(T9, value);
2042 __ sb(T9, AT, disp);
2043 }
2044 } else {
2045 if (value == 0) {
2046 __ daddu(AT, as_Register(base), as_Register(index));
2047 __ move(T9, disp);
2048 __ gssbx(R0, AT, T9, 0);
2049 } else {
2050 __ move(AT, disp);
2051 __ move(T9, value);
2052 __ daddu(AT, as_Register(base), AT);
2053 __ gssbx(T9, AT, as_Register(index), 0);
2054 }
2055 }
2057 } else {
2059 if( Assembler::is_simm(disp, 8) ) {
2060 __ dsll(AT, as_Register(index), scale);
2061 if (value == 0) {
2062 __ gssbx(R0, as_Register(base), AT, disp);
2063 } else {
2064 __ move(T9, value);
2065 __ gssbx(T9, as_Register(base), AT, disp);
2066 }
2067 } else if( Assembler::is_simm16(disp) ) {
2068 __ dsll(AT, as_Register(index), scale);
2069 __ daddu(AT, as_Register(base), AT);
2070 if (value == 0) {
2071 __ sb(R0, AT, disp);
2072 } else {
2073 __ move(T9, value);
2074 __ sb(T9, AT, disp);
2075 }
2076 } else {
2077 __ dsll(AT, as_Register(index), scale);
2078 if (value == 0) {
2079 __ daddu(AT, as_Register(base), AT);
2080 __ move(T9, disp);
2081 __ gssbx(R0, AT, T9, 0);
2082 } else {
2083 __ move(T9, disp);
2084 __ daddu(AT, AT, T9);
2085 __ move(T9, value);
2086 __ gssbx(T9, as_Register(base), AT, 0);
2087 }
2088 }
2089 }
2090 }
2091 } else {
2092 if( Assembler::is_simm16(disp) ) {
2093 if (value == 0) {
2094 __ sb(R0, as_Register(base), disp);
2095 } else {
2096 __ move(AT, value);
2097 __ sb(AT, as_Register(base), disp);
2098 }
2099 } else {
2100 if (value == 0) {
2101 __ move(T9, disp);
2102 if (UseLoongsonISA) {
2103 __ gssbx(R0, as_Register(base), T9, 0);
2104 } else {
2105 __ daddu(AT, as_Register(base), T9);
2106 __ sb(R0, AT, 0);
2107 }
2108 } else {
2109 __ move(T9, disp);
2110 if (UseLoongsonISA) {
2111 __ move(AT, value);
2112 __ gssbx(AT, as_Register(base), T9, 0);
2113 } else {
2114 __ daddu(AT, as_Register(base), T9);
2115 __ move(T9, value);
2116 __ sb(T9, AT, 0);
2117 }
2118 }
2119 }
2120 }
2121 %}
2124 enc_class store_B_immI_enc_sync (memory mem, immI8 src) %{
2125 MacroAssembler _masm(&cbuf);
2126 int base = $mem$$base;
2127 int index = $mem$$index;
2128 int scale = $mem$$scale;
2129 int disp = $mem$$disp;
2130 int value = $src$$constant;
2132 if( index != 0 ) {
2133 if (scale == 0) {
2134 __ daddu(AT, as_Register(base), as_Register(index));
2135 } else {
2136 __ dsll(AT, as_Register(index), scale);
2137 __ daddu(AT, as_Register(base), AT);
2138 }
2139 if( Assembler::is_simm16(disp) ) {
2140 if (value == 0) {
2141 __ sb(R0, AT, disp);
2142 } else {
2143 __ move(T9, value);
2144 __ sb(T9, AT, disp);
2145 }
2146 } else {
2147 if (value == 0) {
2148 __ move(T9, disp);
2149 __ daddu(AT, AT, T9);
2150 __ sb(R0, AT, 0);
2151 } else {
2152 __ move(T9, disp);
2153 __ daddu(AT, AT, T9);
2154 __ move(T9, value);
2155 __ sb(T9, AT, 0);
2156 }
2157 }
2158 } else {
2159 if( Assembler::is_simm16(disp) ) {
2160 if (value == 0) {
2161 __ sb(R0, as_Register(base), disp);
2162 } else {
2163 __ move(AT, value);
2164 __ sb(AT, as_Register(base), disp);
2165 }
2166 } else {
2167 if (value == 0) {
2168 __ move(T9, disp);
2169 __ daddu(AT, as_Register(base), T9);
2170 __ sb(R0, AT, 0);
2171 } else {
2172 __ move(T9, disp);
2173 __ daddu(AT, as_Register(base), T9);
2174 __ move(T9, value);
2175 __ sb(T9, AT, 0);
2176 }
2177 }
2178 }
2180 __ sync();
2181 %}
2183 // Load Short (16bit signed)
2184 enc_class load_S_enc (mRegI dst, memory mem) %{
2185 MacroAssembler _masm(&cbuf);
2186 int dst = $dst$$reg;
2187 int base = $mem$$base;
2188 int index = $mem$$index;
2189 int scale = $mem$$scale;
2190 int disp = $mem$$disp;
2192 if( index != 0 ) {
2193 if (scale == 0) {
2194 __ daddu(AT, as_Register(base), as_Register(index));
2195 } else {
2196 __ dsll(AT, as_Register(index), scale);
2197 __ daddu(AT, as_Register(base), AT);
2198 }
2199 if( Assembler::is_simm16(disp) ) {
2200 __ lh(as_Register(dst), AT, disp);
2201 } else {
2202 __ move(T9, disp);
2203 __ addu(AT, AT, T9);
2204 __ lh(as_Register(dst), AT, 0);
2205 }
2206 } else {
2207 if( Assembler::is_simm16(disp) ) {
2208 __ lh(as_Register(dst), as_Register(base), disp);
2209 } else {
2210 __ move(T9, disp);
2211 __ addu(AT, as_Register(base), T9);
2212 __ lh(as_Register(dst), AT, 0);
2213 }
2214 }
2215 %}
2217 // Load Char (16bit unsigned)
2218 enc_class load_C_enc (mRegI dst, memory mem) %{
2219 MacroAssembler _masm(&cbuf);
2220 int dst = $dst$$reg;
2221 int base = $mem$$base;
2222 int index = $mem$$index;
2223 int scale = $mem$$scale;
2224 int disp = $mem$$disp;
2226 if( index != 0 ) {
2227 if (scale == 0) {
2228 __ daddu(AT, as_Register(base), as_Register(index));
2229 } else {
2230 __ dsll(AT, as_Register(index), scale);
2231 __ daddu(AT, as_Register(base), AT);
2232 }
2233 if( Assembler::is_simm16(disp) ) {
2234 __ lhu(as_Register(dst), AT, disp);
2235 } else {
2236 __ move(T9, disp);
2237 __ addu(AT, AT, T9);
2238 __ lhu(as_Register(dst), AT, 0);
2239 }
2240 } else {
2241 if( Assembler::is_simm16(disp) ) {
2242 __ lhu(as_Register(dst), as_Register(base), disp);
2243 } else {
2244 __ move(T9, disp);
2245 __ daddu(AT, as_Register(base), T9);
2246 __ lhu(as_Register(dst), AT, 0);
2247 }
2248 }
2249 %}
2251 // Store Char (16bit unsigned)
2252 enc_class store_C_reg_enc (memory mem, mRegI src) %{
2253 MacroAssembler _masm(&cbuf);
2254 int src = $src$$reg;
2255 int base = $mem$$base;
2256 int index = $mem$$index;
2257 int scale = $mem$$scale;
2258 int disp = $mem$$disp;
2260 if( index != 0 ) {
2261 if( Assembler::is_simm16(disp) ) {
2262 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
2263 if (scale == 0) {
2264 __ gsshx(as_Register(src), as_Register(base), as_Register(index), disp);
2265 } else {
2266 __ dsll(AT, as_Register(index), scale);
2267 __ gsshx(as_Register(src), as_Register(base), AT, disp);
2268 }
2269 } else {
2270 if (scale == 0) {
2271 __ addu(AT, as_Register(base), as_Register(index));
2272 } else {
2273 __ dsll(AT, as_Register(index), scale);
2274 __ addu(AT, as_Register(base), AT);
2275 }
2276 __ sh(as_Register(src), AT, disp);
2277 }
2278 } else {
2279 if (scale == 0) {
2280 __ addu(AT, as_Register(base), as_Register(index));
2281 } else {
2282 __ dsll(AT, as_Register(index), scale);
2283 __ addu(AT, as_Register(base), AT);
2284 }
2285 __ move(T9, disp);
2286 if( UseLoongsonISA ) {
2287 __ gsshx(as_Register(src), AT, T9, 0);
2288 } else {
2289 __ addu(AT, AT, T9);
2290 __ sh(as_Register(src), AT, 0);
2291 }
2292 }
2293 } else {
2294 if( Assembler::is_simm16(disp) ) {
2295 __ sh(as_Register(src), as_Register(base), disp);
2296 } else {
2297 __ move(T9, disp);
2298 if( UseLoongsonISA ) {
2299 __ gsshx(as_Register(src), as_Register(base), T9, 0);
2300 } else {
2301 __ addu(AT, as_Register(base), T9);
2302 __ sh(as_Register(src), AT, 0);
2303 }
2304 }
2305 }
2306 %}
2308 enc_class load_I_enc (mRegI dst, memory mem) %{
2309 MacroAssembler _masm(&cbuf);
2310 int dst = $dst$$reg;
2311 int base = $mem$$base;
2312 int index = $mem$$index;
2313 int scale = $mem$$scale;
2314 int disp = $mem$$disp;
2316 if( index != 0 ) {
2317 if( Assembler::is_simm16(disp) ) {
2318 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
2319 if (scale == 0) {
2320 __ gslwx(as_Register(dst), as_Register(base), as_Register(index), disp);
2321 } else {
2322 __ dsll(AT, as_Register(index), scale);
2323 __ gslwx(as_Register(dst), as_Register(base), AT, disp);
2324 }
2325 } else {
2326 if (scale == 0) {
2327 __ addu(AT, as_Register(base), as_Register(index));
2328 } else {
2329 __ dsll(AT, as_Register(index), scale);
2330 __ addu(AT, as_Register(base), AT);
2331 }
2332 __ lw(as_Register(dst), AT, disp);
2333 }
2334 } else {
2335 if (scale == 0) {
2336 __ addu(AT, as_Register(base), as_Register(index));
2337 } else {
2338 __ dsll(AT, as_Register(index), scale);
2339 __ addu(AT, as_Register(base), AT);
2340 }
2341 __ move(T9, disp);
2342 if( UseLoongsonISA ) {
2343 __ gslwx(as_Register(dst), AT, T9, 0);
2344 } else {
2345 __ addu(AT, AT, T9);
2346 __ lw(as_Register(dst), AT, 0);
2347 }
2348 }
2349 } else {
2350 if( Assembler::is_simm16(disp) ) {
2351 __ lw(as_Register(dst), as_Register(base), disp);
2352 } else {
2353 __ move(T9, disp);
2354 if( UseLoongsonISA ) {
2355 __ gslwx(as_Register(dst), as_Register(base), T9, 0);
2356 } else {
2357 __ addu(AT, as_Register(base), T9);
2358 __ lw(as_Register(dst), AT, 0);
2359 }
2360 }
2361 }
2362 %}
2364 enc_class store_I_reg_enc (memory mem, mRegI src) %{
2365 MacroAssembler _masm(&cbuf);
2366 int src = $src$$reg;
2367 int base = $mem$$base;
2368 int index = $mem$$index;
2369 int scale = $mem$$scale;
2370 int disp = $mem$$disp;
2372 if( index != 0 ) {
2373 if( Assembler::is_simm16(disp) ) {
2374 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
2375 if (scale == 0) {
2376 __ gsswx(as_Register(src), as_Register(base), as_Register(index), disp);
2377 } else {
2378 __ dsll(AT, as_Register(index), scale);
2379 __ gsswx(as_Register(src), as_Register(base), AT, disp);
2380 }
2381 } else {
2382 if (scale == 0) {
2383 __ addu(AT, as_Register(base), as_Register(index));
2384 } else {
2385 __ dsll(AT, as_Register(index), scale);
2386 __ addu(AT, as_Register(base), AT);
2387 }
2388 __ sw(as_Register(src), AT, disp);
2389 }
2390 } else {
2391 if (scale == 0) {
2392 __ addu(AT, as_Register(base), as_Register(index));
2393 } else {
2394 __ dsll(AT, as_Register(index), scale);
2395 __ addu(AT, as_Register(base), AT);
2396 }
2397 __ move(T9, disp);
2398 if( UseLoongsonISA ) {
2399 __ gsswx(as_Register(src), AT, T9, 0);
2400 } else {
2401 __ addu(AT, AT, T9);
2402 __ sw(as_Register(src), AT, 0);
2403 }
2404 }
2405 } else {
2406 if( Assembler::is_simm16(disp) ) {
2407 __ sw(as_Register(src), as_Register(base), disp);
2408 } else {
2409 __ move(T9, disp);
2410 if( UseLoongsonISA ) {
2411 __ gsswx(as_Register(src), as_Register(base), T9, 0);
2412 } else {
2413 __ addu(AT, as_Register(base), T9);
2414 __ sw(as_Register(src), AT, 0);
2415 }
2416 }
2417 }
2418 %}
2420 enc_class store_I_immI_enc (memory mem, immI src) %{
2421 MacroAssembler _masm(&cbuf);
2422 int base = $mem$$base;
2423 int index = $mem$$index;
2424 int scale = $mem$$scale;
2425 int disp = $mem$$disp;
2426 int value = $src$$constant;
2428 if( index != 0 ) {
2429 if (scale == 0) {
2430 __ daddu(AT, as_Register(base), as_Register(index));
2431 } else {
2432 __ dsll(AT, as_Register(index), scale);
2433 __ daddu(AT, as_Register(base), AT);
2434 }
2435 if( Assembler::is_simm16(disp) ) {
2436 if (value == 0) {
2437 __ sw(R0, AT, disp);
2438 } else {
2439 __ move(T9, value);
2440 __ sw(T9, AT, disp);
2441 }
2442 } else {
2443 if (value == 0) {
2444 __ move(T9, disp);
2445 __ addu(AT, AT, T9);
2446 __ sw(R0, AT, 0);
2447 } else {
2448 __ move(T9, disp);
2449 __ addu(AT, AT, T9);
2450 __ move(T9, value);
2451 __ sw(T9, AT, 0);
2452 }
2453 }
2454 } else {
2455 if( Assembler::is_simm16(disp) ) {
2456 if (value == 0) {
2457 __ sw(R0, as_Register(base), disp);
2458 } else {
2459 __ move(AT, value);
2460 __ sw(AT, as_Register(base), disp);
2461 }
2462 } else {
2463 if (value == 0) {
2464 __ move(T9, disp);
2465 __ addu(AT, as_Register(base), T9);
2466 __ sw(R0, AT, 0);
2467 } else {
2468 __ move(T9, disp);
2469 __ addu(AT, as_Register(base), T9);
2470 __ move(T9, value);
2471 __ sw(T9, AT, 0);
2472 }
2473 }
2474 }
2475 %}
2477 enc_class load_N_enc (mRegN dst, memory mem) %{
2478 MacroAssembler _masm(&cbuf);
2479 int dst = $dst$$reg;
2480 int base = $mem$$base;
2481 int index = $mem$$index;
2482 int scale = $mem$$scale;
2483 int disp = $mem$$disp;
2484 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2485 assert(disp_reloc == relocInfo::none, "cannot have disp");
2487 if( index != 0 ) {
2488 if (scale == 0) {
2489 __ daddu(AT, as_Register(base), as_Register(index));
2490 } else {
2491 __ dsll(AT, as_Register(index), scale);
2492 __ daddu(AT, as_Register(base), AT);
2493 }
2494 if( Assembler::is_simm16(disp) ) {
2495 __ lwu(as_Register(dst), AT, disp);
2496 } else {
2497 __ li(T9, disp);
2498 __ daddu(AT, AT, T9);
2499 __ lwu(as_Register(dst), AT, 0);
2500 }
2501 } else {
2502 if( Assembler::is_simm16(disp) ) {
2503 __ lwu(as_Register(dst), as_Register(base), disp);
2504 } else {
2505 __ li(T9, disp);
2506 __ daddu(AT, as_Register(base), T9);
2507 __ lwu(as_Register(dst), AT, 0);
2508 }
2509 }
2511 %}
2514 enc_class load_P_enc (mRegP dst, memory mem) %{
2515 MacroAssembler _masm(&cbuf);
2516 int dst = $dst$$reg;
2517 int base = $mem$$base;
2518 int index = $mem$$index;
2519 int scale = $mem$$scale;
2520 int disp = $mem$$disp;
2521 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2522 assert(disp_reloc == relocInfo::none, "cannot have disp");
2524 if( index != 0 ) {
2525 if (scale == 0) {
2526 __ daddu(AT, as_Register(base), as_Register(index));
2527 } else {
2528 __ dsll(AT, as_Register(index), scale);
2529 __ daddu(AT, as_Register(base), AT);
2530 }
2531 if( Assembler::is_simm16(disp) ) {
2532 __ ld(as_Register(dst), AT, disp);
2533 } else {
2534 __ li(T9, disp);
2535 __ daddu(AT, AT, T9);
2536 __ ld(as_Register(dst), AT, 0);
2537 }
2538 } else {
2539 if( Assembler::is_simm16(disp) ) {
2540 __ ld(as_Register(dst), as_Register(base), disp);
2541 } else {
2542 __ li(T9, disp);
2543 __ daddu(AT, as_Register(base), T9);
2544 __ ld(as_Register(dst), AT, 0);
2545 }
2546 }
2547 // if( disp_reloc != relocInfo::none) __ ld(as_Register(dst), as_Register(dst), 0);
2548 %}
2550 enc_class store_P_reg_enc (memory mem, mRegP src) %{
2551 MacroAssembler _masm(&cbuf);
2552 int src = $src$$reg;
2553 int base = $mem$$base;
2554 int index = $mem$$index;
2555 int scale = $mem$$scale;
2556 int disp = $mem$$disp;
2558 if( index != 0 ) {
2559 if (scale == 0) {
2560 __ daddu(AT, as_Register(base), as_Register(index));
2561 } else {
2562 __ dsll(AT, as_Register(index), scale);
2563 __ daddu(AT, as_Register(base), AT);
2564 }
2565 if( Assembler::is_simm16(disp) ) {
2566 __ sd(as_Register(src), AT, disp);
2567 } else {
2568 __ move(T9, disp);
2569 __ daddu(AT, AT, T9);
2570 __ sd(as_Register(src), AT, 0);
2571 }
2572 } else {
2573 if( Assembler::is_simm16(disp) ) {
2574 __ sd(as_Register(src), as_Register(base), disp);
2575 } else {
2576 __ move(T9, disp);
2577 __ daddu(AT, as_Register(base), T9);
2578 __ sd(as_Register(src), AT, 0);
2579 }
2580 }
2581 %}
2583 enc_class store_N_reg_enc (memory mem, mRegN src) %{
2584 MacroAssembler _masm(&cbuf);
2585 int src = $src$$reg;
2586 int base = $mem$$base;
2587 int index = $mem$$index;
2588 int scale = $mem$$scale;
2589 int disp = $mem$$disp;
2591 if( index != 0 ) {
2592 if (scale == 0) {
2593 __ daddu(AT, as_Register(base), as_Register(index));
2594 } else {
2595 __ dsll(AT, as_Register(index), scale);
2596 __ daddu(AT, as_Register(base), AT);
2597 }
2598 if( Assembler::is_simm16(disp) ) {
2599 __ sw(as_Register(src), AT, disp);
2600 } else {
2601 __ move(T9, disp);
2602 __ addu(AT, AT, T9);
2603 __ sw(as_Register(src), AT, 0);
2604 }
2605 } else {
2606 if( Assembler::is_simm16(disp) ) {
2607 __ sw(as_Register(src), as_Register(base), disp);
2608 } else {
2609 __ move(T9, disp);
2610 __ addu(AT, as_Register(base), T9);
2611 __ sw(as_Register(src), AT, 0);
2612 }
2613 }
2614 %}
2616 enc_class store_P_immP_enc (memory mem, immP31 src) %{
2617 MacroAssembler _masm(&cbuf);
2618 int base = $mem$$base;
2619 int index = $mem$$index;
2620 int scale = $mem$$scale;
2621 int disp = $mem$$disp;
2622 long value = $src$$constant;
2624 if( index != 0 ) {
2625 if (scale == 0) {
2626 __ daddu(AT, as_Register(base), as_Register(index));
2627 } else {
2628 __ dsll(AT, as_Register(index), scale);
2629 __ daddu(AT, as_Register(base), AT);
2630 }
2631 if( Assembler::is_simm16(disp) ) {
2632 if (value == 0) {
2633 __ sd(R0, AT, disp);
2634 } else {
2635 __ move(T9, value);
2636 __ sd(T9, AT, disp);
2637 }
2638 } else {
2639 if (value == 0) {
2640 __ move(T9, disp);
2641 __ daddu(AT, AT, T9);
2642 __ sd(R0, AT, 0);
2643 } else {
2644 __ move(T9, disp);
2645 __ daddu(AT, AT, T9);
2646 __ move(T9, value);
2647 __ sd(T9, AT, 0);
2648 }
2649 }
2650 } else {
2651 if( Assembler::is_simm16(disp) ) {
2652 if (value == 0) {
2653 __ sd(R0, as_Register(base), disp);
2654 } else {
2655 __ move(AT, value);
2656 __ sd(AT, as_Register(base), disp);
2657 }
2658 } else {
2659 if (value == 0) {
2660 __ move(T9, disp);
2661 __ daddu(AT, as_Register(base), T9);
2662 __ sd(R0, AT, 0);
2663 } else {
2664 __ move(T9, disp);
2665 __ daddu(AT, as_Register(base), T9);
2666 __ move(T9, value);
2667 __ sd(T9, AT, 0);
2668 }
2669 }
2670 }
2671 %}
2673 /*
2674 * 1d4 storeImmN [S0 + #16 (8-bit)], narrowoop: spec/benchmarks/_213_javac/Identifier:exact *
2675 * # compressed ptr ! Field: spec/benchmarks/_213_javac/Identifier.value
2676 * 0x00000055648065d4: daddu at, s0, zero
2677 * 0x00000055648065d8: lui t9, 0x0 ; {oop(a 'spec/benchmarks/_213_javac/Identifier')}
2678 * 0x00000055648065dc: ori t9, t9, 0xfffff610
2679 * 0x00000055648065e0: dsll t9, t9, 16
2680 * 0x00000055648065e4: ori t9, t9, 0xffffc628
2681 * 0x00000055648065e8: sw t9, 0x10(at)
2682 */
2683 enc_class storeImmN_enc (memory mem, immN src) %{
2684 MacroAssembler _masm(&cbuf);
2685 int base = $mem$$base;
2686 int index = $mem$$index;
2687 int scale = $mem$$scale;
2688 int disp = $mem$$disp;
2689 long * value = (long *)$src$$constant;
2691 if (value == NULL) {
2692 guarantee(Assembler::is_simm16(disp), "FIXME: disp is not simm16!");
2693 if (index == 0) {
2694 __ sw(R0, as_Register(base), disp);
2695 } else {
2696 if (scale == 0) {
2697 __ daddu(AT, as_Register(base), as_Register(index));
2698 } else {
2699 __ dsll(AT, as_Register(index), scale);
2700 __ daddu(AT, as_Register(base), AT);
2701 }
2702 __ sw(R0, AT, disp);
2703 }
2705 return;
2706 }
2708 int oop_index = __ oop_recorder()->find_index((jobject)value);
2709 RelocationHolder rspec = oop_Relocation::spec(oop_index);
2711 guarantee(scale == 0, "FIXME: scale is not zero !");
2712 guarantee(value != 0, "FIXME: value is zero !");
2714 if (index != 0) {
2715 if (scale == 0) {
2716 __ daddu(AT, as_Register(base), as_Register(index));
2717 } else {
2718 __ dsll(AT, as_Register(index), scale);
2719 __ daddu(AT, as_Register(base), AT);
2720 }
2721 if( Assembler::is_simm16(disp) ) {
2722 if(rspec.type() != relocInfo::none) {
2723 __ relocate(rspec, Assembler::narrow_oop_operand);
2724 __ li48(T9, oop_index);
2725 } else {
2726 __ set64(T9, oop_index);
2727 }
2728 __ sw(T9, AT, disp);
2729 } else {
2730 __ move(T9, disp);
2731 __ addu(AT, AT, T9);
2733 if(rspec.type() != relocInfo::none) {
2734 __ relocate(rspec, Assembler::narrow_oop_operand);
2735 __ li48(T9, oop_index);
2736 } else {
2737 __ set64(T9, oop_index);
2738 }
2739 __ sw(T9, AT, 0);
2740 }
2741 }
2742 else {
2743 if( Assembler::is_simm16(disp) ) {
2744 if($src->constant_reloc() != relocInfo::none) {
2745 __ relocate(rspec, Assembler::narrow_oop_operand);
2746 __ li48(T9, oop_index);
2747 } else {
2748 __ set64(T9, oop_index);
2749 }
2750 __ sw(T9, as_Register(base), disp);
2751 } else {
2752 __ move(T9, disp);
2753 __ daddu(AT, as_Register(base), T9);
2755 if($src->constant_reloc() != relocInfo::none){
2756 __ relocate(rspec, Assembler::narrow_oop_operand);
2757 __ li48(T9, oop_index);
2758 } else {
2759 __ set64(T9, oop_index);
2760 }
2761 __ sw(T9, AT, 0);
2762 }
2763 }
2764 %}
2766 enc_class storeImmNKlass_enc (memory mem, immNKlass src) %{
2767 MacroAssembler _masm(&cbuf);
2769 assert (UseCompressedOops, "should only be used for compressed headers");
2770 assert (__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
2772 int base = $mem$$base;
2773 int index = $mem$$index;
2774 int scale = $mem$$scale;
2775 int disp = $mem$$disp;
2776 long value = $src$$constant;
2778 int klass_index = __ oop_recorder()->find_index((Klass*)value);
2779 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
2780 long narrowp = Klass::encode_klass((Klass*)value);
2782 if(index!=0){
2783 if (scale == 0) {
2784 __ daddu(AT, as_Register(base), as_Register(index));
2785 } else {
2786 __ dsll(AT, as_Register(index), scale);
2787 __ daddu(AT, as_Register(base), AT);
2788 }
2790 if( Assembler::is_simm16(disp) ) {
2791 if(rspec.type() != relocInfo::none){
2792 __ relocate(rspec, Assembler::narrow_oop_operand);
2793 __ li48(T9, narrowp);
2794 } else {
2795 __ set64(T9, narrowp);
2796 }
2797 __ sw(T9, AT, disp);
2798 } else {
2799 __ move(T9, disp);
2800 __ daddu(AT, AT, T9);
2802 if(rspec.type() != relocInfo::none){
2803 __ relocate(rspec, Assembler::narrow_oop_operand);
2804 __ li48(T9, narrowp);
2805 } else {
2806 __ set64(T9, narrowp);
2807 }
2809 __ sw(T9, AT, 0);
2810 }
2811 } else {
2812 if( Assembler::is_simm16(disp) ) {
2813 if(rspec.type() != relocInfo::none){
2814 __ relocate(rspec, Assembler::narrow_oop_operand);
2815 __ li48(T9, narrowp);
2816 }
2817 else {
2818 __ set64(T9, narrowp);
2819 }
2820 __ sw(T9, as_Register(base), disp);
2821 } else {
2822 __ move(T9, disp);
2823 __ daddu(AT, as_Register(base), T9);
2825 if(rspec.type() != relocInfo::none){
2826 __ relocate(rspec, Assembler::narrow_oop_operand);
2827 __ li48(T9, narrowp);
2828 } else {
2829 __ set64(T9, narrowp);
2830 }
2831 __ sw(T9, AT, 0);
2832 }
2833 }
2834 %}
2836 enc_class storeImmN0_enc(memory mem, ImmN0 src) %{
2837 MacroAssembler _masm(&cbuf);
2838 int base = $mem$$base;
2839 int index = $mem$$index;
2840 int scale = $mem$$scale;
2841 int disp = $mem$$disp;
2843 if(index!=0){
2844 if (scale == 0) {
2845 __ daddu(AT, as_Register(base), as_Register(index));
2846 } else {
2847 __ dsll(AT, as_Register(index), scale);
2848 __ daddu(AT, as_Register(base), AT);
2849 }
2851 if( Assembler::is_simm16(disp) ) {
2852 __ sw(R0, AT, disp);
2853 } else {
2854 __ move(T9, disp);
2855 __ daddu(AT, AT, T9);
2856 __ sw(R0, AT, 0);
2857 }
2858 }
2859 else {
2860 if( Assembler::is_simm16(disp) ) {
2861 __ sw(R0, as_Register(base), disp);
2862 } else {
2863 __ move(T9, disp);
2864 __ daddu(AT, as_Register(base), T9);
2865 __ sw(R0, AT, 0);
2866 }
2867 }
2868 %}
2870 enc_class load_L_enc (mRegL dst, memory mem) %{
2871 MacroAssembler _masm(&cbuf);
2872 int base = $mem$$base;
2873 int index = $mem$$index;
2874 int scale = $mem$$scale;
2875 int disp = $mem$$disp;
2876 Register dst_reg = as_Register($dst$$reg);
2878 /*********************2013/03/27**************************
2879 * Jin: $base may contain a null object.
2880 * Server JIT force the exception_offset to be the pos of
2881 * the first instruction.
2882 * I insert such a 'null_check' at the beginning.
2883 *******************************************************/
2885 __ lw(AT, as_Register(base), 0);
2887 /*********************2012/10/04**************************
2888 * Error case found in SortTest
2889 * 337 b java.util.Arrays::sort1 (401 bytes)
2890 * B73:
2891 * d34 lw T4.lo, [T4 + #16] #@loadL-lo
2892 * lw T4.hi, [T4 + #16]+4 #@loadL-hi
2893 *
2894 * The original instructions generated here are :
2895 * __ lw(dst_lo, as_Register(base), disp);
2896 * __ lw(dst_hi, as_Register(base), disp + 4);
2897 *******************************************************/
2899 if( index != 0 ) {
2900 if (scale == 0) {
2901 __ daddu(AT, as_Register(base), as_Register(index));
2902 } else {
2903 __ dsll(AT, as_Register(index), scale);
2904 __ daddu(AT, as_Register(base), AT);
2905 }
2906 if( Assembler::is_simm16(disp) ) {
2907 __ ld(dst_reg, AT, disp);
2908 } else {
2909 __ move(T9, disp);
2910 __ daddu(AT, AT, T9);
2911 __ ld(dst_reg, AT, 0);
2912 }
2913 } else {
2914 if( Assembler::is_simm16(disp) ) {
2915 __ move(AT, as_Register(base));
2916 __ ld(dst_reg, AT, disp);
2917 } else {
2918 __ move(T9, disp);
2919 __ daddu(AT, as_Register(base), T9);
2920 __ ld(dst_reg, AT, 0);
2921 }
2922 }
2923 %}
2925 enc_class store_L_reg_enc (memory mem, mRegL src) %{
2926 MacroAssembler _masm(&cbuf);
2927 int base = $mem$$base;
2928 int index = $mem$$index;
2929 int scale = $mem$$scale;
2930 int disp = $mem$$disp;
2931 Register src_reg = as_Register($src$$reg);
2933 if( index != 0 ) {
2934 if (scale == 0) {
2935 __ daddu(AT, as_Register(base), as_Register(index));
2936 } else {
2937 __ dsll(AT, as_Register(index), scale);
2938 __ daddu(AT, as_Register(base), AT);
2939 }
2940 if( Assembler::is_simm16(disp) ) {
2941 __ sd(src_reg, AT, disp);
2942 } else {
2943 __ move(T9, disp);
2944 __ daddu(AT, AT, T9);
2945 __ sd(src_reg, AT, 0);
2946 }
2947 } else {
2948 if( Assembler::is_simm16(disp) ) {
2949 __ move(AT, as_Register(base));
2950 __ sd(src_reg, AT, disp);
2951 } else {
2952 __ move(T9, disp);
2953 __ daddu(AT, as_Register(base), T9);
2954 __ sd(src_reg, AT, 0);
2955 }
2956 }
2957 %}
2959 enc_class store_L_immL0_enc (memory mem, immL0 src) %{
2960 MacroAssembler _masm(&cbuf);
2961 int base = $mem$$base;
2962 int index = $mem$$index;
2963 int scale = $mem$$scale;
2964 int disp = $mem$$disp;
2966 if( index != 0 ) {
2967 if (scale == 0) {
2968 __ daddu(AT, as_Register(base), as_Register(index));
2969 } else {
2970 __ dsll(AT, as_Register(index), scale);
2971 __ daddu(AT, as_Register(base), AT);
2972 }
2973 if( Assembler::is_simm16(disp) ) {
2974 __ sd(R0, AT, disp);
2975 } else {
2976 __ move(T9, disp);
2977 __ addu(AT, AT, T9);
2978 __ sd(R0, AT, 0);
2979 }
2980 } else {
2981 if( Assembler::is_simm16(disp) ) {
2982 __ move(AT, as_Register(base));
2983 __ sd(R0, AT, disp);
2984 } else {
2985 __ move(T9, disp);
2986 __ addu(AT, as_Register(base), T9);
2987 __ sd(R0, AT, 0);
2988 }
2989 }
2990 %}
2992 enc_class store_L_immL_enc (memory mem, immL src) %{
2993 MacroAssembler _masm(&cbuf);
2994 int base = $mem$$base;
2995 int index = $mem$$index;
2996 int scale = $mem$$scale;
2997 int disp = $mem$$disp;
2998 long imm = $src$$constant;
3000 if( index != 0 ) {
3001 if (scale == 0) {
3002 __ daddu(AT, as_Register(base), as_Register(index));
3003 } else {
3004 __ dsll(AT, as_Register(index), scale);
3005 __ daddu(AT, as_Register(base), AT);
3006 }
3007 if( Assembler::is_simm16(disp) ) {
3008 __ li(T9, imm);
3009 __ sd(T9, AT, disp);
3010 } else {
3011 __ move(T9, disp);
3012 __ addu(AT, AT, T9);
3013 __ li(T9, imm);
3014 __ sd(T9, AT, 0);
3015 }
3016 } else {
3017 if( Assembler::is_simm16(disp) ) {
3018 __ move(AT, as_Register(base));
3019 __ li(T9, imm);
3020 __ sd(T9, AT, disp);
3021 } else {
3022 __ move(T9, disp);
3023 __ addu(AT, as_Register(base), T9);
3024 __ li(T9, imm);
3025 __ sd(T9, AT, 0);
3026 }
3027 }
3028 %}
3030 enc_class load_F_enc (regF dst, memory mem) %{
3031 MacroAssembler _masm(&cbuf);
3032 int base = $mem$$base;
3033 int index = $mem$$index;
3034 int scale = $mem$$scale;
3035 int disp = $mem$$disp;
3036 FloatRegister dst = $dst$$FloatRegister;
3038 if( index != 0 ) {
3039 if( Assembler::is_simm16(disp) ) {
3040 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
3041 if (scale == 0) {
3042 __ gslwxc1(dst, as_Register(base), as_Register(index), disp);
3043 } else {
3044 __ dsll(AT, as_Register(index), scale);
3045 __ gslwxc1(dst, as_Register(base), AT, disp);
3046 }
3047 } else {
3048 if (scale == 0) {
3049 __ daddu(AT, as_Register(base), as_Register(index));
3050 } else {
3051 __ dsll(AT, as_Register(index), scale);
3052 __ daddu(AT, as_Register(base), AT);
3053 }
3054 __ lwc1(dst, AT, disp);
3055 }
3056 } else {
3057 if (scale == 0) {
3058 __ daddu(AT, as_Register(base), as_Register(index));
3059 } else {
3060 __ dsll(AT, as_Register(index), scale);
3061 __ daddu(AT, as_Register(base), AT);
3062 }
3063 __ move(T9, disp);
3064 if( UseLoongsonISA ) {
3065 __ gslwxc1(dst, AT, T9, 0);
3066 } else {
3067 __ daddu(AT, AT, T9);
3068 __ lwc1(dst, AT, 0);
3069 }
3070 }
3071 } else {
3072 if( Assembler::is_simm16(disp) ) {
3073 __ lwc1(dst, as_Register(base), disp);
3074 } else {
3075 __ move(T9, disp);
3076 if( UseLoongsonISA ) {
3077 __ gslwxc1(dst, as_Register(base), T9, 0);
3078 } else {
3079 __ daddu(AT, as_Register(base), T9);
3080 __ lwc1(dst, AT, 0);
3081 }
3082 }
3083 }
3084 %}
3086 enc_class store_F_reg_enc (memory mem, regF src) %{
3087 MacroAssembler _masm(&cbuf);
3088 int base = $mem$$base;
3089 int index = $mem$$index;
3090 int scale = $mem$$scale;
3091 int disp = $mem$$disp;
3092 FloatRegister src = $src$$FloatRegister;
3094 if( index != 0 ) {
3095 if( Assembler::is_simm16(disp) ) {
3096 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
3097 if (scale == 0) {
3098 __ gsswxc1(src, as_Register(base), as_Register(index), disp);
3099 } else {
3100 __ dsll(AT, as_Register(index), scale);
3101 __ gsswxc1(src, as_Register(base), AT, disp);
3102 }
3103 } else {
3104 if (scale == 0) {
3105 __ daddu(AT, as_Register(base), as_Register(index));
3106 } else {
3107 __ dsll(AT, as_Register(index), scale);
3108 __ daddu(AT, as_Register(base), AT);
3109 }
3110 __ swc1(src, AT, disp);
3111 }
3112 } else {
3113 if (scale == 0) {
3114 __ daddu(AT, as_Register(base), as_Register(index));
3115 } else {
3116 __ dsll(AT, as_Register(index), scale);
3117 __ daddu(AT, as_Register(base), AT);
3118 }
3119 __ move(T9, disp);
3120 if( UseLoongsonISA ) {
3121 __ gsswxc1(src, AT, T9, 0);
3122 } else {
3123 __ daddu(AT, AT, T9);
3124 __ swc1(src, AT, 0);
3125 }
3126 }
3127 } else {
3128 if( Assembler::is_simm16(disp) ) {
3129 __ swc1(src, as_Register(base), disp);
3130 } else {
3131 __ move(T9, disp);
3132 if( UseLoongsonISA ) {
3133 __ gslwxc1(src, as_Register(base), T9, 0);
3134 } else {
3135 __ daddu(AT, as_Register(base), T9);
3136 __ swc1(src, AT, 0);
3137 }
3138 }
3139 }
3140 %}
3142 enc_class load_D_enc (regD dst, memory mem) %{
3143 MacroAssembler _masm(&cbuf);
3144 int base = $mem$$base;
3145 int index = $mem$$index;
3146 int scale = $mem$$scale;
3147 int disp = $mem$$disp;
3148 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
3150 if( index != 0 ) {
3151 if( Assembler::is_simm16(disp) ) {
3152 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
3153 if (scale == 0) {
3154 __ gsldxc1(dst_reg, as_Register(base), as_Register(index), disp);
3155 } else {
3156 __ dsll(AT, as_Register(index), scale);
3157 __ gsldxc1(dst_reg, as_Register(base), AT, disp);
3158 }
3159 } else {
3160 if (scale == 0) {
3161 __ daddu(AT, as_Register(base), as_Register(index));
3162 } else {
3163 __ dsll(AT, as_Register(index), scale);
3164 __ daddu(AT, as_Register(base), AT);
3165 }
3166 __ ldc1(dst_reg, AT, disp);
3167 }
3168 } else {
3169 if (scale == 0) {
3170 __ daddu(AT, as_Register(base), as_Register(index));
3171 } else {
3172 __ dsll(AT, as_Register(index), scale);
3173 __ daddu(AT, as_Register(base), AT);
3174 }
3175 __ move(T9, disp);
3176 if( UseLoongsonISA ) {
3177 __ gsldxc1(dst_reg, AT, T9, 0);
3178 } else {
3179 __ addu(AT, AT, T9);
3180 __ ldc1(dst_reg, AT, 0);
3181 }
3182 }
3183 } else {
3184 if( Assembler::is_simm16(disp) ) {
3185 __ ldc1(dst_reg, as_Register(base), disp);
3186 } else {
3187 __ move(T9, disp);
3188 if( UseLoongsonISA ) {
3189 __ gsldxc1(dst_reg, as_Register(base), T9, 0);
3190 } else {
3191 __ addu(AT, as_Register(base), T9);
3192 __ ldc1(dst_reg, AT, 0);
3193 }
3194 }
3195 }
3196 %}
3198 enc_class store_D_reg_enc (memory mem, regD src) %{
3199 MacroAssembler _masm(&cbuf);
3200 int base = $mem$$base;
3201 int index = $mem$$index;
3202 int scale = $mem$$scale;
3203 int disp = $mem$$disp;
3204 FloatRegister src_reg = as_FloatRegister($src$$reg);
3206 if( index != 0 ) {
3207 if( Assembler::is_simm16(disp) ) {
3208 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
3209 if (scale == 0) {
3210 __ gssdxc1(src_reg, as_Register(base), as_Register(index), disp);
3211 } else {
3212 __ dsll(AT, as_Register(index), scale);
3213 __ gssdxc1(src_reg, as_Register(base), AT, disp);
3214 }
3215 } else {
3216 if (scale == 0) {
3217 __ daddu(AT, as_Register(base), as_Register(index));
3218 } else {
3219 __ dsll(AT, as_Register(index), scale);
3220 __ daddu(AT, as_Register(base), AT);
3221 }
3222 __ sdc1(src_reg, AT, disp);
3223 }
3224 } else {
3225 if (scale == 0) {
3226 __ daddu(AT, as_Register(base), as_Register(index));
3227 } else {
3228 __ dsll(AT, as_Register(index), scale);
3229 __ daddu(AT, as_Register(base), AT);
3230 }
3231 __ move(T9, disp);
3232 if( UseLoongsonISA ) {
3233 __ gssdxc1(src_reg, AT, T9, 0);
3234 } else {
3235 __ addu(AT, AT, T9);
3236 __ sdc1(src_reg, AT, 0);
3237 }
3238 }
3239 } else {
3240 if( Assembler::is_simm16(disp) ) {
3241 __ sdc1(src_reg, as_Register(base), disp);
3242 } else {
3243 __ move(T9, disp);
3244 if( UseLoongsonISA ) {
3245 __ gssdxc1(src_reg, as_Register(base), T9, 0);
3246 } else {
3247 __ addu(AT, as_Register(base), T9);
3248 __ sdc1(src_reg, AT, 0);
3249 }
3250 }
3251 }
3252 %}
3254 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
3255 MacroAssembler _masm(&cbuf);
3256 // This is the instruction starting address for relocation info.
3257 __ block_comment("Java_To_Runtime");
3258 cbuf.set_insts_mark();
3259 __ relocate(relocInfo::runtime_call_type);
3261 __ li48(T9, (long)$meth$$method);
3262 __ jalr(T9);
3263 __ nop();
3264 %}
3266 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
3267 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
3268 // who we intended to call.
3269 MacroAssembler _masm(&cbuf);
3270 cbuf.set_insts_mark();
3272 if ( !_method ) {
3273 __ relocate(relocInfo::runtime_call_type);
3274 //emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
3275 // runtime_call_Relocation::spec(), RELOC_IMM32 );
3276 } else if(_optimized_virtual) {
3277 __ relocate(relocInfo::opt_virtual_call_type);
3278 //emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
3279 // opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
3280 } else {
3281 __ relocate(relocInfo::static_call_type);
3282 //emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
3283 // static_call_Relocation::spec(), RELOC_IMM32 );
3284 }
3286 __ li(T9, $meth$$method);
3287 __ jalr(T9);
3288 __ nop();
3289 if( _method ) { // Emit stub for static call
3290 emit_java_to_interp(cbuf);
3291 }
3292 %}
3295 /*
3296 * [Ref: LIR_Assembler::ic_call() ]
3297 */
3298 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
3299 MacroAssembler _masm(&cbuf);
3300 __ block_comment("Java_Dynamic_Call");
3301 __ ic_call((address)$meth$$method);
3302 %}
3305 enc_class Set_Flags_After_Fast_Lock_Unlock(FlagsReg cr) %{
3306 Register flags = $cr$$Register;
3307 Label L;
3309 MacroAssembler _masm(&cbuf);
3311 __ addu(flags, R0, R0);
3312 __ beq(AT, R0, L);
3313 __ delayed()->nop();
3314 __ move(flags, 0xFFFFFFFF);
3315 __ bind(L);
3316 %}
3318 enc_class enc_PartialSubtypeCheck(mRegP result, mRegP sub, mRegP super, mRegI tmp) %{
3319 Register result = $result$$Register;
3320 Register sub = $sub$$Register;
3321 Register super = $super$$Register;
3322 Register length = $tmp$$Register;
3323 Register tmp = T9;
3324 Label miss;
3326 /* 2012/9/28 Jin: result may be the same as sub
3327 * 47c B40: # B21 B41 <- B20 Freq: 0.155379
3328 * 47c partialSubtypeCheck result=S1, sub=S1, super=S3, length=S0
3329 * 4bc mov S2, NULL #@loadConP
3330 * 4c0 beq S1, S2, B21 #@branchConP P=0.999999 C=-1.000000
3331 */
3332 MacroAssembler _masm(&cbuf);
3333 Label done;
3334 __ check_klass_subtype_slow_path(sub, super, length, tmp,
3335 NULL, &miss,
3336 /*set_cond_codes:*/ true);
3337 /* 2013/7/22 Jin: Refer to X86_64's RDI */
3338 __ move(result, 0);
3339 __ b(done);
3340 __ nop();
3342 __ bind(miss);
3343 __ move(result, 1);
3344 __ bind(done);
3345 %}
3347 %}
3350 //---------MIPS FRAME--------------------------------------------------------------
3351 // Definition of frame structure and management information.
3352 //
3353 // S T A C K L A Y O U T Allocators stack-slot number
3354 // | (to get allocators register number
3355 // G Owned by | | v add SharedInfo::stack0)
3356 // r CALLER | |
3357 // o | +--------+ pad to even-align allocators stack-slot
3358 // w V | pad0 | numbers; owned by CALLER
3359 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3360 // h ^ | in | 5
3361 // | | args | 4 Holes in incoming args owned by SELF
3362 // | | old | | 3
3363 // | | SP-+--------+----> Matcher::_old_SP, even aligned
3364 // v | | ret | 3 return address
3365 // Owned by +--------+
3366 // Self | pad2 | 2 pad to align old SP
3367 // | +--------+ 1
3368 // | | locks | 0
3369 // | +--------+----> SharedInfo::stack0, even aligned
3370 // | | pad1 | 11 pad to align new SP
3371 // | +--------+
3372 // | | | 10
3373 // | | spills | 9 spills
3374 // V | | 8 (pad0 slot for callee)
3375 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3376 // ^ | out | 7
3377 // | | args | 6 Holes in outgoing args owned by CALLEE
3378 // Owned by new | |
3379 // Callee SP-+--------+----> Matcher::_new_SP, even aligned
3380 // | |
3381 //
3382 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3383 // known from SELF's arguments and the Java calling convention.
3384 // Region 6-7 is determined per call site.
3385 // Note 2: If the calling convention leaves holes in the incoming argument
3386 // area, those holes are owned by SELF. Holes in the outgoing area
3387 // are owned by the CALLEE. Holes should not be nessecary in the
3388 // incoming area, as the Java calling convention is completely under
3389 // the control of the AD file. Doubles can be sorted and packed to
3390 // avoid holes. Holes in the outgoing arguments may be nessecary for
3391 // varargs C calling conventions.
3392 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3393 // even aligned with pad0 as needed.
3394 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3395 // region 6-11 is even aligned; it may be padded out more so that
3396 // the region from SP to FP meets the minimum stack alignment.
3397 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
3398 // alignment. Region 11, pad1, may be dynamically extended so that
3399 // SP meets the minimum alignment.
3402 frame %{
3404 stack_direction(TOWARDS_LOW);
3406 // These two registers define part of the calling convention
3407 // between compiled code and the interpreter.
3408 // SEE StartI2CNode::calling_convention & StartC2INode::calling_convention & StartOSRNode::calling_convention
3409 // for more information. by yjl 3/16/2006
3411 inline_cache_reg(T1); // Inline Cache Register
3412 interpreter_method_oop_reg(S3); // Method Oop Register when calling interpreter
3413 /*
3414 inline_cache_reg(T1); // Inline Cache Register or methodOop for I2C
3415 interpreter_arg_ptr_reg(A0); // Argument pointer for I2C adapters
3416 */
3418 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3419 cisc_spilling_operand_name(indOffset32);
3421 // Number of stack slots consumed by locking an object
3422 // generate Compile::sync_stack_slots
3423 #ifdef _LP64
3424 sync_stack_slots(2);
3425 #else
3426 sync_stack_slots(1);
3427 #endif
3429 frame_pointer(SP);
3431 // Interpreter stores its frame pointer in a register which is
3432 // stored to the stack by I2CAdaptors.
3433 // I2CAdaptors convert from interpreted java to compiled java.
3435 interpreter_frame_pointer(FP);
3437 // generate Matcher::stack_alignment
3438 stack_alignment(StackAlignmentInBytes); //wordSize = sizeof(char*);
3440 // Number of stack slots between incoming argument block and the start of
3441 // a new frame. The PROLOG must add this many slots to the stack. The
3442 // EPILOG must remove this many slots. Intel needs one slot for
3443 // return address.
3444 // generate Matcher::in_preserve_stack_slots
3445 //in_preserve_stack_slots(VerifyStackAtCalls + 2); //Now VerifyStackAtCalls is defined as false ! Leave one stack slot for ra and fp
3446 in_preserve_stack_slots(4); //Now VerifyStackAtCalls is defined as false ! Leave two stack slots for ra and fp
3448 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3449 // for calls to C. Supports the var-args backing area for register parms.
3450 varargs_C_out_slots_killed(0);
3452 // The after-PROLOG location of the return address. Location of
3453 // return address specifies a type (REG or STACK) and a number
3454 // representing the register number (i.e. - use a register name) or
3455 // stack slot.
3456 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3457 // Otherwise, it is above the locks and verification slot and alignment word
3458 //return_addr(STACK -1+ round_to(1+VerifyStackAtCalls+Compile::current()->sync()*Compile::current()->sync_stack_slots(),WordsPerLong));
3459 return_addr(REG RA);
3461 // Body of function which returns an integer array locating
3462 // arguments either in registers or in stack slots. Passed an array
3463 // of ideal registers called "sig" and a "length" count. Stack-slot
3464 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3465 // arguments for a CALLEE. Incoming stack arguments are
3466 // automatically biased by the preserve_stack_slots field above.
3469 // will generated to Matcher::calling_convention(OptoRegPair *sig, uint length, bool is_outgoing)
3470 // StartNode::calling_convention call this. by yjl 3/16/2006
3471 calling_convention %{
3472 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3473 %}
3478 // Body of function which returns an integer array locating
3479 // arguments either in registers or in stack slots. Passed an array
3480 // of ideal registers called "sig" and a "length" count. Stack-slot
3481 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3482 // arguments for a CALLEE. Incoming stack arguments are
3483 // automatically biased by the preserve_stack_slots field above.
3486 // SEE CallRuntimeNode::calling_convention for more information. by yjl 3/16/2006
3487 c_calling_convention %{
3488 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3489 %}
3492 // Location of C & interpreter return values
3493 // register(s) contain(s) return value for Op_StartI2C and Op_StartOSR.
3494 // SEE Matcher::match. by yjl 3/16/2006
3495 c_return_value %{
3496 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3497 /* -- , -- , Op_RegN, Op_RegI, Op_RegP, Op_RegF, Op_RegD, Op_RegL */
3498 static int lo[Op_RegL+1] = { 0, 0, V0_num, V0_num, V0_num, F0_num, F0_num, V0_num };
3499 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, V0_H_num, OptoReg::Bad, F0_H_num, V0_H_num };
3500 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3501 %}
3503 // Location of return values
3504 // register(s) contain(s) return value for Op_StartC2I and Op_Start.
3505 // SEE Matcher::match. by yjl 3/16/2006
3507 return_value %{
3508 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3509 /* -- , -- , Op_RegN, Op_RegI, Op_RegP, Op_RegF, Op_RegD, Op_RegL */
3510 static int lo[Op_RegL+1] = { 0, 0, V0_num, V0_num, V0_num, F0_num, F0_num, V0_num };
3511 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, V0_H_num, OptoReg::Bad, F0_H_num, V0_H_num};
3512 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3513 %}
3515 %}
3517 //----------ATTRIBUTES---------------------------------------------------------
3518 //----------Operand Attributes-------------------------------------------------
3519 op_attrib op_cost(0); // Required cost attribute
3521 //----------Instruction Attributes---------------------------------------------
3522 ins_attrib ins_cost(100); // Required cost attribute
3523 ins_attrib ins_size(32); // Required size attribute (in bits)
3524 ins_attrib ins_pc_relative(0); // Required PC Relative flag
3525 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3526 // non-matching short branch variant of some
3527 // long branch?
3528 ins_attrib ins_alignment(4); // Required alignment attribute (must be a power of 2)
3529 // specifies the alignment that some part of the instruction (not
3530 // necessarily the start) requires. If > 1, a compute_padding()
3531 // function must be provided for the instruction
3533 //----------OPERANDS-----------------------------------------------------------
3534 // Operand definitions must precede instruction definitions for correct parsing
3535 // in the ADLC because operands constitute user defined types which are used in
3536 // instruction definitions.
3538 // Vectors
3539 operand vecD() %{
3540 constraint(ALLOC_IN_RC(dbl_reg));
3541 match(VecD);
3543 format %{ %}
3544 interface(REG_INTER);
3545 %}
3547 // Flags register, used as output of compare instructions
3548 operand FlagsReg() %{
3549 constraint(ALLOC_IN_RC(mips_flags));
3550 match(RegFlags);
3552 format %{ "EFLAGS" %}
3553 interface(REG_INTER);
3554 %}
3556 //----------Simple Operands----------------------------------------------------
3557 //TODO: Should we need to define some more special immediate number ?
3558 // Immediate Operands
3559 // Integer Immediate
3560 operand immI() %{
3561 match(ConI);
3562 //TODO: should not match immI8 here LEE
3563 match(immI8);
3565 op_cost(20);
3566 format %{ %}
3567 interface(CONST_INTER);
3568 %}
3570 // Long Immediate 8-bit
3571 operand immL8()
3572 %{
3573 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3574 match(ConL);
3576 op_cost(5);
3577 format %{ %}
3578 interface(CONST_INTER);
3579 %}
3581 // Constant for test vs zero
3582 operand immI0() %{
3583 predicate(n->get_int() == 0);
3584 match(ConI);
3586 op_cost(0);
3587 format %{ %}
3588 interface(CONST_INTER);
3589 %}
3591 // Constant for increment
3592 operand immI1() %{
3593 predicate(n->get_int() == 1);
3594 match(ConI);
3596 op_cost(0);
3597 format %{ %}
3598 interface(CONST_INTER);
3599 %}
3601 // Constant for decrement
3602 operand immI_M1() %{
3603 predicate(n->get_int() == -1);
3604 match(ConI);
3606 op_cost(0);
3607 format %{ %}
3608 interface(CONST_INTER);
3609 %}
3611 // Valid scale values for addressing modes
3612 operand immI2() %{
3613 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3614 match(ConI);
3616 format %{ %}
3617 interface(CONST_INTER);
3618 %}
3620 operand immI8() %{
3621 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3622 match(ConI);
3624 op_cost(5);
3625 format %{ %}
3626 interface(CONST_INTER);
3627 %}
3629 operand immI16() %{
3630 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3631 match(ConI);
3633 op_cost(10);
3634 format %{ %}
3635 interface(CONST_INTER);
3636 %}
3638 // Constant for long shifts
3639 operand immI_32() %{
3640 predicate( n->get_int() == 32 );
3641 match(ConI);
3643 op_cost(0);
3644 format %{ %}
3645 interface(CONST_INTER);
3646 %}
3648 operand immI_63() %{
3649 predicate( n->get_int() == 63 );
3650 match(ConI);
3652 op_cost(0);
3653 format %{ %}
3654 interface(CONST_INTER);
3655 %}
3657 operand immI_0_31() %{
3658 predicate( n->get_int() >= 0 && n->get_int() <= 31 );
3659 match(ConI);
3661 op_cost(0);
3662 format %{ %}
3663 interface(CONST_INTER);
3664 %}
3666 // Operand for non-negtive integer mask
3667 operand immI_nonneg_mask() %{
3668 predicate( (n->get_int() >= 0) && (Assembler::is_int_mask(n->get_int()) != -1) );
3669 match(ConI);
3671 op_cost(0);
3672 format %{ %}
3673 interface(CONST_INTER);
3674 %}
3676 operand immI_32_63() %{
3677 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3678 match(ConI);
3679 op_cost(0);
3681 format %{ %}
3682 interface(CONST_INTER);
3683 %}
3685 operand immI16_sub() %{
3686 predicate((-32767 <= n->get_int()) && (n->get_int() <= 32768));
3687 match(ConI);
3689 op_cost(10);
3690 format %{ %}
3691 interface(CONST_INTER);
3692 %}
3694 operand immI_0_32767() %{
3695 predicate( n->get_int() >= 0 && n->get_int() <= 32767 );
3696 match(ConI);
3697 op_cost(0);
3699 format %{ %}
3700 interface(CONST_INTER);
3701 %}
3703 operand immI_0_65535() %{
3704 predicate( n->get_int() >= 0 && n->get_int() <= 65535 );
3705 match(ConI);
3706 op_cost(0);
3708 format %{ %}
3709 interface(CONST_INTER);
3710 %}
3712 operand immI_1() %{
3713 predicate( n->get_int() == 1 );
3714 match(ConI);
3716 op_cost(0);
3717 format %{ %}
3718 interface(CONST_INTER);
3719 %}
3721 operand immI_2() %{
3722 predicate( n->get_int() == 2 );
3723 match(ConI);
3725 op_cost(0);
3726 format %{ %}
3727 interface(CONST_INTER);
3728 %}
3730 operand immI_3() %{
3731 predicate( n->get_int() == 3 );
3732 match(ConI);
3734 op_cost(0);
3735 format %{ %}
3736 interface(CONST_INTER);
3737 %}
3739 operand immI_7() %{
3740 predicate( n->get_int() == 7 );
3741 match(ConI);
3743 format %{ %}
3744 interface(CONST_INTER);
3745 %}
3747 // Immediates for special shifts (sign extend)
3749 // Constants for increment
3750 operand immI_16() %{
3751 predicate( n->get_int() == 16 );
3752 match(ConI);
3754 format %{ %}
3755 interface(CONST_INTER);
3756 %}
3758 operand immI_24() %{
3759 predicate( n->get_int() == 24 );
3760 match(ConI);
3762 format %{ %}
3763 interface(CONST_INTER);
3764 %}
3766 // Constant for byte-wide masking
3767 operand immI_255() %{
3768 predicate( n->get_int() == 255 );
3769 match(ConI);
3771 op_cost(0);
3772 format %{ %}
3773 interface(CONST_INTER);
3774 %}
3776 operand immI_65535() %{
3777 predicate( n->get_int() == 65535 );
3778 match(ConI);
3780 op_cost(5);
3781 format %{ %}
3782 interface(CONST_INTER);
3783 %}
3785 operand immI_65536() %{
3786 predicate( n->get_int() == 65536 );
3787 match(ConI);
3789 op_cost(5);
3790 format %{ %}
3791 interface(CONST_INTER);
3792 %}
3794 operand immI_M65536() %{
3795 predicate( n->get_int() == -65536 );
3796 match(ConI);
3798 op_cost(5);
3799 format %{ %}
3800 interface(CONST_INTER);
3801 %}
3803 // Pointer Immediate
3804 operand immP() %{
3805 match(ConP);
3807 op_cost(10);
3808 format %{ %}
3809 interface(CONST_INTER);
3810 %}
3812 operand immP31()
3813 %{
3814 predicate(n->as_Type()->type()->reloc() == relocInfo::none
3815 && (n->get_ptr() >> 31) == 0);
3816 match(ConP);
3818 op_cost(5);
3819 format %{ %}
3820 interface(CONST_INTER);
3821 %}
3823 // NULL Pointer Immediate
3824 operand immP0() %{
3825 predicate( n->get_ptr() == 0 );
3826 match(ConP);
3827 op_cost(0);
3829 format %{ %}
3830 interface(CONST_INTER);
3831 %}
3833 // Pointer Immediate: 64-bit
3834 operand immP_set() %{
3835 match(ConP);
3837 op_cost(5);
3838 // formats are generated automatically for constants and base registers
3839 format %{ %}
3840 interface(CONST_INTER);
3841 %}
3843 // Pointer Immediate: 64-bit
3844 operand immP_load() %{
3845 predicate(n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set64(n->get_ptr()) > 3));
3846 match(ConP);
3848 op_cost(5);
3849 // formats are generated automatically for constants and base registers
3850 format %{ %}
3851 interface(CONST_INTER);
3852 %}
3854 // Pointer Immediate: 64-bit
3855 operand immP_no_oop_cheap() %{
3856 predicate(!n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set64(n->get_ptr()) <= 3));
3857 match(ConP);
3859 op_cost(5);
3860 // formats are generated automatically for constants and base registers
3861 format %{ %}
3862 interface(CONST_INTER);
3863 %}
3865 // Pointer for polling page
3866 operand immP_poll() %{
3867 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3868 match(ConP);
3869 op_cost(5);
3871 format %{ %}
3872 interface(CONST_INTER);
3873 %}
3875 // Pointer Immediate
3876 operand immN() %{
3877 match(ConN);
3879 op_cost(10);
3880 format %{ %}
3881 interface(CONST_INTER);
3882 %}
3884 operand immNKlass() %{
3885 match(ConNKlass);
3887 op_cost(10);
3888 format %{ %}
3889 interface(CONST_INTER);
3890 %}
3892 // NULL Pointer Immediate
3893 operand immN0() %{
3894 predicate(n->get_narrowcon() == 0);
3895 match(ConN);
3897 op_cost(5);
3898 format %{ %}
3899 interface(CONST_INTER);
3900 %}
3902 // Long Immediate
3903 operand immL() %{
3904 match(ConL);
3906 op_cost(20);
3907 format %{ %}
3908 interface(CONST_INTER);
3909 %}
3911 // Long Immediate zero
3912 operand immL0() %{
3913 predicate( n->get_long() == 0L );
3914 match(ConL);
3915 op_cost(0);
3917 format %{ %}
3918 interface(CONST_INTER);
3919 %}
3921 operand immL7() %{
3922 predicate( n->get_long() == 7L );
3923 match(ConL);
3924 op_cost(0);
3926 format %{ %}
3927 interface(CONST_INTER);
3928 %}
3930 operand immL_M1() %{
3931 predicate( n->get_long() == -1L );
3932 match(ConL);
3933 op_cost(0);
3935 format %{ %}
3936 interface(CONST_INTER);
3937 %}
3939 // bit 0..2 zero
3940 operand immL_M8() %{
3941 predicate( n->get_long() == -8L );
3942 match(ConL);
3943 op_cost(0);
3945 format %{ %}
3946 interface(CONST_INTER);
3947 %}
3949 // bit 2 zero
3950 operand immL_M5() %{
3951 predicate( n->get_long() == -5L );
3952 match(ConL);
3953 op_cost(0);
3955 format %{ %}
3956 interface(CONST_INTER);
3957 %}
3959 // bit 1..2 zero
3960 operand immL_M7() %{
3961 predicate( n->get_long() == -7L );
3962 match(ConL);
3963 op_cost(0);
3965 format %{ %}
3966 interface(CONST_INTER);
3967 %}
3969 // bit 0..1 zero
3970 operand immL_M4() %{
3971 predicate( n->get_long() == -4L );
3972 match(ConL);
3973 op_cost(0);
3975 format %{ %}
3976 interface(CONST_INTER);
3977 %}
3979 // bit 3..6 zero
3980 operand immL_M121() %{
3981 predicate( n->get_long() == -121L );
3982 match(ConL);
3983 op_cost(0);
3985 format %{ %}
3986 interface(CONST_INTER);
3987 %}
3989 // Long immediate from 0 to 127.
3990 // Used for a shorter form of long mul by 10.
3991 operand immL_127() %{
3992 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
3993 match(ConL);
3994 op_cost(0);
3996 format %{ %}
3997 interface(CONST_INTER);
3998 %}
4000 // Operand for non-negtive long mask
4001 operand immL_nonneg_mask() %{
4002 predicate( (n->get_long() >= 0) && (Assembler::is_jlong_mask(n->get_long()) != -1) );
4003 match(ConL);
4005 op_cost(0);
4006 format %{ %}
4007 interface(CONST_INTER);
4008 %}
4010 operand immL_0_65535() %{
4011 predicate( n->get_long() >= 0 && n->get_long() <= 65535 );
4012 match(ConL);
4013 op_cost(0);
4015 format %{ %}
4016 interface(CONST_INTER);
4017 %}
4019 // Long Immediate: cheap (materialize in <= 3 instructions)
4020 operand immL_cheap() %{
4021 predicate(MacroAssembler::insts_for_set64(n->get_long()) <= 3);
4022 match(ConL);
4023 op_cost(0);
4025 format %{ %}
4026 interface(CONST_INTER);
4027 %}
4029 // Long Immediate: expensive (materialize in > 3 instructions)
4030 operand immL_expensive() %{
4031 predicate(MacroAssembler::insts_for_set64(n->get_long()) > 3);
4032 match(ConL);
4033 op_cost(0);
4035 format %{ %}
4036 interface(CONST_INTER);
4037 %}
4039 operand immL16() %{
4040 predicate((-32768 <= n->get_long()) && (n->get_long() <= 32767));
4041 match(ConL);
4043 op_cost(10);
4044 format %{ %}
4045 interface(CONST_INTER);
4046 %}
4048 operand immL16_sub() %{
4049 predicate((-32767 <= n->get_long()) && (n->get_long() <= 32768));
4050 match(ConL);
4052 op_cost(10);
4053 format %{ %}
4054 interface(CONST_INTER);
4055 %}
4057 // Long Immediate: low 32-bit mask
4058 operand immL_32bits() %{
4059 predicate(n->get_long() == 0xFFFFFFFFL);
4060 match(ConL);
4061 op_cost(20);
4063 format %{ %}
4064 interface(CONST_INTER);
4065 %}
4067 // Long Immediate 32-bit signed
4068 operand immL32()
4069 %{
4070 predicate(n->get_long() == (int) (n->get_long()));
4071 match(ConL);
4073 op_cost(15);
4074 format %{ %}
4075 interface(CONST_INTER);
4076 %}
4079 //single-precision floating-point zero
4080 operand immF0() %{
4081 predicate(jint_cast(n->getf()) == 0);
4082 match(ConF);
4084 op_cost(5);
4085 format %{ %}
4086 interface(CONST_INTER);
4087 %}
4089 //single-precision floating-point immediate
4090 operand immF() %{
4091 match(ConF);
4093 op_cost(20);
4094 format %{ %}
4095 interface(CONST_INTER);
4096 %}
4098 //double-precision floating-point zero
4099 operand immD0() %{
4100 predicate(jlong_cast(n->getd()) == 0);
4101 match(ConD);
4103 op_cost(5);
4104 format %{ %}
4105 interface(CONST_INTER);
4106 %}
4108 //double-precision floating-point immediate
4109 operand immD() %{
4110 match(ConD);
4112 op_cost(20);
4113 format %{ %}
4114 interface(CONST_INTER);
4115 %}
4117 // Register Operands
4118 // Integer Register
4119 operand mRegI() %{
4120 constraint(ALLOC_IN_RC(int_reg));
4121 match(RegI);
4123 format %{ %}
4124 interface(REG_INTER);
4125 %}
4127 operand no_Ax_mRegI() %{
4128 constraint(ALLOC_IN_RC(no_Ax_int_reg));
4129 match(RegI);
4130 match(mRegI);
4132 format %{ %}
4133 interface(REG_INTER);
4134 %}
4136 operand mS0RegI() %{
4137 constraint(ALLOC_IN_RC(s0_reg));
4138 match(RegI);
4139 match(mRegI);
4141 format %{ "S0" %}
4142 interface(REG_INTER);
4143 %}
4145 operand mS1RegI() %{
4146 constraint(ALLOC_IN_RC(s1_reg));
4147 match(RegI);
4148 match(mRegI);
4150 format %{ "S1" %}
4151 interface(REG_INTER);
4152 %}
4154 operand mS2RegI() %{
4155 constraint(ALLOC_IN_RC(s2_reg));
4156 match(RegI);
4157 match(mRegI);
4159 format %{ "S2" %}
4160 interface(REG_INTER);
4161 %}
4163 operand mS3RegI() %{
4164 constraint(ALLOC_IN_RC(s3_reg));
4165 match(RegI);
4166 match(mRegI);
4168 format %{ "S3" %}
4169 interface(REG_INTER);
4170 %}
4172 operand mS4RegI() %{
4173 constraint(ALLOC_IN_RC(s4_reg));
4174 match(RegI);
4175 match(mRegI);
4177 format %{ "S4" %}
4178 interface(REG_INTER);
4179 %}
4181 operand mS5RegI() %{
4182 constraint(ALLOC_IN_RC(s5_reg));
4183 match(RegI);
4184 match(mRegI);
4186 format %{ "S5" %}
4187 interface(REG_INTER);
4188 %}
4190 operand mS6RegI() %{
4191 constraint(ALLOC_IN_RC(s6_reg));
4192 match(RegI);
4193 match(mRegI);
4195 format %{ "S6" %}
4196 interface(REG_INTER);
4197 %}
4199 operand mS7RegI() %{
4200 constraint(ALLOC_IN_RC(s7_reg));
4201 match(RegI);
4202 match(mRegI);
4204 format %{ "S7" %}
4205 interface(REG_INTER);
4206 %}
4209 operand mT0RegI() %{
4210 constraint(ALLOC_IN_RC(t0_reg));
4211 match(RegI);
4212 match(mRegI);
4214 format %{ "T0" %}
4215 interface(REG_INTER);
4216 %}
4218 operand mT1RegI() %{
4219 constraint(ALLOC_IN_RC(t1_reg));
4220 match(RegI);
4221 match(mRegI);
4223 format %{ "T1" %}
4224 interface(REG_INTER);
4225 %}
4227 operand mT2RegI() %{
4228 constraint(ALLOC_IN_RC(t2_reg));
4229 match(RegI);
4230 match(mRegI);
4232 format %{ "T2" %}
4233 interface(REG_INTER);
4234 %}
4236 operand mT3RegI() %{
4237 constraint(ALLOC_IN_RC(t3_reg));
4238 match(RegI);
4239 match(mRegI);
4241 format %{ "T3" %}
4242 interface(REG_INTER);
4243 %}
4245 operand mT8RegI() %{
4246 constraint(ALLOC_IN_RC(t8_reg));
4247 match(RegI);
4248 match(mRegI);
4250 format %{ "T8" %}
4251 interface(REG_INTER);
4252 %}
4254 operand mT9RegI() %{
4255 constraint(ALLOC_IN_RC(t9_reg));
4256 match(RegI);
4257 match(mRegI);
4259 format %{ "T9" %}
4260 interface(REG_INTER);
4261 %}
4263 operand mA0RegI() %{
4264 constraint(ALLOC_IN_RC(a0_reg));
4265 match(RegI);
4266 match(mRegI);
4268 format %{ "A0" %}
4269 interface(REG_INTER);
4270 %}
4272 operand mA1RegI() %{
4273 constraint(ALLOC_IN_RC(a1_reg));
4274 match(RegI);
4275 match(mRegI);
4277 format %{ "A1" %}
4278 interface(REG_INTER);
4279 %}
4281 operand mA2RegI() %{
4282 constraint(ALLOC_IN_RC(a2_reg));
4283 match(RegI);
4284 match(mRegI);
4286 format %{ "A2" %}
4287 interface(REG_INTER);
4288 %}
4290 operand mA3RegI() %{
4291 constraint(ALLOC_IN_RC(a3_reg));
4292 match(RegI);
4293 match(mRegI);
4295 format %{ "A3" %}
4296 interface(REG_INTER);
4297 %}
4299 operand mA4RegI() %{
4300 constraint(ALLOC_IN_RC(a4_reg));
4301 match(RegI);
4302 match(mRegI);
4304 format %{ "A4" %}
4305 interface(REG_INTER);
4306 %}
4308 operand mA5RegI() %{
4309 constraint(ALLOC_IN_RC(a5_reg));
4310 match(RegI);
4311 match(mRegI);
4313 format %{ "A5" %}
4314 interface(REG_INTER);
4315 %}
4317 operand mA6RegI() %{
4318 constraint(ALLOC_IN_RC(a6_reg));
4319 match(RegI);
4320 match(mRegI);
4322 format %{ "A6" %}
4323 interface(REG_INTER);
4324 %}
4326 operand mA7RegI() %{
4327 constraint(ALLOC_IN_RC(a7_reg));
4328 match(RegI);
4329 match(mRegI);
4331 format %{ "A7" %}
4332 interface(REG_INTER);
4333 %}
4335 operand mV0RegI() %{
4336 constraint(ALLOC_IN_RC(v0_reg));
4337 match(RegI);
4338 match(mRegI);
4340 format %{ "V0" %}
4341 interface(REG_INTER);
4342 %}
4344 operand mV1RegI() %{
4345 constraint(ALLOC_IN_RC(v1_reg));
4346 match(RegI);
4347 match(mRegI);
4349 format %{ "V1" %}
4350 interface(REG_INTER);
4351 %}
4353 operand mRegN() %{
4354 constraint(ALLOC_IN_RC(int_reg));
4355 match(RegN);
4357 format %{ %}
4358 interface(REG_INTER);
4359 %}
4361 operand t0_RegN() %{
4362 constraint(ALLOC_IN_RC(t0_reg));
4363 match(RegN);
4364 match(mRegN);
4366 format %{ %}
4367 interface(REG_INTER);
4368 %}
4370 operand t1_RegN() %{
4371 constraint(ALLOC_IN_RC(t1_reg));
4372 match(RegN);
4373 match(mRegN);
4375 format %{ %}
4376 interface(REG_INTER);
4377 %}
4379 operand t2_RegN() %{
4380 constraint(ALLOC_IN_RC(t2_reg));
4381 match(RegN);
4382 match(mRegN);
4384 format %{ %}
4385 interface(REG_INTER);
4386 %}
4388 operand t3_RegN() %{
4389 constraint(ALLOC_IN_RC(t3_reg));
4390 match(RegN);
4391 match(mRegN);
4393 format %{ %}
4394 interface(REG_INTER);
4395 %}
4397 operand t8_RegN() %{
4398 constraint(ALLOC_IN_RC(t8_reg));
4399 match(RegN);
4400 match(mRegN);
4402 format %{ %}
4403 interface(REG_INTER);
4404 %}
4406 operand t9_RegN() %{
4407 constraint(ALLOC_IN_RC(t9_reg));
4408 match(RegN);
4409 match(mRegN);
4411 format %{ %}
4412 interface(REG_INTER);
4413 %}
4415 operand a0_RegN() %{
4416 constraint(ALLOC_IN_RC(a0_reg));
4417 match(RegN);
4418 match(mRegN);
4420 format %{ %}
4421 interface(REG_INTER);
4422 %}
4424 operand a1_RegN() %{
4425 constraint(ALLOC_IN_RC(a1_reg));
4426 match(RegN);
4427 match(mRegN);
4429 format %{ %}
4430 interface(REG_INTER);
4431 %}
4433 operand a2_RegN() %{
4434 constraint(ALLOC_IN_RC(a2_reg));
4435 match(RegN);
4436 match(mRegN);
4438 format %{ %}
4439 interface(REG_INTER);
4440 %}
4442 operand a3_RegN() %{
4443 constraint(ALLOC_IN_RC(a3_reg));
4444 match(RegN);
4445 match(mRegN);
4447 format %{ %}
4448 interface(REG_INTER);
4449 %}
4451 operand a4_RegN() %{
4452 constraint(ALLOC_IN_RC(a4_reg));
4453 match(RegN);
4454 match(mRegN);
4456 format %{ %}
4457 interface(REG_INTER);
4458 %}
4460 operand a5_RegN() %{
4461 constraint(ALLOC_IN_RC(a5_reg));
4462 match(RegN);
4463 match(mRegN);
4465 format %{ %}
4466 interface(REG_INTER);
4467 %}
4469 operand a6_RegN() %{
4470 constraint(ALLOC_IN_RC(a6_reg));
4471 match(RegN);
4472 match(mRegN);
4474 format %{ %}
4475 interface(REG_INTER);
4476 %}
4478 operand a7_RegN() %{
4479 constraint(ALLOC_IN_RC(a7_reg));
4480 match(RegN);
4481 match(mRegN);
4483 format %{ %}
4484 interface(REG_INTER);
4485 %}
4487 operand s0_RegN() %{
4488 constraint(ALLOC_IN_RC(s0_reg));
4489 match(RegN);
4490 match(mRegN);
4492 format %{ %}
4493 interface(REG_INTER);
4494 %}
4496 operand s1_RegN() %{
4497 constraint(ALLOC_IN_RC(s1_reg));
4498 match(RegN);
4499 match(mRegN);
4501 format %{ %}
4502 interface(REG_INTER);
4503 %}
4505 operand s2_RegN() %{
4506 constraint(ALLOC_IN_RC(s2_reg));
4507 match(RegN);
4508 match(mRegN);
4510 format %{ %}
4511 interface(REG_INTER);
4512 %}
4514 operand s3_RegN() %{
4515 constraint(ALLOC_IN_RC(s3_reg));
4516 match(RegN);
4517 match(mRegN);
4519 format %{ %}
4520 interface(REG_INTER);
4521 %}
4523 operand s4_RegN() %{
4524 constraint(ALLOC_IN_RC(s4_reg));
4525 match(RegN);
4526 match(mRegN);
4528 format %{ %}
4529 interface(REG_INTER);
4530 %}
4532 operand s5_RegN() %{
4533 constraint(ALLOC_IN_RC(s5_reg));
4534 match(RegN);
4535 match(mRegN);
4537 format %{ %}
4538 interface(REG_INTER);
4539 %}
4541 operand s6_RegN() %{
4542 constraint(ALLOC_IN_RC(s6_reg));
4543 match(RegN);
4544 match(mRegN);
4546 format %{ %}
4547 interface(REG_INTER);
4548 %}
4550 operand s7_RegN() %{
4551 constraint(ALLOC_IN_RC(s7_reg));
4552 match(RegN);
4553 match(mRegN);
4555 format %{ %}
4556 interface(REG_INTER);
4557 %}
4559 operand v0_RegN() %{
4560 constraint(ALLOC_IN_RC(v0_reg));
4561 match(RegN);
4562 match(mRegN);
4564 format %{ %}
4565 interface(REG_INTER);
4566 %}
4568 operand v1_RegN() %{
4569 constraint(ALLOC_IN_RC(v1_reg));
4570 match(RegN);
4571 match(mRegN);
4573 format %{ %}
4574 interface(REG_INTER);
4575 %}
4577 // Pointer Register
4578 operand mRegP() %{
4579 constraint(ALLOC_IN_RC(p_reg));
4580 match(RegP);
4582 format %{ %}
4583 interface(REG_INTER);
4584 %}
4586 operand no_T8_mRegP() %{
4587 constraint(ALLOC_IN_RC(no_T8_p_reg));
4588 match(RegP);
4589 match(mRegP);
4591 format %{ %}
4592 interface(REG_INTER);
4593 %}
4595 operand s0_RegP()
4596 %{
4597 constraint(ALLOC_IN_RC(s0_long_reg));
4598 match(RegP);
4599 match(mRegP);
4600 match(no_T8_mRegP);
4602 format %{ %}
4603 interface(REG_INTER);
4604 %}
4606 operand s1_RegP()
4607 %{
4608 constraint(ALLOC_IN_RC(s1_long_reg));
4609 match(RegP);
4610 match(mRegP);
4611 match(no_T8_mRegP);
4613 format %{ %}
4614 interface(REG_INTER);
4615 %}
4617 operand s2_RegP()
4618 %{
4619 constraint(ALLOC_IN_RC(s2_long_reg));
4620 match(RegP);
4621 match(mRegP);
4622 match(no_T8_mRegP);
4624 format %{ %}
4625 interface(REG_INTER);
4626 %}
4628 operand s3_RegP()
4629 %{
4630 constraint(ALLOC_IN_RC(s3_long_reg));
4631 match(RegP);
4632 match(mRegP);
4633 match(no_T8_mRegP);
4635 format %{ %}
4636 interface(REG_INTER);
4637 %}
4639 operand s4_RegP()
4640 %{
4641 constraint(ALLOC_IN_RC(s4_long_reg));
4642 match(RegP);
4643 match(mRegP);
4644 match(no_T8_mRegP);
4646 format %{ %}
4647 interface(REG_INTER);
4648 %}
4650 operand s5_RegP()
4651 %{
4652 constraint(ALLOC_IN_RC(s5_long_reg));
4653 match(RegP);
4654 match(mRegP);
4655 match(no_T8_mRegP);
4657 format %{ %}
4658 interface(REG_INTER);
4659 %}
4661 operand s6_RegP()
4662 %{
4663 constraint(ALLOC_IN_RC(s6_long_reg));
4664 match(RegP);
4665 match(mRegP);
4666 match(no_T8_mRegP);
4668 format %{ %}
4669 interface(REG_INTER);
4670 %}
4672 operand s7_RegP()
4673 %{
4674 constraint(ALLOC_IN_RC(s7_long_reg));
4675 match(RegP);
4676 match(mRegP);
4677 match(no_T8_mRegP);
4679 format %{ %}
4680 interface(REG_INTER);
4681 %}
4683 operand t0_RegP()
4684 %{
4685 constraint(ALLOC_IN_RC(t0_long_reg));
4686 match(RegP);
4687 match(mRegP);
4688 match(no_T8_mRegP);
4690 format %{ %}
4691 interface(REG_INTER);
4692 %}
4694 operand t1_RegP()
4695 %{
4696 constraint(ALLOC_IN_RC(t1_long_reg));
4697 match(RegP);
4698 match(mRegP);
4699 match(no_T8_mRegP);
4701 format %{ %}
4702 interface(REG_INTER);
4703 %}
4705 operand t2_RegP()
4706 %{
4707 constraint(ALLOC_IN_RC(t2_long_reg));
4708 match(RegP);
4709 match(mRegP);
4710 match(no_T8_mRegP);
4712 format %{ %}
4713 interface(REG_INTER);
4714 %}
4716 operand t3_RegP()
4717 %{
4718 constraint(ALLOC_IN_RC(t3_long_reg));
4719 match(RegP);
4720 match(mRegP);
4721 match(no_T8_mRegP);
4723 format %{ %}
4724 interface(REG_INTER);
4725 %}
4727 operand t8_RegP()
4728 %{
4729 constraint(ALLOC_IN_RC(t8_long_reg));
4730 match(RegP);
4731 match(mRegP);
4733 format %{ %}
4734 interface(REG_INTER);
4735 %}
4737 operand t9_RegP()
4738 %{
4739 constraint(ALLOC_IN_RC(t9_long_reg));
4740 match(RegP);
4741 match(mRegP);
4742 match(no_T8_mRegP);
4744 format %{ %}
4745 interface(REG_INTER);
4746 %}
4748 operand a0_RegP()
4749 %{
4750 constraint(ALLOC_IN_RC(a0_long_reg));
4751 match(RegP);
4752 match(mRegP);
4753 match(no_T8_mRegP);
4755 format %{ %}
4756 interface(REG_INTER);
4757 %}
4759 operand a1_RegP()
4760 %{
4761 constraint(ALLOC_IN_RC(a1_long_reg));
4762 match(RegP);
4763 match(mRegP);
4764 match(no_T8_mRegP);
4766 format %{ %}
4767 interface(REG_INTER);
4768 %}
4770 operand a2_RegP()
4771 %{
4772 constraint(ALLOC_IN_RC(a2_long_reg));
4773 match(RegP);
4774 match(mRegP);
4775 match(no_T8_mRegP);
4777 format %{ %}
4778 interface(REG_INTER);
4779 %}
4781 operand a3_RegP()
4782 %{
4783 constraint(ALLOC_IN_RC(a3_long_reg));
4784 match(RegP);
4785 match(mRegP);
4786 match(no_T8_mRegP);
4788 format %{ %}
4789 interface(REG_INTER);
4790 %}
4792 operand a4_RegP()
4793 %{
4794 constraint(ALLOC_IN_RC(a4_long_reg));
4795 match(RegP);
4796 match(mRegP);
4797 match(no_T8_mRegP);
4799 format %{ %}
4800 interface(REG_INTER);
4801 %}
4804 operand a5_RegP()
4805 %{
4806 constraint(ALLOC_IN_RC(a5_long_reg));
4807 match(RegP);
4808 match(mRegP);
4809 match(no_T8_mRegP);
4811 format %{ %}
4812 interface(REG_INTER);
4813 %}
4815 operand a6_RegP()
4816 %{
4817 constraint(ALLOC_IN_RC(a6_long_reg));
4818 match(RegP);
4819 match(mRegP);
4820 match(no_T8_mRegP);
4822 format %{ %}
4823 interface(REG_INTER);
4824 %}
4826 operand a7_RegP()
4827 %{
4828 constraint(ALLOC_IN_RC(a7_long_reg));
4829 match(RegP);
4830 match(mRegP);
4831 match(no_T8_mRegP);
4833 format %{ %}
4834 interface(REG_INTER);
4835 %}
4837 operand v0_RegP()
4838 %{
4839 constraint(ALLOC_IN_RC(v0_long_reg));
4840 match(RegP);
4841 match(mRegP);
4842 match(no_T8_mRegP);
4844 format %{ %}
4845 interface(REG_INTER);
4846 %}
4848 operand v1_RegP()
4849 %{
4850 constraint(ALLOC_IN_RC(v1_long_reg));
4851 match(RegP);
4852 match(mRegP);
4853 match(no_T8_mRegP);
4855 format %{ %}
4856 interface(REG_INTER);
4857 %}
4859 /*
4860 operand mSPRegP(mRegP reg) %{
4861 constraint(ALLOC_IN_RC(sp_reg));
4862 match(reg);
4864 format %{ "SP" %}
4865 interface(REG_INTER);
4866 %}
4868 operand mFPRegP(mRegP reg) %{
4869 constraint(ALLOC_IN_RC(fp_reg));
4870 match(reg);
4872 format %{ "FP" %}
4873 interface(REG_INTER);
4874 %}
4875 */
4877 operand mRegL() %{
4878 constraint(ALLOC_IN_RC(long_reg));
4879 match(RegL);
4881 format %{ %}
4882 interface(REG_INTER);
4883 %}
4885 operand v0RegL() %{
4886 constraint(ALLOC_IN_RC(v0_long_reg));
4887 match(RegL);
4888 match(mRegL);
4890 format %{ %}
4891 interface(REG_INTER);
4892 %}
4894 operand v1RegL() %{
4895 constraint(ALLOC_IN_RC(v1_long_reg));
4896 match(RegL);
4897 match(mRegL);
4899 format %{ %}
4900 interface(REG_INTER);
4901 %}
4903 operand a0RegL() %{
4904 constraint(ALLOC_IN_RC(a0_long_reg));
4905 match(RegL);
4906 match(mRegL);
4908 format %{ "A0" %}
4909 interface(REG_INTER);
4910 %}
4912 operand a1RegL() %{
4913 constraint(ALLOC_IN_RC(a1_long_reg));
4914 match(RegL);
4915 match(mRegL);
4917 format %{ %}
4918 interface(REG_INTER);
4919 %}
4921 operand a2RegL() %{
4922 constraint(ALLOC_IN_RC(a2_long_reg));
4923 match(RegL);
4924 match(mRegL);
4926 format %{ %}
4927 interface(REG_INTER);
4928 %}
4930 operand a3RegL() %{
4931 constraint(ALLOC_IN_RC(a3_long_reg));
4932 match(RegL);
4933 match(mRegL);
4935 format %{ %}
4936 interface(REG_INTER);
4937 %}
4939 operand t0RegL() %{
4940 constraint(ALLOC_IN_RC(t0_long_reg));
4941 match(RegL);
4942 match(mRegL);
4944 format %{ %}
4945 interface(REG_INTER);
4946 %}
4948 operand t1RegL() %{
4949 constraint(ALLOC_IN_RC(t1_long_reg));
4950 match(RegL);
4951 match(mRegL);
4953 format %{ %}
4954 interface(REG_INTER);
4955 %}
4957 operand t2RegL() %{
4958 constraint(ALLOC_IN_RC(t2_long_reg));
4959 match(RegL);
4960 match(mRegL);
4962 format %{ %}
4963 interface(REG_INTER);
4964 %}
4966 operand t3RegL() %{
4967 constraint(ALLOC_IN_RC(t3_long_reg));
4968 match(RegL);
4969 match(mRegL);
4971 format %{ %}
4972 interface(REG_INTER);
4973 %}
4975 operand t8RegL() %{
4976 constraint(ALLOC_IN_RC(t8_long_reg));
4977 match(RegL);
4978 match(mRegL);
4980 format %{ %}
4981 interface(REG_INTER);
4982 %}
4984 operand a4RegL() %{
4985 constraint(ALLOC_IN_RC(a4_long_reg));
4986 match(RegL);
4987 match(mRegL);
4989 format %{ %}
4990 interface(REG_INTER);
4991 %}
4993 operand a5RegL() %{
4994 constraint(ALLOC_IN_RC(a5_long_reg));
4995 match(RegL);
4996 match(mRegL);
4998 format %{ %}
4999 interface(REG_INTER);
5000 %}
5002 operand a6RegL() %{
5003 constraint(ALLOC_IN_RC(a6_long_reg));
5004 match(RegL);
5005 match(mRegL);
5007 format %{ %}
5008 interface(REG_INTER);
5009 %}
5011 operand a7RegL() %{
5012 constraint(ALLOC_IN_RC(a7_long_reg));
5013 match(RegL);
5014 match(mRegL);
5016 format %{ %}
5017 interface(REG_INTER);
5018 %}
5020 operand s0RegL() %{
5021 constraint(ALLOC_IN_RC(s0_long_reg));
5022 match(RegL);
5023 match(mRegL);
5025 format %{ %}
5026 interface(REG_INTER);
5027 %}
5029 operand s1RegL() %{
5030 constraint(ALLOC_IN_RC(s1_long_reg));
5031 match(RegL);
5032 match(mRegL);
5034 format %{ %}
5035 interface(REG_INTER);
5036 %}
5038 operand s2RegL() %{
5039 constraint(ALLOC_IN_RC(s2_long_reg));
5040 match(RegL);
5041 match(mRegL);
5043 format %{ %}
5044 interface(REG_INTER);
5045 %}
5047 operand s3RegL() %{
5048 constraint(ALLOC_IN_RC(s3_long_reg));
5049 match(RegL);
5050 match(mRegL);
5052 format %{ %}
5053 interface(REG_INTER);
5054 %}
5056 operand s4RegL() %{
5057 constraint(ALLOC_IN_RC(s4_long_reg));
5058 match(RegL);
5059 match(mRegL);
5061 format %{ %}
5062 interface(REG_INTER);
5063 %}
5065 operand s7RegL() %{
5066 constraint(ALLOC_IN_RC(s7_long_reg));
5067 match(RegL);
5068 match(mRegL);
5070 format %{ %}
5071 interface(REG_INTER);
5072 %}
5074 // Floating register operands
5075 operand regF() %{
5076 constraint(ALLOC_IN_RC(flt_reg));
5077 match(RegF);
5079 format %{ %}
5080 interface(REG_INTER);
5081 %}
5083 //Double Precision Floating register operands
5084 operand regD() %{
5085 constraint(ALLOC_IN_RC(dbl_reg));
5086 match(RegD);
5088 format %{ %}
5089 interface(REG_INTER);
5090 %}
5092 //----------Memory Operands----------------------------------------------------
5093 // Indirect Memory Operand
5094 operand indirect(mRegP reg) %{
5095 constraint(ALLOC_IN_RC(p_reg));
5096 match(reg);
5098 format %{ "[$reg] @ indirect" %}
5099 interface(MEMORY_INTER) %{
5100 base($reg);
5101 index(0x0); /* NO_INDEX */
5102 scale(0x0);
5103 disp(0x0);
5104 %}
5105 %}
5107 // Indirect Memory Plus Short Offset Operand
5108 operand indOffset8(mRegP reg, immL8 off)
5109 %{
5110 constraint(ALLOC_IN_RC(p_reg));
5111 match(AddP reg off);
5113 format %{ "[$reg + $off (8-bit)] @ indOffset8" %}
5114 interface(MEMORY_INTER) %{
5115 base($reg);
5116 index(0x0); /* NO_INDEX */
5117 scale(0x0);
5118 disp($off);
5119 %}
5120 %}
5122 // Indirect Memory Times Scale Plus Index Register
5123 operand indIndexScale(mRegP reg, mRegL lreg, immI2 scale)
5124 %{
5125 constraint(ALLOC_IN_RC(p_reg));
5126 match(AddP reg (LShiftL lreg scale));
5128 op_cost(10);
5129 format %{"[$reg + $lreg << $scale] @ indIndexScale" %}
5130 interface(MEMORY_INTER) %{
5131 base($reg);
5132 index($lreg);
5133 scale($scale);
5134 disp(0x0);
5135 %}
5136 %}
5139 // [base + index + offset]
5140 operand baseIndexOffset8(mRegP base, mRegL index, immL8 off)
5141 %{
5142 constraint(ALLOC_IN_RC(p_reg));
5143 op_cost(5);
5144 match(AddP (AddP base index) off);
5146 format %{ "[$base + $index + $off (8-bit)] @ baseIndexOffset8" %}
5147 interface(MEMORY_INTER) %{
5148 base($base);
5149 index($index);
5150 scale(0x0);
5151 disp($off);
5152 %}
5153 %}
5155 // [base + index + offset]
5156 operand baseIndexOffset8_convI2L(mRegP base, mRegI index, immL8 off)
5157 %{
5158 constraint(ALLOC_IN_RC(p_reg));
5159 op_cost(5);
5160 match(AddP (AddP base (ConvI2L index)) off);
5162 format %{ "[$base + $index + $off (8-bit)] @ baseIndexOffset8_convI2L" %}
5163 interface(MEMORY_INTER) %{
5164 base($base);
5165 index($index);
5166 scale(0x0);
5167 disp($off);
5168 %}
5169 %}
5171 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5172 operand indIndexScaleOffset8(mRegP reg, immL8 off, mRegL lreg, immI2 scale)
5173 %{
5174 constraint(ALLOC_IN_RC(p_reg));
5175 match(AddP (AddP reg (LShiftL lreg scale)) off);
5177 op_cost(10);
5178 format %{"[$reg + $off + $lreg << $scale] @ indIndexScaleOffset8" %}
5179 interface(MEMORY_INTER) %{
5180 base($reg);
5181 index($lreg);
5182 scale($scale);
5183 disp($off);
5184 %}
5185 %}
5187 operand indIndexScaleOffset8_convI2L(mRegP reg, immL8 off, mRegI ireg, immI2 scale)
5188 %{
5189 constraint(ALLOC_IN_RC(p_reg));
5190 match(AddP (AddP reg (LShiftL (ConvI2L ireg) scale)) off);
5192 op_cost(10);
5193 format %{"[$reg + $off + $ireg << $scale] @ indIndexScaleOffset8_convI2L" %}
5194 interface(MEMORY_INTER) %{
5195 base($reg);
5196 index($ireg);
5197 scale($scale);
5198 disp($off);
5199 %}
5200 %}
5202 // [base + index<<scale + offset]
5203 operand basePosIndexScaleOffset8(mRegP base, mRegI index, immL8 off, immI_0_31 scale)
5204 %{
5205 constraint(ALLOC_IN_RC(p_reg));
5206 //predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
5207 op_cost(10);
5208 match(AddP (AddP base (LShiftL (ConvI2L index) scale)) off);
5210 format %{ "[$base + $index << $scale + $off (8-bit)] @ basePosIndexScaleOffset8" %}
5211 interface(MEMORY_INTER) %{
5212 base($base);
5213 index($index);
5214 scale($scale);
5215 disp($off);
5216 %}
5217 %}
5219 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5220 operand indIndexScaleOffsetNarrow(mRegN reg, immL8 off, mRegL lreg, immI2 scale)
5221 %{
5222 predicate(Universe::narrow_oop_shift() == 0);
5223 constraint(ALLOC_IN_RC(p_reg));
5224 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
5226 op_cost(10);
5227 format %{"[$reg + $off + $lreg << $scale] @ indIndexScaleOffsetNarrow" %}
5228 interface(MEMORY_INTER) %{
5229 base($reg);
5230 index($lreg);
5231 scale($scale);
5232 disp($off);
5233 %}
5234 %}
5236 // [base + index<<scale + offset] for compressd Oops
5237 operand indPosIndexI2LScaleOffset8Narrow(mRegN base, mRegI index, immL8 off, immI_0_31 scale)
5238 %{
5239 constraint(ALLOC_IN_RC(p_reg));
5240 //predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
5241 predicate(Universe::narrow_oop_shift() == 0);
5242 op_cost(10);
5243 match(AddP (AddP (DecodeN base) (LShiftL (ConvI2L index) scale)) off);
5245 format %{ "[$base + $index << $scale + $off (8-bit)] @ indPosIndexI2LScaleOffset8Narrow" %}
5246 interface(MEMORY_INTER) %{
5247 base($base);
5248 index($index);
5249 scale($scale);
5250 disp($off);
5251 %}
5252 %}
5254 //FIXME: I think it's better to limit the immI to be 16-bit at most!
5255 // Indirect Memory Plus Long Offset Operand
5256 operand indOffset32(mRegP reg, immL32 off) %{
5257 constraint(ALLOC_IN_RC(p_reg));
5258 op_cost(20);
5259 match(AddP reg off);
5261 format %{ "[$reg + $off (32-bit)] @ indOffset32" %}
5262 interface(MEMORY_INTER) %{
5263 base($reg);
5264 index(0x0); /* NO_INDEX */
5265 scale(0x0);
5266 disp($off);
5267 %}
5268 %}
5270 // Indirect Memory Plus Index Register
5271 operand indIndex(mRegP addr, mRegL index) %{
5272 constraint(ALLOC_IN_RC(p_reg));
5273 match(AddP addr index);
5275 op_cost(20);
5276 format %{"[$addr + $index] @ indIndex" %}
5277 interface(MEMORY_INTER) %{
5278 base($addr);
5279 index($index);
5280 scale(0x0);
5281 disp(0x0);
5282 %}
5283 %}
5285 operand indirectNarrowKlass(mRegN reg)
5286 %{
5287 predicate(Universe::narrow_klass_shift() == 0);
5288 constraint(ALLOC_IN_RC(p_reg));
5289 op_cost(10);
5290 match(DecodeNKlass reg);
5292 format %{ "[$reg] @ indirectNarrowKlass" %}
5293 interface(MEMORY_INTER) %{
5294 base($reg);
5295 index(0x0);
5296 scale(0x0);
5297 disp(0x0);
5298 %}
5299 %}
5301 operand indOffset8NarrowKlass(mRegN reg, immL8 off)
5302 %{
5303 predicate(Universe::narrow_klass_shift() == 0);
5304 constraint(ALLOC_IN_RC(p_reg));
5305 op_cost(10);
5306 match(AddP (DecodeNKlass reg) off);
5308 format %{ "[$reg + $off (8-bit)] @ indOffset8NarrowKlass" %}
5309 interface(MEMORY_INTER) %{
5310 base($reg);
5311 index(0x0);
5312 scale(0x0);
5313 disp($off);
5314 %}
5315 %}
5317 operand indOffset32NarrowKlass(mRegN reg, immL32 off)
5318 %{
5319 predicate(Universe::narrow_klass_shift() == 0);
5320 constraint(ALLOC_IN_RC(p_reg));
5321 op_cost(10);
5322 match(AddP (DecodeNKlass reg) off);
5324 format %{ "[$reg + $off (32-bit)] @ indOffset32NarrowKlass" %}
5325 interface(MEMORY_INTER) %{
5326 base($reg);
5327 index(0x0);
5328 scale(0x0);
5329 disp($off);
5330 %}
5331 %}
5333 operand indIndexOffsetNarrowKlass(mRegN reg, mRegL lreg, immL32 off)
5334 %{
5335 predicate(Universe::narrow_klass_shift() == 0);
5336 constraint(ALLOC_IN_RC(p_reg));
5337 match(AddP (AddP (DecodeNKlass reg) lreg) off);
5339 op_cost(10);
5340 format %{"[$reg + $off + $lreg] @ indIndexOffsetNarrowKlass" %}
5341 interface(MEMORY_INTER) %{
5342 base($reg);
5343 index($lreg);
5344 scale(0x0);
5345 disp($off);
5346 %}
5347 %}
5349 operand indIndexNarrowKlass(mRegN reg, mRegL lreg)
5350 %{
5351 predicate(Universe::narrow_klass_shift() == 0);
5352 constraint(ALLOC_IN_RC(p_reg));
5353 match(AddP (DecodeNKlass reg) lreg);
5355 op_cost(10);
5356 format %{"[$reg + $lreg] @ indIndexNarrowKlass" %}
5357 interface(MEMORY_INTER) %{
5358 base($reg);
5359 index($lreg);
5360 scale(0x0);
5361 disp(0x0);
5362 %}
5363 %}
5365 // Indirect Memory Operand
5366 operand indirectNarrow(mRegN reg)
5367 %{
5368 predicate(Universe::narrow_oop_shift() == 0);
5369 constraint(ALLOC_IN_RC(p_reg));
5370 op_cost(10);
5371 match(DecodeN reg);
5373 format %{ "[$reg] @ indirectNarrow" %}
5374 interface(MEMORY_INTER) %{
5375 base($reg);
5376 index(0x0);
5377 scale(0x0);
5378 disp(0x0);
5379 %}
5380 %}
5382 // Indirect Memory Plus Short Offset Operand
5383 operand indOffset8Narrow(mRegN reg, immL8 off)
5384 %{
5385 predicate(Universe::narrow_oop_shift() == 0);
5386 constraint(ALLOC_IN_RC(p_reg));
5387 op_cost(10);
5388 match(AddP (DecodeN reg) off);
5390 format %{ "[$reg + $off (8-bit)] @ indOffset8Narrow" %}
5391 interface(MEMORY_INTER) %{
5392 base($reg);
5393 index(0x0);
5394 scale(0x0);
5395 disp($off);
5396 %}
5397 %}
5399 // Indirect Memory Plus Index Register Plus Offset Operand
5400 operand indIndexOffset8Narrow(mRegN reg, mRegL lreg, immL8 off)
5401 %{
5402 predicate(Universe::narrow_oop_shift() == 0);
5403 constraint(ALLOC_IN_RC(p_reg));
5404 match(AddP (AddP (DecodeN reg) lreg) off);
5406 op_cost(10);
5407 format %{"[$reg + $off + $lreg] @ indIndexOffset8Narrow" %}
5408 interface(MEMORY_INTER) %{
5409 base($reg);
5410 index($lreg);
5411 scale(0x0);
5412 disp($off);
5413 %}
5414 %}
5416 //----------Load Long Memory Operands------------------------------------------
5417 // The load-long idiom will use it's address expression again after loading
5418 // the first word of the long. If the load-long destination overlaps with
5419 // registers used in the addressing expression, the 2nd half will be loaded
5420 // from a clobbered address. Fix this by requiring that load-long use
5421 // address registers that do not overlap with the load-long target.
5423 // load-long support
5424 operand load_long_RegP() %{
5425 constraint(ALLOC_IN_RC(p_reg));
5426 match(RegP);
5427 match(mRegP);
5428 op_cost(100);
5429 format %{ %}
5430 interface(REG_INTER);
5431 %}
5433 // Indirect Memory Operand Long
5434 operand load_long_indirect(load_long_RegP reg) %{
5435 constraint(ALLOC_IN_RC(p_reg));
5436 match(reg);
5438 format %{ "[$reg]" %}
5439 interface(MEMORY_INTER) %{
5440 base($reg);
5441 index(0x0);
5442 scale(0x0);
5443 disp(0x0);
5444 %}
5445 %}
5447 // Indirect Memory Plus Long Offset Operand
5448 operand load_long_indOffset32(load_long_RegP reg, immL32 off) %{
5449 match(AddP reg off);
5451 format %{ "[$reg + $off]" %}
5452 interface(MEMORY_INTER) %{
5453 base($reg);
5454 index(0x0);
5455 scale(0x0);
5456 disp($off);
5457 %}
5458 %}
5460 //----------Conditional Branch Operands----------------------------------------
5461 // Comparison Op - This is the operation of the comparison, and is limited to
5462 // the following set of codes:
5463 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
5464 //
5465 // Other attributes of the comparison, such as unsignedness, are specified
5466 // by the comparison instruction that sets a condition code flags register.
5467 // That result is represented by a flags operand whose subtype is appropriate
5468 // to the unsignedness (etc.) of the comparison.
5469 //
5470 // Later, the instruction which matches both the Comparison Op (a Bool) and
5471 // the flags (produced by the Cmp) specifies the coding of the comparison op
5472 // by matching a specific subtype of Bool operand below, such as cmpOpU.
5474 // Comparision Code
5475 operand cmpOp() %{
5476 match(Bool);
5478 format %{ "" %}
5479 interface(COND_INTER) %{
5480 equal(0x01);
5481 not_equal(0x02);
5482 greater(0x03);
5483 greater_equal(0x04);
5484 less(0x05);
5485 less_equal(0x06);
5486 overflow(0x7);
5487 no_overflow(0x8);
5488 %}
5489 %}
5492 // Comparision Code
5493 // Comparison Code, unsigned compare. Used by FP also, with
5494 // C2 (unordered) turned into GT or LT already. The other bits
5495 // C0 and C3 are turned into Carry & Zero flags.
5496 operand cmpOpU() %{
5497 match(Bool);
5499 format %{ "" %}
5500 interface(COND_INTER) %{
5501 equal(0x01);
5502 not_equal(0x02);
5503 greater(0x03);
5504 greater_equal(0x04);
5505 less(0x05);
5506 less_equal(0x06);
5507 overflow(0x7);
5508 no_overflow(0x8);
5509 %}
5510 %}
5512 /*
5513 // Comparison Code, unsigned compare. Used by FP also, with
5514 // C2 (unordered) turned into GT or LT already. The other bits
5515 // C0 and C3 are turned into Carry & Zero flags.
5516 operand cmpOpU() %{
5517 match(Bool);
5519 format %{ "" %}
5520 interface(COND_INTER) %{
5521 equal(0x4);
5522 not_equal(0x5);
5523 less(0x2);
5524 greater_equal(0x3);
5525 less_equal(0x6);
5526 greater(0x7);
5527 %}
5528 %}
5529 */
5530 /*
5531 // Comparison Code for FP conditional move
5532 operand cmpOp_fcmov() %{
5533 match(Bool);
5535 format %{ "" %}
5536 interface(COND_INTER) %{
5537 equal (0x01);
5538 not_equal (0x02);
5539 greater (0x03);
5540 greater_equal(0x04);
5541 less (0x05);
5542 less_equal (0x06);
5543 %}
5544 %}
5546 // Comparision Code used in long compares
5547 operand cmpOp_commute() %{
5548 match(Bool);
5550 format %{ "" %}
5551 interface(COND_INTER) %{
5552 equal(0x4);
5553 not_equal(0x5);
5554 less(0xF);
5555 greater_equal(0xE);
5556 less_equal(0xD);
5557 greater(0xC);
5558 %}
5559 %}
5560 */
5562 //----------Special Memory Operands--------------------------------------------
5563 // Stack Slot Operand - This operand is used for loading and storing temporary
5564 // values on the stack where a match requires a value to
5565 // flow through memory.
5566 operand stackSlotP(sRegP reg) %{
5567 constraint(ALLOC_IN_RC(stack_slots));
5568 // No match rule because this operand is only generated in matching
5569 op_cost(50);
5570 format %{ "[$reg]" %}
5571 interface(MEMORY_INTER) %{
5572 base(0x1d); // SP
5573 index(0x0); // No Index
5574 scale(0x0); // No Scale
5575 disp($reg); // Stack Offset
5576 %}
5577 %}
5579 operand stackSlotI(sRegI reg) %{
5580 constraint(ALLOC_IN_RC(stack_slots));
5581 // No match rule because this operand is only generated in matching
5582 op_cost(50);
5583 format %{ "[$reg]" %}
5584 interface(MEMORY_INTER) %{
5585 base(0x1d); // SP
5586 index(0x0); // No Index
5587 scale(0x0); // No Scale
5588 disp($reg); // Stack Offset
5589 %}
5590 %}
5592 operand stackSlotF(sRegF reg) %{
5593 constraint(ALLOC_IN_RC(stack_slots));
5594 // No match rule because this operand is only generated in matching
5595 op_cost(50);
5596 format %{ "[$reg]" %}
5597 interface(MEMORY_INTER) %{
5598 base(0x1d); // SP
5599 index(0x0); // No Index
5600 scale(0x0); // No Scale
5601 disp($reg); // Stack Offset
5602 %}
5603 %}
5605 operand stackSlotD(sRegD reg) %{
5606 constraint(ALLOC_IN_RC(stack_slots));
5607 // No match rule because this operand is only generated in matching
5608 op_cost(50);
5609 format %{ "[$reg]" %}
5610 interface(MEMORY_INTER) %{
5611 base(0x1d); // SP
5612 index(0x0); // No Index
5613 scale(0x0); // No Scale
5614 disp($reg); // Stack Offset
5615 %}
5616 %}
5618 operand stackSlotL(sRegL reg) %{
5619 constraint(ALLOC_IN_RC(stack_slots));
5620 // No match rule because this operand is only generated in matching
5621 op_cost(50);
5622 format %{ "[$reg]" %}
5623 interface(MEMORY_INTER) %{
5624 base(0x1d); // SP
5625 index(0x0); // No Index
5626 scale(0x0); // No Scale
5627 disp($reg); // Stack Offset
5628 %}
5629 %}
5632 //------------------------OPERAND CLASSES--------------------------------------
5633 //opclass memory( direct, indirect, indOffset16, indOffset32, indOffset32X, indIndexOffset );
5634 opclass memory( indirect, indirectNarrow, indOffset8, indOffset32, indIndex, indIndexScale, load_long_indirect, load_long_indOffset32, baseIndexOffset8, baseIndexOffset8_convI2L, indIndexScaleOffset8, indIndexScaleOffset8_convI2L, basePosIndexScaleOffset8, indIndexScaleOffsetNarrow, indPosIndexI2LScaleOffset8Narrow, indOffset8Narrow, indIndexOffset8Narrow);
5637 //----------PIPELINE-----------------------------------------------------------
5638 // Rules which define the behavior of the target architectures pipeline.
5640 pipeline %{
5642 //----------ATTRIBUTES---------------------------------------------------------
5643 attributes %{
5644 fixed_size_instructions; // Fixed size instructions
5645 branch_has_delay_slot; // branch have delay slot in gs2
5646 max_instructions_per_bundle = 1; // 1 instruction per bundle
5647 max_bundles_per_cycle = 4; // Up to 4 bundles per cycle
5648 bundle_unit_size=4;
5649 instruction_unit_size = 4; // An instruction is 4 bytes long
5650 instruction_fetch_unit_size = 16; // The processor fetches one line
5651 instruction_fetch_units = 1; // of 16 bytes
5653 // List of nop instructions
5654 nops( MachNop );
5655 %}
5657 //----------RESOURCES----------------------------------------------------------
5658 // Resources are the functional units available to the machine
5660 resources(D1, D2, D3, D4, DECODE = D1 | D2 | D3| D4, ALU1, ALU2, ALU = ALU1 | ALU2, FPU1, FPU2, FPU = FPU1 | FPU2, MEM, BR);
5662 //----------PIPELINE DESCRIPTION-----------------------------------------------
5663 // Pipeline Description specifies the stages in the machine's pipeline
5665 // IF: fetch
5666 // ID: decode
5667 // RD: read
5668 // CA: caculate
5669 // WB: write back
5670 // CM: commit
5672 pipe_desc(IF, ID, RD, CA, WB, CM);
5675 //----------PIPELINE CLASSES---------------------------------------------------
5676 // Pipeline Classes describe the stages in which input and output are
5677 // referenced by the hardware pipeline.
5679 //No.1 Integer ALU reg-reg operation : dst <-- reg1 op reg2
5680 pipe_class ialu_regI_regI(mRegI dst, mRegI src1, mRegI src2) %{
5681 single_instruction;
5682 src1 : RD(read);
5683 src2 : RD(read);
5684 dst : WB(write)+1;
5685 DECODE : ID;
5686 ALU : CA;
5687 %}
5689 //No.19 Integer mult operation : dst <-- reg1 mult reg2
5690 pipe_class ialu_mult(mRegI dst, mRegI src1, mRegI src2) %{
5691 src1 : RD(read);
5692 src2 : RD(read);
5693 dst : WB(write)+5;
5694 DECODE : ID;
5695 ALU2 : CA;
5696 %}
5698 pipe_class mulL_reg_reg(mRegL dst, mRegL src1, mRegL src2) %{
5699 src1 : RD(read);
5700 src2 : RD(read);
5701 dst : WB(write)+10;
5702 DECODE : ID;
5703 ALU2 : CA;
5704 %}
5706 //No.19 Integer div operation : dst <-- reg1 div reg2
5707 pipe_class ialu_div(mRegI dst, mRegI src1, mRegI src2) %{
5708 src1 : RD(read);
5709 src2 : RD(read);
5710 dst : WB(write)+10;
5711 DECODE : ID;
5712 ALU2 : CA;
5713 %}
5715 //No.19 Integer mod operation : dst <-- reg1 mod reg2
5716 pipe_class ialu_mod(mRegI dst, mRegI src1, mRegI src2) %{
5717 instruction_count(2);
5718 src1 : RD(read);
5719 src2 : RD(read);
5720 dst : WB(write)+10;
5721 DECODE : ID;
5722 ALU2 : CA;
5723 %}
5725 //No.15 Long ALU reg-reg operation : dst <-- reg1 op reg2
5726 pipe_class ialu_regL_regL(mRegL dst, mRegL src1, mRegL src2) %{
5727 instruction_count(2);
5728 src1 : RD(read);
5729 src2 : RD(read);
5730 dst : WB(write);
5731 DECODE : ID;
5732 ALU : CA;
5733 %}
5735 //No.18 Long ALU reg-imm16 operation : dst <-- reg1 op imm16
5736 pipe_class ialu_regL_imm16(mRegL dst, mRegL src) %{
5737 instruction_count(2);
5738 src : RD(read);
5739 dst : WB(write);
5740 DECODE : ID;
5741 ALU : CA;
5742 %}
5744 //no.16 load Long from memory :
5745 pipe_class ialu_loadL(mRegL dst, memory mem) %{
5746 instruction_count(2);
5747 mem : RD(read);
5748 dst : WB(write)+5;
5749 DECODE : ID;
5750 MEM : RD;
5751 %}
5753 //No.17 Store Long to Memory :
5754 pipe_class ialu_storeL(mRegL src, memory mem) %{
5755 instruction_count(2);
5756 mem : RD(read);
5757 src : RD(read);
5758 DECODE : ID;
5759 MEM : RD;
5760 %}
5762 //No.2 Integer ALU reg-imm16 operation : dst <-- reg1 op imm16
5763 pipe_class ialu_regI_imm16(mRegI dst, mRegI src) %{
5764 single_instruction;
5765 src : RD(read);
5766 dst : WB(write);
5767 DECODE : ID;
5768 ALU : CA;
5769 %}
5771 //No.3 Integer move operation : dst <-- reg
5772 pipe_class ialu_regI_mov(mRegI dst, mRegI src) %{
5773 src : RD(read);
5774 dst : WB(write);
5775 DECODE : ID;
5776 ALU : CA;
5777 %}
5779 //No.4 No instructions : do nothing
5780 pipe_class empty( ) %{
5781 instruction_count(0);
5782 %}
5784 //No.5 UnConditional branch :
5785 pipe_class pipe_jump( label labl ) %{
5786 multiple_bundles;
5787 DECODE : ID;
5788 BR : RD;
5789 %}
5791 //No.6 ALU Conditional branch :
5792 pipe_class pipe_alu_branch(mRegI src1, mRegI src2, label labl ) %{
5793 multiple_bundles;
5794 src1 : RD(read);
5795 src2 : RD(read);
5796 DECODE : ID;
5797 BR : RD;
5798 %}
5800 //no.7 load integer from memory :
5801 pipe_class ialu_loadI(mRegI dst, memory mem) %{
5802 mem : RD(read);
5803 dst : WB(write)+3;
5804 DECODE : ID;
5805 MEM : RD;
5806 %}
5808 //No.8 Store Integer to Memory :
5809 pipe_class ialu_storeI(mRegI src, memory mem) %{
5810 mem : RD(read);
5811 src : RD(read);
5812 DECODE : ID;
5813 MEM : RD;
5814 %}
5817 //No.10 Floating FPU reg-reg operation : dst <-- reg1 op reg2
5818 pipe_class fpu_regF_regF(regF dst, regF src1, regF src2) %{
5819 src1 : RD(read);
5820 src2 : RD(read);
5821 dst : WB(write);
5822 DECODE : ID;
5823 FPU : CA;
5824 %}
5826 //No.22 Floating div operation : dst <-- reg1 div reg2
5827 pipe_class fpu_div(regF dst, regF src1, regF src2) %{
5828 src1 : RD(read);
5829 src2 : RD(read);
5830 dst : WB(write);
5831 DECODE : ID;
5832 FPU2 : CA;
5833 %}
5835 pipe_class fcvt_I2D(regD dst, mRegI src) %{
5836 src : RD(read);
5837 dst : WB(write);
5838 DECODE : ID;
5839 FPU1 : CA;
5840 %}
5842 pipe_class fcvt_D2I(mRegI dst, regD src) %{
5843 src : RD(read);
5844 dst : WB(write);
5845 DECODE : ID;
5846 FPU1 : CA;
5847 %}
5849 pipe_class pipe_mfc1(mRegI dst, regD src) %{
5850 src : RD(read);
5851 dst : WB(write);
5852 DECODE : ID;
5853 MEM : RD;
5854 %}
5856 pipe_class pipe_mtc1(regD dst, mRegI src) %{
5857 src : RD(read);
5858 dst : WB(write);
5859 DECODE : ID;
5860 MEM : RD(5);
5861 %}
5863 //No.23 Floating sqrt operation : dst <-- reg1 sqrt reg2
5864 pipe_class fpu_sqrt(regF dst, regF src1, regF src2) %{
5865 multiple_bundles;
5866 src1 : RD(read);
5867 src2 : RD(read);
5868 dst : WB(write);
5869 DECODE : ID;
5870 FPU2 : CA;
5871 %}
5873 //No.11 Load Floating from Memory :
5874 pipe_class fpu_loadF(regF dst, memory mem) %{
5875 instruction_count(1);
5876 mem : RD(read);
5877 dst : WB(write)+3;
5878 DECODE : ID;
5879 MEM : RD;
5880 %}
5882 //No.12 Store Floating to Memory :
5883 pipe_class fpu_storeF(regF src, memory mem) %{
5884 instruction_count(1);
5885 mem : RD(read);
5886 src : RD(read);
5887 DECODE : ID;
5888 MEM : RD;
5889 %}
5891 //No.13 FPU Conditional branch :
5892 pipe_class pipe_fpu_branch(regF src1, regF src2, label labl ) %{
5893 multiple_bundles;
5894 src1 : RD(read);
5895 src2 : RD(read);
5896 DECODE : ID;
5897 BR : RD;
5898 %}
5900 //No.14 Floating FPU reg operation : dst <-- op reg
5901 pipe_class fpu1_regF(regF dst, regF src) %{
5902 src : RD(read);
5903 dst : WB(write);
5904 DECODE : ID;
5905 FPU : CA;
5906 %}
5908 pipe_class long_memory_op() %{
5909 instruction_count(10); multiple_bundles; force_serialization;
5910 fixed_latency(30);
5911 %}
5913 pipe_class simple_call() %{
5914 instruction_count(10); multiple_bundles; force_serialization;
5915 fixed_latency(200);
5916 BR : RD;
5917 %}
5919 pipe_class call() %{
5920 instruction_count(10); multiple_bundles; force_serialization;
5921 fixed_latency(200);
5922 %}
5924 //FIXME:
5925 //No.9 Piple slow : for multi-instructions
5926 pipe_class pipe_slow( ) %{
5927 instruction_count(20);
5928 force_serialization;
5929 multiple_bundles;
5930 fixed_latency(50);
5931 %}
5933 %}
5937 //----------INSTRUCTIONS-------------------------------------------------------
5938 //
5939 // match -- States which machine-independent subtree may be replaced
5940 // by this instruction.
5941 // ins_cost -- The estimated cost of this instruction is used by instruction
5942 // selection to identify a minimum cost tree of machine
5943 // instructions that matches a tree of machine-independent
5944 // instructions.
5945 // format -- A string providing the disassembly for this instruction.
5946 // The value of an instruction's operand may be inserted
5947 // by referring to it with a '$' prefix.
5948 // opcode -- Three instruction opcodes may be provided. These are referred
5949 // to within an encode class as $primary, $secondary, and $tertiary
5950 // respectively. The primary opcode is commonly used to
5951 // indicate the type of machine instruction, while secondary
5952 // and tertiary are often used for prefix options or addressing
5953 // modes.
5954 // ins_encode -- A list of encode classes with parameters. The encode class
5955 // name must have been defined in an 'enc_class' specification
5956 // in the encode section of the architecture description.
5959 // Load Integer
5960 instruct loadI(mRegI dst, memory mem) %{
5961 match(Set dst (LoadI mem));
5963 ins_cost(125);
5964 format %{ "lw $dst, $mem #@loadI" %}
5965 ins_encode (load_I_enc(dst, mem));
5966 ins_pipe( ialu_loadI );
5967 %}
5969 instruct loadI_convI2L(mRegL dst, memory mem) %{
5970 match(Set dst (ConvI2L (LoadI mem)));
5972 ins_cost(125);
5973 format %{ "lw $dst, $mem #@loadI_convI2L" %}
5974 ins_encode (load_I_enc(dst, mem));
5975 ins_pipe( ialu_loadI );
5976 %}
5978 // Load Integer (32 bit signed) to Byte (8 bit signed)
5979 instruct loadI2B(mRegI dst, memory mem, immI_24 twentyfour) %{
5980 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5982 ins_cost(125);
5983 format %{ "lb $dst, $mem\t# int -> byte #@loadI2B" %}
5984 ins_encode(load_B_enc(dst, mem));
5985 ins_pipe(ialu_loadI);
5986 %}
5988 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
5989 instruct loadI2UB(mRegI dst, memory mem, immI_255 mask) %{
5990 match(Set dst (AndI (LoadI mem) mask));
5992 ins_cost(125);
5993 format %{ "lbu $dst, $mem\t# int -> ubyte #@loadI2UB" %}
5994 ins_encode(load_UB_enc(dst, mem));
5995 ins_pipe(ialu_loadI);
5996 %}
5998 // Load Integer (32 bit signed) to Short (16 bit signed)
5999 instruct loadI2S(mRegI dst, memory mem, immI_16 sixteen) %{
6000 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6002 ins_cost(125);
6003 format %{ "lh $dst, $mem\t# int -> short #@loadI2S" %}
6004 ins_encode(load_S_enc(dst, mem));
6005 ins_pipe(ialu_loadI);
6006 %}
6008 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6009 instruct loadI2US(mRegI dst, memory mem, immI_65535 mask) %{
6010 match(Set dst (AndI (LoadI mem) mask));
6012 ins_cost(125);
6013 format %{ "lhu $dst, $mem\t# int -> ushort/char #@loadI2US" %}
6014 ins_encode(load_C_enc(dst, mem));
6015 ins_pipe(ialu_loadI);
6016 %}
6018 // Load Long.
6019 instruct loadL(mRegL dst, memory mem) %{
6020 // predicate(!((LoadLNode*)n)->require_atomic_access());
6021 match(Set dst (LoadL mem));
6023 ins_cost(250);
6024 format %{ "ld $dst, $mem #@loadL" %}
6025 ins_encode(load_L_enc(dst, mem));
6026 ins_pipe( ialu_loadL );
6027 %}
6029 // Load Long - UNaligned
6030 instruct loadL_unaligned(mRegL dst, memory mem) %{
6031 match(Set dst (LoadL_unaligned mem));
6033 // FIXME: Jin: Need more effective ldl/ldr
6034 ins_cost(450);
6035 format %{ "ld $dst, $mem #@loadL_unaligned\n\t" %}
6036 ins_encode(load_L_enc(dst, mem));
6037 ins_pipe( ialu_loadL );
6038 %}
6040 // Store Long
6041 instruct storeL_reg(memory mem, mRegL src) %{
6042 predicate(!((StoreLNode*)n)->require_atomic_access());
6043 match(Set mem (StoreL mem src));
6045 ins_cost(200);
6046 format %{ "sd $mem, $src #@storeL_reg\n" %}
6047 ins_encode(store_L_reg_enc(mem, src));
6048 ins_pipe( ialu_storeL );
6049 %}
6051 //FIXME:volatile! atomic!
6052 // Volatile Store Long. Must be atomic, so move it into
6053 // the FP TOS and then do a 64-bit FIST. Has to probe the
6054 // target address before the store (for null-ptr checks)
6055 // so the memory operand is used twice in the encoding.
6056 instruct storeL_reg_atomic(memory mem, mRegL src) %{
6057 predicate(((StoreLNode*)n)->require_atomic_access());
6058 match(Set mem (StoreL mem src));
6060 ins_cost(200);
6061 format %{ "sw $mem, $src #@storeL_reg_atomic\n" %}
6062 ins_encode %{
6063 Register src = as_Register($src$$reg);
6065 int base = $mem$$base;
6066 int index = $mem$$index;
6067 int scale = $mem$$scale;
6068 int disp = $mem$$disp;
6070 if( index != 0 ) {
6071 if( Assembler::is_simm16(disp) ) {
6072 if (scale == 0) {
6073 __ addu(AT, as_Register(base), as_Register(index));
6074 } else {
6075 __ dsll(AT, as_Register(index), scale);
6076 __ addu(AT, as_Register(base), AT);
6077 }
6078 __ sd(src, AT, disp);
6079 } else {
6080 if (scale == 0) {
6081 __ addu(AT, as_Register(base), as_Register(index));
6082 } else {
6083 __ dsll(AT, as_Register(index), scale);
6084 __ addu(AT, as_Register(base), AT);
6085 }
6086 __ move(T9, disp);
6087 __ addu(AT, AT, T9);
6088 __ sd(src, AT, 0);
6089 }
6090 } else {
6091 if( Assembler::is_simm16(disp) ) {
6092 __ move(AT, as_Register(base));
6093 __ sd(src, AT, disp);
6094 } else {
6095 __ move(AT, as_Register(base));
6096 __ move(T9, disp);
6097 __ addu(AT, AT, T9);
6098 __ sd(src, AT, 0);
6099 }
6100 }
6102 %}
6103 ins_pipe( ialu_storeL );
6104 %}
6106 instruct storeL_immL0(memory mem, immL0 zero) %{
6107 match(Set mem (StoreL mem zero));
6109 ins_cost(180);
6110 format %{ "sd $mem, zero #@storeL_immL0" %}
6111 ins_encode(store_L_immL0_enc(mem, zero));
6112 ins_pipe( ialu_storeL );
6113 %}
6115 instruct storeL_imm(memory mem, immL src) %{
6116 match(Set mem (StoreL mem src));
6118 ins_cost(200);
6119 format %{ "sw $mem, $src #@storeL_imm" %}
6120 ins_encode(store_L_immL_enc(mem, src));
6121 ins_pipe( ialu_storeL );
6122 %}
6124 // Load Compressed Pointer
6125 instruct loadN(mRegN dst, memory mem)
6126 %{
6127 match(Set dst (LoadN mem));
6129 ins_cost(125); // XXX
6130 format %{ "lwu $dst, $mem\t# compressed ptr @ loadN" %}
6131 ins_encode (load_N_enc(dst, mem));
6132 ins_pipe( ialu_loadI ); // XXX
6133 %}
6135 // Load Pointer
6136 instruct loadP(mRegP dst, memory mem) %{
6137 match(Set dst (LoadP mem));
6139 ins_cost(125);
6140 format %{ "ld $dst, $mem #@loadP" %}
6141 ins_encode (load_P_enc(dst, mem));
6142 ins_pipe( ialu_loadI );
6143 %}
6145 // Load Klass Pointer
6146 instruct loadKlass(mRegP dst, memory mem) %{
6147 match(Set dst (LoadKlass mem));
6149 ins_cost(125);
6150 format %{ "MOV $dst,$mem @ loadKlass" %}
6151 ins_encode (load_P_enc(dst, mem));
6152 ins_pipe( ialu_loadI );
6153 %}
6155 // Load narrow Klass Pointer
6156 instruct loadNKlass(mRegN dst, memory mem)
6157 %{
6158 match(Set dst (LoadNKlass mem));
6160 ins_cost(125); // XXX
6161 format %{ "lwu $dst, $mem\t# compressed klass ptr @ loadNKlass" %}
6162 ins_encode (load_N_enc(dst, mem));
6163 ins_pipe( ialu_loadI ); // XXX
6164 %}
6166 // Load Constant
6167 instruct loadConI(mRegI dst, immI src) %{
6168 match(Set dst src);
6170 ins_cost(150);
6171 format %{ "mov $dst, $src #@loadConI" %}
6172 ins_encode %{
6173 Register dst = $dst$$Register;
6174 int value = $src$$constant;
6175 __ move(dst, value);
6176 %}
6177 ins_pipe( ialu_regI_regI );
6178 %}
6181 instruct loadConL_set64(mRegL dst, immL src) %{
6182 match(Set dst src);
6183 ins_cost(120);
6184 format %{ "li $dst, $src @ loadConL_set64" %}
6185 ins_encode %{
6186 __ set64($dst$$Register, $src$$constant);
6187 %}
6188 ins_pipe(ialu_regL_regL);
6189 %}
6191 /*
6192 // Load long value from constant table (predicated by immL_expensive).
6193 instruct loadConL_load(mRegL dst, immL_expensive src) %{
6194 match(Set dst src);
6195 ins_cost(150);
6196 format %{ "ld $dst, $constantoffset[$constanttablebase] # load long $src from table @ loadConL_ldx" %}
6197 ins_encode %{
6198 int con_offset = $constantoffset($src);
6200 if (Assembler::is_simm16(con_offset)) {
6201 __ ld($dst$$Register, $constanttablebase, con_offset);
6202 } else {
6203 __ set64(AT, con_offset);
6204 if (UseLoongsonISA) {
6205 __ gsldx($dst$$Register, $constanttablebase, AT, 0);
6206 } else {
6207 __ daddu(AT, $constanttablebase, AT);
6208 __ ld($dst$$Register, AT, 0);
6209 }
6210 }
6211 %}
6212 ins_pipe(ialu_loadI);
6213 %}
6214 */
6216 instruct loadConL16(mRegL dst, immL16 src) %{
6217 match(Set dst src);
6218 ins_cost(105);
6219 format %{ "mov $dst, $src #@loadConL16" %}
6220 ins_encode %{
6221 Register dst_reg = as_Register($dst$$reg);
6222 int value = $src$$constant;
6223 __ daddiu(dst_reg, R0, value);
6224 %}
6225 ins_pipe( ialu_regL_regL );
6226 %}
6229 instruct loadConL0(mRegL dst, immL0 src) %{
6230 match(Set dst src);
6231 ins_cost(100);
6232 format %{ "mov $dst, zero #@loadConL0" %}
6233 ins_encode %{
6234 Register dst_reg = as_Register($dst$$reg);
6235 __ daddu(dst_reg, R0, R0);
6236 %}
6237 ins_pipe( ialu_regL_regL );
6238 %}
6240 // Load Range
6241 instruct loadRange(mRegI dst, memory mem) %{
6242 match(Set dst (LoadRange mem));
6244 ins_cost(125);
6245 format %{ "MOV $dst,$mem @ loadRange" %}
6246 ins_encode(load_I_enc(dst, mem));
6247 ins_pipe( ialu_loadI );
6248 %}
6251 instruct storeP(memory mem, mRegP src ) %{
6252 match(Set mem (StoreP mem src));
6254 ins_cost(125);
6255 format %{ "sd $src, $mem #@storeP" %}
6256 ins_encode(store_P_reg_enc(mem, src));
6257 ins_pipe( ialu_storeI );
6258 %}
6260 /*
6261 [Ref: loadConP]
6263 Error:
6264 0x2d4b6d40: lui t9, 0x4f <--- handle
6265 0x2d4b6d44: addiu t9, t9, 0xffff808c
6266 0x2d4b6d48: sw t9, 0x4(s2)
6268 OK:
6269 0x2cc5ed40: lui t9, 0x336a <--- klass
6270 0x2cc5ed44: addiu t9, t9, 0x5a10
6271 0x2cc5ed48: sw t9, 0x4(s2)
6272 */
6273 // Store Pointer Immediate; null pointers or constant oops that do not
6274 // need card-mark barriers.
6276 // Store NULL Pointer, mark word, or other simple pointer constant.
6277 instruct storeImmP(memory mem, immP31 src) %{
6278 match(Set mem (StoreP mem src));
6280 ins_cost(150);
6281 format %{ "mov $mem, $src #@storeImmP" %}
6282 ins_encode(store_P_immP_enc(mem, src));
6283 ins_pipe( ialu_storeI );
6284 %}
6286 // Store Byte Immediate
6287 instruct storeImmB(memory mem, immI8 src) %{
6288 match(Set mem (StoreB mem src));
6290 ins_cost(150);
6291 format %{ "movb $mem, $src #@storeImmB" %}
6292 ins_encode(store_B_immI_enc(mem, src));
6293 ins_pipe( ialu_storeI );
6294 %}
6296 // Store Compressed Pointer
6297 instruct storeN(memory mem, mRegN src)
6298 %{
6299 match(Set mem (StoreN mem src));
6301 ins_cost(125); // XXX
6302 format %{ "sw $mem, $src\t# compressed ptr @ storeN" %}
6303 ins_encode(store_N_reg_enc(mem, src));
6304 ins_pipe( ialu_storeI );
6305 %}
6307 instruct storeNKlass(memory mem, mRegN src)
6308 %{
6309 match(Set mem (StoreNKlass mem src));
6311 ins_cost(125); // XXX
6312 format %{ "sw $mem, $src\t# compressed klass ptr @ storeNKlass" %}
6313 ins_encode(store_N_reg_enc(mem, src));
6314 ins_pipe( ialu_storeI );
6315 %}
6317 instruct storeImmN0(memory mem, immN0 zero)
6318 %{
6319 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL);
6320 match(Set mem (StoreN mem zero));
6322 ins_cost(125); // XXX
6323 format %{ "storeN0 $mem, R12\t# compressed ptr" %}
6324 ins_encode(storeImmN0_enc(mem, zero));
6325 ins_pipe( ialu_storeI );
6326 %}
6328 instruct storeImmN(memory mem, immN src)
6329 %{
6330 match(Set mem (StoreN mem src));
6332 ins_cost(150); // XXX
6333 format %{ "storeImmN $mem, $src\t# compressed ptr @ storeImmN" %}
6334 ins_encode(storeImmN_enc(mem, src));
6335 ins_pipe( ialu_storeI );
6336 %}
6338 instruct storeImmNKlass(memory mem, immNKlass src)
6339 %{
6340 match(Set mem (StoreNKlass mem src));
6342 ins_cost(150); // XXX
6343 format %{ "sw $mem, $src\t# compressed klass ptr @ storeImmNKlass" %}
6344 ins_encode(storeImmNKlass_enc(mem, src));
6345 ins_pipe( ialu_storeI );
6346 %}
6348 // Store Byte
6349 instruct storeB(memory mem, mRegI src) %{
6350 match(Set mem (StoreB mem src));
6352 ins_cost(125);
6353 format %{ "sb $src, $mem #@storeB" %}
6354 ins_encode(store_B_reg_enc(mem, src));
6355 ins_pipe( ialu_storeI );
6356 %}
6358 // Load Byte (8bit signed)
6359 instruct loadB(mRegI dst, memory mem) %{
6360 match(Set dst (LoadB mem));
6362 ins_cost(125);
6363 format %{ "lb $dst, $mem #@loadB" %}
6364 ins_encode(load_B_enc(dst, mem));
6365 ins_pipe( ialu_loadI );
6366 %}
6368 instruct loadB_convI2L(mRegL dst, memory mem) %{
6369 match(Set dst (ConvI2L (LoadB mem)));
6371 ins_cost(125);
6372 format %{ "lb $dst, $mem #@loadB_convI2L" %}
6373 ins_encode(load_B_enc(dst, mem));
6374 ins_pipe( ialu_loadI );
6375 %}
6377 // Load Byte (8bit UNsigned)
6378 instruct loadUB(mRegI dst, memory mem) %{
6379 match(Set dst (LoadUB mem));
6381 ins_cost(125);
6382 format %{ "lbu $dst, $mem #@loadUB" %}
6383 ins_encode(load_UB_enc(dst, mem));
6384 ins_pipe( ialu_loadI );
6385 %}
6387 instruct loadUB_convI2L(mRegL dst, memory mem) %{
6388 match(Set dst (ConvI2L (LoadUB mem)));
6390 ins_cost(125);
6391 format %{ "lbu $dst, $mem #@loadUB_convI2L" %}
6392 ins_encode(load_UB_enc(dst, mem));
6393 ins_pipe( ialu_loadI );
6394 %}
6396 // Load Short (16bit signed)
6397 instruct loadS(mRegI dst, memory mem) %{
6398 match(Set dst (LoadS mem));
6400 ins_cost(125);
6401 format %{ "lh $dst, $mem #@loadS" %}
6402 ins_encode(load_S_enc(dst, mem));
6403 ins_pipe( ialu_loadI );
6404 %}
6406 // Load Short (16 bit signed) to Byte (8 bit signed)
6407 instruct loadS2B(mRegI dst, memory mem, immI_24 twentyfour) %{
6408 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
6410 ins_cost(125);
6411 format %{ "lb $dst, $mem\t# short -> byte #@loadS2B" %}
6412 ins_encode(load_B_enc(dst, mem));
6413 ins_pipe(ialu_loadI);
6414 %}
6416 instruct loadS_convI2L(mRegL dst, memory mem) %{
6417 match(Set dst (ConvI2L (LoadS mem)));
6419 ins_cost(125);
6420 format %{ "lh $dst, $mem #@loadS_convI2L" %}
6421 ins_encode(load_S_enc(dst, mem));
6422 ins_pipe( ialu_loadI );
6423 %}
6425 // Store Integer Immediate
6426 instruct storeImmI(memory mem, immI src) %{
6427 match(Set mem (StoreI mem src));
6429 ins_cost(150);
6430 format %{ "mov $mem, $src #@storeImmI" %}
6431 ins_encode(store_I_immI_enc(mem, src));
6432 ins_pipe( ialu_storeI );
6433 %}
6435 // Store Integer
6436 instruct storeI(memory mem, mRegI src) %{
6437 match(Set mem (StoreI mem src));
6439 ins_cost(125);
6440 format %{ "sw $mem, $src #@storeI" %}
6441 ins_encode(store_I_reg_enc(mem, src));
6442 ins_pipe( ialu_storeI );
6443 %}
6445 instruct storeI_convL2I(memory mem, mRegL src) %{
6446 match(Set mem (StoreI mem (ConvL2I src)));
6448 ins_cost(125);
6449 format %{ "sw $mem, $src #@storeI_convL2I" %}
6450 ins_encode(store_I_reg_enc(mem, src));
6451 ins_pipe( ialu_storeI );
6452 %}
6454 // Load Float
6455 instruct loadF(regF dst, memory mem) %{
6456 match(Set dst (LoadF mem));
6458 ins_cost(150);
6459 format %{ "loadF $dst, $mem #@loadF" %}
6460 ins_encode(load_F_enc(dst, mem));
6461 ins_pipe( ialu_loadI );
6462 %}
6464 instruct loadConP_general(mRegP dst, immP src) %{
6465 match(Set dst src);
6467 ins_cost(120);
6468 format %{ "li $dst, $src #@loadConP_general" %}
6470 ins_encode %{
6471 Register dst = $dst$$Register;
6472 long* value = (long*)$src$$constant;
6473 bool is_need_reloc = $src->constant_reloc() != relocInfo::none;
6475 /* During GC, klassOop may be moved to new position in the heap.
6476 * It must be relocated.
6477 * Refer: [c1_LIRAssembler_mips.cpp] jobject2reg()
6478 */
6479 if (is_need_reloc) {
6480 if($src->constant_reloc() == relocInfo::metadata_type){
6481 int klass_index = __ oop_recorder()->find_index((Klass*)value);
6482 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6484 __ relocate(rspec);
6485 __ li48(dst, (long)value);
6486 }
6488 if($src->constant_reloc() == relocInfo::oop_type){
6489 int oop_index = __ oop_recorder()->find_index((jobject)value);
6490 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6492 __ relocate(rspec);
6493 __ li48(dst, (long)value);
6494 }
6495 } else {
6496 __ set64(dst, (long)value);
6497 }
6498 %}
6500 ins_pipe( ialu_regI_regI );
6501 %}
6503 /*
6504 instruct loadConP_load(mRegP dst, immP_load src) %{
6505 match(Set dst src);
6507 ins_cost(100);
6508 format %{ "ld $dst, [$constanttablebase + $constantoffset] load from constant table: ptr=$src @ loadConP_load" %}
6510 ins_encode %{
6512 int con_offset = $constantoffset($src);
6514 if (Assembler::is_simm16(con_offset)) {
6515 __ ld($dst$$Register, $constanttablebase, con_offset);
6516 } else {
6517 __ set64(AT, con_offset);
6518 if (UseLoongsonISA) {
6519 __ gsldx($dst$$Register, $constanttablebase, AT, 0);
6520 } else {
6521 __ daddu(AT, $constanttablebase, AT);
6522 __ ld($dst$$Register, AT, 0);
6523 }
6524 }
6525 %}
6527 ins_pipe(ialu_loadI);
6528 %}
6529 */
6531 instruct loadConP_no_oop_cheap(mRegP dst, immP_no_oop_cheap src) %{
6532 match(Set dst src);
6534 ins_cost(80);
6535 format %{ "li $dst, $src @ loadConP_no_oop_cheap" %}
6537 ins_encode %{
6538 __ set64($dst$$Register, $src$$constant);
6539 %}
6541 ins_pipe(ialu_regI_regI);
6542 %}
6545 instruct loadConP_poll(mRegP dst, immP_poll src) %{
6546 match(Set dst src);
6548 ins_cost(50);
6549 format %{ "li $dst, $src #@loadConP_poll" %}
6551 ins_encode %{
6552 Register dst = $dst$$Register;
6553 intptr_t value = (intptr_t)$src$$constant;
6555 __ set64(dst, (jlong)value);
6556 %}
6558 ins_pipe( ialu_regI_regI );
6559 %}
6561 instruct loadConP0(mRegP dst, immP0 src)
6562 %{
6563 match(Set dst src);
6565 ins_cost(50);
6566 format %{ "mov $dst, R0\t# ptr" %}
6567 ins_encode %{
6568 Register dst_reg = $dst$$Register;
6569 __ daddu(dst_reg, R0, R0);
6570 %}
6571 ins_pipe( ialu_regI_regI );
6572 %}
6574 instruct loadConN0(mRegN dst, immN0 src) %{
6575 match(Set dst src);
6576 format %{ "move $dst, R0\t# compressed NULL ptr" %}
6577 ins_encode %{
6578 __ move($dst$$Register, R0);
6579 %}
6580 ins_pipe( ialu_regI_regI );
6581 %}
6583 instruct loadConN(mRegN dst, immN src) %{
6584 match(Set dst src);
6586 ins_cost(125);
6587 format %{ "li $dst, $src\t# compressed ptr @ loadConN" %}
6588 ins_encode %{
6589 address con = (address)$src$$constant;
6590 if (con == NULL) {
6591 ShouldNotReachHere();
6592 } else {
6593 assert (UseCompressedOops, "should only be used for compressed headers");
6594 assert (Universe::heap() != NULL, "java heap should be initialized");
6595 assert (__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6597 Register dst = $dst$$Register;
6598 long* value = (long*)$src$$constant;
6599 int oop_index = __ oop_recorder()->find_index((jobject)value);
6600 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6601 if(rspec.type()!=relocInfo::none){
6602 __ relocate(rspec, Assembler::narrow_oop_operand);
6603 __ li48(dst, oop_index);
6604 } else {
6605 __ set64(dst, oop_index);
6606 }
6607 }
6608 %}
6609 ins_pipe( ialu_regI_regI ); // XXX
6610 %}
6612 instruct loadConNKlass(mRegN dst, immNKlass src) %{
6613 match(Set dst src);
6615 ins_cost(125);
6616 format %{ "li $dst, $src\t# compressed klass ptr @ loadConNKlass" %}
6617 ins_encode %{
6618 address con = (address)$src$$constant;
6619 if (con == NULL) {
6620 ShouldNotReachHere();
6621 } else {
6622 Register dst = $dst$$Register;
6623 long* value = (long*)$src$$constant;
6625 int klass_index = __ oop_recorder()->find_index((Klass*)value);
6626 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6627 long narrowp = (long)Klass::encode_klass((Klass*)value);
6629 if(rspec.type()!=relocInfo::none){
6630 __ relocate(rspec, Assembler::narrow_oop_operand);
6631 __ li48(dst, narrowp);
6632 } else {
6633 __ set64(dst, narrowp);
6634 }
6635 }
6636 %}
6637 ins_pipe( ialu_regI_regI ); // XXX
6638 %}
6640 //FIXME
6641 // Tail Call; Jump from runtime stub to Java code.
6642 // Also known as an 'interprocedural jump'.
6643 // Target of jump will eventually return to caller.
6644 // TailJump below removes the return address.
6645 instruct TailCalljmpInd(mRegP jump_target, mRegP method_oop) %{
6646 match(TailCall jump_target method_oop );
6647 ins_cost(300);
6648 format %{ "JMP $jump_target \t# @TailCalljmpInd" %}
6650 ins_encode %{
6651 Register target = $jump_target$$Register;
6652 Register oop = $method_oop$$Register;
6654 /* 2012/10/12 Jin: RA will be used in generate_forward_exception() */
6655 __ push(RA);
6657 __ move(S3, oop);
6658 __ jr(target);
6659 __ nop();
6660 %}
6662 ins_pipe( pipe_jump );
6663 %}
6665 // Create exception oop: created by stack-crawling runtime code.
6666 // Created exception is now available to this handler, and is setup
6667 // just prior to jumping to this handler. No code emitted.
6668 instruct CreateException( a0_RegP ex_oop )
6669 %{
6670 match(Set ex_oop (CreateEx));
6672 // use the following format syntax
6673 format %{ "# exception oop is in A0; no code emitted @CreateException" %}
6674 ins_encode %{
6675 /* Jin: X86 leaves this function empty */
6676 __ block_comment("CreateException is empty in X86/MIPS");
6677 %}
6678 ins_pipe( empty );
6679 // ins_pipe( pipe_jump );
6680 %}
6683 /* 2012/9/14 Jin: The mechanism of exception handling is clear now.
6685 - Common try/catch:
6686 2012/9/14 Jin: [stubGenerator_mips.cpp] generate_forward_exception()
6687 |- V0, V1 are created
6688 |- T9 <= SharedRuntime::exception_handler_for_return_address
6689 `- jr T9
6690 `- the caller's exception_handler
6691 `- jr OptoRuntime::exception_blob
6692 `- here
6693 - Rethrow(e.g. 'unwind'):
6694 * The callee:
6695 |- an exception is triggered during execution
6696 `- exits the callee method through RethrowException node
6697 |- The callee pushes exception_oop(T0) and exception_pc(RA)
6698 `- The callee jumps to OptoRuntime::rethrow_stub()
6699 * In OptoRuntime::rethrow_stub:
6700 |- The VM calls _rethrow_Java to determine the return address in the caller method
6701 `- exits the stub with tailjmpInd
6702 |- pops exception_oop(V0) and exception_pc(V1)
6703 `- jumps to the return address(usually an exception_handler)
6704 * The caller:
6705 `- continues processing the exception_blob with V0/V1
6706 */
6708 /*
6709 Disassembling OptoRuntime::rethrow_stub()
6711 ; locals
6712 0x2d3bf320: addiu sp, sp, 0xfffffff8
6713 0x2d3bf324: sw ra, 0x4(sp)
6714 0x2d3bf328: sw fp, 0x0(sp)
6715 0x2d3bf32c: addu fp, sp, zero
6716 0x2d3bf330: addiu sp, sp, 0xfffffff0
6717 0x2d3bf334: sw ra, 0x8(sp)
6718 0x2d3bf338: sw t0, 0x4(sp)
6719 0x2d3bf33c: sw sp, 0x0(sp)
6721 ; get_thread(S2)
6722 0x2d3bf340: addu s2, sp, zero
6723 0x2d3bf344: srl s2, s2, 12
6724 0x2d3bf348: sll s2, s2, 2
6725 0x2d3bf34c: lui at, 0x2c85
6726 0x2d3bf350: addu at, at, s2
6727 0x2d3bf354: lw s2, 0xffffcc80(at)
6729 0x2d3bf358: lw s0, 0x0(sp)
6730 0x2d3bf35c: sw s0, 0x118(s2) // last_sp -> threa
6731 0x2d3bf360: sw s2, 0xc(sp)
6733 ; OptoRuntime::rethrow_C(oopDesc* exception, JavaThread* thread, address ret_pc)
6734 0x2d3bf364: lw a0, 0x4(sp)
6735 0x2d3bf368: lw a1, 0xc(sp)
6736 0x2d3bf36c: lw a2, 0x8(sp)
6737 ;; Java_To_Runtime
6738 0x2d3bf370: lui t9, 0x2c34
6739 0x2d3bf374: addiu t9, t9, 0xffff8a48
6740 0x2d3bf378: jalr t9
6741 0x2d3bf37c: nop
6743 0x2d3bf380: addu s3, v0, zero ; S3: SharedRuntime::raw_exception_handler_for_return_address()
6745 0x2d3bf384: lw s0, 0xc(sp)
6746 0x2d3bf388: sw zero, 0x118(s0)
6747 0x2d3bf38c: sw zero, 0x11c(s0)
6748 0x2d3bf390: lw s1, 0x144(s0) ; ex_oop: S1
6749 0x2d3bf394: addu s2, s0, zero
6750 0x2d3bf398: sw zero, 0x144(s2)
6751 0x2d3bf39c: lw s0, 0x4(s2)
6752 0x2d3bf3a0: addiu s4, zero, 0x0
6753 0x2d3bf3a4: bne s0, s4, 0x2d3bf3d4
6754 0x2d3bf3a8: nop
6755 0x2d3bf3ac: addiu sp, sp, 0x10
6756 0x2d3bf3b0: addiu sp, sp, 0x8
6757 0x2d3bf3b4: lw ra, 0xfffffffc(sp)
6758 0x2d3bf3b8: lw fp, 0xfffffff8(sp)
6759 0x2d3bf3bc: lui at, 0x2b48
6760 0x2d3bf3c0: lw at, 0x100(at)
6762 ; tailjmpInd: Restores exception_oop & exception_pc
6763 0x2d3bf3c4: addu v1, ra, zero
6764 0x2d3bf3c8: addu v0, s1, zero
6765 0x2d3bf3cc: jr s3
6766 0x2d3bf3d0: nop
6767 ; Exception:
6768 0x2d3bf3d4: lui s1, 0x2cc8 ; generate_forward_exception()
6769 0x2d3bf3d8: addiu s1, s1, 0x40
6770 0x2d3bf3dc: addiu s2, zero, 0x0
6771 0x2d3bf3e0: addiu sp, sp, 0x10
6772 0x2d3bf3e4: addiu sp, sp, 0x8
6773 0x2d3bf3e8: lw ra, 0xfffffffc(sp)
6774 0x2d3bf3ec: lw fp, 0xfffffff8(sp)
6775 0x2d3bf3f0: lui at, 0x2b48
6776 0x2d3bf3f4: lw at, 0x100(at)
6777 ; TailCalljmpInd
6778 __ push(RA); ; to be used in generate_forward_exception()
6779 0x2d3bf3f8: addu t7, s2, zero
6780 0x2d3bf3fc: jr s1
6781 0x2d3bf400: nop
6782 */
6783 // Rethrow exception:
6784 // The exception oop will come in the first argument position.
6785 // Then JUMP (not call) to the rethrow stub code.
6786 instruct RethrowException()
6787 %{
6788 match(Rethrow);
6790 // use the following format syntax
6791 format %{ "JMP rethrow_stub #@RethrowException" %}
6792 ins_encode %{
6793 __ block_comment("@ RethrowException");
6795 cbuf.set_insts_mark();
6796 cbuf.relocate(cbuf.insts_mark(), runtime_call_Relocation::spec());
6798 // call OptoRuntime::rethrow_stub to get the exception handler in parent method
6799 __ li(T9, OptoRuntime::rethrow_stub());
6800 __ jr(T9);
6801 __ nop();
6802 %}
6803 ins_pipe( pipe_jump );
6804 %}
6806 instruct branchConP_zero(cmpOpU cmp, mRegP op1, immP0 zero, label labl) %{
6807 match(If cmp (CmpP op1 zero));
6808 effect(USE labl);
6810 ins_cost(180);
6811 format %{ "b$cmp $op1, R0, $labl #@branchConP_zero" %}
6813 ins_encode %{
6814 Register op1 = $op1$$Register;
6815 Register op2 = R0;
6816 Label &L = *($labl$$label);
6817 int flag = $cmp$$cmpcode;
6819 switch(flag)
6820 {
6821 case 0x01: //equal
6822 if (&L)
6823 __ beq(op1, op2, L);
6824 else
6825 __ beq(op1, op2, (int)0);
6826 break;
6827 case 0x02: //not_equal
6828 if (&L)
6829 __ bne(op1, op2, L);
6830 else
6831 __ bne(op1, op2, (int)0);
6832 break;
6833 /*
6834 case 0x03: //above
6835 __ sltu(AT, op2, op1);
6836 if(&L)
6837 __ bne(R0, AT, L);
6838 else
6839 __ bne(R0, AT, (int)0);
6840 break;
6841 case 0x04: //above_equal
6842 __ sltu(AT, op1, op2);
6843 if(&L)
6844 __ beq(AT, R0, L);
6845 else
6846 __ beq(AT, R0, (int)0);
6847 break;
6848 case 0x05: //below
6849 __ sltu(AT, op1, op2);
6850 if(&L)
6851 __ bne(R0, AT, L);
6852 else
6853 __ bne(R0, AT, (int)0);
6854 break;
6855 case 0x06: //below_equal
6856 __ sltu(AT, op2, op1);
6857 if(&L)
6858 __ beq(AT, R0, L);
6859 else
6860 __ beq(AT, R0, (int)0);
6861 break;
6862 */
6863 default:
6864 Unimplemented();
6865 }
6866 __ nop();
6867 %}
6869 ins_pc_relative(1);
6870 ins_pipe( pipe_alu_branch );
6871 %}
6874 instruct branchConP(cmpOpU cmp, mRegP op1, mRegP op2, label labl) %{
6875 match(If cmp (CmpP op1 op2));
6876 // predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
6877 effect(USE labl);
6879 ins_cost(200);
6880 format %{ "b$cmp $op1, $op2, $labl #@branchConP" %}
6882 ins_encode %{
6883 Register op1 = $op1$$Register;
6884 Register op2 = $op2$$Register;
6885 Label &L = *($labl$$label);
6886 int flag = $cmp$$cmpcode;
6888 switch(flag)
6889 {
6890 case 0x01: //equal
6891 if (&L)
6892 __ beq(op1, op2, L);
6893 else
6894 __ beq(op1, op2, (int)0);
6895 break;
6896 case 0x02: //not_equal
6897 if (&L)
6898 __ bne(op1, op2, L);
6899 else
6900 __ bne(op1, op2, (int)0);
6901 break;
6902 case 0x03: //above
6903 __ sltu(AT, op2, op1);
6904 if(&L)
6905 __ bne(R0, AT, L);
6906 else
6907 __ bne(R0, AT, (int)0);
6908 break;
6909 case 0x04: //above_equal
6910 __ sltu(AT, op1, op2);
6911 if(&L)
6912 __ beq(AT, R0, L);
6913 else
6914 __ beq(AT, R0, (int)0);
6915 break;
6916 case 0x05: //below
6917 __ sltu(AT, op1, op2);
6918 if(&L)
6919 __ bne(R0, AT, L);
6920 else
6921 __ bne(R0, AT, (int)0);
6922 break;
6923 case 0x06: //below_equal
6924 __ sltu(AT, op2, op1);
6925 if(&L)
6926 __ beq(AT, R0, L);
6927 else
6928 __ beq(AT, R0, (int)0);
6929 break;
6930 default:
6931 Unimplemented();
6932 }
6933 __ nop();
6934 %}
6936 ins_pc_relative(1);
6937 ins_pipe( pipe_alu_branch );
6938 %}
6940 instruct cmpN_null_branch(cmpOp cmp, mRegN op1, immN0 null, label labl) %{
6941 match(If cmp (CmpN op1 null));
6942 effect(USE labl);
6944 ins_cost(180);
6945 format %{ "CMP $op1,0\t! compressed ptr\n\t"
6946 "BP$cmp $labl @ cmpN_null_branch" %}
6947 ins_encode %{
6948 Register op1 = $op1$$Register;
6949 Register op2 = R0;
6950 Label &L = *($labl$$label);
6951 int flag = $cmp$$cmpcode;
6953 switch(flag)
6954 {
6955 case 0x01: //equal
6956 if (&L)
6957 __ beq(op1, op2, L);
6958 else
6959 __ beq(op1, op2, (int)0);
6960 break;
6961 case 0x02: //not_equal
6962 if (&L)
6963 __ bne(op1, op2, L);
6964 else
6965 __ bne(op1, op2, (int)0);
6966 break;
6967 default:
6968 Unimplemented();
6969 }
6970 __ nop();
6971 %}
6972 //TODO: pipe_branchP or create pipe_branchN LEE
6973 ins_pc_relative(1);
6974 ins_pipe( pipe_alu_branch );
6975 %}
6977 instruct cmpN_reg_branch(cmpOp cmp, mRegN op1, mRegN op2, label labl) %{
6978 match(If cmp (CmpN op1 op2));
6979 effect(USE labl);
6981 ins_cost(180);
6982 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
6983 "BP$cmp $labl" %}
6984 ins_encode %{
6985 Register op1_reg = $op1$$Register;
6986 Register op2_reg = $op2$$Register;
6987 Label &L = *($labl$$label);
6988 int flag = $cmp$$cmpcode;
6990 switch(flag)
6991 {
6992 case 0x01: //equal
6993 if (&L)
6994 __ beq(op1_reg, op2_reg, L);
6995 else
6996 __ beq(op1_reg, op2_reg, (int)0);
6997 break;
6998 case 0x02: //not_equal
6999 if (&L)
7000 __ bne(op1_reg, op2_reg, L);
7001 else
7002 __ bne(op1_reg, op2_reg, (int)0);
7003 break;
7004 case 0x03: //above
7005 __ sltu(AT, op2_reg, op1_reg);
7006 if(&L)
7007 __ bne(R0, AT, L);
7008 else
7009 __ bne(R0, AT, (int)0);
7010 break;
7011 case 0x04: //above_equal
7012 __ sltu(AT, op1_reg, op2_reg);
7013 if(&L)
7014 __ beq(AT, R0, L);
7015 else
7016 __ beq(AT, R0, (int)0);
7017 break;
7018 case 0x05: //below
7019 __ sltu(AT, op1_reg, op2_reg);
7020 if(&L)
7021 __ bne(R0, AT, L);
7022 else
7023 __ bne(R0, AT, (int)0);
7024 break;
7025 case 0x06: //below_equal
7026 __ sltu(AT, op2_reg, op1_reg);
7027 if(&L)
7028 __ beq(AT, R0, L);
7029 else
7030 __ beq(AT, R0, (int)0);
7031 break;
7032 default:
7033 Unimplemented();
7034 }
7035 __ nop();
7036 %}
7037 ins_pc_relative(1);
7038 ins_pipe( pipe_alu_branch );
7039 %}
7041 instruct branchConIU_reg_reg(cmpOpU cmp, mRegI src1, mRegI src2, label labl) %{
7042 match( If cmp (CmpU src1 src2) );
7043 effect(USE labl);
7044 format %{ "BR$cmp $src1, $src2, $labl #@branchConIU_reg_reg" %}
7046 ins_encode %{
7047 Register op1 = $src1$$Register;
7048 Register op2 = $src2$$Register;
7049 Label &L = *($labl$$label);
7050 int flag = $cmp$$cmpcode;
7052 switch(flag)
7053 {
7054 case 0x01: //equal
7055 if (&L)
7056 __ beq(op1, op2, L);
7057 else
7058 __ beq(op1, op2, (int)0);
7059 break;
7060 case 0x02: //not_equal
7061 if (&L)
7062 __ bne(op1, op2, L);
7063 else
7064 __ bne(op1, op2, (int)0);
7065 break;
7066 case 0x03: //above
7067 __ sltu(AT, op2, op1);
7068 if(&L)
7069 __ bne(AT, R0, L);
7070 else
7071 __ bne(AT, R0, (int)0);
7072 break;
7073 case 0x04: //above_equal
7074 __ sltu(AT, op1, op2);
7075 if(&L)
7076 __ beq(AT, R0, L);
7077 else
7078 __ beq(AT, R0, (int)0);
7079 break;
7080 case 0x05: //below
7081 __ sltu(AT, op1, op2);
7082 if(&L)
7083 __ bne(AT, R0, L);
7084 else
7085 __ bne(AT, R0, (int)0);
7086 break;
7087 case 0x06: //below_equal
7088 __ sltu(AT, op2, op1);
7089 if(&L)
7090 __ beq(AT, R0, L);
7091 else
7092 __ beq(AT, R0, (int)0);
7093 break;
7094 default:
7095 Unimplemented();
7096 }
7097 __ nop();
7098 %}
7100 ins_pc_relative(1);
7101 ins_pipe( pipe_alu_branch );
7102 %}
7105 instruct branchConIU_reg_imm(cmpOpU cmp, mRegI src1, immI src2, label labl) %{
7106 match( If cmp (CmpU src1 src2) );
7107 effect(USE labl);
7108 format %{ "BR$cmp $src1, $src2, $labl #@branchConIU_reg_imm" %}
7110 ins_encode %{
7111 Register op1 = $src1$$Register;
7112 int val = $src2$$constant;
7113 Label &L = *($labl$$label);
7114 int flag = $cmp$$cmpcode;
7116 __ move(AT, val);
7117 switch(flag)
7118 {
7119 case 0x01: //equal
7120 if (&L)
7121 __ beq(op1, AT, L);
7122 else
7123 __ beq(op1, AT, (int)0);
7124 break;
7125 case 0x02: //not_equal
7126 if (&L)
7127 __ bne(op1, AT, L);
7128 else
7129 __ bne(op1, AT, (int)0);
7130 break;
7131 case 0x03: //above
7132 __ sltu(AT, AT, op1);
7133 if(&L)
7134 __ bne(R0, AT, L);
7135 else
7136 __ bne(R0, AT, (int)0);
7137 break;
7138 case 0x04: //above_equal
7139 __ sltu(AT, op1, AT);
7140 if(&L)
7141 __ beq(AT, R0, L);
7142 else
7143 __ beq(AT, R0, (int)0);
7144 break;
7145 case 0x05: //below
7146 __ sltu(AT, op1, AT);
7147 if(&L)
7148 __ bne(R0, AT, L);
7149 else
7150 __ bne(R0, AT, (int)0);
7151 break;
7152 case 0x06: //below_equal
7153 __ sltu(AT, AT, op1);
7154 if(&L)
7155 __ beq(AT, R0, L);
7156 else
7157 __ beq(AT, R0, (int)0);
7158 break;
7159 default:
7160 Unimplemented();
7161 }
7162 __ nop();
7163 %}
7165 ins_pc_relative(1);
7166 ins_pipe( pipe_alu_branch );
7167 %}
7169 instruct branchConI_reg_reg(cmpOp cmp, mRegI src1, mRegI src2, label labl) %{
7170 match( If cmp (CmpI src1 src2) );
7171 effect(USE labl);
7172 format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_reg" %}
7174 ins_encode %{
7175 Register op1 = $src1$$Register;
7176 Register op2 = $src2$$Register;
7177 Label &L = *($labl$$label);
7178 int flag = $cmp$$cmpcode;
7180 switch(flag)
7181 {
7182 case 0x01: //equal
7183 if (&L)
7184 __ beq(op1, op2, L);
7185 else
7186 __ beq(op1, op2, (int)0);
7187 break;
7188 case 0x02: //not_equal
7189 if (&L)
7190 __ bne(op1, op2, L);
7191 else
7192 __ bne(op1, op2, (int)0);
7193 break;
7194 case 0x03: //above
7195 __ slt(AT, op2, op1);
7196 if(&L)
7197 __ bne(R0, AT, L);
7198 else
7199 __ bne(R0, AT, (int)0);
7200 break;
7201 case 0x04: //above_equal
7202 __ slt(AT, op1, op2);
7203 if(&L)
7204 __ beq(AT, R0, L);
7205 else
7206 __ beq(AT, R0, (int)0);
7207 break;
7208 case 0x05: //below
7209 __ slt(AT, op1, op2);
7210 if(&L)
7211 __ bne(R0, AT, L);
7212 else
7213 __ bne(R0, AT, (int)0);
7214 break;
7215 case 0x06: //below_equal
7216 __ slt(AT, op2, op1);
7217 if(&L)
7218 __ beq(AT, R0, L);
7219 else
7220 __ beq(AT, R0, (int)0);
7221 break;
7222 default:
7223 Unimplemented();
7224 }
7225 __ nop();
7226 %}
7228 ins_pc_relative(1);
7229 ins_pipe( pipe_alu_branch );
7230 %}
7232 instruct branchConI_reg_imm0(cmpOp cmp, mRegI src1, immI0 src2, label labl) %{
7233 match( If cmp (CmpI src1 src2) );
7234 effect(USE labl);
7235 ins_cost(170);
7236 format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_imm0" %}
7238 ins_encode %{
7239 Register op1 = $src1$$Register;
7240 // int val = $src2$$constant;
7241 Label &L = *($labl$$label);
7242 int flag = $cmp$$cmpcode;
7244 //__ move(AT, val);
7245 switch(flag)
7246 {
7247 case 0x01: //equal
7248 if (&L)
7249 __ beq(op1, R0, L);
7250 else
7251 __ beq(op1, R0, (int)0);
7252 break;
7253 case 0x02: //not_equal
7254 if (&L)
7255 __ bne(op1, R0, L);
7256 else
7257 __ bne(op1, R0, (int)0);
7258 break;
7259 case 0x03: //greater
7260 if(&L)
7261 __ bgtz(op1, L);
7262 else
7263 __ bgtz(op1, (int)0);
7264 break;
7265 case 0x04: //greater_equal
7266 if(&L)
7267 __ bgez(op1, L);
7268 else
7269 __ bgez(op1, (int)0);
7270 break;
7271 case 0x05: //less
7272 if(&L)
7273 __ bltz(op1, L);
7274 else
7275 __ bltz(op1, (int)0);
7276 break;
7277 case 0x06: //less_equal
7278 if(&L)
7279 __ blez(op1, L);
7280 else
7281 __ blez(op1, (int)0);
7282 break;
7283 default:
7284 Unimplemented();
7285 }
7286 __ nop();
7287 %}
7289 ins_pc_relative(1);
7290 ins_pipe( pipe_alu_branch );
7291 %}
7294 instruct branchConI_reg_imm(cmpOp cmp, mRegI src1, immI src2, label labl) %{
7295 match( If cmp (CmpI src1 src2) );
7296 effect(USE labl);
7297 ins_cost(200);
7298 format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_imm" %}
7300 ins_encode %{
7301 Register op1 = $src1$$Register;
7302 int val = $src2$$constant;
7303 Label &L = *($labl$$label);
7304 int flag = $cmp$$cmpcode;
7306 __ move(AT, val);
7307 switch(flag)
7308 {
7309 case 0x01: //equal
7310 if (&L)
7311 __ beq(op1, AT, L);
7312 else
7313 __ beq(op1, AT, (int)0);
7314 break;
7315 case 0x02: //not_equal
7316 if (&L)
7317 __ bne(op1, AT, L);
7318 else
7319 __ bne(op1, AT, (int)0);
7320 break;
7321 case 0x03: //greater
7322 __ slt(AT, AT, op1);
7323 if(&L)
7324 __ bne(R0, AT, L);
7325 else
7326 __ bne(R0, AT, (int)0);
7327 break;
7328 case 0x04: //greater_equal
7329 __ slt(AT, op1, AT);
7330 if(&L)
7331 __ beq(AT, R0, L);
7332 else
7333 __ beq(AT, R0, (int)0);
7334 break;
7335 case 0x05: //less
7336 __ slt(AT, op1, AT);
7337 if(&L)
7338 __ bne(R0, AT, L);
7339 else
7340 __ bne(R0, AT, (int)0);
7341 break;
7342 case 0x06: //less_equal
7343 __ slt(AT, AT, op1);
7344 if(&L)
7345 __ beq(AT, R0, L);
7346 else
7347 __ beq(AT, R0, (int)0);
7348 break;
7349 default:
7350 Unimplemented();
7351 }
7352 __ nop();
7353 %}
7355 ins_pc_relative(1);
7356 ins_pipe( pipe_alu_branch );
7357 %}
7359 instruct branchConIU_reg_imm0(cmpOpU cmp, mRegI src1, immI0 zero, label labl) %{
7360 match( If cmp (CmpU src1 zero) );
7361 effect(USE labl);
7362 format %{ "BR$cmp $src1, zero, $labl #@branchConIU_reg_imm0" %}
7364 ins_encode %{
7365 Register op1 = $src1$$Register;
7366 Label &L = *($labl$$label);
7367 int flag = $cmp$$cmpcode;
7369 switch(flag)
7370 {
7371 case 0x01: //equal
7372 if (&L)
7373 __ beq(op1, R0, L);
7374 else
7375 __ beq(op1, R0, (int)0);
7376 break;
7377 case 0x02: //not_equal
7378 if (&L)
7379 __ bne(op1, R0, L);
7380 else
7381 __ bne(op1, R0, (int)0);
7382 break;
7383 case 0x03: //above
7384 if(&L)
7385 __ bne(R0, op1, L);
7386 else
7387 __ bne(R0, op1, (int)0);
7388 break;
7389 case 0x04: //above_equal
7390 if(&L)
7391 __ beq(R0, R0, L);
7392 else
7393 __ beq(R0, R0, (int)0);
7394 break;
7395 case 0x05: //below
7396 return;
7397 break;
7398 case 0x06: //below_equal
7399 if(&L)
7400 __ beq(op1, R0, L);
7401 else
7402 __ beq(op1, R0, (int)0);
7403 break;
7404 default:
7405 Unimplemented();
7406 }
7407 __ nop();
7408 %}
7410 ins_pc_relative(1);
7411 ins_pipe( pipe_alu_branch );
7412 %}
7415 instruct branchConIU_reg_immI16(cmpOpU cmp, mRegI src1, immI16 src2, label labl) %{
7416 match( If cmp (CmpU src1 src2) );
7417 effect(USE labl);
7418 ins_cost(180);
7419 format %{ "BR$cmp $src1, $src2, $labl #@branchConIU_reg_immI16" %}
7421 ins_encode %{
7422 Register op1 = $src1$$Register;
7423 int val = $src2$$constant;
7424 Label &L = *($labl$$label);
7425 int flag = $cmp$$cmpcode;
7427 switch(flag)
7428 {
7429 case 0x01: //equal
7430 __ move(AT, val);
7431 if (&L)
7432 __ beq(op1, AT, L);
7433 else
7434 __ beq(op1, AT, (int)0);
7435 break;
7436 case 0x02: //not_equal
7437 __ move(AT, val);
7438 if (&L)
7439 __ bne(op1, AT, L);
7440 else
7441 __ bne(op1, AT, (int)0);
7442 break;
7443 case 0x03: //above
7444 __ move(AT, val);
7445 __ sltu(AT, AT, op1);
7446 if(&L)
7447 __ bne(R0, AT, L);
7448 else
7449 __ bne(R0, AT, (int)0);
7450 break;
7451 case 0x04: //above_equal
7452 __ sltiu(AT, op1, val);
7453 if(&L)
7454 __ beq(AT, R0, L);
7455 else
7456 __ beq(AT, R0, (int)0);
7457 break;
7458 case 0x05: //below
7459 __ sltiu(AT, op1, val);
7460 if(&L)
7461 __ bne(R0, AT, L);
7462 else
7463 __ bne(R0, AT, (int)0);
7464 break;
7465 case 0x06: //below_equal
7466 __ move(AT, val);
7467 __ sltu(AT, AT, op1);
7468 if(&L)
7469 __ beq(AT, R0, L);
7470 else
7471 __ beq(AT, R0, (int)0);
7472 break;
7473 default:
7474 Unimplemented();
7475 }
7476 __ nop();
7477 %}
7479 ins_pc_relative(1);
7480 ins_pipe( pipe_alu_branch );
7481 %}
7484 instruct branchConL_regL_regL(cmpOp cmp, mRegL src1, mRegL src2, label labl) %{
7485 match( If cmp (CmpL src1 src2) );
7486 effect(USE labl);
7487 format %{ "BR$cmp $src1, $src2, $labl #@branchConL_regL_regL" %}
7488 ins_cost(250);
7490 ins_encode %{
7491 Register opr1_reg = as_Register($src1$$reg);
7492 Register opr2_reg = as_Register($src2$$reg);
7494 Label &target = *($labl$$label);
7495 int flag = $cmp$$cmpcode;
7497 switch(flag)
7498 {
7499 case 0x01: //equal
7500 if (&target)
7501 __ beq(opr1_reg, opr2_reg, target);
7502 else
7503 __ beq(opr1_reg, opr2_reg, (int)0);
7504 __ delayed()->nop();
7505 break;
7507 case 0x02: //not_equal
7508 if(&target)
7509 __ bne(opr1_reg, opr2_reg, target);
7510 else
7511 __ bne(opr1_reg, opr2_reg, (int)0);
7512 __ delayed()->nop();
7513 break;
7515 case 0x03: //greater
7516 __ slt(AT, opr2_reg, opr1_reg);
7517 if(&target)
7518 __ bne(AT, R0, target);
7519 else
7520 __ bne(AT, R0, (int)0);
7521 __ delayed()->nop();
7522 break;
7524 case 0x04: //greater_equal
7525 __ slt(AT, opr1_reg, opr2_reg);
7526 if(&target)
7527 __ beq(AT, R0, target);
7528 else
7529 __ beq(AT, R0, (int)0);
7530 __ delayed()->nop();
7532 break;
7534 case 0x05: //less
7535 __ slt(AT, opr1_reg, opr2_reg);
7536 if(&target)
7537 __ bne(AT, R0, target);
7538 else
7539 __ bne(AT, R0, (int)0);
7540 __ delayed()->nop();
7542 break;
7544 case 0x06: //less_equal
7545 __ slt(AT, opr2_reg, opr1_reg);
7547 if(&target)
7548 __ beq(AT, R0, target);
7549 else
7550 __ beq(AT, R0, (int)0);
7551 __ delayed()->nop();
7553 break;
7555 default:
7556 Unimplemented();
7557 }
7558 %}
7561 ins_pc_relative(1);
7562 ins_pipe( pipe_alu_branch );
7563 %}
7565 instruct branchConL_reg_immL16_sub(cmpOp cmp, mRegL src1, immL16_sub src2, label labl) %{
7566 match( If cmp (CmpL src1 src2) );
7567 effect(USE labl);
7568 ins_cost(180);
7569 format %{ "BR$cmp $src1, $src2, $labl #@branchConL_reg_immL16_sub" %}
7571 ins_encode %{
7572 Register op1 = $src1$$Register;
7573 int val = $src2$$constant;
7574 Label &L = *($labl$$label);
7575 int flag = $cmp$$cmpcode;
7577 __ daddiu(AT, op1, -1 * val);
7578 switch(flag)
7579 {
7580 case 0x01: //equal
7581 if (&L)
7582 __ beq(R0, AT, L);
7583 else
7584 __ beq(R0, AT, (int)0);
7585 break;
7586 case 0x02: //not_equal
7587 if (&L)
7588 __ bne(R0, AT, L);
7589 else
7590 __ bne(R0, AT, (int)0);
7591 break;
7592 case 0x03: //greater
7593 if(&L)
7594 __ bgtz(AT, L);
7595 else
7596 __ bgtz(AT, (int)0);
7597 break;
7598 case 0x04: //greater_equal
7599 if(&L)
7600 __ bgez(AT, L);
7601 else
7602 __ bgez(AT, (int)0);
7603 break;
7604 case 0x05: //less
7605 if(&L)
7606 __ bltz(AT, L);
7607 else
7608 __ bltz(AT, (int)0);
7609 break;
7610 case 0x06: //less_equal
7611 if(&L)
7612 __ blez(AT, L);
7613 else
7614 __ blez(AT, (int)0);
7615 break;
7616 default:
7617 Unimplemented();
7618 }
7619 __ nop();
7620 %}
7622 ins_pc_relative(1);
7623 ins_pipe( pipe_alu_branch );
7624 %}
7627 instruct branchConI_reg_imm16_sub(cmpOp cmp, mRegI src1, immI16_sub src2, label labl) %{
7628 match( If cmp (CmpI src1 src2) );
7629 effect(USE labl);
7630 ins_cost(180);
7631 format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_imm16_sub" %}
7633 ins_encode %{
7634 Register op1 = $src1$$Register;
7635 int val = $src2$$constant;
7636 Label &L = *($labl$$label);
7637 int flag = $cmp$$cmpcode;
7639 __ addiu32(AT, op1, -1 * val);
7640 switch(flag)
7641 {
7642 case 0x01: //equal
7643 if (&L)
7644 __ beq(R0, AT, L);
7645 else
7646 __ beq(R0, AT, (int)0);
7647 break;
7648 case 0x02: //not_equal
7649 if (&L)
7650 __ bne(R0, AT, L);
7651 else
7652 __ bne(R0, AT, (int)0);
7653 break;
7654 case 0x03: //greater
7655 if(&L)
7656 __ bgtz(AT, L);
7657 else
7658 __ bgtz(AT, (int)0);
7659 break;
7660 case 0x04: //greater_equal
7661 if(&L)
7662 __ bgez(AT, L);
7663 else
7664 __ bgez(AT, (int)0);
7665 break;
7666 case 0x05: //less
7667 if(&L)
7668 __ bltz(AT, L);
7669 else
7670 __ bltz(AT, (int)0);
7671 break;
7672 case 0x06: //less_equal
7673 if(&L)
7674 __ blez(AT, L);
7675 else
7676 __ blez(AT, (int)0);
7677 break;
7678 default:
7679 Unimplemented();
7680 }
7681 __ nop();
7682 %}
7684 ins_pc_relative(1);
7685 ins_pipe( pipe_alu_branch );
7686 %}
7688 instruct branchConL_regL_immL0(cmpOp cmp, mRegL src1, immL0 zero, label labl) %{
7689 match( If cmp (CmpL src1 zero) );
7690 effect(USE labl);
7691 format %{ "BR$cmp $src1, zero, $labl #@branchConL_regL_immL0" %}
7692 ins_cost(150);
7694 ins_encode %{
7695 Register opr1_reg = as_Register($src1$$reg);
7696 Label &target = *($labl$$label);
7697 int flag = $cmp$$cmpcode;
7699 switch(flag)
7700 {
7701 case 0x01: //equal
7702 if (&target)
7703 __ beq(opr1_reg, R0, target);
7704 else
7705 __ beq(opr1_reg, R0, int(0));
7706 break;
7708 case 0x02: //not_equal
7709 if(&target)
7710 __ bne(opr1_reg, R0, target);
7711 else
7712 __ bne(opr1_reg, R0, (int)0);
7713 break;
7715 case 0x03: //greater
7716 if(&target)
7717 __ bgtz(opr1_reg, target);
7718 else
7719 __ bgtz(opr1_reg, (int)0);
7720 break;
7722 case 0x04: //greater_equal
7723 if(&target)
7724 __ bgez(opr1_reg, target);
7725 else
7726 __ bgez(opr1_reg, (int)0);
7727 break;
7729 case 0x05: //less
7730 __ slt(AT, opr1_reg, R0);
7731 if(&target)
7732 __ bne(AT, R0, target);
7733 else
7734 __ bne(AT, R0, (int)0);
7735 break;
7737 case 0x06: //less_equal
7738 if (&target)
7739 __ blez(opr1_reg, target);
7740 else
7741 __ blez(opr1_reg, int(0));
7742 break;
7744 default:
7745 Unimplemented();
7746 }
7747 __ delayed()->nop();
7748 %}
7751 ins_pc_relative(1);
7752 ins_pipe( pipe_alu_branch );
7753 %}
7756 //FIXME
7757 instruct branchConF_reg_reg(cmpOp cmp, regF src1, regF src2, label labl) %{
7758 match( If cmp (CmpF src1 src2) );
7759 effect(USE labl);
7760 format %{ "BR$cmp $src1, $src2, $labl #@branchConF_reg_reg" %}
7762 ins_encode %{
7763 FloatRegister reg_op1 = $src1$$FloatRegister;
7764 FloatRegister reg_op2 = $src2$$FloatRegister;
7765 Label &L = *($labl$$label);
7766 int flag = $cmp$$cmpcode;
7768 switch(flag)
7769 {
7770 case 0x01: //equal
7771 __ c_eq_s(reg_op1, reg_op2);
7772 if (&L)
7773 __ bc1t(L);
7774 else
7775 __ bc1t((int)0);
7776 break;
7777 case 0x02: //not_equal
7778 __ c_eq_s(reg_op1, reg_op2);
7779 if (&L)
7780 __ bc1f(L);
7781 else
7782 __ bc1f((int)0);
7783 break;
7784 case 0x03: //greater
7785 __ c_ule_s(reg_op1, reg_op2);
7786 if(&L)
7787 __ bc1f(L);
7788 else
7789 __ bc1f((int)0);
7790 break;
7791 case 0x04: //greater_equal
7792 __ c_ult_s(reg_op1, reg_op2);
7793 if(&L)
7794 __ bc1f(L);
7795 else
7796 __ bc1f((int)0);
7797 break;
7798 case 0x05: //less
7799 __ c_ult_s(reg_op1, reg_op2);
7800 if(&L)
7801 __ bc1t(L);
7802 else
7803 __ bc1t((int)0);
7804 break;
7805 case 0x06: //less_equal
7806 __ c_ule_s(reg_op1, reg_op2);
7807 if(&L)
7808 __ bc1t(L);
7809 else
7810 __ bc1t((int)0);
7811 break;
7812 default:
7813 Unimplemented();
7814 }
7815 __ nop();
7816 %}
7818 ins_pc_relative(1);
7819 ins_pipe(pipe_slow);
7820 %}
7822 instruct branchConD_reg_reg(cmpOp cmp, regD src1, regD src2, label labl) %{
7823 match( If cmp (CmpD src1 src2) );
7824 effect(USE labl);
7825 format %{ "BR$cmp $src1, $src2, $labl #@branchConD_reg_reg" %}
7827 ins_encode %{
7828 FloatRegister reg_op1 = $src1$$FloatRegister;
7829 FloatRegister reg_op2 = $src2$$FloatRegister;
7830 Label &L = *($labl$$label);
7831 int flag = $cmp$$cmpcode;
7833 switch(flag)
7834 {
7835 case 0x01: //equal
7836 __ c_eq_d(reg_op1, reg_op2);
7837 if (&L)
7838 __ bc1t(L);
7839 else
7840 __ bc1t((int)0);
7841 break;
7842 case 0x02: //not_equal
7843 //2016/4/19 aoqi: c_ueq_d cannot distinguish NaN from equal. Double.isNaN(Double) is implemented by 'f != f', so the use of c_ueq_d causes bugs.
7844 __ c_eq_d(reg_op1, reg_op2);
7845 if (&L)
7846 __ bc1f(L);
7847 else
7848 __ bc1f((int)0);
7849 break;
7850 case 0x03: //greater
7851 __ c_ule_d(reg_op1, reg_op2);
7852 if(&L)
7853 __ bc1f(L);
7854 else
7855 __ bc1f((int)0);
7856 break;
7857 case 0x04: //greater_equal
7858 __ c_ult_d(reg_op1, reg_op2);
7859 if(&L)
7860 __ bc1f(L);
7861 else
7862 __ bc1f((int)0);
7863 break;
7864 case 0x05: //less
7865 __ c_ult_d(reg_op1, reg_op2);
7866 if(&L)
7867 __ bc1t(L);
7868 else
7869 __ bc1t((int)0);
7870 break;
7871 case 0x06: //less_equal
7872 __ c_ule_d(reg_op1, reg_op2);
7873 if(&L)
7874 __ bc1t(L);
7875 else
7876 __ bc1t((int)0);
7877 break;
7878 default:
7879 Unimplemented();
7880 }
7881 __ nop();
7882 %}
7884 ins_pc_relative(1);
7885 ins_pipe(pipe_slow);
7886 %}
7889 // Call Runtime Instruction
7890 instruct CallRuntimeDirect(method meth) %{
7891 match(CallRuntime );
7892 effect(USE meth);
7894 ins_cost(300);
7895 format %{ "CALL,runtime #@CallRuntimeDirect" %}
7896 ins_encode( Java_To_Runtime( meth ) );
7897 ins_pipe( pipe_slow );
7898 ins_alignment(16);
7899 %}
7903 //------------------------MemBar Instructions-------------------------------
7904 //Memory barrier flavors
7906 instruct membar_acquire() %{
7907 match(MemBarAcquire);
7908 ins_cost(0);
7910 size(0);
7911 format %{ "MEMBAR-acquire (empty) @ membar_acquire" %}
7912 ins_encode();
7913 ins_pipe(empty);
7914 %}
7916 instruct load_fence() %{
7917 match(LoadFence);
7918 ins_cost(400);
7920 format %{ "MEMBAR @ load_fence" %}
7921 ins_encode %{
7922 __ sync();
7923 %}
7924 ins_pipe(pipe_slow);
7925 %}
7927 instruct membar_acquire_lock()
7928 %{
7929 match(MemBarAcquireLock);
7930 ins_cost(0);
7932 size(0);
7933 format %{ "MEMBAR-acquire (acquire as part of CAS in prior FastLock so empty encoding) @ membar_acquire_lock" %}
7934 ins_encode();
7935 ins_pipe(empty);
7936 %}
7938 instruct membar_release() %{
7939 match(MemBarRelease);
7940 ins_cost(0);
7942 size(0);
7943 format %{ "MEMBAR-release (empty) @ membar_release" %}
7944 ins_encode();
7945 ins_pipe(empty);
7946 %}
7948 instruct store_fence() %{
7949 match(StoreFence);
7950 ins_cost(400);
7952 format %{ "MEMBAR @ store_fence" %}
7954 ins_encode %{
7955 __ sync();
7956 %}
7958 ins_pipe(pipe_slow);
7959 %}
7961 instruct membar_release_lock()
7962 %{
7963 match(MemBarReleaseLock);
7964 ins_cost(0);
7966 size(0);
7967 format %{ "MEMBAR-release-lock (release in FastUnlock so empty) @ membar_release_lock" %}
7968 ins_encode();
7969 ins_pipe(empty);
7970 %}
7973 instruct membar_volatile() %{
7974 match(MemBarVolatile);
7975 ins_cost(400);
7977 format %{ "MEMBAR-volatile" %}
7978 ins_encode %{
7979 if( !os::is_MP() ) return; // Not needed on single CPU
7980 __ sync();
7982 %}
7983 ins_pipe(pipe_slow);
7984 %}
7986 instruct unnecessary_membar_volatile() %{
7987 match(MemBarVolatile);
7988 predicate(Matcher::post_store_load_barrier(n));
7989 ins_cost(0);
7991 size(0);
7992 format %{ "MEMBAR-volatile (unnecessary so empty encoding) @ unnecessary_membar_volatile" %}
7993 ins_encode( );
7994 ins_pipe(empty);
7995 %}
7997 instruct membar_storestore() %{
7998 match(MemBarStoreStore);
8000 ins_cost(0);
8001 size(0);
8002 format %{ "MEMBAR-storestore (empty encoding) @ membar_storestore" %}
8003 ins_encode( );
8004 ins_pipe(empty);
8005 %}
8007 //----------Move Instructions--------------------------------------------------
8008 instruct castX2P(mRegP dst, mRegL src) %{
8009 match(Set dst (CastX2P src));
8010 format %{ "castX2P $dst, $src @ castX2P" %}
8011 ins_encode %{
8012 Register src = $src$$Register;
8013 Register dst = $dst$$Register;
8015 if(src != dst)
8016 __ move(dst, src);
8017 %}
8018 ins_cost(10);
8019 ins_pipe( ialu_regI_mov );
8020 %}
8022 instruct castP2X(mRegL dst, mRegP src ) %{
8023 match(Set dst (CastP2X src));
8025 format %{ "mov $dst, $src\t #@castP2X" %}
8026 ins_encode %{
8027 Register src = $src$$Register;
8028 Register dst = $dst$$Register;
8030 if(src != dst)
8031 __ move(dst, src);
8032 %}
8033 ins_pipe( ialu_regI_mov );
8034 %}
8036 instruct MoveF2I_reg_reg(mRegI dst, regF src) %{
8037 match(Set dst (MoveF2I src));
8038 effect(DEF dst, USE src);
8039 ins_cost(85);
8040 format %{ "MoveF2I $dst, $src @ MoveF2I_reg_reg" %}
8041 ins_encode %{
8042 Register dst = as_Register($dst$$reg);
8043 FloatRegister src = as_FloatRegister($src$$reg);
8045 __ mfc1(dst, src);
8046 %}
8047 ins_pipe( pipe_slow );
8048 %}
8050 instruct MoveI2F_reg_reg(regF dst, mRegI src) %{
8051 match(Set dst (MoveI2F src));
8052 effect(DEF dst, USE src);
8053 ins_cost(85);
8054 format %{ "MoveI2F $dst, $src @ MoveI2F_reg_reg" %}
8055 ins_encode %{
8056 Register src = as_Register($src$$reg);
8057 FloatRegister dst = as_FloatRegister($dst$$reg);
8059 __ mtc1(src, dst);
8060 %}
8061 ins_pipe( pipe_slow );
8062 %}
8064 instruct MoveD2L_reg_reg(mRegL dst, regD src) %{
8065 match(Set dst (MoveD2L src));
8066 effect(DEF dst, USE src);
8067 ins_cost(85);
8068 format %{ "MoveD2L $dst, $src @ MoveD2L_reg_reg" %}
8069 ins_encode %{
8070 Register dst = as_Register($dst$$reg);
8071 FloatRegister src = as_FloatRegister($src$$reg);
8073 __ dmfc1(dst, src);
8074 %}
8075 ins_pipe( pipe_slow );
8076 %}
8078 instruct MoveL2D_reg_reg(regD dst, mRegL src) %{
8079 match(Set dst (MoveL2D src));
8080 effect(DEF dst, USE src);
8081 ins_cost(85);
8082 format %{ "MoveL2D $dst, $src @ MoveL2D_reg_reg" %}
8083 ins_encode %{
8084 FloatRegister dst = as_FloatRegister($dst$$reg);
8085 Register src = as_Register($src$$reg);
8087 __ dmtc1(src, dst);
8088 %}
8089 ins_pipe( pipe_slow );
8090 %}
8092 //----------Conditional Move---------------------------------------------------
8093 // Conditional move
8094 instruct cmovI_cmpI_reg_reg(mRegI dst, mRegI src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
8095 match(Set dst (CMoveI (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
8096 ins_cost(80);
8097 format %{
8098 "CMP$cop $tmp1, $tmp2\t @cmovI_cmpI_reg_reg\n"
8099 "\tCMOV $dst,$src \t @cmovI_cmpI_reg_reg"
8100 %}
8102 ins_encode %{
8103 Register op1 = $tmp1$$Register;
8104 Register op2 = $tmp2$$Register;
8105 Register dst = $dst$$Register;
8106 Register src = $src$$Register;
8107 int flag = $cop$$cmpcode;
8109 switch(flag)
8110 {
8111 case 0x01: //equal
8112 __ subu32(AT, op1, op2);
8113 __ movz(dst, src, AT);
8114 break;
8116 case 0x02: //not_equal
8117 __ subu32(AT, op1, op2);
8118 __ movn(dst, src, AT);
8119 break;
8121 case 0x03: //great
8122 __ slt(AT, op2, op1);
8123 __ movn(dst, src, AT);
8124 break;
8126 case 0x04: //great_equal
8127 __ slt(AT, op1, op2);
8128 __ movz(dst, src, AT);
8129 break;
8131 case 0x05: //less
8132 __ slt(AT, op1, op2);
8133 __ movn(dst, src, AT);
8134 break;
8136 case 0x06: //less_equal
8137 __ slt(AT, op2, op1);
8138 __ movz(dst, src, AT);
8139 break;
8141 default:
8142 Unimplemented();
8143 }
8144 %}
8146 ins_pipe( pipe_slow );
8147 %}
8149 instruct cmovI_cmpP_reg_reg(mRegI dst, mRegI src, mRegP tmp1, mRegP tmp2, cmpOpU cop ) %{
8150 match(Set dst (CMoveI (Binary cop (CmpP tmp1 tmp2)) (Binary dst src)));
8151 ins_cost(80);
8152 format %{
8153 "CMPU$cop $tmp1,$tmp2\t @cmovI_cmpP_reg_reg\n\t"
8154 "CMOV $dst,$src\t @cmovI_cmpP_reg_reg"
8155 %}
8156 ins_encode %{
8157 Register op1 = $tmp1$$Register;
8158 Register op2 = $tmp2$$Register;
8159 Register dst = $dst$$Register;
8160 Register src = $src$$Register;
8161 int flag = $cop$$cmpcode;
8163 switch(flag)
8164 {
8165 case 0x01: //equal
8166 __ subu(AT, op1, op2);
8167 __ movz(dst, src, AT);
8168 break;
8170 case 0x02: //not_equal
8171 __ subu(AT, op1, op2);
8172 __ movn(dst, src, AT);
8173 break;
8175 case 0x03: //above
8176 __ sltu(AT, op2, op1);
8177 __ movn(dst, src, AT);
8178 break;
8180 case 0x04: //above_equal
8181 __ sltu(AT, op1, op2);
8182 __ movz(dst, src, AT);
8183 break;
8185 case 0x05: //below
8186 __ sltu(AT, op1, op2);
8187 __ movn(dst, src, AT);
8188 break;
8190 case 0x06: //below_equal
8191 __ sltu(AT, op2, op1);
8192 __ movz(dst, src, AT);
8193 break;
8195 default:
8196 Unimplemented();
8197 }
8198 %}
8200 ins_pipe( pipe_slow );
8201 %}
8203 instruct cmovI_cmpN_reg_reg(mRegI dst, mRegI src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{
8204 match(Set dst (CMoveI (Binary cop (CmpN tmp1 tmp2)) (Binary dst src)));
8205 ins_cost(80);
8206 format %{
8207 "CMPU$cop $tmp1,$tmp2\t @cmovI_cmpN_reg_reg\n\t"
8208 "CMOV $dst,$src\t @cmovI_cmpN_reg_reg"
8209 %}
8210 ins_encode %{
8211 Register op1 = $tmp1$$Register;
8212 Register op2 = $tmp2$$Register;
8213 Register dst = $dst$$Register;
8214 Register src = $src$$Register;
8215 int flag = $cop$$cmpcode;
8217 switch(flag)
8218 {
8219 case 0x01: //equal
8220 __ subu32(AT, op1, op2);
8221 __ movz(dst, src, AT);
8222 break;
8224 case 0x02: //not_equal
8225 __ subu32(AT, op1, op2);
8226 __ movn(dst, src, AT);
8227 break;
8229 case 0x03: //above
8230 __ sltu(AT, op2, op1);
8231 __ movn(dst, src, AT);
8232 break;
8234 case 0x04: //above_equal
8235 __ sltu(AT, op1, op2);
8236 __ movz(dst, src, AT);
8237 break;
8239 case 0x05: //below
8240 __ sltu(AT, op1, op2);
8241 __ movn(dst, src, AT);
8242 break;
8244 case 0x06: //below_equal
8245 __ sltu(AT, op2, op1);
8246 __ movz(dst, src, AT);
8247 break;
8249 default:
8250 Unimplemented();
8251 }
8252 %}
8254 ins_pipe( pipe_slow );
8255 %}
8257 instruct cmovP_cmpN_reg_reg(mRegP dst, mRegP src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{
8258 match(Set dst (CMoveP (Binary cop (CmpN tmp1 tmp2)) (Binary dst src)));
8259 ins_cost(80);
8260 format %{
8261 "CMPU$cop $tmp1,$tmp2\t @cmovP_cmpN_reg_reg\n\t"
8262 "CMOV $dst,$src\t @cmovP_cmpN_reg_reg"
8263 %}
8264 ins_encode %{
8265 Register op1 = $tmp1$$Register;
8266 Register op2 = $tmp2$$Register;
8267 Register dst = $dst$$Register;
8268 Register src = $src$$Register;
8269 int flag = $cop$$cmpcode;
8271 switch(flag)
8272 {
8273 case 0x01: //equal
8274 __ subu32(AT, op1, op2);
8275 __ movz(dst, src, AT);
8276 break;
8278 case 0x02: //not_equal
8279 __ subu32(AT, op1, op2);
8280 __ movn(dst, src, AT);
8281 break;
8283 case 0x03: //above
8284 __ sltu(AT, op2, op1);
8285 __ movn(dst, src, AT);
8286 break;
8288 case 0x04: //above_equal
8289 __ sltu(AT, op1, op2);
8290 __ movz(dst, src, AT);
8291 break;
8293 case 0x05: //below
8294 __ sltu(AT, op1, op2);
8295 __ movn(dst, src, AT);
8296 break;
8298 case 0x06: //below_equal
8299 __ sltu(AT, op2, op1);
8300 __ movz(dst, src, AT);
8301 break;
8303 default:
8304 Unimplemented();
8305 }
8306 %}
8308 ins_pipe( pipe_slow );
8309 %}
8311 instruct cmovN_cmpP_reg_reg(mRegN dst, mRegN src, mRegP tmp1, mRegP tmp2, cmpOpU cop ) %{
8312 match(Set dst (CMoveN (Binary cop (CmpP tmp1 tmp2)) (Binary dst src)));
8313 ins_cost(80);
8314 format %{
8315 "CMPU$cop $tmp1,$tmp2\t @cmovN_cmpP_reg_reg\n\t"
8316 "CMOV $dst,$src\t @cmovN_cmpP_reg_reg"
8317 %}
8318 ins_encode %{
8319 Register op1 = $tmp1$$Register;
8320 Register op2 = $tmp2$$Register;
8321 Register dst = $dst$$Register;
8322 Register src = $src$$Register;
8323 int flag = $cop$$cmpcode;
8325 switch(flag)
8326 {
8327 case 0x01: //equal
8328 __ subu(AT, op1, op2);
8329 __ movz(dst, src, AT);
8330 break;
8332 case 0x02: //not_equal
8333 __ subu(AT, op1, op2);
8334 __ movn(dst, src, AT);
8335 break;
8337 case 0x03: //above
8338 __ sltu(AT, op2, op1);
8339 __ movn(dst, src, AT);
8340 break;
8342 case 0x04: //above_equal
8343 __ sltu(AT, op1, op2);
8344 __ movz(dst, src, AT);
8345 break;
8347 case 0x05: //below
8348 __ sltu(AT, op1, op2);
8349 __ movn(dst, src, AT);
8350 break;
8352 case 0x06: //below_equal
8353 __ sltu(AT, op2, op1);
8354 __ movz(dst, src, AT);
8355 break;
8357 default:
8358 Unimplemented();
8359 }
8360 %}
8362 ins_pipe( pipe_slow );
8363 %}
8365 instruct cmovP_cmpD_reg_reg(mRegP dst, mRegP src, regD tmp1, regD tmp2, cmpOp cop ) %{
8366 match(Set dst (CMoveP (Binary cop (CmpD tmp1 tmp2)) (Binary dst src)));
8367 ins_cost(80);
8368 format %{
8369 "CMP$cop $tmp1, $tmp2\t @cmovP_cmpD_reg_reg\n"
8370 "\tCMOV $dst,$src \t @cmovP_cmpD_reg_reg"
8371 %}
8372 ins_encode %{
8373 FloatRegister reg_op1 = as_FloatRegister($tmp1$$reg);
8374 FloatRegister reg_op2 = as_FloatRegister($tmp2$$reg);
8375 Register dst = as_Register($dst$$reg);
8376 Register src = as_Register($src$$reg);
8378 int flag = $cop$$cmpcode;
8380 switch(flag)
8381 {
8382 case 0x01: //equal
8383 __ c_eq_d(reg_op1, reg_op2);
8384 __ movt(dst, src);
8385 break;
8386 case 0x02: //not_equal
8387 __ c_eq_d(reg_op1, reg_op2);
8388 __ movf(dst, src);
8389 break;
8390 case 0x03: //greater
8391 __ c_ole_d(reg_op1, reg_op2);
8392 __ movf(dst, src);
8393 break;
8394 case 0x04: //greater_equal
8395 __ c_olt_d(reg_op1, reg_op2);
8396 __ movf(dst, src);
8397 break;
8398 case 0x05: //less
8399 __ c_ult_d(reg_op1, reg_op2);
8400 __ movt(dst, src);
8401 break;
8402 case 0x06: //less_equal
8403 __ c_ule_d(reg_op1, reg_op2);
8404 __ movt(dst, src);
8405 break;
8406 default:
8407 Unimplemented();
8408 }
8409 %}
8411 ins_pipe( pipe_slow );
8412 %}
8415 instruct cmovN_cmpN_reg_reg(mRegN dst, mRegN src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{
8416 match(Set dst (CMoveN (Binary cop (CmpN tmp1 tmp2)) (Binary dst src)));
8417 ins_cost(80);
8418 format %{
8419 "CMPU$cop $tmp1,$tmp2\t @cmovN_cmpN_reg_reg\n\t"
8420 "CMOV $dst,$src\t @cmovN_cmpN_reg_reg"
8421 %}
8422 ins_encode %{
8423 Register op1 = $tmp1$$Register;
8424 Register op2 = $tmp2$$Register;
8425 Register dst = $dst$$Register;
8426 Register src = $src$$Register;
8427 int flag = $cop$$cmpcode;
8429 switch(flag)
8430 {
8431 case 0x01: //equal
8432 __ subu32(AT, op1, op2);
8433 __ movz(dst, src, AT);
8434 break;
8436 case 0x02: //not_equal
8437 __ subu32(AT, op1, op2);
8438 __ movn(dst, src, AT);
8439 break;
8441 case 0x03: //above
8442 __ sltu(AT, op2, op1);
8443 __ movn(dst, src, AT);
8444 break;
8446 case 0x04: //above_equal
8447 __ sltu(AT, op1, op2);
8448 __ movz(dst, src, AT);
8449 break;
8451 case 0x05: //below
8452 __ sltu(AT, op1, op2);
8453 __ movn(dst, src, AT);
8454 break;
8456 case 0x06: //below_equal
8457 __ sltu(AT, op2, op1);
8458 __ movz(dst, src, AT);
8459 break;
8461 default:
8462 Unimplemented();
8463 }
8464 %}
8466 ins_pipe( pipe_slow );
8467 %}
8470 instruct cmovI_cmpU_reg_reg(mRegI dst, mRegI src, mRegI tmp1, mRegI tmp2, cmpOpU cop ) %{
8471 match(Set dst (CMoveI (Binary cop (CmpU tmp1 tmp2)) (Binary dst src)));
8472 ins_cost(80);
8473 format %{
8474 "CMPU$cop $tmp1,$tmp2\t @cmovI_cmpU_reg_reg\n\t"
8475 "CMOV $dst,$src\t @cmovI_cmpU_reg_reg"
8476 %}
8477 ins_encode %{
8478 Register op1 = $tmp1$$Register;
8479 Register op2 = $tmp2$$Register;
8480 Register dst = $dst$$Register;
8481 Register src = $src$$Register;
8482 int flag = $cop$$cmpcode;
8484 switch(flag)
8485 {
8486 case 0x01: //equal
8487 __ subu(AT, op1, op2);
8488 __ movz(dst, src, AT);
8489 break;
8491 case 0x02: //not_equal
8492 __ subu(AT, op1, op2);
8493 __ movn(dst, src, AT);
8494 break;
8496 case 0x03: //above
8497 __ sltu(AT, op2, op1);
8498 __ movn(dst, src, AT);
8499 break;
8501 case 0x04: //above_equal
8502 __ sltu(AT, op1, op2);
8503 __ movz(dst, src, AT);
8504 break;
8506 case 0x05: //below
8507 __ sltu(AT, op1, op2);
8508 __ movn(dst, src, AT);
8509 break;
8511 case 0x06: //below_equal
8512 __ sltu(AT, op2, op1);
8513 __ movz(dst, src, AT);
8514 break;
8516 default:
8517 Unimplemented();
8518 }
8519 %}
8521 ins_pipe( pipe_slow );
8522 %}
8524 instruct cmovI_cmpL_reg_reg(mRegI dst, mRegI src, mRegL tmp1, mRegL tmp2, cmpOp cop ) %{
8525 match(Set dst (CMoveI (Binary cop (CmpL tmp1 tmp2)) (Binary dst src)));
8526 ins_cost(80);
8527 format %{
8528 "CMP$cop $tmp1, $tmp2\t @cmovI_cmpL_reg_reg\n"
8529 "\tCMOV $dst,$src \t @cmovI_cmpL_reg_reg"
8530 %}
8531 ins_encode %{
8532 Register opr1 = as_Register($tmp1$$reg);
8533 Register opr2 = as_Register($tmp2$$reg);
8534 Register dst = $dst$$Register;
8535 Register src = $src$$Register;
8536 int flag = $cop$$cmpcode;
8538 switch(flag)
8539 {
8540 case 0x01: //equal
8541 __ subu(AT, opr1, opr2);
8542 __ movz(dst, src, AT);
8543 break;
8545 case 0x02: //not_equal
8546 __ subu(AT, opr1, opr2);
8547 __ movn(dst, src, AT);
8548 break;
8550 case 0x03: //greater
8551 __ slt(AT, opr2, opr1);
8552 __ movn(dst, src, AT);
8553 break;
8555 case 0x04: //greater_equal
8556 __ slt(AT, opr1, opr2);
8557 __ movz(dst, src, AT);
8558 break;
8560 case 0x05: //less
8561 __ slt(AT, opr1, opr2);
8562 __ movn(dst, src, AT);
8563 break;
8565 case 0x06: //less_equal
8566 __ slt(AT, opr2, opr1);
8567 __ movz(dst, src, AT);
8568 break;
8570 default:
8571 Unimplemented();
8572 }
8573 %}
8575 ins_pipe( pipe_slow );
8576 %}
8578 instruct cmovP_cmpL_reg_reg(mRegP dst, mRegP src, mRegL tmp1, mRegL tmp2, cmpOp cop ) %{
8579 match(Set dst (CMoveP (Binary cop (CmpL tmp1 tmp2)) (Binary dst src)));
8580 ins_cost(80);
8581 format %{
8582 "CMP$cop $tmp1, $tmp2\t @cmovP_cmpL_reg_reg\n"
8583 "\tCMOV $dst,$src \t @cmovP_cmpL_reg_reg"
8584 %}
8585 ins_encode %{
8586 Register opr1 = as_Register($tmp1$$reg);
8587 Register opr2 = as_Register($tmp2$$reg);
8588 Register dst = $dst$$Register;
8589 Register src = $src$$Register;
8590 int flag = $cop$$cmpcode;
8592 switch(flag)
8593 {
8594 case 0x01: //equal
8595 __ subu(AT, opr1, opr2);
8596 __ movz(dst, src, AT);
8597 break;
8599 case 0x02: //not_equal
8600 __ subu(AT, opr1, opr2);
8601 __ movn(dst, src, AT);
8602 break;
8604 case 0x03: //greater
8605 __ slt(AT, opr2, opr1);
8606 __ movn(dst, src, AT);
8607 break;
8609 case 0x04: //greater_equal
8610 __ slt(AT, opr1, opr2);
8611 __ movz(dst, src, AT);
8612 break;
8614 case 0x05: //less
8615 __ slt(AT, opr1, opr2);
8616 __ movn(dst, src, AT);
8617 break;
8619 case 0x06: //less_equal
8620 __ slt(AT, opr2, opr1);
8621 __ movz(dst, src, AT);
8622 break;
8624 default:
8625 Unimplemented();
8626 }
8627 %}
8629 ins_pipe( pipe_slow );
8630 %}
8632 instruct cmovI_cmpD_reg_reg(mRegI dst, mRegI src, regD tmp1, regD tmp2, cmpOp cop ) %{
8633 match(Set dst (CMoveI (Binary cop (CmpD tmp1 tmp2)) (Binary dst src)));
8634 ins_cost(80);
8635 format %{
8636 "CMP$cop $tmp1, $tmp2\t @cmovI_cmpD_reg_reg\n"
8637 "\tCMOV $dst,$src \t @cmovI_cmpD_reg_reg"
8638 %}
8639 ins_encode %{
8640 FloatRegister reg_op1 = as_FloatRegister($tmp1$$reg);
8641 FloatRegister reg_op2 = as_FloatRegister($tmp2$$reg);
8642 Register dst = as_Register($dst$$reg);
8643 Register src = as_Register($src$$reg);
8645 int flag = $cop$$cmpcode;
8647 switch(flag)
8648 {
8649 case 0x01: //equal
8650 __ c_eq_d(reg_op1, reg_op2);
8651 __ movt(dst, src);
8652 break;
8653 case 0x02: //not_equal
8654 //2016/4/19 aoqi: See instruct branchConD_reg_reg. The change in branchConD_reg_reg fixed a bug. It seems similar here, so I made thesame change.
8655 __ c_eq_d(reg_op1, reg_op2);
8656 __ movf(dst, src);
8657 break;
8658 case 0x03: //greater
8659 __ c_ole_d(reg_op1, reg_op2);
8660 __ movf(dst, src);
8661 break;
8662 case 0x04: //greater_equal
8663 __ c_olt_d(reg_op1, reg_op2);
8664 __ movf(dst, src);
8665 break;
8666 case 0x05: //less
8667 __ c_ult_d(reg_op1, reg_op2);
8668 __ movt(dst, src);
8669 break;
8670 case 0x06: //less_equal
8671 __ c_ule_d(reg_op1, reg_op2);
8672 __ movt(dst, src);
8673 break;
8674 default:
8675 Unimplemented();
8676 }
8677 %}
8679 ins_pipe( pipe_slow );
8680 %}
8683 instruct cmovP_cmpP_reg_reg(mRegP dst, mRegP src, mRegP tmp1, mRegP tmp2, cmpOpU cop ) %{
8684 match(Set dst (CMoveP (Binary cop (CmpP tmp1 tmp2)) (Binary dst src)));
8685 ins_cost(80);
8686 format %{
8687 "CMPU$cop $tmp1,$tmp2\t @cmovP_cmpP_reg_reg\n\t"
8688 "CMOV $dst,$src\t @cmovP_cmpP_reg_reg"
8689 %}
8690 ins_encode %{
8691 Register op1 = $tmp1$$Register;
8692 Register op2 = $tmp2$$Register;
8693 Register dst = $dst$$Register;
8694 Register src = $src$$Register;
8695 int flag = $cop$$cmpcode;
8697 switch(flag)
8698 {
8699 case 0x01: //equal
8700 __ subu(AT, op1, op2);
8701 __ movz(dst, src, AT);
8702 break;
8704 case 0x02: //not_equal
8705 __ subu(AT, op1, op2);
8706 __ movn(dst, src, AT);
8707 break;
8709 case 0x03: //above
8710 __ sltu(AT, op2, op1);
8711 __ movn(dst, src, AT);
8712 break;
8714 case 0x04: //above_equal
8715 __ sltu(AT, op1, op2);
8716 __ movz(dst, src, AT);
8717 break;
8719 case 0x05: //below
8720 __ sltu(AT, op1, op2);
8721 __ movn(dst, src, AT);
8722 break;
8724 case 0x06: //below_equal
8725 __ sltu(AT, op2, op1);
8726 __ movz(dst, src, AT);
8727 break;
8729 default:
8730 Unimplemented();
8731 }
8732 %}
8734 ins_pipe( pipe_slow );
8735 %}
8737 instruct cmovP_cmpI_reg_reg(mRegP dst, mRegP src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
8738 match(Set dst (CMoveP (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
8739 ins_cost(80);
8740 format %{
8741 "CMP$cop $tmp1,$tmp2\t @cmovP_cmpI_reg_reg\n\t"
8742 "CMOV $dst,$src\t @cmovP_cmpI_reg_reg"
8743 %}
8744 ins_encode %{
8745 Register op1 = $tmp1$$Register;
8746 Register op2 = $tmp2$$Register;
8747 Register dst = $dst$$Register;
8748 Register src = $src$$Register;
8749 int flag = $cop$$cmpcode;
8751 switch(flag)
8752 {
8753 case 0x01: //equal
8754 __ subu32(AT, op1, op2);
8755 __ movz(dst, src, AT);
8756 break;
8758 case 0x02: //not_equal
8759 __ subu32(AT, op1, op2);
8760 __ movn(dst, src, AT);
8761 break;
8763 case 0x03: //above
8764 __ slt(AT, op2, op1);
8765 __ movn(dst, src, AT);
8766 break;
8768 case 0x04: //above_equal
8769 __ slt(AT, op1, op2);
8770 __ movz(dst, src, AT);
8771 break;
8773 case 0x05: //below
8774 __ slt(AT, op1, op2);
8775 __ movn(dst, src, AT);
8776 break;
8778 case 0x06: //below_equal
8779 __ slt(AT, op2, op1);
8780 __ movz(dst, src, AT);
8781 break;
8783 default:
8784 Unimplemented();
8785 }
8786 %}
8788 ins_pipe( pipe_slow );
8789 %}
8791 instruct cmovN_cmpI_reg_reg(mRegN dst, mRegN src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
8792 match(Set dst (CMoveN (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
8793 ins_cost(80);
8794 format %{
8795 "CMP$cop $tmp1,$tmp2\t @cmovN_cmpI_reg_reg\n\t"
8796 "CMOV $dst,$src\t @cmovN_cmpI_reg_reg"
8797 %}
8798 ins_encode %{
8799 Register op1 = $tmp1$$Register;
8800 Register op2 = $tmp2$$Register;
8801 Register dst = $dst$$Register;
8802 Register src = $src$$Register;
8803 int flag = $cop$$cmpcode;
8805 switch(flag)
8806 {
8807 case 0x01: //equal
8808 __ subu32(AT, op1, op2);
8809 __ movz(dst, src, AT);
8810 break;
8812 case 0x02: //not_equal
8813 __ subu32(AT, op1, op2);
8814 __ movn(dst, src, AT);
8815 break;
8817 case 0x03: //above
8818 __ slt(AT, op2, op1);
8819 __ movn(dst, src, AT);
8820 break;
8822 case 0x04: //above_equal
8823 __ slt(AT, op1, op2);
8824 __ movz(dst, src, AT);
8825 break;
8827 case 0x05: //below
8828 __ slt(AT, op1, op2);
8829 __ movn(dst, src, AT);
8830 break;
8832 case 0x06: //below_equal
8833 __ slt(AT, op2, op1);
8834 __ movz(dst, src, AT);
8835 break;
8837 default:
8838 Unimplemented();
8839 }
8840 %}
8842 ins_pipe( pipe_slow );
8843 %}
8846 instruct cmovL_cmpI_reg_reg(mRegL dst, mRegL src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
8847 match(Set dst (CMoveL (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
8848 ins_cost(80);
8849 format %{
8850 "CMP$cop $tmp1, $tmp2\t @cmovL_cmpI_reg_reg\n"
8851 "\tCMOV $dst,$src \t @cmovL_cmpI_reg_reg"
8852 %}
8854 ins_encode %{
8855 Register op1 = $tmp1$$Register;
8856 Register op2 = $tmp2$$Register;
8857 Register dst = as_Register($dst$$reg);
8858 Register src = as_Register($src$$reg);
8859 int flag = $cop$$cmpcode;
8861 switch(flag)
8862 {
8863 case 0x01: //equal
8864 __ subu32(AT, op1, op2);
8865 __ movz(dst, src, AT);
8866 break;
8868 case 0x02: //not_equal
8869 __ subu32(AT, op1, op2);
8870 __ movn(dst, src, AT);
8871 break;
8873 case 0x03: //great
8874 __ slt(AT, op2, op1);
8875 __ movn(dst, src, AT);
8876 break;
8878 case 0x04: //great_equal
8879 __ slt(AT, op1, op2);
8880 __ movz(dst, src, AT);
8881 break;
8883 case 0x05: //less
8884 __ slt(AT, op1, op2);
8885 __ movn(dst, src, AT);
8886 break;
8888 case 0x06: //less_equal
8889 __ slt(AT, op2, op1);
8890 __ movz(dst, src, AT);
8891 break;
8893 default:
8894 Unimplemented();
8895 }
8896 %}
8898 ins_pipe( pipe_slow );
8899 %}
8901 instruct cmovL_cmpL_reg_reg(mRegL dst, mRegL src, mRegL tmp1, mRegL tmp2, cmpOp cop ) %{
8902 match(Set dst (CMoveL (Binary cop (CmpL tmp1 tmp2)) (Binary dst src)));
8903 ins_cost(80);
8904 format %{
8905 "CMP$cop $tmp1, $tmp2\t @cmovL_cmpL_reg_reg\n"
8906 "\tCMOV $dst,$src \t @cmovL_cmpL_reg_reg"
8907 %}
8908 ins_encode %{
8909 Register opr1 = as_Register($tmp1$$reg);
8910 Register opr2 = as_Register($tmp2$$reg);
8911 Register dst = as_Register($dst$$reg);
8912 Register src = as_Register($src$$reg);
8913 int flag = $cop$$cmpcode;
8915 switch(flag)
8916 {
8917 case 0x01: //equal
8918 __ subu(AT, opr1, opr2);
8919 __ movz(dst, src, AT);
8920 break;
8922 case 0x02: //not_equal
8923 __ subu(AT, opr1, opr2);
8924 __ movn(dst, src, AT);
8925 break;
8927 case 0x03: //greater
8928 __ slt(AT, opr2, opr1);
8929 __ movn(dst, src, AT);
8930 break;
8932 case 0x04: //greater_equal
8933 __ slt(AT, opr1, opr2);
8934 __ movz(dst, src, AT);
8935 break;
8937 case 0x05: //less
8938 __ slt(AT, opr1, opr2);
8939 __ movn(dst, src, AT);
8940 break;
8942 case 0x06: //less_equal
8943 __ slt(AT, opr2, opr1);
8944 __ movz(dst, src, AT);
8945 break;
8947 default:
8948 Unimplemented();
8949 }
8950 %}
8952 ins_pipe( pipe_slow );
8953 %}
8955 instruct cmovL_cmpN_reg_reg(mRegL dst, mRegL src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{
8956 match(Set dst (CMoveL (Binary cop (CmpN tmp1 tmp2)) (Binary dst src)));
8957 ins_cost(80);
8958 format %{
8959 "CMPU$cop $tmp1,$tmp2\t @cmovL_cmpN_reg_reg\n\t"
8960 "CMOV $dst,$src\t @cmovL_cmpN_reg_reg"
8961 %}
8962 ins_encode %{
8963 Register op1 = $tmp1$$Register;
8964 Register op2 = $tmp2$$Register;
8965 Register dst = $dst$$Register;
8966 Register src = $src$$Register;
8967 int flag = $cop$$cmpcode;
8969 switch(flag)
8970 {
8971 case 0x01: //equal
8972 __ subu32(AT, op1, op2);
8973 __ movz(dst, src, AT);
8974 break;
8976 case 0x02: //not_equal
8977 __ subu32(AT, op1, op2);
8978 __ movn(dst, src, AT);
8979 break;
8981 case 0x03: //above
8982 __ sltu(AT, op2, op1);
8983 __ movn(dst, src, AT);
8984 break;
8986 case 0x04: //above_equal
8987 __ sltu(AT, op1, op2);
8988 __ movz(dst, src, AT);
8989 break;
8991 case 0x05: //below
8992 __ sltu(AT, op1, op2);
8993 __ movn(dst, src, AT);
8994 break;
8996 case 0x06: //below_equal
8997 __ sltu(AT, op2, op1);
8998 __ movz(dst, src, AT);
8999 break;
9001 default:
9002 Unimplemented();
9003 }
9004 %}
9006 ins_pipe( pipe_slow );
9007 %}
9010 instruct cmovL_cmpD_reg_reg(mRegL dst, mRegL src, regD tmp1, regD tmp2, cmpOp cop ) %{
9011 match(Set dst (CMoveL (Binary cop (CmpD tmp1 tmp2)) (Binary dst src)));
9012 ins_cost(80);
9013 format %{
9014 "CMP$cop $tmp1, $tmp2\t @cmovL_cmpD_reg_reg\n"
9015 "\tCMOV $dst,$src \t @cmovL_cmpD_reg_reg"
9016 %}
9017 ins_encode %{
9018 FloatRegister reg_op1 = as_FloatRegister($tmp1$$reg);
9019 FloatRegister reg_op2 = as_FloatRegister($tmp2$$reg);
9020 Register dst = as_Register($dst$$reg);
9021 Register src = as_Register($src$$reg);
9023 int flag = $cop$$cmpcode;
9025 switch(flag)
9026 {
9027 case 0x01: //equal
9028 __ c_eq_d(reg_op1, reg_op2);
9029 __ movt(dst, src);
9030 break;
9031 case 0x02: //not_equal
9032 __ c_eq_d(reg_op1, reg_op2);
9033 __ movf(dst, src);
9034 break;
9035 case 0x03: //greater
9036 __ c_ole_d(reg_op1, reg_op2);
9037 __ movf(dst, src);
9038 break;
9039 case 0x04: //greater_equal
9040 __ c_olt_d(reg_op1, reg_op2);
9041 __ movf(dst, src);
9042 break;
9043 case 0x05: //less
9044 __ c_ult_d(reg_op1, reg_op2);
9045 __ movt(dst, src);
9046 break;
9047 case 0x06: //less_equal
9048 __ c_ule_d(reg_op1, reg_op2);
9049 __ movt(dst, src);
9050 break;
9051 default:
9052 Unimplemented();
9053 }
9054 %}
9056 ins_pipe( pipe_slow );
9057 %}
9059 instruct cmovD_cmpD_reg_reg(regD dst, regD src, regD tmp1, regD tmp2, cmpOp cop ) %{
9060 match(Set dst (CMoveD (Binary cop (CmpD tmp1 tmp2)) (Binary dst src)));
9061 ins_cost(200);
9062 format %{
9063 "CMP$cop $tmp1, $tmp2\t @cmovD_cmpD_reg_reg\n"
9064 "\tCMOV $dst,$src \t @cmovD_cmpD_reg_reg"
9065 %}
9066 ins_encode %{
9067 FloatRegister reg_op1 = as_FloatRegister($tmp1$$reg);
9068 FloatRegister reg_op2 = as_FloatRegister($tmp2$$reg);
9069 FloatRegister dst = as_FloatRegister($dst$$reg);
9070 FloatRegister src = as_FloatRegister($src$$reg);
9072 int flag = $cop$$cmpcode;
9074 Label L;
9076 switch(flag)
9077 {
9078 case 0x01: //equal
9079 __ c_eq_d(reg_op1, reg_op2);
9080 __ bc1f(L);
9081 __ nop();
9082 __ mov_d(dst, src);
9083 __ bind(L);
9084 break;
9085 case 0x02: //not_equal
9086 //2016/4/19 aoqi: See instruct branchConD_reg_reg. The change in branchConD_reg_reg fixed a bug. It seems similar here, so I made thesame change.
9087 __ c_eq_d(reg_op1, reg_op2);
9088 __ bc1t(L);
9089 __ nop();
9090 __ mov_d(dst, src);
9091 __ bind(L);
9092 break;
9093 case 0x03: //greater
9094 __ c_ole_d(reg_op1, reg_op2);
9095 __ bc1t(L);
9096 __ nop();
9097 __ mov_d(dst, src);
9098 __ bind(L);
9099 break;
9100 case 0x04: //greater_equal
9101 __ c_olt_d(reg_op1, reg_op2);
9102 __ bc1t(L);
9103 __ nop();
9104 __ mov_d(dst, src);
9105 __ bind(L);
9106 break;
9107 case 0x05: //less
9108 __ c_ult_d(reg_op1, reg_op2);
9109 __ bc1f(L);
9110 __ nop();
9111 __ mov_d(dst, src);
9112 __ bind(L);
9113 break;
9114 case 0x06: //less_equal
9115 __ c_ule_d(reg_op1, reg_op2);
9116 __ bc1f(L);
9117 __ nop();
9118 __ mov_d(dst, src);
9119 __ bind(L);
9120 break;
9121 default:
9122 Unimplemented();
9123 }
9124 %}
9126 ins_pipe( pipe_slow );
9127 %}
9129 instruct cmovF_cmpI_reg_reg(regF dst, regF src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
9130 match(Set dst (CMoveF (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
9131 ins_cost(200);
9132 format %{
9133 "CMP$cop $tmp1, $tmp2\t @cmovF_cmpI_reg_reg\n"
9134 "\tCMOV $dst, $src \t @cmovF_cmpI_reg_reg"
9135 %}
9137 ins_encode %{
9138 Register op1 = $tmp1$$Register;
9139 Register op2 = $tmp2$$Register;
9140 FloatRegister dst = as_FloatRegister($dst$$reg);
9141 FloatRegister src = as_FloatRegister($src$$reg);
9142 int flag = $cop$$cmpcode;
9143 Label L;
9145 switch(flag)
9146 {
9147 case 0x01: //equal
9148 __ bne(op1, op2, L);
9149 __ nop();
9150 __ mov_s(dst, src);
9151 __ bind(L);
9152 break;
9153 case 0x02: //not_equal
9154 __ beq(op1, op2, L);
9155 __ nop();
9156 __ mov_s(dst, src);
9157 __ bind(L);
9158 break;
9159 case 0x03: //great
9160 __ slt(AT, op2, op1);
9161 __ beq(AT, R0, L);
9162 __ nop();
9163 __ mov_s(dst, src);
9164 __ bind(L);
9165 break;
9166 case 0x04: //great_equal
9167 __ slt(AT, op1, op2);
9168 __ bne(AT, R0, L);
9169 __ nop();
9170 __ mov_s(dst, src);
9171 __ bind(L);
9172 break;
9173 case 0x05: //less
9174 __ slt(AT, op1, op2);
9175 __ beq(AT, R0, L);
9176 __ nop();
9177 __ mov_s(dst, src);
9178 __ bind(L);
9179 break;
9180 case 0x06: //less_equal
9181 __ slt(AT, op2, op1);
9182 __ bne(AT, R0, L);
9183 __ nop();
9184 __ mov_s(dst, src);
9185 __ bind(L);
9186 break;
9187 default:
9188 Unimplemented();
9189 }
9190 %}
9192 ins_pipe( pipe_slow );
9193 %}
9195 instruct cmovD_cmpI_reg_reg(regD dst, regD src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
9196 match(Set dst (CMoveD (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
9197 ins_cost(200);
9198 format %{
9199 "CMP$cop $tmp1, $tmp2\t @cmovD_cmpI_reg_reg\n"
9200 "\tCMOV $dst, $src \t @cmovD_cmpI_reg_reg"
9201 %}
9203 ins_encode %{
9204 Register op1 = $tmp1$$Register;
9205 Register op2 = $tmp2$$Register;
9206 FloatRegister dst = as_FloatRegister($dst$$reg);
9207 FloatRegister src = as_FloatRegister($src$$reg);
9208 int flag = $cop$$cmpcode;
9209 Label L;
9211 switch(flag)
9212 {
9213 case 0x01: //equal
9214 __ bne(op1, op2, L);
9215 __ nop();
9216 __ mov_d(dst, src);
9217 __ bind(L);
9218 break;
9219 case 0x02: //not_equal
9220 __ beq(op1, op2, L);
9221 __ nop();
9222 __ mov_d(dst, src);
9223 __ bind(L);
9224 break;
9225 case 0x03: //great
9226 __ slt(AT, op2, op1);
9227 __ beq(AT, R0, L);
9228 __ nop();
9229 __ mov_d(dst, src);
9230 __ bind(L);
9231 break;
9232 case 0x04: //great_equal
9233 __ slt(AT, op1, op2);
9234 __ bne(AT, R0, L);
9235 __ nop();
9236 __ mov_d(dst, src);
9237 __ bind(L);
9238 break;
9239 case 0x05: //less
9240 __ slt(AT, op1, op2);
9241 __ beq(AT, R0, L);
9242 __ nop();
9243 __ mov_d(dst, src);
9244 __ bind(L);
9245 break;
9246 case 0x06: //less_equal
9247 __ slt(AT, op2, op1);
9248 __ bne(AT, R0, L);
9249 __ nop();
9250 __ mov_d(dst, src);
9251 __ bind(L);
9252 break;
9253 default:
9254 Unimplemented();
9255 }
9256 %}
9258 ins_pipe( pipe_slow );
9259 %}
9261 instruct cmovD_cmpP_reg_reg(regD dst, regD src, mRegP tmp1, mRegP tmp2, cmpOp cop ) %{
9262 match(Set dst (CMoveD (Binary cop (CmpP tmp1 tmp2)) (Binary dst src)));
9263 ins_cost(200);
9264 format %{
9265 "CMP$cop $tmp1, $tmp2\t @cmovD_cmpP_reg_reg\n"
9266 "\tCMOV $dst, $src \t @cmovD_cmpP_reg_reg"
9267 %}
9269 ins_encode %{
9270 Register op1 = $tmp1$$Register;
9271 Register op2 = $tmp2$$Register;
9272 FloatRegister dst = as_FloatRegister($dst$$reg);
9273 FloatRegister src = as_FloatRegister($src$$reg);
9274 int flag = $cop$$cmpcode;
9275 Label L;
9277 switch(flag)
9278 {
9279 case 0x01: //equal
9280 __ bne(op1, op2, L);
9281 __ nop();
9282 __ mov_d(dst, src);
9283 __ bind(L);
9284 break;
9285 case 0x02: //not_equal
9286 __ beq(op1, op2, L);
9287 __ nop();
9288 __ mov_d(dst, src);
9289 __ bind(L);
9290 break;
9291 case 0x03: //great
9292 __ slt(AT, op2, op1);
9293 __ beq(AT, R0, L);
9294 __ nop();
9295 __ mov_d(dst, src);
9296 __ bind(L);
9297 break;
9298 case 0x04: //great_equal
9299 __ slt(AT, op1, op2);
9300 __ bne(AT, R0, L);
9301 __ nop();
9302 __ mov_d(dst, src);
9303 __ bind(L);
9304 break;
9305 case 0x05: //less
9306 __ slt(AT, op1, op2);
9307 __ beq(AT, R0, L);
9308 __ nop();
9309 __ mov_d(dst, src);
9310 __ bind(L);
9311 break;
9312 case 0x06: //less_equal
9313 __ slt(AT, op2, op1);
9314 __ bne(AT, R0, L);
9315 __ nop();
9316 __ mov_d(dst, src);
9317 __ bind(L);
9318 break;
9319 default:
9320 Unimplemented();
9321 }
9322 %}
9324 ins_pipe( pipe_slow );
9325 %}
9327 //FIXME
9328 instruct cmovI_cmpF_reg_reg(mRegI dst, mRegI src, regF tmp1, regF tmp2, cmpOp cop ) %{
9329 match(Set dst (CMoveI (Binary cop (CmpF tmp1 tmp2)) (Binary dst src)));
9330 ins_cost(80);
9331 format %{
9332 "CMP$cop $tmp1, $tmp2\t @cmovI_cmpF_reg_reg\n"
9333 "\tCMOV $dst,$src \t @cmovI_cmpF_reg_reg"
9334 %}
9336 ins_encode %{
9337 FloatRegister reg_op1 = $tmp1$$FloatRegister;
9338 FloatRegister reg_op2 = $tmp2$$FloatRegister;
9339 Register dst = $dst$$Register;
9340 Register src = $src$$Register;
9341 int flag = $cop$$cmpcode;
9343 switch(flag)
9344 {
9345 case 0x01: //equal
9346 __ c_eq_s(reg_op1, reg_op2);
9347 __ movt(dst, src);
9348 break;
9349 case 0x02: //not_equal
9350 __ c_eq_s(reg_op1, reg_op2);
9351 __ movf(dst, src);
9352 break;
9353 case 0x03: //greater
9354 __ c_ole_s(reg_op1, reg_op2);
9355 __ movf(dst, src);
9356 break;
9357 case 0x04: //greater_equal
9358 __ c_olt_s(reg_op1, reg_op2);
9359 __ movf(dst, src);
9360 break;
9361 case 0x05: //less
9362 __ c_ult_s(reg_op1, reg_op2);
9363 __ movt(dst, src);
9364 break;
9365 case 0x06: //less_equal
9366 __ c_ule_s(reg_op1, reg_op2);
9367 __ movt(dst, src);
9368 break;
9369 default:
9370 Unimplemented();
9371 }
9372 %}
9373 ins_pipe( pipe_slow );
9374 %}
9376 instruct cmovF_cmpF_reg_reg(regF dst, regF src, regF tmp1, regF tmp2, cmpOp cop ) %{
9377 match(Set dst (CMoveF (Binary cop (CmpF tmp1 tmp2)) (Binary dst src)));
9378 ins_cost(200);
9379 format %{
9380 "CMP$cop $tmp1, $tmp2\t @cmovF_cmpF_reg_reg\n"
9381 "\tCMOV $dst,$src \t @cmovF_cmpF_reg_reg"
9382 %}
9384 ins_encode %{
9385 FloatRegister reg_op1 = $tmp1$$FloatRegister;
9386 FloatRegister reg_op2 = $tmp2$$FloatRegister;
9387 FloatRegister dst = $dst$$FloatRegister;
9388 FloatRegister src = $src$$FloatRegister;
9389 Label L;
9390 int flag = $cop$$cmpcode;
9392 switch(flag)
9393 {
9394 case 0x01: //equal
9395 __ c_eq_s(reg_op1, reg_op2);
9396 __ bc1f(L);
9397 __ nop();
9398 __ mov_s(dst, src);
9399 __ bind(L);
9400 break;
9401 case 0x02: //not_equal
9402 __ c_eq_s(reg_op1, reg_op2);
9403 __ bc1t(L);
9404 __ nop();
9405 __ mov_s(dst, src);
9406 __ bind(L);
9407 break;
9408 case 0x03: //greater
9409 __ c_ole_s(reg_op1, reg_op2);
9410 __ bc1t(L);
9411 __ nop();
9412 __ mov_s(dst, src);
9413 __ bind(L);
9414 break;
9415 case 0x04: //greater_equal
9416 __ c_olt_s(reg_op1, reg_op2);
9417 __ bc1t(L);
9418 __ nop();
9419 __ mov_s(dst, src);
9420 __ bind(L);
9421 break;
9422 case 0x05: //less
9423 __ c_ult_s(reg_op1, reg_op2);
9424 __ bc1f(L);
9425 __ nop();
9426 __ mov_s(dst, src);
9427 __ bind(L);
9428 break;
9429 case 0x06: //less_equal
9430 __ c_ule_s(reg_op1, reg_op2);
9431 __ bc1f(L);
9432 __ nop();
9433 __ mov_s(dst, src);
9434 __ bind(L);
9435 break;
9436 default:
9437 Unimplemented();
9438 }
9439 %}
9440 ins_pipe( pipe_slow );
9441 %}
9443 // Manifest a CmpL result in an integer register. Very painful.
9444 // This is the test to avoid.
9445 instruct cmpL3_reg_reg(mRegI dst, mRegL src1, mRegL src2) %{
9446 match(Set dst (CmpL3 src1 src2));
9447 ins_cost(1000);
9448 format %{ "cmpL3 $dst, $src1, $src2 @ cmpL3_reg_reg" %}
9449 ins_encode %{
9450 Register opr1 = as_Register($src1$$reg);
9451 Register opr2 = as_Register($src2$$reg);
9452 Register dst = as_Register($dst$$reg);
9454 Label Done;
9456 __ subu(AT, opr1, opr2);
9457 __ bltz(AT, Done);
9458 __ delayed()->daddiu(dst, R0, -1);
9460 __ move(dst, 1);
9461 __ movz(dst, R0, AT);
9463 __ bind(Done);
9464 %}
9465 ins_pipe( pipe_slow );
9466 %}
9468 //
9469 // less_rsult = -1
9470 // greater_result = 1
9471 // equal_result = 0
9472 // nan_result = -1
9473 //
9474 instruct cmpF3_reg_reg(mRegI dst, regF src1, regF src2) %{
9475 match(Set dst (CmpF3 src1 src2));
9476 ins_cost(1000);
9477 format %{ "cmpF3 $dst, $src1, $src2 @ cmpF3_reg_reg" %}
9478 ins_encode %{
9479 FloatRegister src1 = as_FloatRegister($src1$$reg);
9480 FloatRegister src2 = as_FloatRegister($src2$$reg);
9481 Register dst = as_Register($dst$$reg);
9483 Label Done;
9485 __ c_ult_s(src1, src2);
9486 __ bc1t(Done);
9487 __ delayed()->daddiu(dst, R0, -1);
9489 __ c_eq_s(src1, src2);
9490 __ move(dst, 1);
9491 __ movt(dst, R0);
9493 __ bind(Done);
9494 %}
9495 ins_pipe( pipe_slow );
9496 %}
9498 instruct cmpD3_reg_reg(mRegI dst, regD src1, regD src2) %{
9499 match(Set dst (CmpD3 src1 src2));
9500 ins_cost(1000);
9501 format %{ "cmpD3 $dst, $src1, $src2 @ cmpD3_reg_reg" %}
9502 ins_encode %{
9503 FloatRegister src1 = as_FloatRegister($src1$$reg);
9504 FloatRegister src2 = as_FloatRegister($src2$$reg);
9505 Register dst = as_Register($dst$$reg);
9507 Label Done;
9509 __ c_ult_d(src1, src2);
9510 __ bc1t(Done);
9511 __ delayed()->daddiu(dst, R0, -1);
9513 __ c_eq_d(src1, src2);
9514 __ move(dst, 1);
9515 __ movt(dst, R0);
9517 __ bind(Done);
9518 %}
9519 ins_pipe( pipe_slow );
9520 %}
9522 instruct clear_array(mRegL cnt, mRegP base, Universe dummy) %{
9523 match(Set dummy (ClearArray cnt base));
9524 format %{ "CLEAR_ARRAY base = $base, cnt = $cnt # Clear doublewords" %}
9525 ins_encode %{
9526 //Assume cnt is the number of bytes in an array to be cleared,
9527 //and base points to the starting address of the array.
9528 Register base = $base$$Register;
9529 Register num = $cnt$$Register;
9530 Label Loop, done;
9532 /* 2012/9/21 Jin: according to X86, $cnt is caculated by doublewords(8 bytes) */
9533 __ move(T9, num); /* T9 = words */
9534 __ beq(T9, R0, done);
9535 __ nop();
9536 __ move(AT, base);
9538 __ bind(Loop);
9539 __ sd(R0, Address(AT, 0));
9540 __ daddi(AT, AT, wordSize);
9541 __ daddi(T9, T9, -1);
9542 __ bne(T9, R0, Loop);
9543 __ delayed()->nop();
9544 __ bind(done);
9545 %}
9546 ins_pipe( pipe_slow );
9547 %}
9549 instruct string_compare(a4_RegP str1, mA5RegI cnt1, a6_RegP str2, mA7RegI cnt2, no_Ax_mRegI result) %{
9550 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
9551 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2);
9553 format %{ "String Compare $str1[len: $cnt1], $str2[len: $cnt2] -> $result @ string_compare" %}
9554 ins_encode %{
9555 // Get the first character position in both strings
9556 // [8] char array, [12] offset, [16] count
9557 Register str1 = $str1$$Register;
9558 Register str2 = $str2$$Register;
9559 Register cnt1 = $cnt1$$Register;
9560 Register cnt2 = $cnt2$$Register;
9561 Register result = $result$$Register;
9563 Label L, Loop, haveResult, done;
9565 // compute the and difference of lengths (in result)
9566 __ subu(result, cnt1, cnt2); // result holds the difference of two lengths
9568 // compute the shorter length (in cnt1)
9569 __ slt(AT, cnt2, cnt1);
9570 __ movn(cnt1, cnt2, AT);
9572 // Now the shorter length is in cnt1 and cnt2 can be used as a tmp register
9573 __ bind(Loop); // Loop begin
9574 __ beq(cnt1, R0, done);
9575 __ delayed()->lhu(AT, str1, 0);;
9577 // compare current character
9578 __ lhu(cnt2, str2, 0);
9579 __ bne(AT, cnt2, haveResult);
9580 __ delayed()->addi(str1, str1, 2);
9581 __ addi(str2, str2, 2);
9582 __ b(Loop);
9583 __ delayed()->addi(cnt1, cnt1, -1); // Loop end
9585 __ bind(haveResult);
9586 __ subu(result, AT, cnt2);
9588 __ bind(done);
9589 %}
9591 ins_pipe( pipe_slow );
9592 %}
9594 // intrinsic optimization
9595 instruct string_equals(a4_RegP str1, a5_RegP str2, mA6RegI cnt, mA7RegI temp, no_Ax_mRegI result) %{
9596 match(Set result (StrEquals (Binary str1 str2) cnt));
9597 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL temp);
9599 format %{ "String Equal $str1, $str2, len:$cnt tmp:$temp -> $result @ string_equals" %}
9600 ins_encode %{
9601 // Get the first character position in both strings
9602 // [8] char array, [12] offset, [16] count
9603 Register str1 = $str1$$Register;
9604 Register str2 = $str2$$Register;
9605 Register cnt = $cnt$$Register;
9606 Register tmp = $temp$$Register;
9607 Register result = $result$$Register;
9609 Label Loop, done;
9612 __ beq(str1, str2, done); // same char[] ?
9613 __ daddiu(result, R0, 1);
9615 __ bind(Loop); // Loop begin
9616 __ beq(cnt, R0, done);
9617 __ daddiu(result, R0, 1); // count == 0
9619 // compare current character
9620 __ lhu(AT, str1, 0);;
9621 __ lhu(tmp, str2, 0);
9622 __ bne(AT, tmp, done);
9623 __ delayed()->daddi(result, R0, 0);
9624 __ addi(str1, str1, 2);
9625 __ addi(str2, str2, 2);
9626 __ b(Loop);
9627 __ delayed()->addi(cnt, cnt, -1); // Loop end
9629 __ bind(done);
9630 %}
9632 ins_pipe( pipe_slow );
9633 %}
9635 //----------Arithmetic Instructions-------------------------------------------
9636 //----------Addition Instructions---------------------------------------------
9637 instruct addI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
9638 match(Set dst (AddI src1 src2));
9640 format %{ "add $dst, $src1, $src2 #@addI_Reg_Reg" %}
9641 ins_encode %{
9642 Register dst = $dst$$Register;
9643 Register src1 = $src1$$Register;
9644 Register src2 = $src2$$Register;
9645 __ addu32(dst, src1, src2);
9646 %}
9647 ins_pipe( ialu_regI_regI );
9648 %}
9650 instruct addI_Reg_imm(mRegI dst, mRegI src1, immI src2) %{
9651 match(Set dst (AddI src1 src2));
9653 format %{ "add $dst, $src1, $src2 #@addI_Reg_imm" %}
9654 ins_encode %{
9655 Register dst = $dst$$Register;
9656 Register src1 = $src1$$Register;
9657 int imm = $src2$$constant;
9659 if(Assembler::is_simm16(imm)) {
9660 __ addiu32(dst, src1, imm);
9661 } else {
9662 __ move(AT, imm);
9663 __ addu32(dst, src1, AT);
9664 }
9665 %}
9666 ins_pipe( ialu_regI_regI );
9667 %}
9669 instruct addP_reg_reg(mRegP dst, mRegP src1, mRegL src2) %{
9670 match(Set dst (AddP src1 src2));
9672 format %{ "dadd $dst, $src1, $src2 #@addP_reg_reg" %}
9674 ins_encode %{
9675 Register dst = $dst$$Register;
9676 Register src1 = $src1$$Register;
9677 Register src2 = $src2$$Register;
9678 __ daddu(dst, src1, src2);
9679 %}
9681 ins_pipe( ialu_regI_regI );
9682 %}
9684 instruct addP_reg_reg_convI2L(mRegP dst, mRegP src1, mRegI src2) %{
9685 match(Set dst (AddP src1 (ConvI2L src2)));
9687 format %{ "dadd $dst, $src1, $src2 #@addP_reg_reg_convI2L" %}
9689 ins_encode %{
9690 Register dst = $dst$$Register;
9691 Register src1 = $src1$$Register;
9692 Register src2 = $src2$$Register;
9693 __ daddu(dst, src1, src2);
9694 %}
9696 ins_pipe( ialu_regI_regI );
9697 %}
9699 instruct addP_reg_imm(mRegP dst, mRegP src1, immL src2) %{
9700 match(Set dst (AddP src1 src2));
9702 format %{ "daddi $dst, $src1, $src2 #@addP_reg_imm" %}
9703 ins_encode %{
9704 Register src1 = $src1$$Register;
9705 long src2 = $src2$$constant;
9706 Register dst = $dst$$Register;
9708 if(Assembler::is_simm16(src2)) {
9709 __ daddiu(dst, src1, src2);
9710 } else {
9711 __ set64(AT, src2);
9712 __ daddu(dst, src1, AT);
9713 }
9714 %}
9715 ins_pipe( ialu_regI_imm16 );
9716 %}
9718 // Add Long Register with Register
9719 instruct addL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{
9720 match(Set dst (AddL src1 src2));
9721 ins_cost(200);
9722 format %{ "ADD $dst, $src1, $src2 #@addL_Reg_Reg\t" %}
9724 ins_encode %{
9725 Register dst_reg = as_Register($dst$$reg);
9726 Register src1_reg = as_Register($src1$$reg);
9727 Register src2_reg = as_Register($src2$$reg);
9729 __ daddu(dst_reg, src1_reg, src2_reg);
9730 %}
9732 ins_pipe( ialu_regL_regL );
9733 %}
9735 instruct addL_Reg_imm(mRegL dst, mRegL src1, immL16 src2)
9736 %{
9737 match(Set dst (AddL src1 src2));
9739 format %{ "ADD $dst, $src1, $src2 #@addL_Reg_imm " %}
9740 ins_encode %{
9741 Register dst_reg = as_Register($dst$$reg);
9742 Register src1_reg = as_Register($src1$$reg);
9743 int src2_imm = $src2$$constant;
9745 __ daddiu(dst_reg, src1_reg, src2_imm);
9746 %}
9748 ins_pipe( ialu_regL_regL );
9749 %}
9751 instruct addL_RegI2L_imm(mRegL dst, mRegI src1, immL16 src2)
9752 %{
9753 match(Set dst (AddL (ConvI2L src1) src2));
9755 format %{ "ADD $dst, $src1, $src2 #@addL_RegI2L_imm " %}
9756 ins_encode %{
9757 Register dst_reg = as_Register($dst$$reg);
9758 Register src1_reg = as_Register($src1$$reg);
9759 int src2_imm = $src2$$constant;
9761 __ daddiu(dst_reg, src1_reg, src2_imm);
9762 %}
9764 ins_pipe( ialu_regL_regL );
9765 %}
9767 instruct addL_RegI2L_Reg(mRegL dst, mRegI src1, mRegL src2) %{
9768 match(Set dst (AddL (ConvI2L src1) src2));
9769 ins_cost(200);
9770 format %{ "ADD $dst, $src1, $src2 #@addL_RegI2L_Reg\t" %}
9772 ins_encode %{
9773 Register dst_reg = as_Register($dst$$reg);
9774 Register src1_reg = as_Register($src1$$reg);
9775 Register src2_reg = as_Register($src2$$reg);
9777 __ daddu(dst_reg, src1_reg, src2_reg);
9778 %}
9780 ins_pipe( ialu_regL_regL );
9781 %}
9783 instruct addL_RegI2L_RegI2L(mRegL dst, mRegI src1, mRegI src2) %{
9784 match(Set dst (AddL (ConvI2L src1) (ConvI2L src2)));
9785 ins_cost(200);
9786 format %{ "ADD $dst, $src1, $src2 #@addL_RegI2L_RegI2L\t" %}
9788 ins_encode %{
9789 Register dst_reg = as_Register($dst$$reg);
9790 Register src1_reg = as_Register($src1$$reg);
9791 Register src2_reg = as_Register($src2$$reg);
9793 __ daddu(dst_reg, src1_reg, src2_reg);
9794 %}
9796 ins_pipe( ialu_regL_regL );
9797 %}
9799 instruct addL_Reg_RegI2L(mRegL dst, mRegL src1, mRegI src2) %{
9800 match(Set dst (AddL src1 (ConvI2L src2)));
9801 ins_cost(200);
9802 format %{ "ADD $dst, $src1, $src2 #@addL_Reg_RegI2L\t" %}
9804 ins_encode %{
9805 Register dst_reg = as_Register($dst$$reg);
9806 Register src1_reg = as_Register($src1$$reg);
9807 Register src2_reg = as_Register($src2$$reg);
9809 __ daddu(dst_reg, src1_reg, src2_reg);
9810 %}
9812 ins_pipe( ialu_regL_regL );
9813 %}
9815 //----------Subtraction Instructions-------------------------------------------
9816 // Integer Subtraction Instructions
9817 instruct subI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
9818 match(Set dst (SubI src1 src2));
9819 ins_cost(100);
9821 format %{ "sub $dst, $src1, $src2 #@subI_Reg_Reg" %}
9822 ins_encode %{
9823 Register dst = $dst$$Register;
9824 Register src1 = $src1$$Register;
9825 Register src2 = $src2$$Register;
9826 __ subu32(dst, src1, src2);
9827 %}
9828 ins_pipe( ialu_regI_regI );
9829 %}
9831 instruct subI_Reg_immI16_sub(mRegI dst, mRegI src1, immI16_sub src2) %{
9832 match(Set dst (SubI src1 src2));
9833 ins_cost(80);
9835 format %{ "sub $dst, $src1, $src2 #@subI_Reg_immI16_sub" %}
9836 ins_encode %{
9837 Register dst = $dst$$Register;
9838 Register src1 = $src1$$Register;
9839 __ addiu32(dst, src1, -1 * $src2$$constant);
9840 %}
9841 ins_pipe( ialu_regI_regI );
9842 %}
9844 instruct negI_Reg(mRegI dst, immI0 zero, mRegI src) %{
9845 match(Set dst (SubI zero src));
9846 ins_cost(80);
9848 format %{ "neg $dst, $src #@negI_Reg" %}
9849 ins_encode %{
9850 Register dst = $dst$$Register;
9851 Register src = $src$$Register;
9852 __ subu32(dst, R0, src);
9853 %}
9854 ins_pipe( ialu_regI_regI );
9855 %}
9857 instruct negL_Reg(mRegL dst, immL0 zero, mRegL src) %{
9858 match(Set dst (SubL zero src));
9859 ins_cost(80);
9861 format %{ "neg $dst, $src #@negL_Reg" %}
9862 ins_encode %{
9863 Register dst = $dst$$Register;
9864 Register src = $src$$Register;
9865 __ subu(dst, R0, src);
9866 %}
9867 ins_pipe( ialu_regI_regI );
9868 %}
9870 instruct subL_Reg_immL16_sub(mRegL dst, mRegL src1, immL16_sub src2) %{
9871 match(Set dst (SubL src1 src2));
9872 ins_cost(80);
9874 format %{ "sub $dst, $src1, $src2 #@subL_Reg_immL16_sub" %}
9875 ins_encode %{
9876 Register dst = $dst$$Register;
9877 Register src1 = $src1$$Register;
9878 __ daddiu(dst, src1, -1 * $src2$$constant);
9879 %}
9880 ins_pipe( ialu_regI_regI );
9881 %}
9883 // Subtract Long Register with Register.
9884 instruct subL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{
9885 match(Set dst (SubL src1 src2));
9886 ins_cost(100);
9887 format %{ "SubL $dst, $src1, $src2 @ subL_Reg_Reg" %}
9888 ins_encode %{
9889 Register dst = as_Register($dst$$reg);
9890 Register src1 = as_Register($src1$$reg);
9891 Register src2 = as_Register($src2$$reg);
9893 __ subu(dst, src1, src2);
9894 %}
9895 ins_pipe( ialu_regL_regL );
9896 %}
9898 instruct subL_Reg_RegI2L(mRegL dst, mRegL src1, mRegI src2) %{
9899 match(Set dst (SubL src1 (ConvI2L src2)));
9900 ins_cost(100);
9901 format %{ "SubL $dst, $src1, $src2 @ subL_Reg_RegI2L" %}
9902 ins_encode %{
9903 Register dst = as_Register($dst$$reg);
9904 Register src1 = as_Register($src1$$reg);
9905 Register src2 = as_Register($src2$$reg);
9907 __ subu(dst, src1, src2);
9908 %}
9909 ins_pipe( ialu_regL_regL );
9910 %}
9912 instruct subL_RegI2L_Reg(mRegL dst, mRegI src1, mRegL src2) %{
9913 match(Set dst (SubL (ConvI2L src1) src2));
9914 ins_cost(200);
9915 format %{ "SubL $dst, $src1, $src2 @ subL_RegI2L_Reg" %}
9916 ins_encode %{
9917 Register dst = as_Register($dst$$reg);
9918 Register src1 = as_Register($src1$$reg);
9919 Register src2 = as_Register($src2$$reg);
9921 __ subu(dst, src1, src2);
9922 %}
9923 ins_pipe( ialu_regL_regL );
9924 %}
9926 instruct subL_RegI2L_RegI2L(mRegL dst, mRegI src1, mRegI src2) %{
9927 match(Set dst (SubL (ConvI2L src1) (ConvI2L src2)));
9928 ins_cost(200);
9929 format %{ "SubL $dst, $src1, $src2 @ subL_RegI2L_RegI2L" %}
9930 ins_encode %{
9931 Register dst = as_Register($dst$$reg);
9932 Register src1 = as_Register($src1$$reg);
9933 Register src2 = as_Register($src2$$reg);
9935 __ subu(dst, src1, src2);
9936 %}
9937 ins_pipe( ialu_regL_regL );
9938 %}
9940 // Integer MOD with Register
9941 instruct modI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
9942 match(Set dst (ModI src1 src2));
9943 ins_cost(300);
9944 format %{ "modi $dst, $src1, $src2 @ modI_Reg_Reg" %}
9945 ins_encode %{
9946 Register dst = $dst$$Register;
9947 Register src1 = $src1$$Register;
9948 Register src2 = $src2$$Register;
9950 //if (UseLoongsonISA) {
9951 if (0) {
9952 // 2016.08.10
9953 // Experiments show that gsmod is slower that div+mfhi.
9954 // So I just disable it here.
9955 __ gsmod(dst, src1, src2);
9956 } else {
9957 __ div(src1, src2);
9958 __ mfhi(dst);
9959 }
9960 %}
9962 //ins_pipe( ialu_mod );
9963 ins_pipe( ialu_regI_regI );
9964 %}
9966 instruct modL_reg_reg(mRegL dst, mRegL src1, mRegL src2) %{
9967 match(Set dst (ModL src1 src2));
9968 format %{ "modL $dst, $src1, $src2 @modL_reg_reg" %}
9970 ins_encode %{
9971 Register dst = as_Register($dst$$reg);
9972 Register op1 = as_Register($src1$$reg);
9973 Register op2 = as_Register($src2$$reg);
9975 if (UseLoongsonISA) {
9976 __ gsdmod(dst, op1, op2);
9977 } else {
9978 __ ddiv(op1, op2);
9979 __ mfhi(dst);
9980 }
9981 %}
9982 ins_pipe( pipe_slow );
9983 %}
9985 instruct mulI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
9986 match(Set dst (MulI src1 src2));
9988 ins_cost(300);
9989 format %{ "mul $dst, $src1, $src2 @ mulI_Reg_Reg" %}
9990 ins_encode %{
9991 Register src1 = $src1$$Register;
9992 Register src2 = $src2$$Register;
9993 Register dst = $dst$$Register;
9995 __ mul(dst, src1, src2);
9996 %}
9997 ins_pipe( ialu_mult );
9998 %}
10000 instruct maddI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2, mRegI src3) %{
10001 match(Set dst (AddI (MulI src1 src2) src3));
10003 ins_cost(999);
10004 format %{ "madd $dst, $src1 * $src2 + $src3 #@maddI_Reg_Reg" %}
10005 ins_encode %{
10006 Register src1 = $src1$$Register;
10007 Register src2 = $src2$$Register;
10008 Register src3 = $src3$$Register;
10009 Register dst = $dst$$Register;
10011 __ mtlo(src3);
10012 __ madd(src1, src2);
10013 __ mflo(dst);
10014 %}
10015 ins_pipe( ialu_mult );
10016 %}
10018 instruct divI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
10019 match(Set dst (DivI src1 src2));
10021 ins_cost(300);
10022 format %{ "div $dst, $src1, $src2 @ divI_Reg_Reg" %}
10023 ins_encode %{
10024 Register src1 = $src1$$Register;
10025 Register src2 = $src2$$Register;
10026 Register dst = $dst$$Register;
10028 /* 2012/4/21 Jin: In MIPS, div does not cause exception.
10029 We must trap an exception manually. */
10030 __ teq(R0, src2, 0x7);
10032 if (UseLoongsonISA) {
10033 __ gsdiv(dst, src1, src2);
10034 } else {
10035 __ div(src1, src2);
10037 __ nop();
10038 __ nop();
10039 __ mflo(dst);
10040 }
10041 %}
10042 ins_pipe( ialu_mod );
10043 %}
10045 instruct divF_Reg_Reg(regF dst, regF src1, regF src2) %{
10046 match(Set dst (DivF src1 src2));
10048 ins_cost(300);
10049 format %{ "divF $dst, $src1, $src2 @ divF_Reg_Reg" %}
10050 ins_encode %{
10051 FloatRegister src1 = $src1$$FloatRegister;
10052 FloatRegister src2 = $src2$$FloatRegister;
10053 FloatRegister dst = $dst$$FloatRegister;
10055 /* Here do we need to trap an exception manually ? */
10056 __ div_s(dst, src1, src2);
10057 %}
10058 ins_pipe( pipe_slow );
10059 %}
10061 instruct divD_Reg_Reg(regD dst, regD src1, regD src2) %{
10062 match(Set dst (DivD src1 src2));
10064 ins_cost(300);
10065 format %{ "divD $dst, $src1, $src2 @ divD_Reg_Reg" %}
10066 ins_encode %{
10067 FloatRegister src1 = $src1$$FloatRegister;
10068 FloatRegister src2 = $src2$$FloatRegister;
10069 FloatRegister dst = $dst$$FloatRegister;
10071 /* Here do we need to trap an exception manually ? */
10072 __ div_d(dst, src1, src2);
10073 %}
10074 ins_pipe( pipe_slow );
10075 %}
10077 instruct mulL_reg_reg(mRegL dst, mRegL src1, mRegL src2) %{
10078 match(Set dst (MulL src1 src2));
10079 format %{ "mulL $dst, $src1, $src2 @mulL_reg_reg" %}
10080 ins_encode %{
10081 Register dst = as_Register($dst$$reg);
10082 Register op1 = as_Register($src1$$reg);
10083 Register op2 = as_Register($src2$$reg);
10085 if (UseLoongsonISA) {
10086 __ gsdmult(dst, op1, op2);
10087 } else {
10088 __ dmult(op1, op2);
10089 __ mflo(dst);
10090 }
10091 %}
10092 ins_pipe( pipe_slow );
10093 %}
10095 instruct mulL_reg_regI2L(mRegL dst, mRegL src1, mRegI src2) %{
10096 match(Set dst (MulL src1 (ConvI2L src2)));
10097 format %{ "mulL $dst, $src1, $src2 @mulL_reg_regI2L" %}
10098 ins_encode %{
10099 Register dst = as_Register($dst$$reg);
10100 Register op1 = as_Register($src1$$reg);
10101 Register op2 = as_Register($src2$$reg);
10103 if (UseLoongsonISA) {
10104 __ gsdmult(dst, op1, op2);
10105 } else {
10106 __ dmult(op1, op2);
10107 __ mflo(dst);
10108 }
10109 %}
10110 ins_pipe( pipe_slow );
10111 %}
10113 instruct divL_reg_reg(mRegL dst, mRegL src1, mRegL src2) %{
10114 match(Set dst (DivL src1 src2));
10115 format %{ "divL $dst, $src1, $src2 @divL_reg_reg" %}
10117 ins_encode %{
10118 Register dst = as_Register($dst$$reg);
10119 Register op1 = as_Register($src1$$reg);
10120 Register op2 = as_Register($src2$$reg);
10122 if (UseLoongsonISA) {
10123 __ gsddiv(dst, op1, op2);
10124 } else {
10125 __ ddiv(op1, op2);
10126 __ mflo(dst);
10127 }
10128 %}
10129 ins_pipe( pipe_slow );
10130 %}
10132 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
10133 match(Set dst (AddF src1 src2));
10134 format %{ "AddF $dst, $src1, $src2 @addF_reg_reg" %}
10135 ins_encode %{
10136 FloatRegister src1 = as_FloatRegister($src1$$reg);
10137 FloatRegister src2 = as_FloatRegister($src2$$reg);
10138 FloatRegister dst = as_FloatRegister($dst$$reg);
10140 __ add_s(dst, src1, src2);
10141 %}
10142 ins_pipe( fpu_regF_regF );
10143 %}
10145 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
10146 match(Set dst (SubF src1 src2));
10147 format %{ "SubF $dst, $src1, $src2 @subF_reg_reg" %}
10148 ins_encode %{
10149 FloatRegister src1 = as_FloatRegister($src1$$reg);
10150 FloatRegister src2 = as_FloatRegister($src2$$reg);
10151 FloatRegister dst = as_FloatRegister($dst$$reg);
10153 __ sub_s(dst, src1, src2);
10154 %}
10155 ins_pipe( fpu_regF_regF );
10156 %}
10157 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
10158 match(Set dst (AddD src1 src2));
10159 format %{ "AddD $dst, $src1, $src2 @addD_reg_reg" %}
10160 ins_encode %{
10161 FloatRegister src1 = as_FloatRegister($src1$$reg);
10162 FloatRegister src2 = as_FloatRegister($src2$$reg);
10163 FloatRegister dst = as_FloatRegister($dst$$reg);
10165 __ add_d(dst, src1, src2);
10166 %}
10167 ins_pipe( fpu_regF_regF );
10168 %}
10170 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
10171 match(Set dst (SubD src1 src2));
10172 format %{ "SubD $dst, $src1, $src2 @subD_reg_reg" %}
10173 ins_encode %{
10174 FloatRegister src1 = as_FloatRegister($src1$$reg);
10175 FloatRegister src2 = as_FloatRegister($src2$$reg);
10176 FloatRegister dst = as_FloatRegister($dst$$reg);
10178 __ sub_d(dst, src1, src2);
10179 %}
10180 ins_pipe( fpu_regF_regF );
10181 %}
10183 instruct negF_reg(regF dst, regF src) %{
10184 match(Set dst (NegF src));
10185 format %{ "negF $dst, $src @negF_reg" %}
10186 ins_encode %{
10187 FloatRegister src = as_FloatRegister($src$$reg);
10188 FloatRegister dst = as_FloatRegister($dst$$reg);
10190 __ neg_s(dst, src);
10191 %}
10192 ins_pipe( fpu_regF_regF );
10193 %}
10195 instruct negD_reg(regD dst, regD src) %{
10196 match(Set dst (NegD src));
10197 format %{ "negD $dst, $src @negD_reg" %}
10198 ins_encode %{
10199 FloatRegister src = as_FloatRegister($src$$reg);
10200 FloatRegister dst = as_FloatRegister($dst$$reg);
10202 __ neg_d(dst, src);
10203 %}
10204 ins_pipe( fpu_regF_regF );
10205 %}
10208 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
10209 match(Set dst (MulF src1 src2));
10210 format %{ "MULF $dst, $src1, $src2 @mulF_reg_reg" %}
10211 ins_encode %{
10212 FloatRegister src1 = $src1$$FloatRegister;
10213 FloatRegister src2 = $src2$$FloatRegister;
10214 FloatRegister dst = $dst$$FloatRegister;
10216 __ mul_s(dst, src1, src2);
10217 %}
10218 ins_pipe( fpu_regF_regF );
10219 %}
10221 instruct maddF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
10222 match(Set dst (AddF (MulF src1 src2) src3));
10223 // For compatibility reason (e.g. on the Loongson platform), disable this guy.
10224 ins_cost(44444);
10225 format %{ "maddF $dst, $src1, $src2, $src3 @maddF_reg_reg" %}
10226 ins_encode %{
10227 FloatRegister src1 = $src1$$FloatRegister;
10228 FloatRegister src2 = $src2$$FloatRegister;
10229 FloatRegister src3 = $src3$$FloatRegister;
10230 FloatRegister dst = $dst$$FloatRegister;
10232 __ madd_s(dst, src1, src2, src3);
10233 %}
10234 ins_pipe( fpu_regF_regF );
10235 %}
10237 // Mul two double precision floating piont number
10238 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
10239 match(Set dst (MulD src1 src2));
10240 format %{ "MULD $dst, $src1, $src2 @mulD_reg_reg" %}
10241 ins_encode %{
10242 FloatRegister src1 = $src1$$FloatRegister;
10243 FloatRegister src2 = $src2$$FloatRegister;
10244 FloatRegister dst = $dst$$FloatRegister;
10246 __ mul_d(dst, src1, src2);
10247 %}
10248 ins_pipe( fpu_regF_regF );
10249 %}
10251 instruct maddD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
10252 match(Set dst (AddD (MulD src1 src2) src3));
10253 // For compatibility reason (e.g. on the Loongson platform), disable this guy.
10254 ins_cost(44444);
10255 format %{ "maddD $dst, $src1, $src2, $src3 @maddD_reg_reg" %}
10256 ins_encode %{
10257 FloatRegister src1 = $src1$$FloatRegister;
10258 FloatRegister src2 = $src2$$FloatRegister;
10259 FloatRegister src3 = $src3$$FloatRegister;
10260 FloatRegister dst = $dst$$FloatRegister;
10262 __ madd_d(dst, src1, src2, src3);
10263 %}
10264 ins_pipe( fpu_regF_regF );
10265 %}
10267 instruct absF_reg(regF dst, regF src) %{
10268 match(Set dst (AbsF src));
10269 ins_cost(100);
10270 format %{ "absF $dst, $src @absF_reg" %}
10271 ins_encode %{
10272 FloatRegister src = as_FloatRegister($src$$reg);
10273 FloatRegister dst = as_FloatRegister($dst$$reg);
10275 __ abs_s(dst, src);
10276 %}
10277 ins_pipe( fpu_regF_regF );
10278 %}
10281 // intrinsics for math_native.
10282 // AbsD SqrtD CosD SinD TanD LogD Log10D
10284 instruct absD_reg(regD dst, regD src) %{
10285 match(Set dst (AbsD src));
10286 ins_cost(100);
10287 format %{ "absD $dst, $src @absD_reg" %}
10288 ins_encode %{
10289 FloatRegister src = as_FloatRegister($src$$reg);
10290 FloatRegister dst = as_FloatRegister($dst$$reg);
10292 __ abs_d(dst, src);
10293 %}
10294 ins_pipe( fpu_regF_regF );
10295 %}
10297 instruct sqrtD_reg(regD dst, regD src) %{
10298 match(Set dst (SqrtD src));
10299 ins_cost(100);
10300 format %{ "SqrtD $dst, $src @sqrtD_reg" %}
10301 ins_encode %{
10302 FloatRegister src = as_FloatRegister($src$$reg);
10303 FloatRegister dst = as_FloatRegister($dst$$reg);
10305 __ sqrt_d(dst, src);
10306 %}
10307 ins_pipe( fpu_regF_regF );
10308 %}
10310 instruct sqrtF_reg(regF dst, regF src) %{
10311 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
10312 ins_cost(100);
10313 format %{ "SqrtF $dst, $src @sqrtF_reg" %}
10314 ins_encode %{
10315 FloatRegister src = as_FloatRegister($src$$reg);
10316 FloatRegister dst = as_FloatRegister($dst$$reg);
10318 __ sqrt_s(dst, src);
10319 %}
10320 ins_pipe( fpu_regF_regF );
10321 %}
10322 //----------------------------------Logical Instructions----------------------
10323 //__________________________________Integer Logical Instructions-------------
10325 //And Instuctions
10326 // And Register with Immediate
10327 instruct andI_Reg_immI(mRegI dst, mRegI src1, immI src2) %{
10328 match(Set dst (AndI src1 src2));
10330 format %{ "and $dst, $src1, $src2 #@andI_Reg_immI" %}
10331 ins_encode %{
10332 Register dst = $dst$$Register;
10333 Register src = $src1$$Register;
10334 int val = $src2$$constant;
10336 __ move(AT, val);
10337 __ andr(dst, src, AT);
10338 %}
10339 ins_pipe( ialu_regI_regI );
10340 %}
10342 instruct andI_Reg_imm_0_65535(mRegI dst, mRegI src1, immI_0_65535 src2) %{
10343 match(Set dst (AndI src1 src2));
10344 ins_cost(60);
10346 format %{ "and $dst, $src1, $src2 #@andI_Reg_imm_0_65535" %}
10347 ins_encode %{
10348 Register dst = $dst$$Register;
10349 Register src = $src1$$Register;
10350 int val = $src2$$constant;
10352 __ andi(dst, src, val);
10353 %}
10354 ins_pipe( ialu_regI_regI );
10355 %}
10357 instruct andI_Reg_immI_nonneg_mask(mRegI dst, mRegI src1, immI_nonneg_mask mask) %{
10358 match(Set dst (AndI src1 mask));
10359 ins_cost(60);
10361 format %{ "and $dst, $src1, $mask #@andI_Reg_immI_nonneg_mask" %}
10362 ins_encode %{
10363 Register dst = $dst$$Register;
10364 Register src = $src1$$Register;
10365 int size = Assembler::is_int_mask($mask$$constant);
10367 __ ext(dst, src, 0, size);
10368 %}
10369 ins_pipe( ialu_regI_regI );
10370 %}
10372 instruct andL_Reg_immL_nonneg_mask(mRegL dst, mRegL src1, immL_nonneg_mask mask) %{
10373 match(Set dst (AndL src1 mask));
10374 ins_cost(60);
10376 format %{ "and $dst, $src1, $mask #@andL_Reg_immL_nonneg_mask" %}
10377 ins_encode %{
10378 Register dst = $dst$$Register;
10379 Register src = $src1$$Register;
10380 int size = Assembler::is_jlong_mask($mask$$constant);
10382 __ dext(dst, src, 0, size);
10383 %}
10384 ins_pipe( ialu_regI_regI );
10385 %}
10387 instruct xorI_Reg_imm_0_65535(mRegI dst, mRegI src1, immI_0_65535 src2) %{
10388 match(Set dst (XorI src1 src2));
10389 ins_cost(60);
10391 format %{ "xori $dst, $src1, $src2 #@xorI_Reg_imm_0_65535" %}
10392 ins_encode %{
10393 Register dst = $dst$$Register;
10394 Register src = $src1$$Register;
10395 int val = $src2$$constant;
10397 __ xori(dst, src, val);
10398 %}
10399 ins_pipe( ialu_regI_regI );
10400 %}
10402 instruct xorI_Reg_immI_M1(mRegI dst, mRegI src1, immI_M1 M1) %{
10403 match(Set dst (XorI src1 M1));
10404 predicate(UseLoongsonISA);
10405 ins_cost(60);
10407 format %{ "xor $dst, $src1, $M1 #@xorI_Reg_immI_M1" %}
10408 ins_encode %{
10409 Register dst = $dst$$Register;
10410 Register src = $src1$$Register;
10412 __ gsorn(dst, R0, src);
10413 %}
10414 ins_pipe( ialu_regI_regI );
10415 %}
10417 instruct xorL_Reg_imm_0_65535(mRegL dst, mRegL src1, immL_0_65535 src2) %{
10418 match(Set dst (XorL src1 src2));
10419 ins_cost(60);
10421 format %{ "xori $dst, $src1, $src2 #@xorL_Reg_imm_0_65535" %}
10422 ins_encode %{
10423 Register dst = $dst$$Register;
10424 Register src = $src1$$Register;
10425 int val = $src2$$constant;
10427 __ xori(dst, src, val);
10428 %}
10429 ins_pipe( ialu_regI_regI );
10430 %}
10432 /*
10433 instruct xorL_Reg_immL_M1(mRegL dst, mRegL src1, immL_M1 M1) %{
10434 match(Set dst (XorL src1 M1));
10435 predicate(UseLoongsonISA);
10436 ins_cost(60);
10438 format %{ "xor $dst, $src1, $M1 #@xorL_Reg_immL_M1" %}
10439 ins_encode %{
10440 Register dst = $dst$$Register;
10441 Register src = $src1$$Register;
10443 __ gsorn(dst, R0, src);
10444 %}
10445 ins_pipe( ialu_regI_regI );
10446 %}
10447 */
10449 instruct lbu_and_lmask(mRegI dst, memory mem, immI_255 mask) %{
10450 match(Set dst (AndI mask (LoadB mem)));
10451 ins_cost(60);
10453 format %{ "lhu $dst, $mem #@lbu_and_lmask" %}
10454 ins_encode(load_UB_enc(dst, mem));
10455 ins_pipe( ialu_loadI );
10456 %}
10458 instruct lbu_and_rmask(mRegI dst, memory mem, immI_255 mask) %{
10459 match(Set dst (AndI (LoadB mem) mask));
10460 ins_cost(60);
10462 format %{ "lhu $dst, $mem #@lbu_and_rmask" %}
10463 ins_encode(load_UB_enc(dst, mem));
10464 ins_pipe( ialu_loadI );
10465 %}
10467 instruct andI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
10468 match(Set dst (AndI src1 src2));
10470 format %{ "and $dst, $src1, $src2 #@andI_Reg_Reg" %}
10471 ins_encode %{
10472 Register dst = $dst$$Register;
10473 Register src1 = $src1$$Register;
10474 Register src2 = $src2$$Register;
10475 __ andr(dst, src1, src2);
10476 %}
10477 ins_pipe( ialu_regI_regI );
10478 %}
10480 instruct andnI_Reg_nReg(mRegI dst, mRegI src1, mRegI src2, immI_M1 M1) %{
10481 match(Set dst (AndI src1 (XorI src2 M1)));
10482 predicate(UseLoongsonISA);
10484 format %{ "andn $dst, $src1, $src2 #@andnI_Reg_nReg" %}
10485 ins_encode %{
10486 Register dst = $dst$$Register;
10487 Register src1 = $src1$$Register;
10488 Register src2 = $src2$$Register;
10490 __ gsandn(dst, src1, src2);
10491 %}
10492 ins_pipe( ialu_regI_regI );
10493 %}
10495 instruct ornI_Reg_nReg(mRegI dst, mRegI src1, mRegI src2, immI_M1 M1) %{
10496 match(Set dst (OrI src1 (XorI src2 M1)));
10497 predicate(UseLoongsonISA);
10499 format %{ "orn $dst, $src1, $src2 #@ornI_Reg_nReg" %}
10500 ins_encode %{
10501 Register dst = $dst$$Register;
10502 Register src1 = $src1$$Register;
10503 Register src2 = $src2$$Register;
10505 __ gsorn(dst, src1, src2);
10506 %}
10507 ins_pipe( ialu_regI_regI );
10508 %}
10510 instruct andnI_nReg_Reg(mRegI dst, mRegI src1, mRegI src2, immI_M1 M1) %{
10511 match(Set dst (AndI (XorI src1 M1) src2));
10512 predicate(UseLoongsonISA);
10514 format %{ "andn $dst, $src2, $src1 #@andnI_nReg_Reg" %}
10515 ins_encode %{
10516 Register dst = $dst$$Register;
10517 Register src1 = $src1$$Register;
10518 Register src2 = $src2$$Register;
10520 __ gsandn(dst, src2, src1);
10521 %}
10522 ins_pipe( ialu_regI_regI );
10523 %}
10525 instruct ornI_nReg_Reg(mRegI dst, mRegI src1, mRegI src2, immI_M1 M1) %{
10526 match(Set dst (OrI (XorI src1 M1) src2));
10527 predicate(UseLoongsonISA);
10529 format %{ "orn $dst, $src2, $src1 #@ornI_nReg_Reg" %}
10530 ins_encode %{
10531 Register dst = $dst$$Register;
10532 Register src1 = $src1$$Register;
10533 Register src2 = $src2$$Register;
10535 __ gsorn(dst, src2, src1);
10536 %}
10537 ins_pipe( ialu_regI_regI );
10538 %}
10540 // And Long Register with Register
10541 instruct andL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{
10542 match(Set dst (AndL src1 src2));
10543 format %{ "AND $dst, $src1, $src2 @ andL_Reg_Reg\n\t" %}
10544 ins_encode %{
10545 Register dst_reg = as_Register($dst$$reg);
10546 Register src1_reg = as_Register($src1$$reg);
10547 Register src2_reg = as_Register($src2$$reg);
10549 __ andr(dst_reg, src1_reg, src2_reg);
10550 %}
10551 ins_pipe( ialu_regL_regL );
10552 %}
10554 instruct andL_Reg_Reg_convI2L(mRegL dst, mRegL src1, mRegI src2) %{
10555 match(Set dst (AndL src1 (ConvI2L src2)));
10556 format %{ "AND $dst, $src1, $src2 @ andL_Reg_Reg_convI2L\n\t" %}
10557 ins_encode %{
10558 Register dst_reg = as_Register($dst$$reg);
10559 Register src1_reg = as_Register($src1$$reg);
10560 Register src2_reg = as_Register($src2$$reg);
10562 __ andr(dst_reg, src1_reg, src2_reg);
10563 %}
10564 ins_pipe( ialu_regL_regL );
10565 %}
10567 instruct andL_Reg_imm_0_65535(mRegL dst, mRegL src1, immL_0_65535 src2) %{
10568 match(Set dst (AndL src1 src2));
10569 ins_cost(60);
10571 format %{ "and $dst, $src1, $src2 #@andL_Reg_imm_0_65535" %}
10572 ins_encode %{
10573 Register dst = $dst$$Register;
10574 Register src = $src1$$Register;
10575 long val = $src2$$constant;
10577 __ andi(dst, src, val);
10578 %}
10579 ins_pipe( ialu_regI_regI );
10580 %}
10582 /*
10583 instruct andnL_Reg_nReg(mRegL dst, mRegL src1, mRegL src2, immL_M1 M1) %{
10584 match(Set dst (AndL src1 (XorL src2 M1)));
10585 predicate(UseLoongsonISA);
10587 format %{ "andn $dst, $src1, $src2 #@andnL_Reg_nReg" %}
10588 ins_encode %{
10589 Register dst = $dst$$Register;
10590 Register src1 = $src1$$Register;
10591 Register src2 = $src2$$Register;
10593 __ gsandn(dst, src1, src2);
10594 %}
10595 ins_pipe( ialu_regI_regI );
10596 %}
10597 */
10599 /*
10600 instruct ornL_Reg_nReg(mRegL dst, mRegL src1, mRegL src2, immL_M1 M1) %{
10601 match(Set dst (OrL src1 (XorL src2 M1)));
10602 predicate(UseLoongsonISA);
10604 format %{ "orn $dst, $src1, $src2 #@ornL_Reg_nReg" %}
10605 ins_encode %{
10606 Register dst = $dst$$Register;
10607 Register src1 = $src1$$Register;
10608 Register src2 = $src2$$Register;
10610 __ gsorn(dst, src1, src2);
10611 %}
10612 ins_pipe( ialu_regI_regI );
10613 %}
10614 */
10616 /*
10617 instruct andnL_nReg_Reg(mRegL dst, mRegL src1, mRegL src2, immL_M1 M1) %{
10618 match(Set dst (AndL (XorL src1 M1) src2));
10619 predicate(UseLoongsonISA);
10621 format %{ "andn $dst, $src2, $src1 #@andnL_nReg_Reg" %}
10622 ins_encode %{
10623 Register dst = $dst$$Register;
10624 Register src1 = $src1$$Register;
10625 Register src2 = $src2$$Register;
10627 __ gsandn(dst, src2, src1);
10628 %}
10629 ins_pipe( ialu_regI_regI );
10630 %}
10631 */
10633 /*
10634 instruct ornL_nReg_Reg(mRegL dst, mRegL src1, mRegL src2, immL_M1 M1) %{
10635 match(Set dst (OrL (XorL src1 M1) src2));
10636 predicate(UseLoongsonISA);
10638 format %{ "orn $dst, $src2, $src1 #@ornL_nReg_Reg" %}
10639 ins_encode %{
10640 Register dst = $dst$$Register;
10641 Register src1 = $src1$$Register;
10642 Register src2 = $src2$$Register;
10644 __ gsorn(dst, src2, src1);
10645 %}
10646 ins_pipe( ialu_regI_regI );
10647 %}
10648 */
10650 instruct andL_Reg_immL_M8(mRegL dst, immL_M8 M8) %{
10651 match(Set dst (AndL dst M8));
10652 ins_cost(60);
10654 format %{ "and $dst, $dst, $M8 #@andL_Reg_immL_M8" %}
10655 ins_encode %{
10656 Register dst = $dst$$Register;
10658 __ dins(dst, R0, 0, 3);
10659 %}
10660 ins_pipe( ialu_regI_regI );
10661 %}
10663 instruct andL_Reg_immL_M5(mRegL dst, immL_M5 M5) %{
10664 match(Set dst (AndL dst M5));
10665 ins_cost(60);
10667 format %{ "and $dst, $dst, $M5 #@andL_Reg_immL_M5" %}
10668 ins_encode %{
10669 Register dst = $dst$$Register;
10671 __ dins(dst, R0, 2, 1);
10672 %}
10673 ins_pipe( ialu_regI_regI );
10674 %}
10676 instruct andL_Reg_immL_M7(mRegL dst, immL_M7 M7) %{
10677 match(Set dst (AndL dst M7));
10678 ins_cost(60);
10680 format %{ "and $dst, $dst, $M7 #@andL_Reg_immL_M7" %}
10681 ins_encode %{
10682 Register dst = $dst$$Register;
10684 __ dins(dst, R0, 1, 2);
10685 %}
10686 ins_pipe( ialu_regI_regI );
10687 %}
10689 instruct andL_Reg_immL_M4(mRegL dst, immL_M4 M4) %{
10690 match(Set dst (AndL dst M4));
10691 ins_cost(60);
10693 format %{ "and $dst, $dst, $M4 #@andL_Reg_immL_M4" %}
10694 ins_encode %{
10695 Register dst = $dst$$Register;
10697 __ dins(dst, R0, 0, 2);
10698 %}
10699 ins_pipe( ialu_regI_regI );
10700 %}
10702 instruct andL_Reg_immL_M121(mRegL dst, immL_M121 M121) %{
10703 match(Set dst (AndL dst M121));
10704 ins_cost(60);
10706 format %{ "and $dst, $dst, $M121 #@andL_Reg_immL_M121" %}
10707 ins_encode %{
10708 Register dst = $dst$$Register;
10710 __ dins(dst, R0, 3, 4);
10711 %}
10712 ins_pipe( ialu_regI_regI );
10713 %}
10715 // Or Long Register with Register
10716 instruct orL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{
10717 match(Set dst (OrL src1 src2));
10718 format %{ "OR $dst, $src1, $src2 @ orL_Reg_Reg\t" %}
10719 ins_encode %{
10720 Register dst_reg = $dst$$Register;
10721 Register src1_reg = $src1$$Register;
10722 Register src2_reg = $src2$$Register;
10724 __ orr(dst_reg, src1_reg, src2_reg);
10725 %}
10726 ins_pipe( ialu_regL_regL );
10727 %}
10729 instruct orL_Reg_P2XReg(mRegL dst, mRegP src1, mRegL src2) %{
10730 match(Set dst (OrL (CastP2X src1) src2));
10731 format %{ "OR $dst, $src1, $src2 @ orL_Reg_P2XReg\t" %}
10732 ins_encode %{
10733 Register dst_reg = $dst$$Register;
10734 Register src1_reg = $src1$$Register;
10735 Register src2_reg = $src2$$Register;
10737 __ orr(dst_reg, src1_reg, src2_reg);
10738 %}
10739 ins_pipe( ialu_regL_regL );
10740 %}
10742 // Xor Long Register with Register
10743 instruct xorL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{
10744 match(Set dst (XorL src1 src2));
10745 format %{ "XOR $dst, $src1, $src2 @ xorL_Reg_Reg\t" %}
10746 ins_encode %{
10747 Register dst_reg = as_Register($dst$$reg);
10748 Register src1_reg = as_Register($src1$$reg);
10749 Register src2_reg = as_Register($src2$$reg);
10751 __ xorr(dst_reg, src1_reg, src2_reg);
10752 %}
10753 ins_pipe( ialu_regL_regL );
10754 %}
10756 // Shift Left by 8-bit immediate
10757 instruct salI_Reg_imm(mRegI dst, mRegI src, immI8 shift) %{
10758 match(Set dst (LShiftI src shift));
10760 format %{ "SHL $dst, $src, $shift #@salI_Reg_imm" %}
10761 ins_encode %{
10762 Register src = $src$$Register;
10763 Register dst = $dst$$Register;
10764 int shamt = $shift$$constant;
10766 __ sll(dst, src, shamt);
10767 %}
10768 ins_pipe( ialu_regI_regI );
10769 %}
10771 instruct salI_Reg_imm_and_M65536(mRegI dst, mRegI src, immI_16 shift, immI_M65536 mask) %{
10772 match(Set dst (AndI (LShiftI src shift) mask));
10774 format %{ "SHL $dst, $src, $shift #@salI_Reg_imm_and_M65536" %}
10775 ins_encode %{
10776 Register src = $src$$Register;
10777 Register dst = $dst$$Register;
10779 __ sll(dst, src, 16);
10780 %}
10781 ins_pipe( ialu_regI_regI );
10782 %}
10784 instruct land7_2_s(mRegI dst, mRegL src, immL7 seven, immI_16 sixteen)
10785 %{
10786 match(Set dst (RShiftI (LShiftI (ConvL2I (AndL src seven)) sixteen) sixteen));
10788 format %{ "andi $dst, $src, 7\t# @land7_2_s" %}
10789 ins_encode %{
10790 Register src = $src$$Register;
10791 Register dst = $dst$$Register;
10793 __ andi(dst, src, 7);
10794 %}
10795 ins_pipe(ialu_regI_regI);
10796 %}
10798 instruct ori2s(mRegI dst, mRegI src1, immI_0_32767 src2, immI_16 sixteen)
10799 %{
10800 match(Set dst (RShiftI (LShiftI (OrI src1 src2) sixteen) sixteen));
10802 format %{ "ori $dst, $src1, $src2\t# @ori2s" %}
10803 ins_encode %{
10804 Register src = $src1$$Register;
10805 int val = $src2$$constant;
10806 Register dst = $dst$$Register;
10808 __ ori(dst, src, val);
10809 %}
10810 ins_pipe(ialu_regI_regI);
10811 %}
10813 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
10814 // This idiom is used by the compiler the i2s bytecode.
10815 instruct i2s(mRegI dst, mRegI src, immI_16 sixteen)
10816 %{
10817 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
10819 format %{ "i2s $dst, $src\t# @i2s" %}
10820 ins_encode %{
10821 Register src = $src$$Register;
10822 Register dst = $dst$$Register;
10824 __ seh(dst, src);
10825 %}
10826 ins_pipe(ialu_regI_regI);
10827 %}
10829 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
10830 // This idiom is used by the compiler for the i2b bytecode.
10831 instruct i2b(mRegI dst, mRegI src, immI_24 twentyfour)
10832 %{
10833 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
10835 format %{ "i2b $dst, $src\t# @i2b" %}
10836 ins_encode %{
10837 Register src = $src$$Register;
10838 Register dst = $dst$$Register;
10840 __ seb(dst, src);
10841 %}
10842 ins_pipe(ialu_regI_regI);
10843 %}
10846 instruct salI_RegL2I_imm(mRegI dst, mRegL src, immI8 shift) %{
10847 match(Set dst (LShiftI (ConvL2I src) shift));
10849 format %{ "SHL $dst, $src, $shift #@salI_RegL2I_imm" %}
10850 ins_encode %{
10851 Register src = $src$$Register;
10852 Register dst = $dst$$Register;
10853 int shamt = $shift$$constant;
10855 __ sll(dst, src, shamt);
10856 %}
10857 ins_pipe( ialu_regI_regI );
10858 %}
10860 // Shift Left by 8-bit immediate
10861 instruct salI_Reg_Reg(mRegI dst, mRegI src, mRegI shift) %{
10862 match(Set dst (LShiftI src shift));
10864 format %{ "SHL $dst, $src, $shift #@salI_Reg_Reg" %}
10865 ins_encode %{
10866 Register src = $src$$Register;
10867 Register dst = $dst$$Register;
10868 Register shamt = $shift$$Register;
10869 __ sllv(dst, src, shamt);
10870 %}
10871 ins_pipe( ialu_regI_regI );
10872 %}
10875 // Shift Left Long
10876 instruct salL_Reg_imm(mRegL dst, mRegL src, immI8 shift) %{
10877 //predicate(UseNewLongLShift);
10878 match(Set dst (LShiftL src shift));
10879 ins_cost(100);
10880 format %{ "salL $dst, $src, $shift @ salL_Reg_imm" %}
10881 ins_encode %{
10882 Register src_reg = as_Register($src$$reg);
10883 Register dst_reg = as_Register($dst$$reg);
10884 int shamt = $shift$$constant;
10886 if (__ is_simm(shamt, 5))
10887 __ dsll(dst_reg, src_reg, shamt);
10888 else
10889 {
10890 int sa = Assembler::low(shamt, 6);
10891 if (sa < 32) {
10892 __ dsll(dst_reg, src_reg, sa);
10893 } else {
10894 __ dsll32(dst_reg, src_reg, sa - 32);
10895 }
10896 }
10897 %}
10898 ins_pipe( ialu_regL_regL );
10899 %}
10901 instruct salL_RegI2L_imm(mRegL dst, mRegI src, immI8 shift) %{
10902 //predicate(UseNewLongLShift);
10903 match(Set dst (LShiftL (ConvI2L src) shift));
10904 ins_cost(100);
10905 format %{ "salL $dst, $src, $shift @ salL_RegI2L_imm" %}
10906 ins_encode %{
10907 Register src_reg = as_Register($src$$reg);
10908 Register dst_reg = as_Register($dst$$reg);
10909 int shamt = $shift$$constant;
10911 if (__ is_simm(shamt, 5))
10912 __ dsll(dst_reg, src_reg, shamt);
10913 else
10914 {
10915 int sa = Assembler::low(shamt, 6);
10916 if (sa < 32) {
10917 __ dsll(dst_reg, src_reg, sa);
10918 } else {
10919 __ dsll32(dst_reg, src_reg, sa - 32);
10920 }
10921 }
10922 %}
10923 ins_pipe( ialu_regL_regL );
10924 %}
10926 // Shift Left Long
10927 instruct salL_Reg_Reg(mRegL dst, mRegL src, mRegI shift) %{
10928 //predicate(UseNewLongLShift);
10929 match(Set dst (LShiftL src shift));
10930 ins_cost(100);
10931 format %{ "salL $dst, $src, $shift @ salL_Reg_Reg" %}
10932 ins_encode %{
10933 Register src_reg = as_Register($src$$reg);
10934 Register dst_reg = as_Register($dst$$reg);
10936 __ dsllv(dst_reg, src_reg, $shift$$Register);
10937 %}
10938 ins_pipe( ialu_regL_regL );
10939 %}
10941 instruct salL_convI2L_Reg_imm(mRegL dst, mRegI src, immI8 shift) %{
10942 match(Set dst (LShiftL (ConvI2L src) shift));
10943 ins_cost(100);
10944 format %{ "salL $dst, $src, $shift @ salL_convI2L_Reg_imm" %}
10945 ins_encode %{
10946 Register src_reg = as_Register($src$$reg);
10947 Register dst_reg = as_Register($dst$$reg);
10948 int shamt = $shift$$constant;
10950 if (__ is_simm(shamt, 5)) {
10951 __ dsll(dst_reg, src_reg, shamt);
10952 } else {
10953 int sa = Assembler::low(shamt, 6);
10954 if (sa < 32) {
10955 __ dsll(dst_reg, src_reg, sa);
10956 } else {
10957 __ dsll32(dst_reg, src_reg, sa - 32);
10958 }
10959 }
10960 %}
10961 ins_pipe( ialu_regL_regL );
10962 %}
10964 // Shift Right Long
10965 instruct sarL_Reg_imm(mRegL dst, mRegL src, immI8 shift) %{
10966 //predicate(UseNewLongLShift);
10967 match(Set dst (RShiftL src shift));
10968 ins_cost(100);
10969 format %{ "sarL $dst, $src, $shift @ sarL_Reg_imm" %}
10970 ins_encode %{
10971 Register src_reg = as_Register($src$$reg);
10972 Register dst_reg = as_Register($dst$$reg);
10973 int shamt = ($shift$$constant & 0x3f);
10974 if (__ is_simm(shamt, 5))
10975 __ dsra(dst_reg, src_reg, shamt);
10976 else {
10977 int sa = Assembler::low(shamt, 6);
10978 if (sa < 32) {
10979 __ dsra(dst_reg, src_reg, sa);
10980 } else {
10981 __ dsra32(dst_reg, src_reg, sa - 32);
10982 }
10983 }
10984 %}
10985 ins_pipe( ialu_regL_regL );
10986 %}
10988 // Shift Right Long arithmetically
10989 instruct sarL_Reg_Reg(mRegL dst, mRegL src, mRegI shift) %{
10990 //predicate(UseNewLongLShift);
10991 match(Set dst (RShiftL src shift));
10992 ins_cost(100);
10993 format %{ "sarL $dst, $src, $shift @ sarL_Reg_Reg" %}
10994 ins_encode %{
10995 Register src_reg = as_Register($src$$reg);
10996 Register dst_reg = as_Register($dst$$reg);
10998 __ dsrav(dst_reg, src_reg, $shift$$Register);
10999 %}
11000 ins_pipe( ialu_regL_regL );
11001 %}
11003 // Shift Right Long logically
11004 instruct slrL_Reg_Reg(mRegL dst, mRegL src, mRegI shift) %{
11005 match(Set dst (URShiftL src shift));
11006 ins_cost(100);
11007 format %{ "slrL $dst, $src, $shift @ slrL_Reg_Reg" %}
11008 ins_encode %{
11009 Register src_reg = as_Register($src$$reg);
11010 Register dst_reg = as_Register($dst$$reg);
11012 __ dsrlv(dst_reg, src_reg, $shift$$Register);
11013 %}
11014 ins_pipe( ialu_regL_regL );
11015 %}
11017 instruct slrL_Reg_immI_0_31(mRegL dst, mRegL src, immI_0_31 shift) %{
11018 match(Set dst (URShiftL src shift));
11019 ins_cost(80);
11020 format %{ "slrL $dst, $src, $shift @ slrL_Reg_immI_0_31" %}
11021 ins_encode %{
11022 Register src_reg = as_Register($src$$reg);
11023 Register dst_reg = as_Register($dst$$reg);
11024 int shamt = $shift$$constant;
11026 __ dsrl(dst_reg, src_reg, shamt);
11027 %}
11028 ins_pipe( ialu_regL_regL );
11029 %}
11031 instruct slrL_P2XReg_immI_0_31(mRegL dst, mRegP src, immI_0_31 shift) %{
11032 match(Set dst (URShiftL (CastP2X src) shift));
11033 ins_cost(80);
11034 format %{ "slrL $dst, $src, $shift @ slrL_P2XReg_immI_0_31" %}
11035 ins_encode %{
11036 Register src_reg = as_Register($src$$reg);
11037 Register dst_reg = as_Register($dst$$reg);
11038 int shamt = $shift$$constant;
11040 __ dsrl(dst_reg, src_reg, shamt);
11041 %}
11042 ins_pipe( ialu_regL_regL );
11043 %}
11045 instruct slrL_Reg_immI_32_63(mRegL dst, mRegL src, immI_32_63 shift) %{
11046 match(Set dst (URShiftL src shift));
11047 ins_cost(80);
11048 format %{ "slrL $dst, $src, $shift @ slrL_Reg_immI_32_63" %}
11049 ins_encode %{
11050 Register src_reg = as_Register($src$$reg);
11051 Register dst_reg = as_Register($dst$$reg);
11052 int shamt = $shift$$constant;
11054 __ dsrl32(dst_reg, src_reg, shamt - 32);
11055 %}
11056 ins_pipe( ialu_regL_regL );
11057 %}
11059 instruct slrL_P2XReg_immI_32_63(mRegL dst, mRegP src, immI_32_63 shift) %{
11060 match(Set dst (URShiftL (CastP2X src) shift));
11061 ins_cost(80);
11062 format %{ "slrL $dst, $src, $shift @ slrL_P2XReg_immI_32_63" %}
11063 ins_encode %{
11064 Register src_reg = as_Register($src$$reg);
11065 Register dst_reg = as_Register($dst$$reg);
11066 int shamt = $shift$$constant;
11068 __ dsrl32(dst_reg, src_reg, shamt - 32);
11069 %}
11070 ins_pipe( ialu_regL_regL );
11071 %}
11073 // Xor Instructions
11074 // Xor Register with Register
11075 instruct xorI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
11076 match(Set dst (XorI src1 src2));
11078 format %{ "XOR $dst, $src1, $src2 #@xorI_Reg_Reg" %}
11080 ins_encode %{
11081 Register dst = $dst$$Register;
11082 Register src1 = $src1$$Register;
11083 Register src2 = $src2$$Register;
11084 __ xorr(dst, src1, src2);
11085 __ sll(dst, dst, 0); /* long -> int */
11086 %}
11088 ins_pipe( ialu_regI_regI );
11089 %}
11091 // Or Instructions
11092 // Or Register with Register
11093 instruct orI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
11094 match(Set dst (OrI src1 src2));
11096 format %{ "OR $dst, $src1, $src2 #@orI_Reg_Reg" %}
11097 ins_encode %{
11098 Register dst = $dst$$Register;
11099 Register src1 = $src1$$Register;
11100 Register src2 = $src2$$Register;
11101 __ orr(dst, src1, src2);
11102 %}
11104 ins_pipe( ialu_regI_regI );
11105 %}
11107 instruct rotI_shr_logical_Reg(mRegI dst, mRegI src, immI_0_31 rshift, immI_0_31 lshift, immI_1 one) %{
11108 match(Set dst (OrI (URShiftI src rshift) (LShiftI (AndI src one) lshift)));
11109 predicate(32 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int())));
11111 format %{ "rotr $dst, $src, 1 ...\n\t"
11112 "srl $dst, $dst, ($rshift-1) @ rotI_shr_logical_Reg" %}
11113 ins_encode %{
11114 Register dst = $dst$$Register;
11115 Register src = $src$$Register;
11116 int rshift = $rshift$$constant;
11118 __ rotr(dst, src, 1);
11119 if (rshift - 1) {
11120 __ srl(dst, dst, rshift - 1);
11121 }
11122 %}
11124 ins_pipe( ialu_regI_regI );
11125 %}
11127 instruct orI_Reg_castP2X(mRegL dst, mRegL src1, mRegP src2) %{
11128 match(Set dst (OrI src1 (CastP2X src2)));
11130 format %{ "OR $dst, $src1, $src2 #@orI_Reg_castP2X" %}
11131 ins_encode %{
11132 Register dst = $dst$$Register;
11133 Register src1 = $src1$$Register;
11134 Register src2 = $src2$$Register;
11135 __ orr(dst, src1, src2);
11136 %}
11138 ins_pipe( ialu_regI_regI );
11139 %}
11141 // Logical Shift Right by 8-bit immediate
11142 instruct shr_logical_Reg_imm(mRegI dst, mRegI src, immI8 shift) %{
11143 match(Set dst (URShiftI src shift));
11144 // effect(KILL cr);
11146 format %{ "SRL $dst, $src, $shift #@shr_logical_Reg_imm" %}
11147 ins_encode %{
11148 Register src = $src$$Register;
11149 Register dst = $dst$$Register;
11150 int shift = $shift$$constant;
11152 __ srl(dst, src, shift);
11153 %}
11154 ins_pipe( ialu_regI_regI );
11155 %}
11157 instruct shr_logical_Reg_imm_nonneg_mask(mRegI dst, mRegI src, immI_0_31 shift, immI_nonneg_mask mask) %{
11158 match(Set dst (AndI (URShiftI src shift) mask));
11160 format %{ "ext $dst, $src, $shift, one-bits($mask) #@shr_logical_Reg_imm_nonneg_mask" %}
11161 ins_encode %{
11162 Register src = $src$$Register;
11163 Register dst = $dst$$Register;
11164 int pos = $shift$$constant;
11165 int size = Assembler::is_int_mask($mask$$constant);
11167 __ ext(dst, src, pos, size);
11168 %}
11169 ins_pipe( ialu_regI_regI );
11170 %}
11172 instruct rolI_Reg_immI_0_31(mRegI dst, immI_0_31 lshift, immI_0_31 rshift)
11173 %{
11174 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
11175 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
11177 ins_cost(100);
11178 format %{ "rotr $dst, $dst, $rshift #@rolI_Reg_immI_0_31" %}
11179 ins_encode %{
11180 Register dst = $dst$$Register;
11181 int sa = $rshift$$constant;
11183 __ rotr(dst, dst, sa);
11184 %}
11185 ins_pipe( ialu_regI_regI );
11186 %}
11188 instruct rolL_Reg_immI_0_31(mRegL dst, immI_32_63 lshift, immI_0_31 rshift)
11189 %{
11190 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
11191 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
11193 ins_cost(100);
11194 format %{ "rotr $dst, $dst, $rshift #@rolL_Reg_immI_0_31" %}
11195 ins_encode %{
11196 Register dst = $dst$$Register;
11197 int sa = $rshift$$constant;
11199 __ drotr(dst, dst, sa);
11200 %}
11201 ins_pipe( ialu_regI_regI );
11202 %}
11204 instruct rolL_Reg_immI_32_63(mRegL dst, immI_0_31 lshift, immI_32_63 rshift)
11205 %{
11206 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
11207 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
11209 ins_cost(100);
11210 format %{ "rotr $dst, $dst, $rshift #@rolL_Reg_immI_32_63" %}
11211 ins_encode %{
11212 Register dst = $dst$$Register;
11213 int sa = $rshift$$constant;
11215 __ drotr32(dst, dst, sa - 32);
11216 %}
11217 ins_pipe( ialu_regI_regI );
11218 %}
11220 instruct rorI_Reg_immI_0_31(mRegI dst, immI_0_31 rshift, immI_0_31 lshift)
11221 %{
11222 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
11223 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
11225 ins_cost(100);
11226 format %{ "rotr $dst, $dst, $rshift #@rorI_Reg_immI_0_31" %}
11227 ins_encode %{
11228 Register dst = $dst$$Register;
11229 int sa = $rshift$$constant;
11231 __ rotr(dst, dst, sa);
11232 %}
11233 ins_pipe( ialu_regI_regI );
11234 %}
11236 instruct rorL_Reg_immI_0_31(mRegL dst, immI_0_31 rshift, immI_32_63 lshift)
11237 %{
11238 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
11239 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
11241 ins_cost(100);
11242 format %{ "rotr $dst, $dst, $rshift #@rorL_Reg_immI_0_31" %}
11243 ins_encode %{
11244 Register dst = $dst$$Register;
11245 int sa = $rshift$$constant;
11247 __ drotr(dst, dst, sa);
11248 %}
11249 ins_pipe( ialu_regI_regI );
11250 %}
11252 instruct rorL_Reg_immI_32_63(mRegL dst, immI_32_63 rshift, immI_0_31 lshift)
11253 %{
11254 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
11255 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
11257 ins_cost(100);
11258 format %{ "rotr $dst, $dst, $rshift #@rorL_Reg_immI_32_63" %}
11259 ins_encode %{
11260 Register dst = $dst$$Register;
11261 int sa = $rshift$$constant;
11263 __ drotr32(dst, dst, sa - 32);
11264 %}
11265 ins_pipe( ialu_regI_regI );
11266 %}
11268 // Logical Shift Right
11269 instruct shr_logical_Reg_Reg(mRegI dst, mRegI src, mRegI shift) %{
11270 match(Set dst (URShiftI src shift));
11272 format %{ "SRL $dst, $src, $shift #@shr_logical_Reg_Reg" %}
11273 ins_encode %{
11274 Register src = $src$$Register;
11275 Register dst = $dst$$Register;
11276 Register shift = $shift$$Register;
11277 __ srlv(dst, src, shift);
11278 %}
11279 ins_pipe( ialu_regI_regI );
11280 %}
11283 instruct shr_arith_Reg_imm(mRegI dst, mRegI src, immI8 shift) %{
11284 match(Set dst (RShiftI src shift));
11285 // effect(KILL cr);
11287 format %{ "SRA $dst, $src, $shift #@shr_arith_Reg_imm" %}
11288 ins_encode %{
11289 Register src = $src$$Register;
11290 Register dst = $dst$$Register;
11291 int shift = $shift$$constant;
11292 __ sra(dst, src, shift);
11293 %}
11294 ins_pipe( ialu_regI_regI );
11295 %}
11297 instruct shr_arith_Reg_Reg(mRegI dst, mRegI src, mRegI shift) %{
11298 match(Set dst (RShiftI src shift));
11299 // effect(KILL cr);
11301 format %{ "SRA $dst, $src, $shift #@shr_arith_Reg_Reg" %}
11302 ins_encode %{
11303 Register src = $src$$Register;
11304 Register dst = $dst$$Register;
11305 Register shift = $shift$$Register;
11306 __ srav(dst, src, shift);
11307 %}
11308 ins_pipe( ialu_regI_regI );
11309 %}
11311 //----------Convert Int to Boolean---------------------------------------------
11313 instruct convI2B(mRegI dst, mRegI src) %{
11314 match(Set dst (Conv2B src));
11316 ins_cost(100);
11317 format %{ "convI2B $dst, $src @ convI2B" %}
11318 ins_encode %{
11319 Register dst = as_Register($dst$$reg);
11320 Register src = as_Register($src$$reg);
11322 if (dst != src) {
11323 __ daddiu(dst, R0, 1);
11324 __ movz(dst, R0, src);
11325 } else {
11326 __ move(AT, src);
11327 __ daddiu(dst, R0, 1);
11328 __ movz(dst, R0, AT);
11329 }
11330 %}
11332 ins_pipe( ialu_regL_regL );
11333 %}
11335 instruct convI2L_reg( mRegL dst, mRegI src) %{
11336 match(Set dst (ConvI2L src));
11338 ins_cost(100);
11339 format %{ "SLL $dst, $src @ convI2L_reg\t" %}
11340 ins_encode %{
11341 Register dst = as_Register($dst$$reg);
11342 Register src = as_Register($src$$reg);
11344 if(dst != src) __ sll(dst, src, 0);
11345 %}
11346 ins_pipe( ialu_regL_regL );
11347 %}
11350 instruct convL2I_reg( mRegI dst, mRegL src ) %{
11351 match(Set dst (ConvL2I src));
11353 format %{ "MOV $dst, $src @ convL2I_reg" %}
11354 ins_encode %{
11355 Register dst = as_Register($dst$$reg);
11356 Register src = as_Register($src$$reg);
11358 __ sll(dst, src, 0);
11359 %}
11361 ins_pipe( ialu_regI_regI );
11362 %}
11364 instruct convL2I2L_reg( mRegL dst, mRegL src ) %{
11365 match(Set dst (ConvI2L (ConvL2I src)));
11367 format %{ "sll $dst, $src, 0 @ convL2I2L_reg" %}
11368 ins_encode %{
11369 Register dst = as_Register($dst$$reg);
11370 Register src = as_Register($src$$reg);
11372 __ sll(dst, src, 0);
11373 %}
11375 ins_pipe( ialu_regI_regI );
11376 %}
11378 instruct convL2D_reg( regD dst, mRegL src ) %{
11379 match(Set dst (ConvL2D src));
11380 format %{ "convL2D $dst, $src @ convL2D_reg" %}
11381 ins_encode %{
11382 Register src = as_Register($src$$reg);
11383 FloatRegister dst = as_FloatRegister($dst$$reg);
11385 __ dmtc1(src, dst);
11386 __ cvt_d_l(dst, dst);
11387 %}
11389 ins_pipe( pipe_slow );
11390 %}
11392 instruct convD2L_reg_fast( mRegL dst, regD src ) %{
11393 match(Set dst (ConvD2L src));
11394 ins_cost(150);
11395 format %{ "convD2L $dst, $src @ convD2L_reg_fast" %}
11396 ins_encode %{
11397 Register dst = as_Register($dst$$reg);
11398 FloatRegister src = as_FloatRegister($src$$reg);
11400 Label Done;
11402 __ trunc_l_d(F30, src);
11403 // max_long: 0x7fffffffffffffff
11404 // __ set64(AT, 0x7fffffffffffffff);
11405 __ daddiu(AT, R0, -1);
11406 __ dsrl(AT, AT, 1);
11407 __ dmfc1(dst, F30);
11409 __ bne(dst, AT, Done);
11410 __ delayed()->mtc1(R0, F30);
11412 __ cvt_d_w(F30, F30);
11413 __ c_ult_d(src, F30);
11414 __ bc1f(Done);
11415 __ delayed()->daddiu(T9, R0, -1);
11417 __ c_un_d(src, src); //NaN?
11418 __ subu(dst, T9, AT);
11419 __ movt(dst, R0);
11421 __ bind(Done);
11422 %}
11424 ins_pipe( pipe_slow );
11425 %}
11427 instruct convD2L_reg_slow( mRegL dst, regD src ) %{
11428 match(Set dst (ConvD2L src));
11429 ins_cost(250);
11430 format %{ "convD2L $dst, $src @ convD2L_reg_slow" %}
11431 ins_encode %{
11432 Register dst = as_Register($dst$$reg);
11433 FloatRegister src = as_FloatRegister($src$$reg);
11435 Label L;
11437 __ c_un_d(src, src); //NaN?
11438 __ bc1t(L);
11439 __ delayed();
11440 __ move(dst, R0);
11442 __ trunc_l_d(F30, src);
11443 __ cfc1(AT, 31);
11444 __ li(T9, 0x10000);
11445 __ andr(AT, AT, T9);
11446 __ beq(AT, R0, L);
11447 __ delayed()->dmfc1(dst, F30);
11449 __ mov_d(F12, src);
11450 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::d2l), 1);
11451 __ move(dst, V0);
11452 __ bind(L);
11453 %}
11455 ins_pipe( pipe_slow );
11456 %}
11458 instruct convF2I_reg_fast( mRegI dst, regF src ) %{
11459 match(Set dst (ConvF2I src));
11460 ins_cost(150);
11461 format %{ "convf2i $dst, $src @ convF2I_reg_fast" %}
11462 ins_encode %{
11463 Register dreg = $dst$$Register;
11464 FloatRegister fval = $src$$FloatRegister;
11466 __ trunc_w_s(F30, fval);
11467 __ mfc1(dreg, F30);
11468 __ c_un_s(fval, fval); //NaN?
11469 __ movt(dreg, R0);
11470 %}
11472 ins_pipe( pipe_slow );
11473 %}
11475 instruct convF2I_reg_slow( mRegI dst, regF src ) %{
11476 match(Set dst (ConvF2I src));
11477 ins_cost(250);
11478 format %{ "convf2i $dst, $src @ convF2I_reg_slow" %}
11479 ins_encode %{
11480 Register dreg = $dst$$Register;
11481 FloatRegister fval = $src$$FloatRegister;
11482 Label L;
11484 __ c_un_s(fval, fval); //NaN?
11485 __ bc1t(L);
11486 __ delayed();
11487 __ move(dreg, R0);
11489 __ trunc_w_s(F30, fval);
11491 /* Call SharedRuntime:f2i() to do valid convention */
11492 __ cfc1(AT, 31);
11493 __ li(T9, 0x10000);
11494 __ andr(AT, AT, T9);
11495 __ beq(AT, R0, L);
11496 __ delayed()->mfc1(dreg, F30);
11498 __ mov_s(F12, fval);
11500 /* 2014/01/08 Fu : This bug was found when running ezDS's control-panel.
11501 * J 982 C2 javax.swing.text.BoxView.layoutMajorAxis(II[I[I)V (283 bytes) @ 0x000000555c46aa74
11502 *
11503 * An interger array index has been assigned to V0, and then changed from 1 to Integer.MAX_VALUE.
11504 * V0 is corrupted during call_VM_leaf(), and should be preserved.
11505 */
11506 if(dreg != V0) {
11507 __ push(V0);
11508 }
11509 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::f2i), 1);
11510 if(dreg != V0) {
11511 __ move(dreg, V0);
11512 __ pop(V0);
11513 }
11514 __ bind(L);
11515 %}
11517 ins_pipe( pipe_slow );
11518 %}
11520 instruct convF2L_reg_fast( mRegL dst, regF src ) %{
11521 match(Set dst (ConvF2L src));
11522 ins_cost(150);
11523 format %{ "convf2l $dst, $src @ convF2L_reg_fast" %}
11524 ins_encode %{
11525 Register dreg = $dst$$Register;
11526 FloatRegister fval = $src$$FloatRegister;
11528 __ trunc_l_s(F30, fval);
11529 __ dmfc1(dreg, F30);
11530 __ c_un_s(fval, fval); //NaN?
11531 __ movt(dreg, R0);
11532 %}
11534 ins_pipe( pipe_slow );
11535 %}
11537 instruct convF2L_reg_slow( mRegL dst, regF src ) %{
11538 match(Set dst (ConvF2L src));
11539 ins_cost(250);
11540 format %{ "convf2l $dst, $src @ convF2L_reg_slow" %}
11541 ins_encode %{
11542 Register dst = as_Register($dst$$reg);
11543 FloatRegister fval = $src$$FloatRegister;
11544 Label L;
11546 __ c_un_s(fval, fval); //NaN?
11547 __ bc1t(L);
11548 __ delayed();
11549 __ move(dst, R0);
11551 __ trunc_l_s(F30, fval);
11552 __ cfc1(AT, 31);
11553 __ li(T9, 0x10000);
11554 __ andr(AT, AT, T9);
11555 __ beq(AT, R0, L);
11556 __ delayed()->dmfc1(dst, F30);
11558 __ mov_s(F12, fval);
11559 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::f2l), 1);
11560 __ move(dst, V0);
11561 __ bind(L);
11562 %}
11564 ins_pipe( pipe_slow );
11565 %}
11567 instruct convL2F_reg( regF dst, mRegL src ) %{
11568 match(Set dst (ConvL2F src));
11569 format %{ "convl2f $dst, $src @ convL2F_reg" %}
11570 ins_encode %{
11571 FloatRegister dst = $dst$$FloatRegister;
11572 Register src = as_Register($src$$reg);
11573 Label L;
11575 __ dmtc1(src, dst);
11576 __ cvt_s_l(dst, dst);
11577 %}
11579 ins_pipe( pipe_slow );
11580 %}
11582 instruct convI2F_reg( regF dst, mRegI src ) %{
11583 match(Set dst (ConvI2F src));
11584 format %{ "convi2f $dst, $src @ convI2F_reg" %}
11585 ins_encode %{
11586 Register src = $src$$Register;
11587 FloatRegister dst = $dst$$FloatRegister;
11589 __ mtc1(src, dst);
11590 __ cvt_s_w(dst, dst);
11591 %}
11593 ins_pipe( fpu_regF_regF );
11594 %}
11596 instruct cmpLTMask_immI0( mRegI dst, mRegI p, immI0 zero ) %{
11597 match(Set dst (CmpLTMask p zero));
11598 ins_cost(100);
11600 format %{ "sra $dst, $p, 31 @ cmpLTMask_immI0" %}
11601 ins_encode %{
11602 Register src = $p$$Register;
11603 Register dst = $dst$$Register;
11605 __ sra(dst, src, 31);
11606 %}
11607 ins_pipe( pipe_slow );
11608 %}
11611 instruct cmpLTMask( mRegI dst, mRegI p, mRegI q ) %{
11612 match(Set dst (CmpLTMask p q));
11613 ins_cost(400);
11615 format %{ "cmpLTMask $dst, $p, $q @ cmpLTMask" %}
11616 ins_encode %{
11617 Register p = $p$$Register;
11618 Register q = $q$$Register;
11619 Register dst = $dst$$Register;
11621 __ slt(dst, p, q);
11622 __ subu(dst, R0, dst);
11623 %}
11624 ins_pipe( pipe_slow );
11625 %}
11627 instruct convP2B(mRegI dst, mRegP src) %{
11628 match(Set dst (Conv2B src));
11630 ins_cost(100);
11631 format %{ "convP2B $dst, $src @ convP2B" %}
11632 ins_encode %{
11633 Register dst = as_Register($dst$$reg);
11634 Register src = as_Register($src$$reg);
11636 if (dst != src) {
11637 __ daddiu(dst, R0, 1);
11638 __ movz(dst, R0, src);
11639 } else {
11640 __ move(AT, src);
11641 __ daddiu(dst, R0, 1);
11642 __ movz(dst, R0, AT);
11643 }
11644 %}
11646 ins_pipe( ialu_regL_regL );
11647 %}
11650 instruct convI2D_reg_reg(regD dst, mRegI src) %{
11651 match(Set dst (ConvI2D src));
11652 format %{ "conI2D $dst, $src @convI2D_reg" %}
11653 ins_encode %{
11654 Register src = $src$$Register;
11655 FloatRegister dst = $dst$$FloatRegister;
11656 __ mtc1(src, dst);
11657 __ cvt_d_w(dst, dst);
11658 %}
11659 ins_pipe( fpu_regF_regF );
11660 %}
11662 instruct convF2D_reg_reg(regD dst, regF src) %{
11663 match(Set dst (ConvF2D src));
11664 format %{ "convF2D $dst, $src\t# @convF2D_reg_reg" %}
11665 ins_encode %{
11666 FloatRegister dst = $dst$$FloatRegister;
11667 FloatRegister src = $src$$FloatRegister;
11669 __ cvt_d_s(dst, src);
11670 %}
11671 ins_pipe( fpu_regF_regF );
11672 %}
11674 instruct convD2F_reg_reg(regF dst, regD src) %{
11675 match(Set dst (ConvD2F src));
11676 format %{ "convD2F $dst, $src\t# @convD2F_reg_reg" %}
11677 ins_encode %{
11678 FloatRegister dst = $dst$$FloatRegister;
11679 FloatRegister src = $src$$FloatRegister;
11681 __ cvt_s_d(dst, src);
11682 %}
11683 ins_pipe( fpu_regF_regF );
11684 %}
11686 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11687 instruct convD2I_reg_reg_fast( mRegI dst, regD src ) %{
11688 match(Set dst (ConvD2I src));
11690 ins_cost(150);
11691 format %{ "convD2I $dst, $src\t# @ convD2I_reg_reg_fast" %}
11693 ins_encode %{
11694 FloatRegister src = $src$$FloatRegister;
11695 Register dst = $dst$$Register;
11697 Label Done;
11699 __ trunc_w_d(F30, src);
11700 // max_int: 2147483647
11701 __ move(AT, 0x7fffffff);
11702 __ mfc1(dst, F30);
11704 __ bne(dst, AT, Done);
11705 __ delayed()->mtc1(R0, F30);
11707 __ cvt_d_w(F30, F30);
11708 __ c_ult_d(src, F30);
11709 __ bc1f(Done);
11710 __ delayed()->addiu(T9, R0, -1);
11712 __ c_un_d(src, src); //NaN?
11713 __ subu32(dst, T9, AT);
11714 __ movt(dst, R0);
11716 __ bind(Done);
11717 %}
11718 ins_pipe( pipe_slow );
11719 %}
11721 instruct convD2I_reg_reg_slow( mRegI dst, regD src ) %{
11722 match(Set dst (ConvD2I src));
11724 ins_cost(250);
11725 format %{ "convD2I $dst, $src\t# @ convD2I_reg_reg_slow" %}
11727 ins_encode %{
11728 FloatRegister src = $src$$FloatRegister;
11729 Register dst = $dst$$Register;
11730 Label L;
11732 __ trunc_w_d(F30, src);
11733 __ cfc1(AT, 31);
11734 __ li(T9, 0x10000);
11735 __ andr(AT, AT, T9);
11736 __ beq(AT, R0, L);
11737 __ delayed()->mfc1(dst, F30);
11739 __ mov_d(F12, src);
11740 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::d2i), 1);
11741 __ move(dst, V0);
11742 __ bind(L);
11744 %}
11745 ins_pipe( pipe_slow );
11746 %}
11748 // Convert oop pointer into compressed form
11749 instruct encodeHeapOop(mRegN dst, mRegP src) %{
11750 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
11751 match(Set dst (EncodeP src));
11752 format %{ "encode_heap_oop $dst,$src" %}
11753 ins_encode %{
11754 Register src = $src$$Register;
11755 Register dst = $dst$$Register;
11756 if (src != dst) {
11757 __ move(dst, src);
11758 }
11759 __ encode_heap_oop(dst);
11760 %}
11761 ins_pipe( ialu_regL_regL );
11762 %}
11764 instruct encodeHeapOop_not_null(mRegN dst, mRegP src) %{
11765 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
11766 match(Set dst (EncodeP src));
11767 format %{ "encode_heap_oop_not_null $dst,$src @ encodeHeapOop_not_null" %}
11768 ins_encode %{
11769 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
11770 %}
11771 ins_pipe( ialu_regL_regL );
11772 %}
11774 instruct decodeHeapOop(mRegP dst, mRegN src) %{
11775 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
11776 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
11777 match(Set dst (DecodeN src));
11778 format %{ "decode_heap_oop $dst,$src @ decodeHeapOop" %}
11779 ins_encode %{
11780 Register s = $src$$Register;
11781 Register d = $dst$$Register;
11782 if (s != d) {
11783 __ move(d, s);
11784 }
11785 __ decode_heap_oop(d);
11786 %}
11787 ins_pipe( ialu_regL_regL );
11788 %}
11790 instruct decodeHeapOop_not_null(mRegP dst, mRegN src) %{
11791 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
11792 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
11793 match(Set dst (DecodeN src));
11794 format %{ "decode_heap_oop_not_null $dst,$src @ decodeHeapOop_not_null" %}
11795 ins_encode %{
11796 Register s = $src$$Register;
11797 Register d = $dst$$Register;
11798 if (s != d) {
11799 __ decode_heap_oop_not_null(d, s);
11800 } else {
11801 __ decode_heap_oop_not_null(d);
11802 }
11803 %}
11804 ins_pipe( ialu_regL_regL );
11805 %}
11807 instruct encodeKlass_not_null(mRegN dst, mRegP src) %{
11808 match(Set dst (EncodePKlass src));
11809 format %{ "encode_heap_oop_not_null $dst,$src @ encodeKlass_not_null" %}
11810 ins_encode %{
11811 __ encode_klass_not_null($dst$$Register, $src$$Register);
11812 %}
11813 ins_pipe( ialu_regL_regL );
11814 %}
11816 instruct decodeKlass_not_null(mRegP dst, mRegN src) %{
11817 match(Set dst (DecodeNKlass src));
11818 format %{ "decode_heap_klass_not_null $dst,$src" %}
11819 ins_encode %{
11820 Register s = $src$$Register;
11821 Register d = $dst$$Register;
11822 if (s != d) {
11823 __ decode_klass_not_null(d, s);
11824 } else {
11825 __ decode_klass_not_null(d);
11826 }
11827 %}
11828 ins_pipe( ialu_regL_regL );
11829 %}
11831 //FIXME
11832 instruct tlsLoadP(mRegP dst) %{
11833 match(Set dst (ThreadLocal));
11835 ins_cost(0);
11836 format %{ " get_thread in $dst #@tlsLoadP" %}
11837 ins_encode %{
11838 Register dst = $dst$$Register;
11839 #ifdef OPT_THREAD
11840 __ move(dst, TREG);
11841 #else
11842 __ get_thread(dst);
11843 #endif
11844 %}
11846 ins_pipe( ialu_loadI );
11847 %}
11850 instruct checkCastPP( mRegP dst ) %{
11851 match(Set dst (CheckCastPP dst));
11853 format %{ "#checkcastPP of $dst (empty encoding) #@chekCastPP" %}
11854 ins_encode( /*empty encoding*/ );
11855 ins_pipe( empty );
11856 %}
11858 instruct castPP(mRegP dst)
11859 %{
11860 match(Set dst (CastPP dst));
11862 size(0);
11863 format %{ "# castPP of $dst" %}
11864 ins_encode(/* empty encoding */);
11865 ins_pipe(empty);
11866 %}
11868 instruct castII( mRegI dst ) %{
11869 match(Set dst (CastII dst));
11870 format %{ "#castII of $dst empty encoding" %}
11871 ins_encode( /*empty encoding*/ );
11872 ins_cost(0);
11873 ins_pipe( empty );
11874 %}
11876 // Return Instruction
11877 // Remove the return address & jump to it.
11878 instruct Ret() %{
11879 match(Return);
11880 format %{ "RET #@Ret" %}
11882 ins_encode %{
11883 __ jr(RA);
11884 __ nop();
11885 %}
11887 ins_pipe( pipe_jump );
11888 %}
11890 /*
11891 // For Loongson CPUs, jr seems too slow, so this rule shouldn't be imported.
11892 instruct jumpXtnd(mRegL switch_val) %{
11893 match(Jump switch_val);
11895 ins_cost(350);
11897 format %{ "load T9 <-- [$constanttablebase, $switch_val, $constantoffset] @ jumpXtnd\n\t"
11898 "jr T9\n\t"
11899 "nop" %}
11900 ins_encode %{
11901 Register table_base = $constanttablebase;
11902 int con_offset = $constantoffset;
11903 Register switch_reg = $switch_val$$Register;
11905 if (UseLoongsonISA) {
11906 if (Assembler::is_simm(con_offset, 8)) {
11907 __ gsldx(T9, table_base, switch_reg, con_offset);
11908 } else if (Assembler::is_simm16(con_offset)) {
11909 __ daddu(T9, table_base, switch_reg);
11910 __ ld(T9, T9, con_offset);
11911 } else {
11912 __ move(T9, con_offset);
11913 __ daddu(AT, table_base, switch_reg);
11914 __ gsldx(T9, AT, T9, 0);
11915 }
11916 } else {
11917 if (Assembler::is_simm16(con_offset)) {
11918 __ daddu(T9, table_base, switch_reg);
11919 __ ld(T9, T9, con_offset);
11920 } else {
11921 __ move(T9, con_offset);
11922 __ daddu(AT, table_base, switch_reg);
11923 __ daddu(AT, T9, AT);
11924 __ ld(T9, AT, 0);
11925 }
11926 }
11928 __ jr(T9);
11929 __ nop();
11931 %}
11932 ins_pipe(pipe_jump);
11933 %}
11934 */
11936 // Jump Direct - Label defines a relative address from JMP
11937 instruct jmpDir(label labl) %{
11938 match(Goto);
11939 effect(USE labl);
11941 ins_cost(300);
11942 format %{ "JMP $labl #@jmpDir" %}
11944 ins_encode %{
11945 Label &L = *($labl$$label);
11946 if(&L)
11947 __ b(L);
11948 else
11949 __ b(int(0));
11950 __ nop();
11951 %}
11953 ins_pipe( pipe_jump );
11954 ins_pc_relative(1);
11955 %}
11959 // Tail Jump; remove the return address; jump to target.
11960 // TailCall above leaves the return address around.
11961 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
11962 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
11963 // "restore" before this instruction (in Epilogue), we need to materialize it
11964 // in %i0.
11965 //FIXME
11966 instruct tailjmpInd(mRegP jump_target,mRegP ex_oop) %{
11967 match( TailJump jump_target ex_oop );
11968 ins_cost(200);
11969 format %{ "Jmp $jump_target ; ex_oop = $ex_oop #@tailjmpInd" %}
11970 ins_encode %{
11971 Register target = $jump_target$$Register;
11973 /* 2012/9/14 Jin: V0, V1 are indicated in:
11974 * [stubGenerator_mips.cpp] generate_forward_exception()
11975 * [runtime_mips.cpp] OptoRuntime::generate_exception_blob()
11976 */
11977 Register oop = $ex_oop$$Register;
11978 Register exception_oop = V0;
11979 Register exception_pc = V1;
11981 __ move(exception_pc, RA);
11982 __ move(exception_oop, oop);
11984 __ jr(target);
11985 __ nop();
11986 %}
11987 ins_pipe( pipe_jump );
11988 %}
11990 // ============================================================================
11991 // Procedure Call/Return Instructions
11992 // Call Java Static Instruction
11993 // Note: If this code changes, the corresponding ret_addr_offset() and
11994 // compute_padding() functions will have to be adjusted.
11995 instruct CallStaticJavaDirect(method meth) %{
11996 match(CallStaticJava);
11997 effect(USE meth);
11999 ins_cost(300);
12000 format %{ "CALL,static #@CallStaticJavaDirect " %}
12001 ins_encode( Java_Static_Call( meth ) );
12002 ins_pipe( pipe_slow );
12003 ins_pc_relative(1);
12004 ins_alignment(16);
12005 %}
12007 // Call Java Dynamic Instruction
12008 // Note: If this code changes, the corresponding ret_addr_offset() and
12009 // compute_padding() functions will have to be adjusted.
12010 instruct CallDynamicJavaDirect(method meth) %{
12011 match(CallDynamicJava);
12012 effect(USE meth);
12014 ins_cost(300);
12015 format %{"MOV IC_Klass, (oop)-1 @ CallDynamicJavaDirect\n\t"
12016 "CallDynamic @ CallDynamicJavaDirect" %}
12017 ins_encode( Java_Dynamic_Call( meth ) );
12018 ins_pipe( pipe_slow );
12019 ins_pc_relative(1);
12020 ins_alignment(16);
12021 %}
12023 instruct CallLeafNoFPDirect(method meth) %{
12024 match(CallLeafNoFP);
12025 effect(USE meth);
12027 ins_cost(300);
12028 format %{ "CALL_LEAF_NOFP,runtime " %}
12029 ins_encode(Java_To_Runtime(meth));
12030 ins_pipe( pipe_slow );
12031 ins_pc_relative(1);
12032 ins_alignment(16);
12033 %}
12035 // Prefetch instructions.
12037 instruct prefetchrNTA( memory mem ) %{
12038 match(PrefetchRead mem);
12039 ins_cost(125);
12041 format %{ "pref $mem\t# Prefetch into non-temporal cache for read @ prefetchrNTA" %}
12042 ins_encode %{
12043 int base = $mem$$base;
12044 int index = $mem$$index;
12045 int scale = $mem$$scale;
12046 int disp = $mem$$disp;
12048 if( index != 0 ) {
12049 if (scale == 0) {
12050 __ daddu(AT, as_Register(base), as_Register(index));
12051 } else {
12052 __ dsll(AT, as_Register(index), scale);
12053 __ daddu(AT, as_Register(base), AT);
12054 }
12055 } else {
12056 __ move(AT, as_Register(base));
12057 }
12058 if( Assembler::is_simm16(disp) ) {
12059 __ daddiu(AT, as_Register(base), disp);
12060 __ daddiu(AT, AT, disp);
12061 } else {
12062 __ move(T9, disp);
12063 __ daddu(AT, as_Register(base), T9);
12064 }
12065 __ pref(0, AT, 0); //hint: 0:load
12066 %}
12067 ins_pipe(pipe_slow);
12068 %}
12070 instruct prefetchwNTA( memory mem ) %{
12071 match(PrefetchWrite mem);
12072 ins_cost(125);
12073 format %{ "pref $mem\t# Prefetch to non-temporal cache for write @ prefetchwNTA" %}
12074 ins_encode %{
12075 int base = $mem$$base;
12076 int index = $mem$$index;
12077 int scale = $mem$$scale;
12078 int disp = $mem$$disp;
12080 if( index != 0 ) {
12081 if (scale == 0) {
12082 __ daddu(AT, as_Register(base), as_Register(index));
12083 } else {
12084 __ dsll(AT, as_Register(index), scale);
12085 __ daddu(AT, as_Register(base), AT);
12086 }
12087 } else {
12088 __ move(AT, as_Register(base));
12089 }
12090 if( Assembler::is_simm16(disp) ) {
12091 __ daddiu(AT, as_Register(base), disp);
12092 __ daddiu(AT, AT, disp);
12093 } else {
12094 __ move(T9, disp);
12095 __ daddu(AT, as_Register(base), T9);
12096 }
12097 __ pref(1, AT, 0); //hint: 1:store
12098 %}
12099 ins_pipe(pipe_slow);
12100 %}
12102 // Prefetch instructions for allocation.
12104 instruct prefetchAllocNTA( memory mem ) %{
12105 match(PrefetchAllocation mem);
12106 ins_cost(125);
12107 format %{ "pref $mem\t# Prefetch allocation @ prefetchAllocNTA" %}
12108 ins_encode %{
12109 int base = $mem$$base;
12110 int index = $mem$$index;
12111 int scale = $mem$$scale;
12112 int disp = $mem$$disp;
12114 Register dst = R0;
12116 if( index != 0 ) {
12117 if( Assembler::is_simm16(disp) ) {
12118 if( UseLoongsonISA ) {
12119 if (scale == 0) {
12120 __ gslbx(dst, as_Register(base), as_Register(index), disp);
12121 } else {
12122 __ dsll(AT, as_Register(index), scale);
12123 __ gslbx(dst, as_Register(base), AT, disp);
12124 }
12125 } else {
12126 if (scale == 0) {
12127 __ addu(AT, as_Register(base), as_Register(index));
12128 } else {
12129 __ dsll(AT, as_Register(index), scale);
12130 __ addu(AT, as_Register(base), AT);
12131 }
12132 __ lb(dst, AT, disp);
12133 }
12134 } else {
12135 if (scale == 0) {
12136 __ addu(AT, as_Register(base), as_Register(index));
12137 } else {
12138 __ dsll(AT, as_Register(index), scale);
12139 __ addu(AT, as_Register(base), AT);
12140 }
12141 __ move(T9, disp);
12142 if( UseLoongsonISA ) {
12143 __ gslbx(dst, AT, T9, 0);
12144 } else {
12145 __ addu(AT, AT, T9);
12146 __ lb(dst, AT, 0);
12147 }
12148 }
12149 } else {
12150 if( Assembler::is_simm16(disp) ) {
12151 __ lb(dst, as_Register(base), disp);
12152 } else {
12153 __ move(T9, disp);
12154 if( UseLoongsonISA ) {
12155 __ gslbx(dst, as_Register(base), T9, 0);
12156 } else {
12157 __ addu(AT, as_Register(base), T9);
12158 __ lb(dst, AT, 0);
12159 }
12160 }
12161 }
12162 %}
12163 ins_pipe(pipe_slow);
12164 %}
12167 // Call runtime without safepoint
12168 instruct CallLeafDirect(method meth) %{
12169 match(CallLeaf);
12170 effect(USE meth);
12172 ins_cost(300);
12173 format %{ "CALL_LEAF,runtime #@CallLeafDirect " %}
12174 ins_encode(Java_To_Runtime(meth));
12175 ins_pipe( pipe_slow );
12176 ins_pc_relative(1);
12177 ins_alignment(16);
12178 %}
12180 // Load Char (16bit unsigned)
12181 instruct loadUS(mRegI dst, memory mem) %{
12182 match(Set dst (LoadUS mem));
12184 ins_cost(125);
12185 format %{ "loadUS $dst,$mem @ loadC" %}
12186 ins_encode(load_C_enc(dst, mem));
12187 ins_pipe( ialu_loadI );
12188 %}
12190 instruct loadUS_convI2L(mRegL dst, memory mem) %{
12191 match(Set dst (ConvI2L (LoadUS mem)));
12193 ins_cost(125);
12194 format %{ "loadUS $dst,$mem @ loadUS_convI2L" %}
12195 ins_encode(load_C_enc(dst, mem));
12196 ins_pipe( ialu_loadI );
12197 %}
12199 // Store Char (16bit unsigned)
12200 instruct storeC(memory mem, mRegI src) %{
12201 match(Set mem (StoreC mem src));
12203 ins_cost(125);
12204 format %{ "storeC $src,$mem @ storeC" %}
12205 ins_encode(store_C_reg_enc(mem, src));
12206 ins_pipe( ialu_loadI );
12207 %}
12210 instruct loadConF0(regF dst, immF0 zero) %{
12211 match(Set dst zero);
12212 ins_cost(100);
12214 format %{ "mov $dst, zero @ loadConF0\n"%}
12215 ins_encode %{
12216 FloatRegister dst = $dst$$FloatRegister;
12218 __ mtc1(R0, dst);
12219 %}
12220 ins_pipe( fpu_loadF );
12221 %}
12224 instruct loadConF(regF dst, immF src) %{
12225 match(Set dst src);
12226 ins_cost(125);
12228 format %{ "lwc1 $dst, $constantoffset[$constanttablebase] # load FLOAT $src from table @ loadConF" %}
12229 ins_encode %{
12230 int con_offset = $constantoffset($src);
12232 if (Assembler::is_simm16(con_offset)) {
12233 __ lwc1($dst$$FloatRegister, $constanttablebase, con_offset);
12234 } else {
12235 __ set64(AT, con_offset);
12236 if (UseLoongsonISA) {
12237 __ gslwxc1($dst$$FloatRegister, $constanttablebase, AT, 0);
12238 } else {
12239 __ daddu(AT, $constanttablebase, AT);
12240 __ lwc1($dst$$FloatRegister, AT, 0);
12241 }
12242 }
12243 %}
12244 ins_pipe( fpu_loadF );
12245 %}
12248 instruct loadConD0(regD dst, immD0 zero) %{
12249 match(Set dst zero);
12250 ins_cost(100);
12252 format %{ "mov $dst, zero @ loadConD0"%}
12253 ins_encode %{
12254 FloatRegister dst = as_FloatRegister($dst$$reg);
12256 __ dmtc1(R0, dst);
12257 %}
12258 ins_pipe( fpu_loadF );
12259 %}
12261 instruct loadConD(regD dst, immD src) %{
12262 match(Set dst src);
12263 ins_cost(125);
12265 format %{ "ldc1 $dst, $constantoffset[$constanttablebase] # load DOUBLE $src from table @ loadConD" %}
12266 ins_encode %{
12267 int con_offset = $constantoffset($src);
12269 if (Assembler::is_simm16(con_offset)) {
12270 __ ldc1($dst$$FloatRegister, $constanttablebase, con_offset);
12271 } else {
12272 __ set64(AT, con_offset);
12273 if (UseLoongsonISA) {
12274 __ gsldxc1($dst$$FloatRegister, $constanttablebase, AT, 0);
12275 } else {
12276 __ daddu(AT, $constanttablebase, AT);
12277 __ ldc1($dst$$FloatRegister, AT, 0);
12278 }
12279 }
12280 %}
12281 ins_pipe( fpu_loadF );
12282 %}
12284 // Store register Float value (it is faster than store from FPU register)
12285 instruct storeF_reg( memory mem, regF src) %{
12286 match(Set mem (StoreF mem src));
12288 ins_cost(50);
12289 format %{ "store $mem, $src\t# store float @ storeF_reg" %}
12290 ins_encode(store_F_reg_enc(mem, src));
12291 ins_pipe( fpu_storeF );
12292 %}
12294 instruct storeF_imm0( memory mem, immF0 zero) %{
12295 match(Set mem (StoreF mem zero));
12297 ins_cost(40);
12298 format %{ "store $mem, zero\t# store float @ storeF_imm0" %}
12299 ins_encode %{
12300 int base = $mem$$base;
12301 int index = $mem$$index;
12302 int scale = $mem$$scale;
12303 int disp = $mem$$disp;
12305 if( index != 0 ) {
12306 if(scale != 0) {
12307 __ dsll(T9, as_Register(index), scale);
12308 __ addu(AT, as_Register(base), T9);
12309 } else {
12310 __ daddu(AT, as_Register(base), as_Register(index));
12311 }
12312 if( Assembler::is_simm16(disp) ) {
12313 __ sw(R0, AT, disp);
12314 } else {
12315 __ move(T9, disp);
12316 __ addu(AT, AT, T9);
12317 __ sw(R0, AT, 0);
12318 }
12320 } else {
12321 if( Assembler::is_simm16(disp) ) {
12322 __ sw(R0, as_Register(base), disp);
12323 } else {
12324 __ move(T9, disp);
12325 __ addu(AT, as_Register(base), T9);
12326 __ sw(R0, AT, 0);
12327 }
12328 }
12329 %}
12330 ins_pipe( ialu_storeI );
12331 %}
12333 // Load Double
12334 instruct loadD(regD dst, memory mem) %{
12335 match(Set dst (LoadD mem));
12337 ins_cost(150);
12338 format %{ "loadD $dst, $mem #@loadD" %}
12339 ins_encode(load_D_enc(dst, mem));
12340 ins_pipe( ialu_loadI );
12341 %}
12343 // Load Double - UNaligned
12344 instruct loadD_unaligned(regD dst, memory mem ) %{
12345 match(Set dst (LoadD_unaligned mem));
12346 ins_cost(250);
12347 // FIXME: Jin: Need more effective ldl/ldr
12348 format %{ "loadD_unaligned $dst, $mem #@loadD_unaligned" %}
12349 ins_encode(load_D_enc(dst, mem));
12350 ins_pipe( ialu_loadI );
12351 %}
12353 instruct storeD_reg( memory mem, regD src) %{
12354 match(Set mem (StoreD mem src));
12356 ins_cost(50);
12357 format %{ "store $mem, $src\t# store float @ storeD_reg" %}
12358 ins_encode(store_D_reg_enc(mem, src));
12359 ins_pipe( fpu_storeF );
12360 %}
12362 instruct storeD_imm0( memory mem, immD0 zero) %{
12363 match(Set mem (StoreD mem zero));
12365 ins_cost(40);
12366 format %{ "store $mem, zero\t# store float @ storeD_imm0" %}
12367 ins_encode %{
12368 int base = $mem$$base;
12369 int index = $mem$$index;
12370 int scale = $mem$$scale;
12371 int disp = $mem$$disp;
12373 __ mtc1(R0, F30);
12374 __ cvt_d_w(F30, F30);
12376 if( index != 0 ) {
12377 if(scale != 0) {
12378 __ dsll(T9, as_Register(index), scale);
12379 __ addu(AT, as_Register(base), T9);
12380 } else {
12381 __ daddu(AT, as_Register(base), as_Register(index));
12382 }
12383 if( Assembler::is_simm16(disp) ) {
12384 __ sdc1(F30, AT, disp);
12385 } else {
12386 __ move(T9, disp);
12387 __ addu(AT, AT, T9);
12388 __ sdc1(F30, AT, 0);
12389 }
12391 } else {
12392 if( Assembler::is_simm16(disp) ) {
12393 __ sdc1(F30, as_Register(base), disp);
12394 } else {
12395 __ move(T9, disp);
12396 __ addu(AT, as_Register(base), T9);
12397 __ sdc1(F30, AT, 0);
12398 }
12399 }
12400 %}
12401 ins_pipe( ialu_storeI );
12402 %}
12404 instruct loadSSI(mRegI dst, stackSlotI src)
12405 %{
12406 match(Set dst src);
12408 ins_cost(125);
12409 format %{ "lw $dst, $src\t# int stk @ loadSSI" %}
12410 ins_encode %{
12411 guarantee( Assembler::is_simm16($src$$disp), "disp too long (loadSSI) !");
12412 __ lw($dst$$Register, SP, $src$$disp);
12413 %}
12414 ins_pipe(ialu_loadI);
12415 %}
12417 instruct storeSSI(stackSlotI dst, mRegI src)
12418 %{
12419 match(Set dst src);
12421 ins_cost(100);
12422 format %{ "sw $dst, $src\t# int stk @ storeSSI" %}
12423 ins_encode %{
12424 guarantee( Assembler::is_simm16($dst$$disp), "disp too long (storeSSI) !");
12425 __ sw($src$$Register, SP, $dst$$disp);
12426 %}
12427 ins_pipe(ialu_storeI);
12428 %}
12430 instruct loadSSL(mRegL dst, stackSlotL src)
12431 %{
12432 match(Set dst src);
12434 ins_cost(125);
12435 format %{ "ld $dst, $src\t# long stk @ loadSSL" %}
12436 ins_encode %{
12437 guarantee( Assembler::is_simm16($src$$disp), "disp too long (loadSSL) !");
12438 __ ld($dst$$Register, SP, $src$$disp);
12439 %}
12440 ins_pipe(ialu_loadI);
12441 %}
12443 instruct storeSSL(stackSlotL dst, mRegL src)
12444 %{
12445 match(Set dst src);
12447 ins_cost(100);
12448 format %{ "sd $dst, $src\t# long stk @ storeSSL" %}
12449 ins_encode %{
12450 guarantee( Assembler::is_simm16($dst$$disp), "disp too long (storeSSL) !");
12451 __ sd($src$$Register, SP, $dst$$disp);
12452 %}
12453 ins_pipe(ialu_storeI);
12454 %}
12456 instruct loadSSP(mRegP dst, stackSlotP src)
12457 %{
12458 match(Set dst src);
12460 ins_cost(125);
12461 format %{ "ld $dst, $src\t# ptr stk @ loadSSP" %}
12462 ins_encode %{
12463 guarantee( Assembler::is_simm16($src$$disp), "disp too long (loadSSP) !");
12464 __ ld($dst$$Register, SP, $src$$disp);
12465 %}
12466 ins_pipe(ialu_loadI);
12467 %}
12469 instruct storeSSP(stackSlotP dst, mRegP src)
12470 %{
12471 match(Set dst src);
12473 ins_cost(100);
12474 format %{ "sd $dst, $src\t# ptr stk @ storeSSP" %}
12475 ins_encode %{
12476 guarantee( Assembler::is_simm16($dst$$disp), "disp too long (storeSSP) !");
12477 __ sd($src$$Register, SP, $dst$$disp);
12478 %}
12479 ins_pipe(ialu_storeI);
12480 %}
12482 instruct loadSSF(regF dst, stackSlotF src)
12483 %{
12484 match(Set dst src);
12486 ins_cost(125);
12487 format %{ "lwc1 $dst, $src\t# float stk @ loadSSF" %}
12488 ins_encode %{
12489 guarantee( Assembler::is_simm16($src$$disp), "disp too long (loadSSF) !");
12490 __ lwc1($dst$$FloatRegister, SP, $src$$disp);
12491 %}
12492 ins_pipe(ialu_loadI);
12493 %}
12495 instruct storeSSF(stackSlotF dst, regF src)
12496 %{
12497 match(Set dst src);
12499 ins_cost(100);
12500 format %{ "swc1 $dst, $src\t# float stk @ storeSSF" %}
12501 ins_encode %{
12502 guarantee( Assembler::is_simm16($dst$$disp), "disp too long (storeSSF) !");
12503 __ swc1($src$$FloatRegister, SP, $dst$$disp);
12504 %}
12505 ins_pipe(fpu_storeF);
12506 %}
12508 // Use the same format since predicate() can not be used here.
12509 instruct loadSSD(regD dst, stackSlotD src)
12510 %{
12511 match(Set dst src);
12513 ins_cost(125);
12514 format %{ "ldc1 $dst, $src\t# double stk @ loadSSD" %}
12515 ins_encode %{
12516 guarantee( Assembler::is_simm16($src$$disp), "disp too long (loadSSD) !");
12517 __ ldc1($dst$$FloatRegister, SP, $src$$disp);
12518 %}
12519 ins_pipe(ialu_loadI);
12520 %}
12522 instruct storeSSD(stackSlotD dst, regD src)
12523 %{
12524 match(Set dst src);
12526 ins_cost(100);
12527 format %{ "sdc1 $dst, $src\t# double stk @ storeSSD" %}
12528 ins_encode %{
12529 guarantee( Assembler::is_simm16($dst$$disp), "disp too long (storeSSD) !");
12530 __ sdc1($src$$FloatRegister, SP, $dst$$disp);
12531 %}
12532 ins_pipe(fpu_storeF);
12533 %}
12535 instruct cmpFastLock( FlagsReg cr, mRegP object, s0_RegP box, mRegI tmp, mRegP scr) %{
12536 match( Set cr (FastLock object box) );
12537 effect( TEMP tmp, TEMP scr, USE_KILL box );
12538 ins_cost(300);
12539 format %{ "FASTLOCK $cr $object, $box, $tmp #@ cmpFastLock" %}
12540 ins_encode %{
12541 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register, $scr$$Register);
12542 %}
12544 ins_pipe( pipe_slow );
12545 ins_pc_relative(1);
12546 %}
12548 instruct cmpFastUnlock( FlagsReg cr, mRegP object, s0_RegP box, mRegP tmp ) %{
12549 match( Set cr (FastUnlock object box) );
12550 effect( TEMP tmp, USE_KILL box );
12551 ins_cost(300);
12552 format %{ "FASTUNLOCK $object, $box, $tmp #@cmpFastUnlock" %}
12553 ins_encode %{
12554 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register);
12555 %}
12557 ins_pipe( pipe_slow );
12558 ins_pc_relative(1);
12559 %}
12561 // Store CMS card-mark Immediate
12562 instruct storeImmCM(memory mem, immI8 src) %{
12563 match(Set mem (StoreCM mem src));
12565 ins_cost(150);
12566 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
12567 // opcode(0xC6);
12568 ins_encode(store_B_immI_enc_sync(mem, src));
12569 ins_pipe( ialu_storeI );
12570 %}
12572 // Die now
12573 instruct ShouldNotReachHere( )
12574 %{
12575 match(Halt);
12576 ins_cost(300);
12578 // Use the following format syntax
12579 format %{ "ILLTRAP ;#@ShouldNotReachHere" %}
12580 ins_encode %{
12581 // Here we should emit illtrap !
12583 __ stop("in ShoudNotReachHere");
12585 %}
12586 ins_pipe( pipe_jump );
12587 %}
12589 instruct leaP8Narrow(mRegP dst, indOffset8Narrow mem)
12590 %{
12591 predicate(Universe::narrow_oop_shift() == 0);
12592 match(Set dst mem);
12594 ins_cost(110);
12595 format %{ "leaq $dst, $mem\t# ptr off8narrow @ leaP8Narrow" %}
12596 ins_encode %{
12597 Register dst = $dst$$Register;
12598 Register base = as_Register($mem$$base);
12599 int disp = $mem$$disp;
12601 __ daddiu(dst, base, disp);
12602 %}
12603 ins_pipe( ialu_regI_imm16 );
12604 %}
12606 instruct leaPPosIdxScaleOff8(mRegP dst, basePosIndexScaleOffset8 mem)
12607 %{
12608 match(Set dst mem);
12610 ins_cost(110);
12611 format %{ "leaq $dst, $mem\t# @ PosIdxScaleOff8" %}
12612 ins_encode %{
12613 Register dst = $dst$$Register;
12614 Register base = as_Register($mem$$base);
12615 Register index = as_Register($mem$$index);
12616 int scale = $mem$$scale;
12617 int disp = $mem$$disp;
12619 if (scale == 0) {
12620 __ daddu(AT, base, index);
12621 __ daddiu(dst, AT, disp);
12622 } else {
12623 __ dsll(AT, index, scale);
12624 __ daddu(AT, base, AT);
12625 __ daddiu(dst, AT, disp);
12626 }
12627 %}
12629 ins_pipe( ialu_regI_imm16 );
12630 %}
12632 instruct leaPIdxScale(mRegP dst, indIndexScale mem)
12633 %{
12634 match(Set dst mem);
12636 ins_cost(110);
12637 format %{ "leaq $dst, $mem\t# @ leaPIdxScale" %}
12638 ins_encode %{
12639 Register dst = $dst$$Register;
12640 Register base = as_Register($mem$$base);
12641 Register index = as_Register($mem$$index);
12642 int scale = $mem$$scale;
12644 if (scale == 0) {
12645 __ daddu(dst, base, index);
12646 } else {
12647 __ dsll(AT, index, scale);
12648 __ daddu(dst, base, AT);
12649 }
12650 %}
12652 ins_pipe( ialu_regI_imm16 );
12653 %}
12655 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12656 instruct jmpLoopEnd(cmpOp cop, mRegI src1, mRegI src2, label labl) %{
12657 match(CountedLoopEnd cop (CmpI src1 src2));
12658 effect(USE labl);
12660 ins_cost(300);
12661 format %{ "J$cop $src1, $src2, $labl\t# Loop end @ jmpLoopEnd" %}
12662 ins_encode %{
12663 Register op1 = $src1$$Register;
12664 Register op2 = $src2$$Register;
12665 Label &L = *($labl$$label);
12666 int flag = $cop$$cmpcode;
12668 switch(flag)
12669 {
12670 case 0x01: //equal
12671 if (&L)
12672 __ beq(op1, op2, L);
12673 else
12674 __ beq(op1, op2, (int)0);
12675 break;
12676 case 0x02: //not_equal
12677 if (&L)
12678 __ bne(op1, op2, L);
12679 else
12680 __ bne(op1, op2, (int)0);
12681 break;
12682 case 0x03: //above
12683 __ slt(AT, op2, op1);
12684 if(&L)
12685 __ bne(AT, R0, L);
12686 else
12687 __ bne(AT, R0, (int)0);
12688 break;
12689 case 0x04: //above_equal
12690 __ slt(AT, op1, op2);
12691 if(&L)
12692 __ beq(AT, R0, L);
12693 else
12694 __ beq(AT, R0, (int)0);
12695 break;
12696 case 0x05: //below
12697 __ slt(AT, op1, op2);
12698 if(&L)
12699 __ bne(AT, R0, L);
12700 else
12701 __ bne(AT, R0, (int)0);
12702 break;
12703 case 0x06: //below_equal
12704 __ slt(AT, op2, op1);
12705 if(&L)
12706 __ beq(AT, R0, L);
12707 else
12708 __ beq(AT, R0, (int)0);
12709 break;
12710 default:
12711 Unimplemented();
12712 }
12713 __ nop();
12714 %}
12715 ins_pipe( pipe_jump );
12716 ins_pc_relative(1);
12717 %}
12720 instruct jmpLoopEnd_reg_imm16_sub(cmpOp cop, mRegI src1, immI16_sub src2, label labl) %{
12721 match(CountedLoopEnd cop (CmpI src1 src2));
12722 effect(USE labl);
12724 ins_cost(250);
12725 format %{ "J$cop $src1, $src2, $labl\t# Loop end @ jmpLoopEnd_reg_imm16_sub" %}
12726 ins_encode %{
12727 Register op1 = $src1$$Register;
12728 int op2 = $src2$$constant;
12729 Label &L = *($labl$$label);
12730 int flag = $cop$$cmpcode;
12732 __ addiu32(AT, op1, -1 * op2);
12734 switch(flag)
12735 {
12736 case 0x01: //equal
12737 if (&L)
12738 __ beq(AT, R0, L);
12739 else
12740 __ beq(AT, R0, (int)0);
12741 break;
12742 case 0x02: //not_equal
12743 if (&L)
12744 __ bne(AT, R0, L);
12745 else
12746 __ bne(AT, R0, (int)0);
12747 break;
12748 case 0x03: //above
12749 if(&L)
12750 __ bgtz(AT, L);
12751 else
12752 __ bgtz(AT, (int)0);
12753 break;
12754 case 0x04: //above_equal
12755 if(&L)
12756 __ bgez(AT, L);
12757 else
12758 __ bgez(AT,(int)0);
12759 break;
12760 case 0x05: //below
12761 if(&L)
12762 __ bltz(AT, L);
12763 else
12764 __ bltz(AT, (int)0);
12765 break;
12766 case 0x06: //below_equal
12767 if(&L)
12768 __ blez(AT, L);
12769 else
12770 __ blez(AT, (int)0);
12771 break;
12772 default:
12773 Unimplemented();
12774 }
12775 __ nop();
12776 %}
12777 ins_pipe( pipe_jump );
12778 ins_pc_relative(1);
12779 %}
12782 /*
12783 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12784 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12785 match(CountedLoopEnd cop cmp);
12786 effect(USE labl);
12788 ins_cost(300);
12789 format %{ "J$cop,u $labl\t# Loop end" %}
12790 size(6);
12791 opcode(0x0F, 0x80);
12792 ins_encode( Jcc( cop, labl) );
12793 ins_pipe( pipe_jump );
12794 ins_pc_relative(1);
12795 %}
12797 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12798 match(CountedLoopEnd cop cmp);
12799 effect(USE labl);
12801 ins_cost(200);
12802 format %{ "J$cop,u $labl\t# Loop end" %}
12803 opcode(0x0F, 0x80);
12804 ins_encode( Jcc( cop, labl) );
12805 ins_pipe( pipe_jump );
12806 ins_pc_relative(1);
12807 %}
12808 */
12810 // This match pattern is created for StoreIConditional since I cannot match IfNode without a RegFlags! fujie 2012/07/17
12811 instruct jmpCon_flags(cmpOp cop, FlagsReg cr, label labl) %{
12812 match(If cop cr);
12813 effect(USE labl);
12815 ins_cost(300);
12816 format %{ "J$cop $labl #mips uses AT as eflag @jmpCon_flags" %}
12818 ins_encode %{
12819 Label &L = *($labl$$label);
12820 switch($cop$$cmpcode)
12821 {
12822 case 0x01: //equal
12823 if (&L)
12824 __ bne(AT, R0, L);
12825 else
12826 __ bne(AT, R0, (int)0);
12827 break;
12828 case 0x02: //not equal
12829 if (&L)
12830 __ beq(AT, R0, L);
12831 else
12832 __ beq(AT, R0, (int)0);
12833 break;
12834 default:
12835 Unimplemented();
12836 }
12837 __ nop();
12838 %}
12840 ins_pipe( pipe_jump );
12841 ins_pc_relative(1);
12842 %}
12845 // ============================================================================
12846 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12847 // array for an instance of the superklass. Set a hidden internal cache on a
12848 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12849 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12850 instruct partialSubtypeCheck( mRegP result, no_T8_mRegP sub, no_T8_mRegP super, mT8RegI tmp ) %{
12851 match(Set result (PartialSubtypeCheck sub super));
12852 effect(KILL tmp);
12853 ins_cost(1100); // slightly larger than the next version
12854 format %{ "partialSubtypeCheck result=$result, sub=$sub, super=$super, tmp=$tmp " %}
12856 ins_encode( enc_PartialSubtypeCheck(result, sub, super, tmp) );
12857 ins_pipe( pipe_slow );
12858 %}
12861 // Conditional-store of an int value.
12862 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
12863 instruct storeIConditional( memory mem, mRegI oldval, mRegI newval, FlagsReg cr ) %{
12864 match(Set cr (StoreIConditional mem (Binary oldval newval)));
12865 // effect(KILL oldval);
12866 format %{ "CMPXCHG $newval, $mem, $oldval \t# @storeIConditional" %}
12868 ins_encode %{
12869 Register oldval = $oldval$$Register;
12870 Register newval = $newval$$Register;
12871 Address addr(as_Register($mem$$base), $mem$$disp);
12872 Label again, failure;
12874 // int base = $mem$$base;
12875 int index = $mem$$index;
12876 int scale = $mem$$scale;
12877 int disp = $mem$$disp;
12879 guarantee(Assembler::is_simm16(disp), "");
12881 if( index != 0 ) {
12882 __ stop("in storeIConditional: index != 0");
12883 } else {
12884 __ bind(again);
12885 __ sync();
12886 __ ll(AT, addr);
12887 __ bne(AT, oldval, failure);
12888 __ delayed()->addu(AT, R0, R0);
12890 __ addu(AT, newval, R0);
12891 __ sc(AT, addr);
12892 __ beq(AT, R0, again);
12893 __ delayed()->addiu(AT, R0, 0xFF);
12894 __ bind(failure);
12895 __ sync();
12896 }
12897 %}
12899 ins_pipe( long_memory_op );
12900 %}
12902 // Conditional-store of a long value.
12903 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
12904 instruct storeLConditional(memory mem, t2RegL oldval, mRegL newval, FlagsReg cr )
12905 %{
12906 match(Set cr (StoreLConditional mem (Binary oldval newval)));
12907 effect(KILL oldval);
12909 format %{ "cmpxchg $mem, $newval\t# If $oldval == $mem then store $newval into $mem" %}
12910 ins_encode%{
12911 Register oldval = $oldval$$Register;
12912 Register newval = $newval$$Register;
12913 Address addr((Register)$mem$$base, $mem$$disp);
12915 int index = $mem$$index;
12916 int scale = $mem$$scale;
12917 int disp = $mem$$disp;
12919 guarantee(Assembler::is_simm16(disp), "");
12921 if( index != 0 ) {
12922 __ stop("in storeIConditional: index != 0");
12923 } else {
12924 __ cmpxchg(newval, addr, oldval);
12925 }
12926 %}
12927 ins_pipe( long_memory_op );
12928 %}
12931 instruct compareAndSwapI( mRegI res, mRegP mem_ptr, mS2RegI oldval, mRegI newval) %{
12932 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
12933 effect(KILL oldval);
12934 // match(CompareAndSwapI mem_ptr (Binary oldval newval));
12935 format %{ "CMPXCHG $newval, [$mem_ptr], $oldval @ compareAndSwapI\n\t"
12936 "MOV $res, 1 @ compareAndSwapI\n\t"
12937 "BNE AT, R0 @ compareAndSwapI\n\t"
12938 "MOV $res, 0 @ compareAndSwapI\n"
12939 "L:" %}
12940 ins_encode %{
12941 Register newval = $newval$$Register;
12942 Register oldval = $oldval$$Register;
12943 Register res = $res$$Register;
12944 Address addr($mem_ptr$$Register, 0);
12945 Label L;
12947 __ cmpxchg32(newval, addr, oldval);
12948 __ move(res, AT);
12949 %}
12950 ins_pipe( long_memory_op );
12951 %}
12953 //FIXME:
12954 instruct compareAndSwapP( mRegI res, mRegP mem_ptr, s2_RegP oldval, mRegP newval) %{
12955 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
12956 effect(KILL oldval);
12957 format %{ "CMPXCHG $newval, [$mem_ptr], $oldval @ compareAndSwapP\n\t"
12958 "MOV $res, AT @ compareAndSwapP\n\t"
12959 "L:" %}
12960 ins_encode %{
12961 Register newval = $newval$$Register;
12962 Register oldval = $oldval$$Register;
12963 Register res = $res$$Register;
12964 Address addr($mem_ptr$$Register, 0);
12965 Label L;
12967 __ cmpxchg(newval, addr, oldval);
12968 __ move(res, AT);
12969 %}
12970 ins_pipe( long_memory_op );
12971 %}
12973 instruct compareAndSwapN( mRegI res, mRegP mem_ptr, t2_RegN oldval, mRegN newval) %{
12974 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
12975 effect(KILL oldval);
12976 format %{ "CMPXCHG $newval, [$mem_ptr], $oldval @ compareAndSwapN\n\t"
12977 "MOV $res, AT @ compareAndSwapN\n\t"
12978 "L:" %}
12979 ins_encode %{
12980 Register newval = $newval$$Register;
12981 Register oldval = $oldval$$Register;
12982 Register res = $res$$Register;
12983 Address addr($mem_ptr$$Register, 0);
12984 Label L;
12986 /* 2013/7/19 Jin: cmpxchg32 is implemented with ll/sc, which will do sign extension.
12987 * Thus, we should extend oldval's sign for correct comparision.
12988 */
12989 __ sll(oldval, oldval, 0);
12991 __ cmpxchg32(newval, addr, oldval);
12992 __ move(res, AT);
12993 %}
12994 ins_pipe( long_memory_op );
12995 %}
12997 //----------Max and Min--------------------------------------------------------
12998 // Min Instructions
12999 ////
13000 // *** Min and Max using the conditional move are slower than the
13001 // *** branch version on a Pentium III.
13002 // // Conditional move for min
13003 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
13004 // effect( USE_DEF op2, USE op1, USE cr );
13005 // format %{ "CMOVlt $op2,$op1\t! min" %}
13006 // opcode(0x4C,0x0F);
13007 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
13008 // ins_pipe( pipe_cmov_reg );
13009 //%}
13010 //
13011 //// Min Register with Register (P6 version)
13012 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{
13013 // predicate(VM_Version::supports_cmov() );
13014 // match(Set op2 (MinI op1 op2));
13015 // ins_cost(200);
13016 // expand %{
13017 // eFlagsReg cr;
13018 // compI_eReg(cr,op1,op2);
13019 // cmovI_reg_lt(op2,op1,cr);
13020 // %}
13021 //%}
13023 // Min Register with Register (generic version)
13024 instruct minI_Reg_Reg(mRegI dst, mRegI src) %{
13025 match(Set dst (MinI dst src));
13026 //effect(KILL flags);
13027 ins_cost(80);
13029 format %{ "MIN $dst, $src @minI_Reg_Reg" %}
13030 ins_encode %{
13031 Register dst = $dst$$Register;
13032 Register src = $src$$Register;
13034 __ slt(AT, src, dst);
13035 __ movn(dst, src, AT);
13037 %}
13039 ins_pipe( pipe_slow );
13040 %}
13042 // Max Register with Register
13043 // *** Min and Max using the conditional move are slower than the
13044 // *** branch version on a Pentium III.
13045 // // Conditional move for max
13046 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
13047 // effect( USE_DEF op2, USE op1, USE cr );
13048 // format %{ "CMOVgt $op2,$op1\t! max" %}
13049 // opcode(0x4F,0x0F);
13050 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
13051 // ins_pipe( pipe_cmov_reg );
13052 //%}
13053 //
13054 // // Max Register with Register (P6 version)
13055 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{
13056 // predicate(VM_Version::supports_cmov() );
13057 // match(Set op2 (MaxI op1 op2));
13058 // ins_cost(200);
13059 // expand %{
13060 // eFlagsReg cr;
13061 // compI_eReg(cr,op1,op2);
13062 // cmovI_reg_gt(op2,op1,cr);
13063 // %}
13064 //%}
13066 // Max Register with Register (generic version)
13067 instruct maxI_Reg_Reg(mRegI dst, mRegI src) %{
13068 match(Set dst (MaxI dst src));
13069 ins_cost(80);
13071 format %{ "MAX $dst, $src @maxI_Reg_Reg" %}
13073 ins_encode %{
13074 Register dst = $dst$$Register;
13075 Register src = $src$$Register;
13077 __ slt(AT, dst, src);
13078 __ movn(dst, src, AT);
13080 %}
13082 ins_pipe( pipe_slow );
13083 %}
13085 instruct maxI_Reg_zero(mRegI dst, immI0 zero) %{
13086 match(Set dst (MaxI dst zero));
13087 ins_cost(50);
13089 format %{ "MAX $dst, 0 @maxI_Reg_zero" %}
13091 ins_encode %{
13092 Register dst = $dst$$Register;
13094 __ slt(AT, dst, R0);
13095 __ movn(dst, R0, AT);
13097 %}
13099 ins_pipe( pipe_slow );
13100 %}
13102 instruct zerox_long_reg_reg(mRegL dst, mRegL src, immL_32bits mask)
13103 %{
13104 match(Set dst (AndL src mask));
13106 format %{ "movl $dst, $src\t# zero-extend long @ zerox_long_reg_reg" %}
13107 ins_encode %{
13108 Register dst = $dst$$Register;
13109 Register src = $src$$Register;
13111 __ dext(dst, src, 0, 32);
13112 %}
13113 ins_pipe(ialu_regI_regI);
13114 %}
13116 instruct combine_i2l(mRegL dst, mRegI src1, immL_32bits mask, mRegI src2, immI_32 shift32)
13117 %{
13118 match(Set dst (OrL (AndL (ConvI2L src1) mask) (LShiftL (ConvI2L src2) shift32)));
13120 format %{ "combine_i2l $dst, $src2(H), $src1(L) @ combine_i2l" %}
13121 ins_encode %{
13122 Register dst = $dst$$Register;
13123 Register src1 = $src1$$Register;
13124 Register src2 = $src2$$Register;
13126 if (src1 == dst) {
13127 __ dinsu(dst, src2, 32, 32);
13128 } else if (src2 == dst) {
13129 __ dsll32(dst, dst, 0);
13130 __ dins(dst, src1, 0, 32);
13131 } else {
13132 __ dext(dst, src1, 0, 32);
13133 __ dinsu(dst, src2, 32, 32);
13134 }
13135 %}
13136 ins_pipe(ialu_regI_regI);
13137 %}
13139 // Zero-extend convert int to long
13140 instruct convI2L_reg_reg_zex(mRegL dst, mRegI src, immL_32bits mask)
13141 %{
13142 match(Set dst (AndL (ConvI2L src) mask));
13144 format %{ "movl $dst, $src\t# i2l zero-extend @ convI2L_reg_reg_zex" %}
13145 ins_encode %{
13146 Register dst = $dst$$Register;
13147 Register src = $src$$Register;
13149 __ dext(dst, src, 0, 32);
13150 %}
13151 ins_pipe(ialu_regI_regI);
13152 %}
13154 instruct convL2I2L_reg_reg_zex(mRegL dst, mRegL src, immL_32bits mask)
13155 %{
13156 match(Set dst (AndL (ConvI2L (ConvL2I src)) mask));
13158 format %{ "movl $dst, $src\t# i2l zero-extend @ convL2I2L_reg_reg_zex" %}
13159 ins_encode %{
13160 Register dst = $dst$$Register;
13161 Register src = $src$$Register;
13163 __ dext(dst, src, 0, 32);
13164 %}
13165 ins_pipe(ialu_regI_regI);
13166 %}
13168 // Match loading integer and casting it to unsigned int in long register.
13169 // LoadI + ConvI2L + AndL 0xffffffff.
13170 instruct loadUI2L_rmask(mRegL dst, memory mem, immL_32bits mask) %{
13171 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
13173 format %{ "lwu $dst, $mem \t// zero-extend to long @ loadUI2L_rmask" %}
13174 ins_encode (load_N_enc(dst, mem));
13175 ins_pipe(ialu_loadI);
13176 %}
13178 instruct loadUI2L_lmask(mRegL dst, memory mem, immL_32bits mask) %{
13179 match(Set dst (AndL mask (ConvI2L (LoadI mem))));
13181 format %{ "lwu $dst, $mem \t// zero-extend to long @ loadUI2L_lmask" %}
13182 ins_encode (load_N_enc(dst, mem));
13183 ins_pipe(ialu_loadI);
13184 %}
13187 // ============================================================================
13188 // Safepoint Instruction
13189 instruct safePoint_poll(mRegP poll) %{
13190 match(SafePoint poll);
13191 effect(USE poll);
13193 ins_cost(125);
13194 format %{ "Safepoint @ [$poll] : poll for GC @ safePoint_poll" %}
13196 ins_encode %{
13197 Register poll_reg = $poll$$Register;
13199 __ block_comment("Safepoint:");
13200 __ relocate(relocInfo::poll_type);
13201 __ lw(AT, poll_reg, 0);
13202 %}
13204 ins_pipe( ialu_storeI );
13205 %}
13207 //----------Arithmetic Conversion Instructions---------------------------------
13209 instruct roundFloat_nop(regF dst)
13210 %{
13211 match(Set dst (RoundFloat dst));
13213 ins_cost(0);
13214 ins_encode();
13215 ins_pipe(empty);
13216 %}
13218 instruct roundDouble_nop(regD dst)
13219 %{
13220 match(Set dst (RoundDouble dst));
13222 ins_cost(0);
13223 ins_encode();
13224 ins_pipe(empty);
13225 %}
13227 //---------- Zeros Count Instructions ------------------------------------------
13228 // CountLeadingZerosINode CountTrailingZerosINode
13229 instruct countLeadingZerosI(mRegI dst, mRegI src) %{
13230 predicate(UseCountLeadingZerosInstruction);
13231 match(Set dst (CountLeadingZerosI src));
13233 format %{ "clz $dst, $src\t# count leading zeros (int)" %}
13234 ins_encode %{
13235 __ clz($dst$$Register, $src$$Register);
13236 %}
13237 ins_pipe( ialu_regL_regL );
13238 %}
13240 instruct countLeadingZerosL(mRegI dst, mRegL src) %{
13241 predicate(UseCountLeadingZerosInstruction);
13242 match(Set dst (CountLeadingZerosL src));
13244 format %{ "dclz $dst, $src\t# count leading zeros (long)" %}
13245 ins_encode %{
13246 __ dclz($dst$$Register, $src$$Register);
13247 %}
13248 ins_pipe( ialu_regL_regL );
13249 %}
13251 instruct countTrailingZerosI(mRegI dst, mRegI src) %{
13252 predicate(UseCountTrailingZerosInstruction);
13253 match(Set dst (CountTrailingZerosI src));
13255 format %{ "ctz $dst, $src\t# count trailing zeros (int)" %}
13256 ins_encode %{
13257 // ctz and dctz is gs instructions.
13258 __ ctz($dst$$Register, $src$$Register);
13259 %}
13260 ins_pipe( ialu_regL_regL );
13261 %}
13263 instruct countTrailingZerosL(mRegI dst, mRegL src) %{
13264 predicate(UseCountTrailingZerosInstruction);
13265 match(Set dst (CountTrailingZerosL src));
13267 format %{ "dcto $dst, $src\t# count trailing zeros (long)" %}
13268 ins_encode %{
13269 __ dctz($dst$$Register, $src$$Register);
13270 %}
13271 ins_pipe( ialu_regL_regL );
13272 %}
13274 // ====================VECTOR INSTRUCTIONS=====================================
13276 // Load vectors (8 bytes long)
13277 instruct loadV8(vecD dst, memory mem) %{
13278 predicate(n->as_LoadVector()->memory_size() == 8);
13279 match(Set dst (LoadVector mem));
13280 ins_cost(125);
13281 format %{ "load $dst, $mem\t! load vector (8 bytes)" %}
13282 ins_encode(load_D_enc(dst, mem));
13283 ins_pipe( fpu_loadF );
13284 %}
13286 // Store vectors (8 bytes long)
13287 instruct storeV8(memory mem, vecD src) %{
13288 predicate(n->as_StoreVector()->memory_size() == 8);
13289 match(Set mem (StoreVector mem src));
13290 ins_cost(145);
13291 format %{ "store $mem, $src\t! store vector (8 bytes)" %}
13292 ins_encode(store_D_reg_enc(mem, src));
13293 ins_pipe( fpu_storeF );
13294 %}
13296 instruct Repl8B(vecD dst, mRegI src) %{
13297 predicate(n->as_Vector()->length() == 8);
13298 match(Set dst (ReplicateB src));
13299 format %{ "replv_ob AT, $src\n\t"
13300 "dmtc1 AT, $dst\t! replicate8B" %}
13301 ins_encode %{
13302 __ replv_ob(AT, $src$$Register);
13303 __ dmtc1(AT, $dst$$FloatRegister);
13304 %}
13305 ins_pipe( pipe_mtc1 );
13306 %}
13308 instruct Repl8B_imm(vecD dst, immI con) %{
13309 predicate(n->as_Vector()->length() == 8);
13310 match(Set dst (ReplicateB con));
13311 format %{ "repl_ob AT, [$con]\n\t"
13312 "dmtc1 AT, $dst,0x00\t! replicate8B($con)" %}
13313 ins_encode %{
13314 int val = $con$$constant;
13315 __ repl_ob(AT, val);
13316 __ dmtc1(AT, $dst$$FloatRegister);
13317 %}
13318 ins_pipe( pipe_mtc1 );
13319 %}
13321 instruct Repl8B_zero(vecD dst, immI0 zero) %{
13322 predicate(n->as_Vector()->length() == 8);
13323 match(Set dst (ReplicateB zero));
13324 format %{ "dmtc1 R0, $dst\t! replicate8B zero" %}
13325 ins_encode %{
13326 __ dmtc1(R0, $dst$$FloatRegister);
13327 %}
13328 ins_pipe( pipe_mtc1 );
13329 %}
13331 instruct Repl8B_M1(vecD dst, immI_M1 M1) %{
13332 predicate(n->as_Vector()->length() == 8);
13333 match(Set dst (ReplicateB M1));
13334 format %{ "dmtc1 -1, $dst\t! replicate8B -1" %}
13335 ins_encode %{
13336 __ nor(AT, R0, R0);
13337 __ dmtc1(AT, $dst$$FloatRegister);
13338 %}
13339 ins_pipe( pipe_mtc1 );
13340 %}
13342 instruct Repl4S(vecD dst, mRegI src) %{
13343 predicate(n->as_Vector()->length() == 4);
13344 match(Set dst (ReplicateS src));
13345 format %{ "replv_qh AT, $src\n\t"
13346 "dmtc1 AT, $dst\t! replicate4S" %}
13347 ins_encode %{
13348 __ replv_qh(AT, $src$$Register);
13349 __ dmtc1(AT, $dst$$FloatRegister);
13350 %}
13351 ins_pipe( pipe_mtc1 );
13352 %}
13354 instruct Repl4S_imm(vecD dst, immI con) %{
13355 predicate(n->as_Vector()->length() == 4);
13356 match(Set dst (ReplicateS con));
13357 format %{ "replv_qh AT, [$con]\n\t"
13358 "dmtc1 AT, $dst\t! replicate4S($con)" %}
13359 ins_encode %{
13360 int val = $con$$constant;
13361 if ( Assembler::is_simm(val, 10)) {
13362 //repl_qh supports 10 bits immediate
13363 __ repl_qh(AT, val);
13364 } else {
13365 __ li32(AT, val);
13366 __ replv_qh(AT, AT);
13367 }
13368 __ dmtc1(AT, $dst$$FloatRegister);
13369 %}
13370 ins_pipe( pipe_mtc1 );
13371 %}
13373 instruct Repl4S_zero(vecD dst, immI0 zero) %{
13374 predicate(n->as_Vector()->length() == 4);
13375 match(Set dst (ReplicateS zero));
13376 format %{ "dmtc1 R0, $dst\t! replicate4S zero" %}
13377 ins_encode %{
13378 __ dmtc1(R0, $dst$$FloatRegister);
13379 %}
13380 ins_pipe( pipe_mtc1 );
13381 %}
13383 instruct Repl4S_M1(vecD dst, immI_M1 M1) %{
13384 predicate(n->as_Vector()->length() == 4);
13385 match(Set dst (ReplicateS M1));
13386 format %{ "dmtc1 -1, $dst\t! replicate4S -1" %}
13387 ins_encode %{
13388 __ nor(AT, R0, R0);
13389 __ dmtc1(AT, $dst$$FloatRegister);
13390 %}
13391 ins_pipe( pipe_mtc1 );
13392 %}
13394 // Replicate integer (4 byte) scalar to be vector
13395 instruct Repl2I(vecD dst, mRegI src) %{
13396 predicate(n->as_Vector()->length() == 2);
13397 match(Set dst (ReplicateI src));
13398 format %{ "dins AT, $src, 0, 32\n\t"
13399 "dinsu AT, $src, 32, 32\n\t"
13400 "dmtc1 AT, $dst\t! replicate2I" %}
13401 ins_encode %{
13402 __ dins(AT, $src$$Register, 0, 32);
13403 __ dinsu(AT, $src$$Register, 32, 32);
13404 __ dmtc1(AT, $dst$$FloatRegister);
13405 %}
13406 ins_pipe( pipe_mtc1 );
13407 %}
13409 // Replicate integer (4 byte) scalar immediate to be vector by loading from const table.
13410 instruct Repl2I_imm(vecD dst, immI con, mA7RegI tmp) %{
13411 predicate(n->as_Vector()->length() == 2);
13412 match(Set dst (ReplicateI con));
13413 effect(KILL tmp);
13414 format %{ "li32 AT, [$con], 32\n\t"
13415 "replv_pw AT, AT\n\t"
13416 "dmtc1 AT, $dst\t! replicate2I($con)" %}
13417 ins_encode %{
13418 int val = $con$$constant;
13419 __ li32(AT, val);
13420 __ replv_pw(AT, AT);
13421 __ dmtc1(AT, $dst$$FloatRegister);
13422 %}
13423 ins_pipe( pipe_mtc1 );
13424 %}
13426 // Replicate integer (4 byte) scalar zero to be vector
13427 instruct Repl2I_zero(vecD dst, immI0 zero) %{
13428 predicate(n->as_Vector()->length() == 2);
13429 match(Set dst (ReplicateI zero));
13430 format %{ "dmtc1 R0, $dst\t! replicate2I zero" %}
13431 ins_encode %{
13432 __ dmtc1(R0, $dst$$FloatRegister);
13433 %}
13434 ins_pipe( pipe_mtc1 );
13435 %}
13437 // Replicate integer (4 byte) scalar -1 to be vector
13438 instruct Repl2I_M1(vecD dst, immI_M1 M1) %{
13439 predicate(n->as_Vector()->length() == 2);
13440 match(Set dst (ReplicateI M1));
13441 format %{ "dmtc1 -1, $dst\t! replicate2I -1, use AT" %}
13442 ins_encode %{
13443 __ nor(AT, R0, R0);
13444 __ dmtc1(AT, $dst$$FloatRegister);
13445 %}
13446 ins_pipe( pipe_mtc1 );
13447 %}
13449 // Replicate float (4 byte) scalar to be vector
13450 instruct Repl2F(vecD dst, regF src) %{
13451 predicate(n->as_Vector()->length() == 2);
13452 match(Set dst (ReplicateF src));
13453 format %{ "cvt.ps $dst, $src, $src\t! replicate2F" %}
13454 ins_encode %{
13455 __ cvt_ps_s($dst$$FloatRegister, $src$$FloatRegister, $src$$FloatRegister);
13456 %}
13457 ins_pipe( pipe_slow );
13458 %}
13460 // Replicate float (4 byte) scalar zero to be vector
13461 instruct Repl2F_zero(vecD dst, immF0 zero) %{
13462 predicate(n->as_Vector()->length() == 2);
13463 match(Set dst (ReplicateF zero));
13464 format %{ "dmtc1 R0, $dst\t! replicate2F zero" %}
13465 ins_encode %{
13466 __ dmtc1(R0, $dst$$FloatRegister);
13467 %}
13468 ins_pipe( pipe_mtc1 );
13469 %}
13472 // ====================VECTOR ARITHMETIC=======================================
13474 // --------------------------------- ADD --------------------------------------
13476 // Floats vector add
13477 instruct vadd2F(vecD dst, vecD src) %{
13478 predicate(n->as_Vector()->length() == 2);
13479 match(Set dst (AddVF dst src));
13480 format %{ "add.ps $dst,$src\t! add packed2F" %}
13481 ins_encode %{
13482 __ add_ps($dst$$FloatRegister, $dst$$FloatRegister, $src$$FloatRegister);
13483 %}
13484 ins_pipe( pipe_slow );
13485 %}
13487 instruct vadd2F3(vecD dst, vecD src1, vecD src2) %{
13488 predicate(n->as_Vector()->length() == 2);
13489 match(Set dst (AddVF src1 src2));
13490 format %{ "add.ps $dst,$src1,$src2\t! add packed2F" %}
13491 ins_encode %{
13492 __ add_ps($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
13493 %}
13494 ins_pipe( fpu_regF_regF );
13495 %}
13497 // --------------------------------- SUB --------------------------------------
13499 // Floats vector sub
13500 instruct vsub2F(vecD dst, vecD src) %{
13501 predicate(n->as_Vector()->length() == 2);
13502 match(Set dst (SubVF dst src));
13503 format %{ "sub.ps $dst,$src\t! sub packed2F" %}
13504 ins_encode %{
13505 __ sub_ps($dst$$FloatRegister, $dst$$FloatRegister, $src$$FloatRegister);
13506 %}
13507 ins_pipe( fpu_regF_regF );
13508 %}
13510 // --------------------------------- MUL --------------------------------------
13512 // Floats vector mul
13513 instruct vmul2F(vecD dst, vecD src) %{
13514 predicate(n->as_Vector()->length() == 2);
13515 match(Set dst (MulVF dst src));
13516 format %{ "mul.ps $dst, $src\t! mul packed2F" %}
13517 ins_encode %{
13518 __ mul_ps($dst$$FloatRegister, $dst$$FloatRegister, $src$$FloatRegister);
13519 %}
13520 ins_pipe( fpu_regF_regF );
13521 %}
13523 instruct vmul2F3(vecD dst, vecD src1, vecD src2) %{
13524 predicate(n->as_Vector()->length() == 2);
13525 match(Set dst (MulVF src1 src2));
13526 format %{ "mul.ps $dst, $src1, $src2\t! mul packed2F" %}
13527 ins_encode %{
13528 __ mul_ps($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
13529 %}
13530 ins_pipe( fpu_regF_regF );
13531 %}
13533 // --------------------------------- DIV --------------------------------------
13534 // MIPS do not have div.ps
13537 //----------PEEPHOLE RULES-----------------------------------------------------
13538 // These must follow all instruction definitions as they use the names
13539 // defined in the instructions definitions.
13540 //
13541 // peepmatch ( root_instr_name [preceeding_instruction]* );
13542 //
13543 // peepconstraint %{
13544 // (instruction_number.operand_name relational_op instruction_number.operand_name
13545 // [, ...] );
13546 // // instruction numbers are zero-based using left to right order in peepmatch
13547 //
13548 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13549 // // provide an instruction_number.operand_name for each operand that appears
13550 // // in the replacement instruction's match rule
13551 //
13552 // ---------VM FLAGS---------------------------------------------------------
13553 //
13554 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13555 //
13556 // Each peephole rule is given an identifying number starting with zero and
13557 // increasing by one in the order seen by the parser. An individual peephole
13558 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13559 // on the command-line.
13560 //
13561 // ---------CURRENT LIMITATIONS----------------------------------------------
13562 //
13563 // Only match adjacent instructions in same basic block
13564 // Only equality constraints
13565 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13566 // Only one replacement instruction
13567 //
13568 // ---------EXAMPLE----------------------------------------------------------
13569 //
13570 // // pertinent parts of existing instructions in architecture description
13571 // instruct movI(eRegI dst, eRegI src) %{
13572 // match(Set dst (CopyI src));
13573 // %}
13574 //
13575 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
13576 // match(Set dst (AddI dst src));
13577 // effect(KILL cr);
13578 // %}
13579 //
13580 // // Change (inc mov) to lea
13581 // peephole %{
13582 // // increment preceeded by register-register move
13583 // peepmatch ( incI_eReg movI );
13584 // // require that the destination register of the increment
13585 // // match the destination register of the move
13586 // peepconstraint ( 0.dst == 1.dst );
13587 // // construct a replacement instruction that sets
13588 // // the destination to ( move's source register + one )
13589 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13590 // %}
13591 //
13592 // Implementation no longer uses movX instructions since
13593 // machine-independent system no longer uses CopyX nodes.
13594 //
13595 // peephole %{
13596 // peepmatch ( incI_eReg movI );
13597 // peepconstraint ( 0.dst == 1.dst );
13598 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13599 // %}
13600 //
13601 // peephole %{
13602 // peepmatch ( decI_eReg movI );
13603 // peepconstraint ( 0.dst == 1.dst );
13604 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13605 // %}
13606 //
13607 // peephole %{
13608 // peepmatch ( addI_eReg_imm movI );
13609 // peepconstraint ( 0.dst == 1.dst );
13610 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13611 // %}
13612 //
13613 // peephole %{
13614 // peepmatch ( addP_eReg_imm movP );
13615 // peepconstraint ( 0.dst == 1.dst );
13616 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13617 // %}
13619 // // Change load of spilled value to only a spill
13620 // instruct storeI(memory mem, eRegI src) %{
13621 // match(Set mem (StoreI mem src));
13622 // %}
13623 //
13624 // instruct loadI(eRegI dst, memory mem) %{
13625 // match(Set dst (LoadI mem));
13626 // %}
13627 //
13628 //peephole %{
13629 // peepmatch ( loadI storeI );
13630 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13631 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13632 //%}
13634 //----------SMARTSPILL RULES---------------------------------------------------
13635 // These must follow all instruction definitions as they use the names
13636 // defined in the instructions definitions.
