1.1 --- a/src/cpu/mips/vm/mips_64.ad Sun Feb 19 17:43:11 2017 -0500 1.2 +++ b/src/cpu/mips/vm/mips_64.ad Mon Feb 20 12:23:10 2017 -0500 1.3 @@ -11104,6 +11104,26 @@ 1.4 ins_pipe( ialu_regI_regI ); 1.5 %} 1.6 1.7 +instruct rotI_shr_logical_Reg(mRegI dst, mRegI src, immI_0_31 rshift, immI_0_31 lshift, immI_1 one) %{ 1.8 + match(Set dst (OrI (URShiftI src rshift) (LShiftI (AndI src one) lshift))); 1.9 + predicate(32 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()))); 1.10 + 1.11 + format %{ "rotr $dst, $src, 1 ...\n\t" 1.12 + "srl $dst, $dst, ($rshift-1) @ rotI_shr_logical_Reg" %} 1.13 + ins_encode %{ 1.14 + Register dst = $dst$$Register; 1.15 + Register src = $src$$Register; 1.16 + int rshift = $rshift$$constant; 1.17 + 1.18 + __ rotr(dst, src, 1); 1.19 + if (rshift - 1) { 1.20 + __ srl(dst, dst, rshift - 1); 1.21 + } 1.22 + %} 1.23 + 1.24 + ins_pipe( ialu_regI_regI ); 1.25 +%} 1.26 + 1.27 instruct orI_Reg_castP2X(mRegL dst, mRegL src1, mRegP src2) %{ 1.28 match(Set dst (OrI src1 (CastP2X src2))); 1.29