1.1 --- a/src/cpu/mips/vm/nativeInst_mips.cpp Sat Jan 06 16:30:58 2018 +0800
1.2 +++ b/src/cpu/mips/vm/nativeInst_mips.cpp Thu May 24 19:49:50 2018 +0800
1.3 @@ -203,6 +203,18 @@
1.4 return;
1.5 }
1.6
1.7 + //daddiu dst, R0, imm16
1.8 + //nop
1.9 + //nop
1.10 + //nop
1.11 + if ( is_op(Assembler::daddiu_op) &&
1.12 + nativeInstruction_at(addr_at(4))->is_nop() &&
1.13 + nativeInstruction_at(addr_at(8))->is_nop() &&
1.14 + nativeInstruction_at(addr_at(12))->is_nop() &&
1.15 + is_special_op(int_at(16), Assembler::jr_op) ) {
1.16 + return;
1.17 + }
1.18 +
1.19 //lui dst, imm16
1.20 //ori dst, dst, imm16
1.21 //nop
1.22 @@ -728,7 +740,7 @@
1.23 __ lui(T9, Assembler::split_high((int)entry));
1.24 __ addiu(T9, T9, Assembler::split_low((int)entry));
1.25 #else
1.26 - __ patchable_set48(T9, (long)entry);
1.27 + __ li48(T9, (long)entry);
1.28 #endif
1.29 __ jalr ();
1.30 __ delayed()->nop();
1.31 @@ -1099,6 +1111,7 @@
1.32 case Assembler::lh_op:
1.33 case Assembler::lhu_op:
1.34 case Assembler::lw_op:
1.35 + case Assembler::lwu_op:
1.36 LP64_ONLY(case Assembler::ld_op:)
1.37 case Assembler::lwc1_op:
1.38 LP64_ONLY(case Assembler::ldc1_op:)
1.39 @@ -1579,7 +1592,7 @@
1.40 "note::Runtime1::patch_code uses NativeCall::instruction_size");
1.41
1.42 /* 2013/6/13 Jin: ensure 100% atomicity */
1.43 - guarantee(!os::is_MP() || (((long)instr_addr % BytesPerWord) == 0), "destination must be aligned for SD");
1.44 + //guarantee(!os::is_MP() || (((long)instr_addr % BytesPerWord) == 0), "destination must be aligned for SD");
1.45
1.46 int *p = (int *)instr_addr;
1.47 int jr_word = p[4];
1.48 @@ -1594,7 +1607,7 @@
1.49 /* 2013/11/5 Jin: ensure 100% atomicity.
1.50 * The destination is fixed and can be cached in JavaThread.
1.51 */
1.52 - guarantee(!os::is_MP() || (((long)verified_entry % BytesPerWord) == 0), "destination must be aligned for SD");
1.53 + //guarantee(!os::is_MP() || (((long)verified_entry % BytesPerWord) == 0), "destination must be aligned for SD");
1.54
1.55 int code_buffer[4];
1.56
