1.1 --- a/src/cpu/mips/vm/bytes_mips.hpp Sun May 08 12:25:24 2016 -0400
1.2 +++ b/src/cpu/mips/vm/bytes_mips.hpp Sun May 08 17:53:51 2016 -0400
1.3 @@ -111,7 +111,22 @@
1.4 }
1.5 }
1.6 static inline void put_native_u4(address p, u4 x) {
1.7 - *(u4*)p = x;
1.8 + /* 2016/5/8 Jin: refer to sparc implementation.
1.9 + Note that sparc is big-endian, while mips is little-endian */
1.10 + switch ( intptr_t(p) & 3 ) {
1.11 + case 0: *(u4*)p = x;
1.12 + break;
1.13 +
1.14 + case 2: ((u2*)p)[1] = x >> 16;
1.15 + ((u2*)p)[0] = x;
1.16 + break;
1.17 +
1.18 + default: ((u1*)p)[3] = x >> 24;
1.19 + ((u1*)p)[2] = x >> 16;
1.20 + ((u1*)p)[1] = x >> 8;
1.21 + ((u1*)p)[0] = x;
1.22 + break;
1.23 + }
1.24 /* if ((int)p&3) {
1.25 __asm__ __volatile__ (
1.26 " .set push\n"
1.27 @@ -131,8 +146,31 @@
1.28 }*/
1.29 }
1.30 static inline void put_native_u8(address p, u8 x) {
1.31 - // u4 tp;//tmp register
1.32 - *(u8*)p = x;
1.33 + /* 2016/5/8 Jin: refer to sparc implementation.
1.34 + Note that sparc is big-endian, while mips is little-endian */
1.35 + switch ( intptr_t(p) & 7 ) {
1.36 + case 0: *(u8*)p = x;
1.37 + break;
1.38 +
1.39 + case 4: ((u4*)p)[1] = x >> 32;
1.40 + ((u4*)p)[0] = x;
1.41 + break;
1.42 +
1.43 + case 2: ((u2*)p)[3] = x >> 48;
1.44 + ((u2*)p)[2] = x >> 32;
1.45 + ((u2*)p)[1] = x >> 16;
1.46 + ((u2*)p)[0] = x;
1.47 + break;
1.48 +
1.49 + default: ((u1*)p)[7] = x >> 56;
1.50 + ((u1*)p)[6] = x >> 48;
1.51 + ((u1*)p)[5] = x >> 40;
1.52 + ((u1*)p)[4] = x >> 32;
1.53 + ((u1*)p)[3] = x >> 24;
1.54 + ((u1*)p)[2] = x >> 16;
1.55 + ((u1*)p)[1] = x >> 8;
1.56 + ((u1*)p)[0] = x;
1.57 + }
1.58 /*if ((int)p&7) {
1.59
1.60 __asm__ __volatile__ (
