1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/cpu/mips/vm/bytes_mips.hpp Fri Apr 29 00:06:10 2016 +0800
1.3 @@ -0,0 +1,195 @@
1.4 +/*
1.5 + * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
1.6 + * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.
1.7 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1.8 + *
1.9 + * This code is free software; you can redistribute it and/or modify it
1.10 + * under the terms of the GNU General Public License version 2 only, as
1.11 + * published by the Free Software Foundation.
1.12 + *
1.13 + * This code is distributed in the hope that it will be useful, but WITHOUT
1.14 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1.15 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1.16 + * version 2 for more details (a copy is included in the LICENSE file that
1.17 + * accompanied this code).
1.18 + *
1.19 + * You should have received a copy of the GNU General Public License version
1.20 + * 2 along with this work; if not, write to the Free Software Foundation,
1.21 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1.22 + *
1.23 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1.24 + * or visit www.oracle.com if you need additional information or have any
1.25 + * questions.
1.26 + *
1.27 + */
1.28 +
1.29 +#ifndef CPU_MIPS_VM_BYTES_MIPS_HPP
1.30 +#define CPU_MIPS_VM_BYTES_MIPS_HPP
1.31 +
1.32 +#include "memory/allocation.hpp"
1.33 +
1.34 +class Bytes: AllStatic {
1.35 + private:
1.36 + // Helper function for swap_u8, not used in Loongson.
1.37 + static inline u8 swap_u8_base(u4 x, u4 y) {} // compiler-dependent implementation
1.38 +
1.39 + public:
1.40 + // Returns true if the byte ordering used by Java is different from the native byte ordering
1.41 + // of the underlying machine. For example, this is true for Intel x86, but false for Solaris
1.42 + // on Sparc.
1.43 + // we use mipsel, so return true
1.44 + static inline bool is_Java_byte_ordering_different(){ return true; }
1.45 +
1.46 +
1.47 + // Efficient reading and writing of unaligned unsigned data in platform-specific byte ordering
1.48 + // (no special code is needed since x86 CPUs can access unaligned data)
1.49 + static inline u2 get_native_u2(address p) {
1.50 + if ((intptr_t)p & 0x1) {
1.51 + return ((u2)p[1] << 8) | (u2)p[0];
1.52 + } else {
1.53 + return *(u2*)p;
1.54 + }
1.55 + }
1.56 +
1.57 + static inline u4 get_native_u4(address p) {
1.58 + if ((intptr_t)p & 3) {
1.59 + u4 res;
1.60 + __asm__ __volatile__ (
1.61 + " .set push\n"
1.62 + " .set mips64\n"
1.63 + " .set noreorder\n"
1.64 +
1.65 + " lwr %[res], 0(%[addr]) \n"
1.66 + " lwl %[res], 3(%[addr]) \n"
1.67 +
1.68 + " .set pop"
1.69 + : [res] "=&r" (res)
1.70 + : [addr] "r" (p)
1.71 + : "memory"
1.72 + );
1.73 + return res;
1.74 + } else {
1.75 + return *(u4*)p;
1.76 + }
1.77 + }
1.78 +
1.79 + static inline u8 get_native_u8(address p) {
1.80 + u8 res;
1.81 + u8 temp;
1.82 + // u4 tp;//tmp register
1.83 + __asm__ __volatile__ (
1.84 + " .set push\n"
1.85 + " .set mips64\n"
1.86 + " .set noreorder\n"
1.87 + " .set noat\n"
1.88 + " andi $1,%[addr],0x7 \n"
1.89 + " beqz $1,1f \n"
1.90 + " nop \n"
1.91 + " ldr %[temp], 0(%[addr]) \n"
1.92 + " ldl %[temp], 7(%[addr]) \n"
1.93 + " b 2f \n"
1.94 + " nop \n"
1.95 + " 1:\t ld %[temp],0(%[addr]) \n"
1.96 + " 2:\t sd %[temp], %[res] \n"
1.97 +
1.98 + " .set at\n"
1.99 + " .set pop\n"
1.100 + : [addr]"=r"(p), [temp]"=r" (temp)
1.101 + : "[addr]"(p), "[temp]" (temp), [res]"m" (*(volatile jint*)&res)
1.102 + : "memory"
1.103 + );
1.104 +
1.105 + return res;
1.106 + }
1.107 + //use mips unaligned load instructions
1.108 + static inline void put_native_u2(address p, u2 x) {
1.109 + if((intptr_t)p & 0x1) {
1.110 + p[0] = (u_char)(x);
1.111 + p[1] = (u_char)(x>>8);
1.112 + } else {
1.113 + *(u2*)p = x;
1.114 + }
1.115 + }
1.116 + static inline void put_native_u4(address p, u4 x) {
1.117 + *(u4*)p = x;
1.118 + /* if ((int)p&3) {
1.119 + __asm__ __volatile__ (
1.120 + " .set push\n"
1.121 + " .set mips64\n"
1.122 + " .set noreorder\n"
1.123 +
1.124 + " swr %[x], 0(%[addr]) \n"
1.125 + " swl %[x], 3(%[addr]) \n"
1.126 +
1.127 + " .set pop"
1.128 + :
1.129 + : [addr] "r" (p), [x] "r" (x)
1.130 + : "memory"
1.131 + );
1.132 + } else {
1.133 + *(u4*)p = x;
1.134 + }*/
1.135 + }
1.136 + static inline void put_native_u8(address p, u8 x) {
1.137 + // u4 tp;//tmp register
1.138 + *(u8*)p = x;
1.139 + /*if ((int)p&7) {
1.140 +
1.141 + __asm__ __volatile__ (
1.142 + " .set push\n"
1.143 + " .set mips64\n"
1.144 + " .set noreorder\n"
1.145 + " .set noat\n"
1.146 + " sdr %[x], 0(%[addr]) \n"
1.147 + " sdl %[x], 7(%[addr]) \n"
1.148 +
1.149 + " .set at\n"
1.150 + " .set pop\n"
1.151 + :
1.152 + : [addr] "r" (p), [x]"r" (x)
1.153 + : "memory"
1.154 + );
1.155 + } else {
1.156 +
1.157 + *(u8*)p = x;
1.158 + }*/
1.159 +
1.160 + }
1.161 +
1.162 +
1.163 + // Efficient reading and writing of unaligned unsigned data in Java
1.164 + // byte ordering (i.e. big-endian ordering). Byte-order reversal is
1.165 + // needed since x86 CPUs use little-endian format.
1.166 + static inline u2 get_Java_u2(address p) { return swap_u2(get_native_u2(p)); }
1.167 + static inline u4 get_Java_u4(address p) { return swap_u4(get_native_u4(p)); }
1.168 + static inline u8 get_Java_u8(address p) { return swap_u8(get_native_u8(p)); }
1.169 +
1.170 + static inline void put_Java_u2(address p, u2 x) { put_native_u2(p, swap_u2(x)); }
1.171 + static inline void put_Java_u4(address p, u4 x) { put_native_u4(p, swap_u4(x)); }
1.172 + static inline void put_Java_u8(address p, u8 x) { put_native_u8(p, swap_u8(x)); }
1.173 +
1.174 +
1.175 + // Efficient swapping of byte ordering
1.176 + static inline u2 swap_u2(u2 x); // compiler-dependent implementation
1.177 + static inline u4 swap_u4(u4 x); // compiler-dependent implementation
1.178 + static inline u8 swap_u8(u8 x);
1.179 +};
1.180 +
1.181 +
1.182 +// The following header contains the implementations of swap_u2, swap_u4, and swap_u8[_base]
1.183 +#ifdef TARGET_OS_ARCH_linux_mips
1.184 +# include "bytes_linux_mips.inline.hpp"
1.185 +#endif
1.186 +#ifdef TARGET_OS_ARCH_solaris_mips
1.187 +# include "bytes_solaris_mips.inline.hpp"
1.188 +#endif
1.189 +#ifdef TARGET_OS_ARCH_windows_mips
1.190 +# include "bytes_windows_mips.inline.hpp"
1.191 +#endif
1.192 +#ifdef TARGET_OS_ARCH_bsd_mips
1.193 +# include "bytes_bsd_mips.inline.hpp"
1.194 +#endif
1.195 +
1.196 +
1.197 +#endif // CPU_MIPS_VM_BYTES_MIPS_HPP
1.198 +
