1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.2 +++ b/src/share/vm/c1/c1_LinearScan.hpp Wed Apr 27 01:25:04 2016 +0800 1.3 @@ -0,0 +1,990 @@ 1.4 +/* 1.5 + * Copyright (c) 2005, 2012, Oracle and/or its affiliates. All rights reserved. 1.6 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 1.7 + * 1.8 + * This code is free software; you can redistribute it and/or modify it 1.9 + * under the terms of the GNU General Public License version 2 only, as 1.10 + * published by the Free Software Foundation. 1.11 + * 1.12 + * This code is distributed in the hope that it will be useful, but WITHOUT 1.13 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1.14 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 1.15 + * version 2 for more details (a copy is included in the LICENSE file that 1.16 + * accompanied this code). 1.17 + * 1.18 + * You should have received a copy of the GNU General Public License version 1.19 + * 2 along with this work; if not, write to the Free Software Foundation, 1.20 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 1.21 + * 1.22 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 1.23 + * or visit www.oracle.com if you need additional information or have any 1.24 + * questions. 1.25 + * 1.26 + */ 1.27 + 1.28 +#ifndef SHARE_VM_C1_C1_LINEARSCAN_HPP 1.29 +#define SHARE_VM_C1_C1_LINEARSCAN_HPP 1.30 + 1.31 +#include "c1/c1_FpuStackSim.hpp" 1.32 +#include "c1/c1_FrameMap.hpp" 1.33 +#include "c1/c1_IR.hpp" 1.34 +#include "c1/c1_Instruction.hpp" 1.35 +#include "c1/c1_LIR.hpp" 1.36 +#include "c1/c1_LIRGenerator.hpp" 1.37 + 1.38 +class DebugInfoCache; 1.39 +class FpuStackAllocator; 1.40 +class IRScopeDebugInfo; 1.41 +class Interval; 1.42 +class IntervalWalker; 1.43 +class LIRGenerator; 1.44 +class LinearScan; 1.45 +class MoveResolver; 1.46 +class Range; 1.47 + 1.48 +define_array(IntervalArray, Interval*) 1.49 +define_stack(IntervalList, IntervalArray) 1.50 + 1.51 +define_array(IntervalsArray, IntervalList*) 1.52 +define_stack(IntervalsList, IntervalsArray) 1.53 + 1.54 +define_array(OopMapArray, OopMap*) 1.55 +define_stack(OopMapList, OopMapArray) 1.56 + 1.57 +define_array(ScopeValueArray, ScopeValue*) 1.58 + 1.59 +define_array(LIR_OpListArray, LIR_OpList*); 1.60 +define_stack(LIR_OpListStack, LIR_OpListArray); 1.61 + 1.62 + 1.63 +enum IntervalUseKind { 1.64 + // priority of use kinds must be ascending 1.65 + noUse = 0, 1.66 + loopEndMarker = 1, 1.67 + shouldHaveRegister = 2, 1.68 + mustHaveRegister = 3, 1.69 + 1.70 + firstValidKind = 1, 1.71 + lastValidKind = 3 1.72 +}; 1.73 +define_array(UseKindArray, IntervalUseKind) 1.74 +define_stack(UseKindStack, UseKindArray) 1.75 + 1.76 + 1.77 +enum IntervalKind { 1.78 + fixedKind = 0, // interval pre-colored by LIR_Generator 1.79 + anyKind = 1, // no register/memory allocated by LIR_Generator 1.80 + nofKinds, 1.81 + firstKind = fixedKind 1.82 +}; 1.83 + 1.84 + 1.85 +// during linear scan an interval is in one of four states in 1.86 +enum IntervalState { 1.87 + unhandledState = 0, // unhandled state (not processed yet) 1.88 + activeState = 1, // life and is in a physical register 1.89 + inactiveState = 2, // in a life time hole and is in a physical register 1.90 + handledState = 3, // spilled or not life again 1.91 + invalidState = -1 1.92 +}; 1.93 + 1.94 + 1.95 +enum IntervalSpillState { 1.96 + noDefinitionFound, // starting state of calculation: no definition found yet 1.97 + oneDefinitionFound, // one definition has already been found. 1.98 + // Note: two consecutive definitions are treated as one (e.g. consecutive move and add because of two-operand LIR form) 1.99 + // the position of this definition is stored in _definition_pos 1.100 + oneMoveInserted, // one spill move has already been inserted. 1.101 + storeAtDefinition, // the interval should be stored immediately after its definition because otherwise 1.102 + // there would be multiple redundant stores 1.103 + startInMemory, // the interval starts in memory (e.g. method parameter), so a store is never necessary 1.104 + noOptimization // the interval has more then one definition (e.g. resulting from phi moves), so stores to memory are not optimized 1.105 +}; 1.106 + 1.107 + 1.108 +#define for_each_interval_kind(kind) \ 1.109 + for (IntervalKind kind = firstKind; kind < nofKinds; kind = (IntervalKind)(kind + 1)) 1.110 + 1.111 +#define for_each_visitor_mode(mode) \ 1.112 + for (LIR_OpVisitState::OprMode mode = LIR_OpVisitState::firstMode; mode < LIR_OpVisitState::numModes; mode = (LIR_OpVisitState::OprMode)(mode + 1)) 1.113 + 1.114 + 1.115 +class LinearScan : public CompilationResourceObj { 1.116 + // declare classes used by LinearScan as friends because they 1.117 + // need a wide variety of functions declared here 1.118 + // 1.119 + // Only the small interface to the rest of the compiler is public 1.120 + friend class Interval; 1.121 + friend class IntervalWalker; 1.122 + friend class LinearScanWalker; 1.123 + friend class FpuStackAllocator; 1.124 + friend class MoveResolver; 1.125 + friend class LinearScanStatistic; 1.126 + friend class LinearScanTimers; 1.127 + friend class RegisterVerifier; 1.128 + 1.129 + public: 1.130 + enum { 1.131 + any_reg = -1, 1.132 + nof_cpu_regs = pd_nof_cpu_regs_linearscan, 1.133 + nof_fpu_regs = pd_nof_fpu_regs_linearscan, 1.134 + nof_xmm_regs = pd_nof_xmm_regs_linearscan, 1.135 + nof_regs = nof_cpu_regs + nof_fpu_regs + nof_xmm_regs 1.136 + }; 1.137 + 1.138 + private: 1.139 + Compilation* _compilation; 1.140 + IR* _ir; 1.141 + LIRGenerator* _gen; 1.142 + FrameMap* _frame_map; 1.143 + 1.144 + BlockList _cached_blocks; // cached list with all blocks in linear-scan order (only correct if original list keeps unchanged) 1.145 + int _num_virtual_regs; // number of virtual registers (without new registers introduced because of splitting intervals) 1.146 + bool _has_fpu_registers; // true if this method uses any floating point registers (and so fpu stack allocation is necessary) 1.147 + int _num_calls; // total number of calls in this method 1.148 + int _max_spills; // number of stack slots used for intervals allocated to memory 1.149 + int _unused_spill_slot; // unused spill slot for a single-word value because of alignment of a double-word value 1.150 + 1.151 + IntervalList _intervals; // mapping from register number to interval 1.152 + IntervalList* _new_intervals_from_allocation; // list with all intervals created during allocation when an existing interval is split 1.153 + IntervalArray* _sorted_intervals; // intervals sorted by Interval::from() 1.154 + bool _needs_full_resort; // set to true if an Interval::from() is changed and _sorted_intervals must be resorted 1.155 + 1.156 + LIR_OpArray _lir_ops; // mapping from LIR_Op id to LIR_Op node 1.157 + BlockBeginArray _block_of_op; // mapping from LIR_Op id to the BlockBegin containing this instruction 1.158 + BitMap _has_info; // bit set for each LIR_Op id that has a CodeEmitInfo 1.159 + BitMap _has_call; // bit set for each LIR_Op id that destroys all caller save registers 1.160 + BitMap2D _interval_in_loop; // bit set for each virtual register that is contained in each loop 1.161 + 1.162 + // cached debug info to prevent multiple creation of same object 1.163 + // TODO: cached scope values for registers could be static 1.164 + ScopeValueArray _scope_value_cache; 1.165 + 1.166 + static ConstantOopWriteValue* _oop_null_scope_value; 1.167 + static ConstantIntValue* _int_m1_scope_value; 1.168 + static ConstantIntValue* _int_0_scope_value; 1.169 + static ConstantIntValue* _int_1_scope_value; 1.170 + static ConstantIntValue* _int_2_scope_value; 1.171 + 1.172 + // accessors 1.173 + IR* ir() const { return _ir; } 1.174 + Compilation* compilation() const { return _compilation; } 1.175 + LIRGenerator* gen() const { return _gen; } 1.176 + FrameMap* frame_map() const { return _frame_map; } 1.177 + 1.178 + // unified bailout support 1.179 + void bailout(const char* msg) const { compilation()->bailout(msg); } 1.180 + bool bailed_out() const { return compilation()->bailed_out(); } 1.181 + 1.182 + // access to block list (sorted in linear scan order) 1.183 + int block_count() const { assert(_cached_blocks.length() == ir()->linear_scan_order()->length(), "invalid cached block list"); return _cached_blocks.length(); } 1.184 + BlockBegin* block_at(int idx) const { assert(_cached_blocks.at(idx) == ir()->linear_scan_order()->at(idx), "invalid cached block list"); return _cached_blocks.at(idx); } 1.185 + 1.186 + int num_virtual_regs() const { return _num_virtual_regs; } 1.187 + // size of live_in and live_out sets of BasicBlocks (BitMap needs rounded size for iteration) 1.188 + int live_set_size() const { return round_to(_num_virtual_regs, BitsPerWord); } 1.189 + bool has_fpu_registers() const { return _has_fpu_registers; } 1.190 + int num_loops() const { return ir()->num_loops(); } 1.191 + bool is_interval_in_loop(int interval, int loop) const { return _interval_in_loop.at(interval, loop); } 1.192 + 1.193 + // handling of fpu stack allocation (platform dependent, needed for debug information generation) 1.194 +#ifdef X86 1.195 + FpuStackAllocator* _fpu_stack_allocator; 1.196 + bool use_fpu_stack_allocation() const { return UseSSE < 2 && has_fpu_registers(); } 1.197 +#else 1.198 + bool use_fpu_stack_allocation() const { return false; } 1.199 +#endif 1.200 + 1.201 + 1.202 + // access to interval list 1.203 + int interval_count() const { return _intervals.length(); } 1.204 + Interval* interval_at(int reg_num) const { return _intervals.at(reg_num); } 1.205 + 1.206 + IntervalList* new_intervals_from_allocation() const { return _new_intervals_from_allocation; } 1.207 + 1.208 + // access to LIR_Ops and Blocks indexed by op_id 1.209 + int max_lir_op_id() const { assert(_lir_ops.length() > 0, "no operations"); return (_lir_ops.length() - 1) << 1; } 1.210 + LIR_Op* lir_op_with_id(int op_id) const { assert(op_id >= 0 && op_id <= max_lir_op_id() && op_id % 2 == 0, "op_id out of range or not even"); return _lir_ops.at(op_id >> 1); } 1.211 + BlockBegin* block_of_op_with_id(int op_id) const { assert(_block_of_op.length() > 0 && op_id >= 0 && op_id <= max_lir_op_id() + 1, "op_id out of range"); return _block_of_op.at(op_id >> 1); } 1.212 + 1.213 + bool is_block_begin(int op_id) { return op_id == 0 || block_of_op_with_id(op_id) != block_of_op_with_id(op_id - 1); } 1.214 + bool covers_block_begin(int op_id_1, int op_id_2) { return block_of_op_with_id(op_id_1) != block_of_op_with_id(op_id_2); } 1.215 + 1.216 + bool has_call(int op_id) { assert(op_id % 2 == 0, "must be even"); return _has_call.at(op_id >> 1); } 1.217 + bool has_info(int op_id) { assert(op_id % 2 == 0, "must be even"); return _has_info.at(op_id >> 1); } 1.218 + 1.219 + 1.220 + // functions for converting LIR-Operands to register numbers 1.221 + static bool is_valid_reg_num(int reg_num) { return reg_num >= 0; } 1.222 + static int reg_num(LIR_Opr opr); 1.223 + static int reg_numHi(LIR_Opr opr); 1.224 + 1.225 + // functions for classification of intervals 1.226 + static bool is_precolored_interval(const Interval* i); 1.227 + static bool is_virtual_interval(const Interval* i); 1.228 + 1.229 + static bool is_precolored_cpu_interval(const Interval* i); 1.230 + static bool is_virtual_cpu_interval(const Interval* i); 1.231 + static bool is_precolored_fpu_interval(const Interval* i); 1.232 + static bool is_virtual_fpu_interval(const Interval* i); 1.233 + 1.234 + static bool is_in_fpu_register(const Interval* i); 1.235 + static bool is_oop_interval(const Interval* i); 1.236 + 1.237 + 1.238 + // General helper functions 1.239 + int allocate_spill_slot(bool double_word); 1.240 + void assign_spill_slot(Interval* it); 1.241 + void propagate_spill_slots(); 1.242 + 1.243 + Interval* create_interval(int reg_num); 1.244 + void append_interval(Interval* it); 1.245 + void copy_register_flags(Interval* from, Interval* to); 1.246 + 1.247 + // platform dependent functions 1.248 + static bool is_processed_reg_num(int reg_num); 1.249 + static int num_physical_regs(BasicType type); 1.250 + static bool requires_adjacent_regs(BasicType type); 1.251 + static bool is_caller_save(int assigned_reg); 1.252 + 1.253 + // spill move optimization: eliminate moves from register to stack if 1.254 + // stack slot is known to be correct 1.255 + void change_spill_definition_pos(Interval* interval, int def_pos); 1.256 + void change_spill_state(Interval* interval, int spill_pos); 1.257 + static bool must_store_at_definition(const Interval* i); 1.258 + void eliminate_spill_moves(); 1.259 + 1.260 + // Phase 1: number all instructions in all blocks 1.261 + void number_instructions(); 1.262 + 1.263 + // Phase 2: compute local live sets separately for each block 1.264 + // (sets live_gen and live_kill for each block) 1.265 + // 1.266 + // helper methods used by compute_local_live_sets() 1.267 + void set_live_gen_kill(Value value, LIR_Op* op, BitMap& live_gen, BitMap& live_kill); 1.268 + 1.269 + void compute_local_live_sets(); 1.270 + 1.271 + // Phase 3: perform a backward dataflow analysis to compute global live sets 1.272 + // (sets live_in and live_out for each block) 1.273 + void compute_global_live_sets(); 1.274 + 1.275 + 1.276 + // Phase 4: build intervals 1.277 + // (fills the list _intervals) 1.278 + // 1.279 + // helper methods used by build_intervals() 1.280 + void add_use (Value value, int from, int to, IntervalUseKind use_kind); 1.281 + 1.282 + void add_def (LIR_Opr opr, int def_pos, IntervalUseKind use_kind); 1.283 + void add_use (LIR_Opr opr, int from, int to, IntervalUseKind use_kind); 1.284 + void add_temp(LIR_Opr opr, int temp_pos, IntervalUseKind use_kind); 1.285 + 1.286 + void add_def (int reg_num, int def_pos, IntervalUseKind use_kind, BasicType type); 1.287 + void add_use (int reg_num, int from, int to, IntervalUseKind use_kind, BasicType type); 1.288 + void add_temp(int reg_num, int temp_pos, IntervalUseKind use_kind, BasicType type); 1.289 + 1.290 + // Add platform dependent kills for particular LIR ops. Can be used 1.291 + // to add platform dependent behaviour for some operations. 1.292 + void pd_add_temps(LIR_Op* op); 1.293 + 1.294 + IntervalUseKind use_kind_of_output_operand(LIR_Op* op, LIR_Opr opr); 1.295 + IntervalUseKind use_kind_of_input_operand(LIR_Op* op, LIR_Opr opr); 1.296 + void handle_method_arguments(LIR_Op* op); 1.297 + void handle_doubleword_moves(LIR_Op* op); 1.298 + void add_register_hints(LIR_Op* op); 1.299 + 1.300 + void build_intervals(); 1.301 + 1.302 + 1.303 + // Phase 5: actual register allocation 1.304 + // (Uses LinearScanWalker) 1.305 + // 1.306 + // helper functions for building a sorted list of intervals 1.307 + NOT_PRODUCT(bool is_sorted(IntervalArray* intervals);) 1.308 + static int interval_cmp(Interval** a, Interval** b); 1.309 + void add_to_list(Interval** first, Interval** prev, Interval* interval); 1.310 + void create_unhandled_lists(Interval** list1, Interval** list2, bool (is_list1)(const Interval* i), bool (is_list2)(const Interval* i)); 1.311 + 1.312 + void sort_intervals_before_allocation(); 1.313 + void sort_intervals_after_allocation(); 1.314 + void allocate_registers(); 1.315 + 1.316 + 1.317 + // Phase 6: resolve data flow 1.318 + // (insert moves at edges between blocks if intervals have been split) 1.319 + // 1.320 + // helper functions for resolve_data_flow() 1.321 + Interval* split_child_at_op_id(Interval* interval, int op_id, LIR_OpVisitState::OprMode mode); 1.322 + Interval* interval_at_block_begin(BlockBegin* block, int reg_num); 1.323 + Interval* interval_at_block_end(BlockBegin* block, int reg_num); 1.324 + Interval* interval_at_op_id(int reg_num, int op_id); 1.325 + void resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver); 1.326 + void resolve_find_insert_pos(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver); 1.327 + void resolve_data_flow(); 1.328 + 1.329 + void resolve_exception_entry(BlockBegin* block, int reg_num, MoveResolver &move_resolver); 1.330 + void resolve_exception_entry(BlockBegin* block, MoveResolver &move_resolver); 1.331 + void resolve_exception_edge(XHandler* handler, int throwing_op_id, int reg_num, Phi* phi, MoveResolver &move_resolver); 1.332 + void resolve_exception_edge(XHandler* handler, int throwing_op_id, MoveResolver &move_resolver); 1.333 + void resolve_exception_handlers(); 1.334 + 1.335 + // Phase 7: assign register numbers back to LIR 1.336 + // (includes computation of debug information and oop maps) 1.337 + // 1.338 + // helper functions for assign_reg_num() 1.339 + VMReg vm_reg_for_interval(Interval* interval); 1.340 + VMReg vm_reg_for_operand(LIR_Opr opr); 1.341 + 1.342 + static LIR_Opr operand_for_interval(Interval* interval); 1.343 + static LIR_Opr calc_operand_for_interval(const Interval* interval); 1.344 + LIR_Opr canonical_spill_opr(Interval* interval); 1.345 + 1.346 + LIR_Opr color_lir_opr(LIR_Opr opr, int id, LIR_OpVisitState::OprMode); 1.347 + 1.348 + // methods used for oop map computation 1.349 + IntervalWalker* init_compute_oop_maps(); 1.350 + OopMap* compute_oop_map(IntervalWalker* iw, LIR_Op* op, CodeEmitInfo* info, bool is_call_site); 1.351 + void compute_oop_map(IntervalWalker* iw, const LIR_OpVisitState &visitor, LIR_Op* op); 1.352 + 1.353 + // methods used for debug information computation 1.354 + void init_compute_debug_info(); 1.355 + 1.356 + MonitorValue* location_for_monitor_index(int monitor_index); 1.357 + LocationValue* location_for_name(int name, Location::Type loc_type); 1.358 + void set_oop(OopMap* map, VMReg name) { 1.359 + if (map->legal_vm_reg_name(name)) { 1.360 + map->set_oop(name); 1.361 + } else { 1.362 + bailout("illegal oopMap register name"); 1.363 + } 1.364 + } 1.365 + 1.366 + int append_scope_value_for_constant(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values); 1.367 + int append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values); 1.368 + int append_scope_value(int op_id, Value value, GrowableArray<ScopeValue*>* scope_values); 1.369 + 1.370 + IRScopeDebugInfo* compute_debug_info_for_scope(int op_id, IRScope* cur_scope, ValueStack* cur_state, ValueStack* innermost_state); 1.371 + void compute_debug_info(CodeEmitInfo* info, int op_id); 1.372 + 1.373 + void assign_reg_num(LIR_OpList* instructions, IntervalWalker* iw); 1.374 + void assign_reg_num(); 1.375 + 1.376 + 1.377 + // Phase 8: fpu stack allocation 1.378 + // (Used only on x86 when fpu operands are present) 1.379 + void allocate_fpu_stack(); 1.380 + 1.381 + 1.382 + // helper functions for printing state 1.383 +#ifndef PRODUCT 1.384 + static void print_bitmap(BitMap& bitmap); 1.385 + void print_intervals(const char* label); 1.386 + void print_lir(int level, const char* label, bool hir_valid = true); 1.387 +#endif 1.388 + 1.389 +#ifdef ASSERT 1.390 + // verification functions for allocation 1.391 + // (check that all intervals have a correct register and that no registers are overwritten) 1.392 + void verify(); 1.393 + void verify_intervals(); 1.394 + void verify_no_oops_in_fixed_intervals(); 1.395 + void verify_constants(); 1.396 + void verify_registers(); 1.397 +#endif 1.398 + 1.399 + public: 1.400 + // creation 1.401 + LinearScan(IR* ir, LIRGenerator* gen, FrameMap* frame_map); 1.402 + 1.403 + // main entry function: perform linear scan register allocation 1.404 + void do_linear_scan(); 1.405 + 1.406 + // accessors used by Compilation 1.407 + int max_spills() const { return _max_spills; } 1.408 + int num_calls() const { assert(_num_calls >= 0, "not set"); return _num_calls; } 1.409 + 1.410 + // entry functions for printing 1.411 +#ifndef PRODUCT 1.412 + static void print_statistics(); 1.413 + static void print_timers(double total); 1.414 +#endif 1.415 +}; 1.416 + 1.417 + 1.418 +// Helper class for ordering moves that are inserted at the same position in the LIR 1.419 +// When moves between registers are inserted, it is important that the moves are 1.420 +// ordered such that no register is overwritten. So moves from register to stack 1.421 +// are processed prior to moves from stack to register. When moves have circular 1.422 +// dependencies, a temporary stack slot is used to break the circle. 1.423 +// The same logic is used in the LinearScanWalker and in LinearScan during resolve_data_flow 1.424 +// and therefore factored out in a separate class 1.425 +class MoveResolver: public StackObj { 1.426 + private: 1.427 + LinearScan* _allocator; 1.428 + 1.429 + LIR_List* _insert_list; 1.430 + int _insert_idx; 1.431 + LIR_InsertionBuffer _insertion_buffer; // buffer where moves are inserted 1.432 + 1.433 + IntervalList _mapping_from; 1.434 + LIR_OprList _mapping_from_opr; 1.435 + IntervalList _mapping_to; 1.436 + bool _multiple_reads_allowed; 1.437 + int _register_blocked[LinearScan::nof_regs]; 1.438 + 1.439 + int register_blocked(int reg) { assert(reg >= 0 && reg < LinearScan::nof_regs, "out of bounds"); return _register_blocked[reg]; } 1.440 + void set_register_blocked(int reg, int direction) { assert(reg >= 0 && reg < LinearScan::nof_regs, "out of bounds"); assert(direction == 1 || direction == -1, "out of bounds"); _register_blocked[reg] += direction; } 1.441 + 1.442 + void block_registers(Interval* it); 1.443 + void unblock_registers(Interval* it); 1.444 + bool save_to_process_move(Interval* from, Interval* to); 1.445 + 1.446 + void create_insertion_buffer(LIR_List* list); 1.447 + void append_insertion_buffer(); 1.448 + void insert_move(Interval* from_interval, Interval* to_interval); 1.449 + void insert_move(LIR_Opr from_opr, Interval* to_interval); 1.450 + 1.451 + DEBUG_ONLY(void verify_before_resolve();) 1.452 + void resolve_mappings(); 1.453 + public: 1.454 + MoveResolver(LinearScan* allocator); 1.455 + 1.456 + DEBUG_ONLY(void check_empty();) 1.457 + void set_multiple_reads_allowed() { _multiple_reads_allowed = true; } 1.458 + void set_insert_position(LIR_List* insert_list, int insert_idx); 1.459 + void move_insert_position(LIR_List* insert_list, int insert_idx); 1.460 + void add_mapping(Interval* from, Interval* to); 1.461 + void add_mapping(LIR_Opr from, Interval* to); 1.462 + void resolve_and_append_moves(); 1.463 + 1.464 + LinearScan* allocator() { return _allocator; } 1.465 + bool has_mappings() { return _mapping_from.length() > 0; } 1.466 +}; 1.467 + 1.468 + 1.469 +class Range : public CompilationResourceObj { 1.470 + friend class Interval; 1.471 + 1.472 + private: 1.473 + static Range* _end; // sentinel (from == to == max_jint) 1.474 + 1.475 + int _from; // from (inclusive) 1.476 + int _to; // to (exclusive) 1.477 + Range* _next; // linear list of Ranges 1.478 + 1.479 + // used only by class Interval, so hide them 1.480 + bool intersects(Range* r) const { return intersects_at(r) != -1; } 1.481 + int intersects_at(Range* r) const; 1.482 + 1.483 + public: 1.484 + Range(int from, int to, Range* next); 1.485 + 1.486 + static void initialize(Arena* arena); 1.487 + static Range* end() { return _end; } 1.488 + 1.489 + int from() const { return _from; } 1.490 + int to() const { return _to; } 1.491 + Range* next() const { return _next; } 1.492 + void set_from(int from) { _from = from; } 1.493 + void set_to(int to) { _to = to; } 1.494 + void set_next(Range* next) { _next = next; } 1.495 + 1.496 + // for testing 1.497 + void print(outputStream* out = tty) const PRODUCT_RETURN; 1.498 +}; 1.499 + 1.500 + 1.501 +// Interval is an ordered list of disjoint ranges. 1.502 + 1.503 +// For pre-colored double word LIR_Oprs, one interval is created for 1.504 +// the low word register and one is created for the hi word register. 1.505 +// On Intel for FPU double registers only one interval is created. At 1.506 +// all times assigned_reg contains the reg. number of the physical 1.507 +// register. 1.508 + 1.509 +// For LIR_Opr in virtual registers a single interval can represent 1.510 +// single and double word values. When a physical register is 1.511 +// assigned to the interval, assigned_reg contains the 1.512 +// phys. reg. number and for double word values assigned_regHi the 1.513 +// phys. reg. number of the hi word if there is any. For spilled 1.514 +// intervals assigned_reg contains the stack index. assigned_regHi is 1.515 +// always -1. 1.516 + 1.517 +class Interval : public CompilationResourceObj { 1.518 + private: 1.519 + static Interval* _end; // sentinel (interval with only range Range::end()) 1.520 + 1.521 + int _reg_num; 1.522 + BasicType _type; // valid only for virtual registers 1.523 + Range* _first; // sorted list of Ranges 1.524 + intStack _use_pos_and_kinds; // sorted list of use-positions and their according use-kinds 1.525 + 1.526 + Range* _current; // interval iteration: the current Range 1.527 + Interval* _next; // interval iteration: sorted list of Intervals (ends with sentinel) 1.528 + IntervalState _state; // interval iteration: to which set belongs this interval 1.529 + 1.530 + 1.531 + int _assigned_reg; 1.532 + int _assigned_regHi; 1.533 + 1.534 + int _cached_to; // cached value: to of last range (-1: not cached) 1.535 + LIR_Opr _cached_opr; 1.536 + VMReg _cached_vm_reg; 1.537 + 1.538 + Interval* _split_parent; // the original interval where this interval is derived from 1.539 + IntervalList _split_children; // list of all intervals that are split off from this interval (only available for split parents) 1.540 + Interval* _current_split_child; // the current split child that has been active or inactive last (always stored in split parents) 1.541 + 1.542 + int _canonical_spill_slot; // the stack slot where all split parts of this interval are spilled to (always stored in split parents) 1.543 + bool _insert_move_when_activated; // true if move is inserted between _current_split_child and this interval when interval gets active the first time 1.544 + IntervalSpillState _spill_state; // for spill move optimization 1.545 + int _spill_definition_pos; // position where the interval is defined (if defined only once) 1.546 + Interval* _register_hint; // this interval should be in the same register as the hint interval 1.547 + 1.548 + int calc_to(); 1.549 + Interval* new_split_child(); 1.550 + public: 1.551 + Interval(int reg_num); 1.552 + 1.553 + static void initialize(Arena* arena); 1.554 + static Interval* end() { return _end; } 1.555 + 1.556 + // accessors 1.557 + int reg_num() const { return _reg_num; } 1.558 + void set_reg_num(int r) { assert(_reg_num == -1, "cannot change reg_num"); _reg_num = r; } 1.559 + BasicType type() const { assert(_reg_num == -1 || _reg_num >= LIR_OprDesc::vreg_base, "cannot access type for fixed interval"); return _type; } 1.560 + void set_type(BasicType type) { assert(_reg_num < LIR_OprDesc::vreg_base || _type == T_ILLEGAL || _type == type, "overwriting existing type"); _type = type; } 1.561 + 1.562 + Range* first() const { return _first; } 1.563 + int from() const { return _first->from(); } 1.564 + int to() { if (_cached_to == -1) _cached_to = calc_to(); assert(_cached_to == calc_to(), "invalid cached value"); return _cached_to; } 1.565 + int num_use_positions() const { return _use_pos_and_kinds.length() / 2; } 1.566 + 1.567 + Interval* next() const { return _next; } 1.568 + Interval** next_addr() { return &_next; } 1.569 + void set_next(Interval* next) { _next = next; } 1.570 + 1.571 + int assigned_reg() const { return _assigned_reg; } 1.572 + int assigned_regHi() const { return _assigned_regHi; } 1.573 + void assign_reg(int reg) { _assigned_reg = reg; _assigned_regHi = LinearScan::any_reg; } 1.574 + void assign_reg(int reg,int regHi) { _assigned_reg = reg; _assigned_regHi = regHi; } 1.575 + 1.576 + Interval* register_hint(bool search_split_child = true) const; // calculation needed 1.577 + void set_register_hint(Interval* i) { _register_hint = i; } 1.578 + 1.579 + int state() const { return _state; } 1.580 + void set_state(IntervalState s) { _state = s; } 1.581 + 1.582 + // access to split parent and split children 1.583 + bool is_split_parent() const { return _split_parent == this; } 1.584 + bool is_split_child() const { return _split_parent != this; } 1.585 + Interval* split_parent() const { assert(_split_parent->is_split_parent(), "must be"); return _split_parent; } 1.586 + Interval* split_child_at_op_id(int op_id, LIR_OpVisitState::OprMode mode); 1.587 + Interval* split_child_before_op_id(int op_id); 1.588 + bool split_child_covers(int op_id, LIR_OpVisitState::OprMode mode); 1.589 + DEBUG_ONLY(void check_split_children();) 1.590 + 1.591 + // information stored in split parent, but available for all children 1.592 + int canonical_spill_slot() const { return split_parent()->_canonical_spill_slot; } 1.593 + void set_canonical_spill_slot(int slot) { assert(split_parent()->_canonical_spill_slot == -1, "overwriting existing value"); split_parent()->_canonical_spill_slot = slot; } 1.594 + Interval* current_split_child() const { return split_parent()->_current_split_child; } 1.595 + void make_current_split_child() { split_parent()->_current_split_child = this; } 1.596 + 1.597 + bool insert_move_when_activated() const { return _insert_move_when_activated; } 1.598 + void set_insert_move_when_activated(bool b) { _insert_move_when_activated = b; } 1.599 + 1.600 + // for spill optimization 1.601 + IntervalSpillState spill_state() const { return split_parent()->_spill_state; } 1.602 + int spill_definition_pos() const { return split_parent()->_spill_definition_pos; } 1.603 + void set_spill_state(IntervalSpillState state) { assert(state >= spill_state(), "state cannot decrease"); split_parent()->_spill_state = state; } 1.604 + void set_spill_definition_pos(int pos) { assert(spill_definition_pos() == -1, "cannot set the position twice"); split_parent()->_spill_definition_pos = pos; } 1.605 + // returns true if this interval has a shadow copy on the stack that is always correct 1.606 + bool always_in_memory() const { return split_parent()->_spill_state == storeAtDefinition || split_parent()->_spill_state == startInMemory; } 1.607 + 1.608 + // caching of values that take time to compute and are used multiple times 1.609 + LIR_Opr cached_opr() const { return _cached_opr; } 1.610 + VMReg cached_vm_reg() const { return _cached_vm_reg; } 1.611 + void set_cached_opr(LIR_Opr opr) { _cached_opr = opr; } 1.612 + void set_cached_vm_reg(VMReg reg) { _cached_vm_reg = reg; } 1.613 + 1.614 + // access to use positions 1.615 + int first_usage(IntervalUseKind min_use_kind) const; // id of the first operation requiring this interval in a register 1.616 + int next_usage(IntervalUseKind min_use_kind, int from) const; // id of next usage seen from the given position 1.617 + int next_usage_exact(IntervalUseKind exact_use_kind, int from) const; 1.618 + int previous_usage(IntervalUseKind min_use_kind, int from) const; 1.619 + 1.620 + // manipulating intervals 1.621 + void add_use_pos(int pos, IntervalUseKind use_kind); 1.622 + void add_range(int from, int to); 1.623 + Interval* split(int split_pos); 1.624 + Interval* split_from_start(int split_pos); 1.625 + void remove_first_use_pos() { _use_pos_and_kinds.truncate(_use_pos_and_kinds.length() - 2); } 1.626 + 1.627 + // test intersection 1.628 + bool covers(int op_id, LIR_OpVisitState::OprMode mode) const; 1.629 + bool has_hole_between(int from, int to); 1.630 + bool intersects(Interval* i) const { return _first->intersects(i->_first); } 1.631 + int intersects_at(Interval* i) const { return _first->intersects_at(i->_first); } 1.632 + 1.633 + // range iteration 1.634 + void rewind_range() { _current = _first; } 1.635 + void next_range() { assert(this != _end, "not allowed on sentinel"); _current = _current->next(); } 1.636 + int current_from() const { return _current->from(); } 1.637 + int current_to() const { return _current->to(); } 1.638 + bool current_at_end() const { return _current == Range::end(); } 1.639 + bool current_intersects(Interval* it) { return _current->intersects(it->_current); }; 1.640 + int current_intersects_at(Interval* it) { return _current->intersects_at(it->_current); }; 1.641 + 1.642 + // printing 1.643 + void print(outputStream* out = tty) const PRODUCT_RETURN; 1.644 +}; 1.645 + 1.646 + 1.647 +class IntervalWalker : public CompilationResourceObj { 1.648 + protected: 1.649 + Compilation* _compilation; 1.650 + LinearScan* _allocator; 1.651 + 1.652 + Interval* _unhandled_first[nofKinds]; // sorted list of intervals, not life before the current position 1.653 + Interval* _active_first [nofKinds]; // sorted list of intervals, life at the current position 1.654 + Interval* _inactive_first [nofKinds]; // sorted list of intervals, intervals in a life time hole at the current position 1.655 + 1.656 + Interval* _current; // the current interval coming from unhandled list 1.657 + int _current_position; // the current position (intercept point through the intervals) 1.658 + IntervalKind _current_kind; // and whether it is fixed_kind or any_kind. 1.659 + 1.660 + 1.661 + Compilation* compilation() const { return _compilation; } 1.662 + LinearScan* allocator() const { return _allocator; } 1.663 + 1.664 + // unified bailout support 1.665 + void bailout(const char* msg) const { compilation()->bailout(msg); } 1.666 + bool bailed_out() const { return compilation()->bailed_out(); } 1.667 + 1.668 + void check_bounds(IntervalKind kind) { assert(kind >= fixedKind && kind <= anyKind, "invalid interval_kind"); } 1.669 + 1.670 + Interval** unhandled_first_addr(IntervalKind kind) { check_bounds(kind); return &_unhandled_first[kind]; } 1.671 + Interval** active_first_addr(IntervalKind kind) { check_bounds(kind); return &_active_first[kind]; } 1.672 + Interval** inactive_first_addr(IntervalKind kind) { check_bounds(kind); return &_inactive_first[kind]; } 1.673 + 1.674 + void append_unsorted(Interval** first, Interval* interval); 1.675 + void append_sorted(Interval** first, Interval* interval); 1.676 + void append_to_unhandled(Interval** list, Interval* interval); 1.677 + 1.678 + bool remove_from_list(Interval** list, Interval* i); 1.679 + void remove_from_list(Interval* i); 1.680 + 1.681 + void next_interval(); 1.682 + Interval* current() const { return _current; } 1.683 + IntervalKind current_kind() const { return _current_kind; } 1.684 + 1.685 + void walk_to(IntervalState state, int from); 1.686 + 1.687 + // activate_current() is called when an unhandled interval becomes active (in current(), current_kind()). 1.688 + // Return false if current() should not be moved the the active interval list. 1.689 + // It is safe to append current to any interval list but the unhandled list. 1.690 + virtual bool activate_current() { return true; } 1.691 + 1.692 + // interval_moved() is called whenever an interval moves from one interval list to another. 1.693 + // In the implementation of this method it is prohibited to move the interval to any list. 1.694 + virtual void interval_moved(Interval* interval, IntervalKind kind, IntervalState from, IntervalState to); 1.695 + 1.696 + public: 1.697 + IntervalWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first); 1.698 + 1.699 + Interval* unhandled_first(IntervalKind kind) { check_bounds(kind); return _unhandled_first[kind]; } 1.700 + Interval* active_first(IntervalKind kind) { check_bounds(kind); return _active_first[kind]; } 1.701 + Interval* inactive_first(IntervalKind kind) { check_bounds(kind); return _inactive_first[kind]; } 1.702 + 1.703 + // active contains the intervals that are live after the lir_op 1.704 + void walk_to(int lir_op_id); 1.705 + // active contains the intervals that are live before the lir_op 1.706 + void walk_before(int lir_op_id) { walk_to(lir_op_id-1); } 1.707 + // walk through all intervals 1.708 + void walk() { walk_to(max_jint); } 1.709 + 1.710 + int current_position() { return _current_position; } 1.711 +}; 1.712 + 1.713 + 1.714 +// The actual linear scan register allocator 1.715 +class LinearScanWalker : public IntervalWalker { 1.716 + enum { 1.717 + any_reg = LinearScan::any_reg 1.718 + }; 1.719 + 1.720 + private: 1.721 + int _first_reg; // the reg. number of the first phys. register 1.722 + int _last_reg; // the reg. nmber of the last phys. register 1.723 + int _num_phys_regs; // required by current interval 1.724 + bool _adjacent_regs; // have lo/hi words of phys. regs be adjacent 1.725 + 1.726 + int _use_pos[LinearScan::nof_regs]; 1.727 + int _block_pos[LinearScan::nof_regs]; 1.728 + IntervalList* _spill_intervals[LinearScan::nof_regs]; 1.729 + 1.730 + MoveResolver _move_resolver; // for ordering spill moves 1.731 + 1.732 + // accessors mapped to same functions in class LinearScan 1.733 + int block_count() const { return allocator()->block_count(); } 1.734 + BlockBegin* block_at(int idx) const { return allocator()->block_at(idx); } 1.735 + BlockBegin* block_of_op_with_id(int op_id) const { return allocator()->block_of_op_with_id(op_id); } 1.736 + 1.737 + void init_use_lists(bool only_process_use_pos); 1.738 + void exclude_from_use(int reg); 1.739 + void exclude_from_use(Interval* i); 1.740 + void set_use_pos(int reg, Interval* i, int use_pos, bool only_process_use_pos); 1.741 + void set_use_pos(Interval* i, int use_pos, bool only_process_use_pos); 1.742 + void set_block_pos(int reg, Interval* i, int block_pos); 1.743 + void set_block_pos(Interval* i, int block_pos); 1.744 + 1.745 + void free_exclude_active_fixed(); 1.746 + void free_exclude_active_any(); 1.747 + void free_collect_inactive_fixed(Interval* cur); 1.748 + void free_collect_inactive_any(Interval* cur); 1.749 + void free_collect_unhandled(IntervalKind kind, Interval* cur); 1.750 + void spill_exclude_active_fixed(); 1.751 + void spill_block_unhandled_fixed(Interval* cur); 1.752 + void spill_block_inactive_fixed(Interval* cur); 1.753 + void spill_collect_active_any(); 1.754 + void spill_collect_inactive_any(Interval* cur); 1.755 + 1.756 + void insert_move(int op_id, Interval* src_it, Interval* dst_it); 1.757 + int find_optimal_split_pos(BlockBegin* min_block, BlockBegin* max_block, int max_split_pos); 1.758 + int find_optimal_split_pos(Interval* it, int min_split_pos, int max_split_pos, bool do_loop_optimization); 1.759 + void split_before_usage(Interval* it, int min_split_pos, int max_split_pos); 1.760 + void split_for_spilling(Interval* it); 1.761 + void split_stack_interval(Interval* it); 1.762 + void split_when_partial_register_available(Interval* it, int register_available_until); 1.763 + void split_and_spill_interval(Interval* it); 1.764 + 1.765 + int find_free_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split); 1.766 + int find_free_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split); 1.767 + bool alloc_free_reg(Interval* cur); 1.768 + 1.769 + int find_locked_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split); 1.770 + int find_locked_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split); 1.771 + void split_and_spill_intersecting_intervals(int reg, int regHi); 1.772 + void alloc_locked_reg(Interval* cur); 1.773 + 1.774 + bool no_allocation_possible(Interval* cur); 1.775 + void update_phys_reg_range(bool requires_cpu_register); 1.776 + void init_vars_for_alloc(Interval* cur); 1.777 + bool pd_init_regs_for_alloc(Interval* cur); 1.778 + 1.779 + void combine_spilled_intervals(Interval* cur); 1.780 + bool is_move(LIR_Op* op, Interval* from, Interval* to); 1.781 + 1.782 + bool activate_current(); 1.783 + 1.784 + public: 1.785 + LinearScanWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first); 1.786 + 1.787 + // must be called when all intervals are allocated 1.788 + void finish_allocation() { _move_resolver.resolve_and_append_moves(); } 1.789 +}; 1.790 + 1.791 + 1.792 + 1.793 +/* 1.794 +When a block has more than one predecessor, and all predecessors end with 1.795 +the same sequence of move-instructions, than this moves can be placed once 1.796 +at the beginning of the block instead of multiple times in the predecessors. 1.797 + 1.798 +Similarly, when a block has more than one successor, then equal sequences of 1.799 +moves at the beginning of the successors can be placed once at the end of 1.800 +the block. But because the moves must be inserted before all branch 1.801 +instructions, this works only when there is exactly one conditional branch 1.802 +at the end of the block (because the moves must be inserted before all 1.803 +branches, but after all compares). 1.804 + 1.805 +This optimization affects all kind of moves (reg->reg, reg->stack and 1.806 +stack->reg). Because this optimization works best when a block contains only 1.807 +few moves, it has a huge impact on the number of blocks that are totally 1.808 +empty. 1.809 +*/ 1.810 +class EdgeMoveOptimizer : public StackObj { 1.811 + private: 1.812 + // the class maintains a list with all lir-instruction-list of the 1.813 + // successors (predecessors) and the current index into the lir-lists 1.814 + LIR_OpListStack _edge_instructions; 1.815 + intStack _edge_instructions_idx; 1.816 + 1.817 + void init_instructions(); 1.818 + void append_instructions(LIR_OpList* instructions, int instructions_idx); 1.819 + LIR_Op* instruction_at(int edge); 1.820 + void remove_cur_instruction(int edge, bool decrement_index); 1.821 + 1.822 + bool operations_different(LIR_Op* op1, LIR_Op* op2); 1.823 + 1.824 + void optimize_moves_at_block_end(BlockBegin* cur); 1.825 + void optimize_moves_at_block_begin(BlockBegin* cur); 1.826 + 1.827 + EdgeMoveOptimizer(); 1.828 + 1.829 + public: 1.830 + static void optimize(BlockList* code); 1.831 +}; 1.832 + 1.833 + 1.834 + 1.835 +class ControlFlowOptimizer : public StackObj { 1.836 + private: 1.837 + BlockList _original_preds; 1.838 + 1.839 + enum { 1.840 + ShortLoopSize = 5 1.841 + }; 1.842 + void reorder_short_loop(BlockList* code, BlockBegin* header_block, int header_idx); 1.843 + void reorder_short_loops(BlockList* code); 1.844 + 1.845 + bool can_delete_block(BlockBegin* cur); 1.846 + void substitute_branch_target(BlockBegin* cur, BlockBegin* target_from, BlockBegin* target_to); 1.847 + void delete_empty_blocks(BlockList* code); 1.848 + 1.849 + void delete_unnecessary_jumps(BlockList* code); 1.850 + void delete_jumps_to_return(BlockList* code); 1.851 + 1.852 + DEBUG_ONLY(void verify(BlockList* code);) 1.853 + 1.854 + ControlFlowOptimizer(); 1.855 + public: 1.856 + static void optimize(BlockList* code); 1.857 +}; 1.858 + 1.859 + 1.860 +#ifndef PRODUCT 1.861 + 1.862 +// Helper class for collecting statistics of LinearScan 1.863 +class LinearScanStatistic : public StackObj { 1.864 + public: 1.865 + enum Counter { 1.866 + // general counters 1.867 + counter_method, 1.868 + counter_fpu_method, 1.869 + counter_loop_method, 1.870 + counter_exception_method, 1.871 + counter_loop, 1.872 + counter_block, 1.873 + counter_loop_block, 1.874 + counter_exception_block, 1.875 + counter_interval, 1.876 + counter_fixed_interval, 1.877 + counter_range, 1.878 + counter_fixed_range, 1.879 + counter_use_pos, 1.880 + counter_fixed_use_pos, 1.881 + counter_spill_slots, 1.882 + blank_line_1, 1.883 + 1.884 + // counter for classes of lir instructions 1.885 + counter_instruction, 1.886 + counter_label, 1.887 + counter_entry, 1.888 + counter_return, 1.889 + counter_call, 1.890 + counter_move, 1.891 + counter_cmp, 1.892 + counter_cond_branch, 1.893 + counter_uncond_branch, 1.894 + counter_stub_branch, 1.895 + counter_alu, 1.896 + counter_alloc, 1.897 + counter_sync, 1.898 + counter_throw, 1.899 + counter_unwind, 1.900 + counter_typecheck, 1.901 + counter_fpu_stack, 1.902 + counter_misc_inst, 1.903 + counter_other_inst, 1.904 + blank_line_2, 1.905 + 1.906 + // counter for different types of moves 1.907 + counter_move_total, 1.908 + counter_move_reg_reg, 1.909 + counter_move_reg_stack, 1.910 + counter_move_stack_reg, 1.911 + counter_move_stack_stack, 1.912 + counter_move_reg_mem, 1.913 + counter_move_mem_reg, 1.914 + counter_move_const_any, 1.915 + 1.916 + number_of_counters, 1.917 + invalid_counter = -1 1.918 + }; 1.919 + 1.920 + private: 1.921 + int _counters_sum[number_of_counters]; 1.922 + int _counters_max[number_of_counters]; 1.923 + 1.924 + void inc_counter(Counter idx, int value = 1) { _counters_sum[idx] += value; } 1.925 + 1.926 + const char* counter_name(int counter_idx); 1.927 + Counter base_counter(int counter_idx); 1.928 + 1.929 + void sum_up(LinearScanStatistic &method_statistic); 1.930 + void collect(LinearScan* allocator); 1.931 + 1.932 + public: 1.933 + LinearScanStatistic(); 1.934 + void print(const char* title); 1.935 + static void compute(LinearScan* allocator, LinearScanStatistic &global_statistic); 1.936 +}; 1.937 + 1.938 + 1.939 +// Helper class for collecting compilation time of LinearScan 1.940 +class LinearScanTimers : public StackObj { 1.941 + public: 1.942 + enum Timer { 1.943 + timer_do_nothing, 1.944 + timer_number_instructions, 1.945 + timer_compute_local_live_sets, 1.946 + timer_compute_global_live_sets, 1.947 + timer_build_intervals, 1.948 + timer_sort_intervals_before, 1.949 + timer_allocate_registers, 1.950 + timer_resolve_data_flow, 1.951 + timer_sort_intervals_after, 1.952 + timer_eliminate_spill_moves, 1.953 + timer_assign_reg_num, 1.954 + timer_allocate_fpu_stack, 1.955 + timer_optimize_lir, 1.956 + 1.957 + number_of_timers 1.958 + }; 1.959 + 1.960 + private: 1.961 + elapsedTimer _timers[number_of_timers]; 1.962 + const char* timer_name(int idx); 1.963 + 1.964 + public: 1.965 + LinearScanTimers(); 1.966 + 1.967 + void begin_method(); // called for each method when register allocation starts 1.968 + void end_method(LinearScan* allocator); // called for each method when register allocation completed 1.969 + void print(double total_time); // called before termination of VM to print global summary 1.970 + 1.971 + elapsedTimer* timer(int idx) { return &(_timers[idx]); } 1.972 +}; 1.973 + 1.974 + 1.975 +#endif // ifndef PRODUCT 1.976 + 1.977 + 1.978 +// Pick up platform-dependent implementation details 1.979 +#ifdef TARGET_ARCH_x86 1.980 +# include "c1_LinearScan_x86.hpp" 1.981 +#endif 1.982 +#ifdef TARGET_ARCH_sparc 1.983 +# include "c1_LinearScan_sparc.hpp" 1.984 +#endif 1.985 +#ifdef TARGET_ARCH_arm 1.986 +# include "c1_LinearScan_arm.hpp" 1.987 +#endif 1.988 +#ifdef TARGET_ARCH_ppc 1.989 +# include "c1_LinearScan_ppc.hpp" 1.990 +#endif 1.991 + 1.992 + 1.993 +#endif // SHARE_VM_C1_C1_LINEARSCAN_HPP