src/cpu/mips/vm/mips_64.ad

changeset 333
f5c309d7d194
parent 332
0b618b424c57
child 334
5758cfd9147a
     1.1 --- a/src/cpu/mips/vm/mips_64.ad	Thu Feb 23 05:09:55 2017 -0500
     1.2 +++ b/src/cpu/mips/vm/mips_64.ad	Thu Feb 23 09:23:48 2017 -0500
     1.3 @@ -10801,6 +10801,20 @@
     1.4    ins_pipe( ialu_regI_regI );
     1.5  %}
     1.6  
     1.7 +instruct salL2I_Reg_imm(mRegI dst, mRegL src, immI8 shift) %{
     1.8 +  match(Set dst (LShiftI (ConvL2I src) shift));
     1.9 +
    1.10 +  format %{ "SHL    $dst, $src, $shift #@salL2I_Reg_imm" %}
    1.11 +  ins_encode %{
    1.12 +    Register src = $src$$Register;
    1.13 +    Register dst = $dst$$Register;
    1.14 +    int    shamt = $shift$$constant;
    1.15 +
    1.16 +    __ sll(dst, src, shamt);
    1.17 +  %}
    1.18 +  ins_pipe( ialu_regI_regI );
    1.19 +%}
    1.20 +
    1.21  instruct salI_Reg_imm_and_M65536(mRegI dst, mRegI src, immI_16 shift, immI_M65536 mask) %{
    1.22    match(Set dst (AndI (LShiftI src shift) mask));
    1.23  

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