src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp

changeset 9637
eef07cd490d4
parent 8604
04d83ba48607
parent 9614
bb44c0e88235
child 9852
70aa912cebe5
     1.1 --- a/src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp	Wed Jul 03 20:04:13 2019 +0800
     1.2 +++ b/src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp	Wed Jul 03 20:42:37 2019 +0800
     1.3 @@ -579,7 +579,7 @@
     1.4          __ and3(Rscratch, divisor - 1, Rscratch);
     1.5        }
     1.6        __ add(Rdividend, Rscratch, Rscratch);
     1.7 -      __ sra(Rscratch, log2_intptr(divisor), Rresult);
     1.8 +      __ sra(Rscratch, log2_int(divisor), Rresult);
     1.9        return;
    1.10      } else {
    1.11        if (divisor == 2) {

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