1.1 --- a/src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp Wed Jul 03 20:04:13 2019 +0800 1.2 +++ b/src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp Wed Jul 03 20:42:37 2019 +0800 1.3 @@ -579,7 +579,7 @@ 1.4 __ and3(Rscratch, divisor - 1, Rscratch); 1.5 } 1.6 __ add(Rdividend, Rscratch, Rscratch); 1.7 - __ sra(Rscratch, log2_intptr(divisor), Rresult); 1.8 + __ sra(Rscratch, log2_int(divisor), Rresult); 1.9 return; 1.10 } else { 1.11 if (divisor == 2) {