src/cpu/mips/vm/mips_64.ad

changeset 416
eda7ffa4af8b
parent 411
f0d5c13451a3
child 420
ac094d2819c2
     1.1 --- a/src/cpu/mips/vm/mips_64.ad	Tue Jul 04 09:57:19 2017 +0800
     1.2 +++ b/src/cpu/mips/vm/mips_64.ad	Wed Jul 12 21:30:15 2017 +0800
     1.3 @@ -3393,7 +3393,7 @@
     1.4          } else {
     1.5             __ move(T9, disp);   
     1.6             if( UseLoongsonISA ) {
     1.7 -              __ gslwxc1(src, as_Register(base), T9, 0);
     1.8 +              __ gsswxc1(src, as_Register(base), T9, 0);
     1.9             } else {
    1.10                __ daddu(AT, as_Register(base), T9); 
    1.11                __ swc1(src, AT, 0);

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