src/share/vm/opto/matcher.hpp

changeset 1934
e9ff18c4ace7
parent 1907
c18cbe5936b8
parent 1930
3657cb01ffc5
child 2269
ae065c367d93
     1.1 --- a/src/share/vm/opto/matcher.hpp	Tue Jun 01 11:48:33 2010 -0700
     1.2 +++ b/src/share/vm/opto/matcher.hpp	Wed Jun 02 22:45:42 2010 -0700
     1.3 @@ -352,6 +352,38 @@
     1.4    // registers?  True for Intel but false for most RISCs
     1.5    static const bool clone_shift_expressions;
     1.6  
     1.7 +  static bool narrow_oop_use_complex_address();
     1.8 +
     1.9 +  // Generate implicit null check for narrow oops if it can fold
    1.10 +  // into address expression (x64).
    1.11 +  //
    1.12 +  // [R12 + narrow_oop_reg<<3 + offset] // fold into address expression
    1.13 +  // NullCheck narrow_oop_reg
    1.14 +  //
    1.15 +  // When narrow oops can't fold into address expression (Sparc) and
    1.16 +  // base is not null use decode_not_null and normal implicit null check.
    1.17 +  // Note, decode_not_null node can be used here since it is referenced
    1.18 +  // only on non null path but it requires special handling, see
    1.19 +  // collect_null_checks():
    1.20 +  //
    1.21 +  // decode_not_null narrow_oop_reg, oop_reg // 'shift' and 'add base'
    1.22 +  // [oop_reg + offset]
    1.23 +  // NullCheck oop_reg
    1.24 +  //
    1.25 +  // With Zero base and when narrow oops can not fold into address
    1.26 +  // expression use normal implicit null check since only shift
    1.27 +  // is needed to decode narrow oop.
    1.28 +  //
    1.29 +  // decode narrow_oop_reg, oop_reg // only 'shift'
    1.30 +  // [oop_reg + offset]
    1.31 +  // NullCheck oop_reg
    1.32 +  //
    1.33 +  inline static bool gen_narrow_oop_implicit_null_checks() {
    1.34 +    return Universe::narrow_oop_use_implicit_null_checks() &&
    1.35 +           (narrow_oop_use_complex_address() ||
    1.36 +            Universe::narrow_oop_base() != NULL);
    1.37 +  }
    1.38 +
    1.39    // Is it better to copy float constants, or load them directly from memory?
    1.40    // Intel can load a float constant from a direct address, requiring no
    1.41    // extra registers.  Most RISCs will have to materialize an address into a

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