1.1 --- a/src/cpu/x86/vm/c1_FrameMap_x86.cpp Tue Aug 26 15:49:40 2008 -0700
1.2 +++ b/src/cpu/x86/vm/c1_FrameMap_x86.cpp Wed Aug 27 00:21:55 2008 -0700
1.3 @@ -39,10 +39,15 @@
1.4 opr = LIR_OprFact::address(new LIR_Address(rsp_opr, st_off, type));
1.5 } else if (r_1->is_Register()) {
1.6 Register reg = r_1->as_Register();
1.7 - if (r_2->is_Register()) {
1.8 + if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) {
1.9 Register reg2 = r_2->as_Register();
1.10 +#ifdef _LP64
1.11 + assert(reg2 == reg, "must be same register");
1.12 + opr = as_long_opr(reg);
1.13 +#else
1.14 opr = as_long_opr(reg2, reg);
1.15 - } else if (type == T_OBJECT) {
1.16 +#endif // _LP64
1.17 + } else if (type == T_OBJECT || type == T_ARRAY) {
1.18 opr = as_oop_opr(reg);
1.19 } else {
1.20 opr = as_opr(reg);
1.21 @@ -88,18 +93,39 @@
1.22 LIR_Opr FrameMap::rdx_oop_opr;
1.23 LIR_Opr FrameMap::rcx_oop_opr;
1.24
1.25 -LIR_Opr FrameMap::rax_rdx_long_opr;
1.26 -LIR_Opr FrameMap::rbx_rcx_long_opr;
1.27 +LIR_Opr FrameMap::long0_opr;
1.28 +LIR_Opr FrameMap::long1_opr;
1.29 LIR_Opr FrameMap::fpu0_float_opr;
1.30 LIR_Opr FrameMap::fpu0_double_opr;
1.31 LIR_Opr FrameMap::xmm0_float_opr;
1.32 LIR_Opr FrameMap::xmm0_double_opr;
1.33
1.34 +#ifdef _LP64
1.35 +
1.36 +LIR_Opr FrameMap::r8_opr;
1.37 +LIR_Opr FrameMap::r9_opr;
1.38 +LIR_Opr FrameMap::r10_opr;
1.39 +LIR_Opr FrameMap::r11_opr;
1.40 +LIR_Opr FrameMap::r12_opr;
1.41 +LIR_Opr FrameMap::r13_opr;
1.42 +LIR_Opr FrameMap::r14_opr;
1.43 +LIR_Opr FrameMap::r15_opr;
1.44 +
1.45 +// r10 and r15 can never contain oops since they aren't available to
1.46 +// the allocator
1.47 +LIR_Opr FrameMap::r8_oop_opr;
1.48 +LIR_Opr FrameMap::r9_oop_opr;
1.49 +LIR_Opr FrameMap::r11_oop_opr;
1.50 +LIR_Opr FrameMap::r12_oop_opr;
1.51 +LIR_Opr FrameMap::r13_oop_opr;
1.52 +LIR_Opr FrameMap::r14_oop_opr;
1.53 +#endif // _LP64
1.54 +
1.55 LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, };
1.56 LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, };
1.57 LIR_Opr FrameMap::_caller_save_xmm_regs[] = { 0, };
1.58
1.59 -XMMRegister FrameMap::_xmm_regs [8] = { 0, };
1.60 +XMMRegister FrameMap::_xmm_regs [] = { 0, };
1.61
1.62 XMMRegister FrameMap::nr2xmmreg(int rnr) {
1.63 assert(_init_done, "tables not initialized");
1.64 @@ -113,18 +139,39 @@
1.65 void FrameMap::init() {
1.66 if (_init_done) return;
1.67
1.68 - assert(nof_cpu_regs == 8, "wrong number of CPU registers");
1.69 - map_register(0, rsi); rsi_opr = LIR_OprFact::single_cpu(0); rsi_oop_opr = LIR_OprFact::single_cpu_oop(0);
1.70 - map_register(1, rdi); rdi_opr = LIR_OprFact::single_cpu(1); rdi_oop_opr = LIR_OprFact::single_cpu_oop(1);
1.71 - map_register(2, rbx); rbx_opr = LIR_OprFact::single_cpu(2); rbx_oop_opr = LIR_OprFact::single_cpu_oop(2);
1.72 - map_register(3, rax); rax_opr = LIR_OprFact::single_cpu(3); rax_oop_opr = LIR_OprFact::single_cpu_oop(3);
1.73 - map_register(4, rdx); rdx_opr = LIR_OprFact::single_cpu(4); rdx_oop_opr = LIR_OprFact::single_cpu_oop(4);
1.74 - map_register(5, rcx); rcx_opr = LIR_OprFact::single_cpu(5); rcx_oop_opr = LIR_OprFact::single_cpu_oop(5);
1.75 - map_register(6, rsp); rsp_opr = LIR_OprFact::single_cpu(6);
1.76 - map_register(7, rbp); rbp_opr = LIR_OprFact::single_cpu(7);
1.77 + assert(nof_cpu_regs == LP64_ONLY(16) NOT_LP64(8), "wrong number of CPU registers");
1.78 + map_register(0, rsi); rsi_opr = LIR_OprFact::single_cpu(0);
1.79 + map_register(1, rdi); rdi_opr = LIR_OprFact::single_cpu(1);
1.80 + map_register(2, rbx); rbx_opr = LIR_OprFact::single_cpu(2);
1.81 + map_register(3, rax); rax_opr = LIR_OprFact::single_cpu(3);
1.82 + map_register(4, rdx); rdx_opr = LIR_OprFact::single_cpu(4);
1.83 + map_register(5, rcx); rcx_opr = LIR_OprFact::single_cpu(5);
1.84
1.85 - rax_rdx_long_opr = LIR_OprFact::double_cpu(3 /*eax*/, 4 /*edx*/);
1.86 - rbx_rcx_long_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 5 /*ecx*/);
1.87 +#ifndef _LP64
1.88 + // The unallocatable registers are at the end
1.89 + map_register(6, rsp);
1.90 + map_register(7, rbp);
1.91 +#else
1.92 + map_register( 6, r8); r8_opr = LIR_OprFact::single_cpu(6);
1.93 + map_register( 7, r9); r9_opr = LIR_OprFact::single_cpu(7);
1.94 + map_register( 8, r11); r11_opr = LIR_OprFact::single_cpu(8);
1.95 + map_register( 9, r12); r12_opr = LIR_OprFact::single_cpu(9);
1.96 + map_register(10, r13); r13_opr = LIR_OprFact::single_cpu(10);
1.97 + map_register(11, r14); r14_opr = LIR_OprFact::single_cpu(11);
1.98 + // The unallocatable registers are at the end
1.99 + map_register(12, r10); r10_opr = LIR_OprFact::single_cpu(12);
1.100 + map_register(13, r15); r15_opr = LIR_OprFact::single_cpu(13);
1.101 + map_register(14, rsp);
1.102 + map_register(15, rbp);
1.103 +#endif // _LP64
1.104 +
1.105 +#ifdef _LP64
1.106 + long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 3 /*eax*/);
1.107 + long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 2 /*ebx*/);
1.108 +#else
1.109 + long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 4 /*edx*/);
1.110 + long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 5 /*ecx*/);
1.111 +#endif // _LP64
1.112 fpu0_float_opr = LIR_OprFact::single_fpu(0);
1.113 fpu0_double_opr = LIR_OprFact::double_fpu(0);
1.114 xmm0_float_opr = LIR_OprFact::single_xmm(0);
1.115 @@ -137,6 +184,15 @@
1.116 _caller_save_cpu_regs[4] = rdx_opr;
1.117 _caller_save_cpu_regs[5] = rcx_opr;
1.118
1.119 +#ifdef _LP64
1.120 + _caller_save_cpu_regs[6] = r8_opr;
1.121 + _caller_save_cpu_regs[7] = r9_opr;
1.122 + _caller_save_cpu_regs[8] = r11_opr;
1.123 + _caller_save_cpu_regs[9] = r12_opr;
1.124 + _caller_save_cpu_regs[10] = r13_opr;
1.125 + _caller_save_cpu_regs[11] = r14_opr;
1.126 +#endif // _LP64
1.127 +
1.128
1.129 _xmm_regs[0] = xmm0;
1.130 _xmm_regs[1] = xmm1;
1.131 @@ -147,18 +203,51 @@
1.132 _xmm_regs[6] = xmm6;
1.133 _xmm_regs[7] = xmm7;
1.134
1.135 +#ifdef _LP64
1.136 + _xmm_regs[8] = xmm8;
1.137 + _xmm_regs[9] = xmm9;
1.138 + _xmm_regs[10] = xmm10;
1.139 + _xmm_regs[11] = xmm11;
1.140 + _xmm_regs[12] = xmm12;
1.141 + _xmm_regs[13] = xmm13;
1.142 + _xmm_regs[14] = xmm14;
1.143 + _xmm_regs[15] = xmm15;
1.144 +#endif // _LP64
1.145 +
1.146 for (int i = 0; i < 8; i++) {
1.147 _caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i);
1.148 + }
1.149 +
1.150 + for (int i = 0; i < nof_caller_save_xmm_regs ; i++) {
1.151 _caller_save_xmm_regs[i] = LIR_OprFact::single_xmm(i);
1.152 }
1.153
1.154 _init_done = true;
1.155
1.156 + rsi_oop_opr = as_oop_opr(rsi);
1.157 + rdi_oop_opr = as_oop_opr(rdi);
1.158 + rbx_oop_opr = as_oop_opr(rbx);
1.159 + rax_oop_opr = as_oop_opr(rax);
1.160 + rdx_oop_opr = as_oop_opr(rdx);
1.161 + rcx_oop_opr = as_oop_opr(rcx);
1.162 +
1.163 + rsp_opr = as_pointer_opr(rsp);
1.164 + rbp_opr = as_pointer_opr(rbp);
1.165 +
1.166 +#ifdef _LP64
1.167 + r8_oop_opr = as_oop_opr(r8);
1.168 + r9_oop_opr = as_oop_opr(r9);
1.169 + r11_oop_opr = as_oop_opr(r11);
1.170 + r12_oop_opr = as_oop_opr(r12);
1.171 + r13_oop_opr = as_oop_opr(r13);
1.172 + r14_oop_opr = as_oop_opr(r14);
1.173 +#endif // _LP64
1.174 +
1.175 VMRegPair regs;
1.176 BasicType sig_bt = T_OBJECT;
1.177 SharedRuntime::java_calling_convention(&sig_bt, ®s, 1, true);
1.178 receiver_opr = as_oop_opr(regs.first()->as_Register());
1.179 - assert(receiver_opr == rcx_oop_opr, "rcvr ought to be rcx");
1.180 +
1.181 }
1.182
1.183
