1.1 --- a/src/cpu/mips/vm/icache_mips.cpp Tue Mar 28 16:09:10 2017 -0400
1.2 +++ b/src/cpu/mips/vm/icache_mips.cpp Thu Mar 30 08:45:59 2017 -0400
1.3 @@ -40,18 +40,34 @@
1.4 void ICacheStubGenerator::generate_icache_flush(ICache::flush_icache_stub_t* flush_icache_stub) {};
1.5
1.6 void ICache::call_flush_stub(address start, int lines) {
1.7 - cacheflush(start, lines * line_size , ICACHE);
1.8 + //in fact, the current os implementation simply flush all ICACHE&DCACHE
1.9 +#ifndef CACHE_OPT
1.10 + /* Loongson3A supports automatic synchronization between Icache and Dcache.
1.11 + * No manual synchronization is needed. */
1.12 + cacheflush(start, lines * line_size , ICACHE);
1.13 +#endif
1.14 +// sysmips(3, 0, 0, 0);
1.15 }
1.16
1.17 void ICache::invalidate_word(address addr) {
1.18 - cacheflush(addr,4, ICACHE);
1.19 + //cacheflush(addr, 4, ICACHE);
1.20 +
1.21 +#ifndef CACHE_OPT
1.22 + cacheflush(addr,4, ICACHE);
1.23 +#endif
1.24 +// sysmips(3, 0, 0, 0);
1.25 }
1.26
1.27 void ICache::invalidate_range(address start, int nbytes) {
1.28 - cacheflush(start, nbytes, ICACHE);
1.29 +#ifndef CACHE_OPT
1.30 + cacheflush(start, nbytes, ICACHE);
1.31 +#endif
1.32 +// sysmips(3, 0, 0, 0);
1.33 }
1.34
1.35 void ICache::invalidate_all() {
1.36 - sysmips(3, 0, 0, 0);
1.37 +#ifndef CACHE_OPT
1.38 + sysmips(3, 0, 0, 0);
1.39 +#endif
1.40 }
1.41
