1.1 --- a/src/cpu/mips/vm/c1_LIRAssembler_mips.cpp Mon Jun 11 17:42:16 2018 +0800 1.2 +++ b/src/cpu/mips/vm/c1_LIRAssembler_mips.cpp Tue Jun 12 13:58:17 2018 +0800 1.3 @@ -297,15 +297,6 @@ 1.4 Register receiver = FrameMap::receiver_opr->as_register(); 1.5 Register ic_klass = IC_Klass; 1.6 1.7 - /*const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); 1.8 - const bool do_post_padding = VerifyOops || UseCompressedOops; 1.9 - if (!do_post_padding) { 1.10 - // insert some nops so that the verified entry point is aligned on CodeEntryAlignment 1.11 - while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) { 1.12 - __ nop(); 1.13 - } 1.14 - }*/ 1.15 - 1.16 int offset = __ offset(); 1.17 __ inline_cache_check(receiver, IC_Klass); 1.18 __ align(CodeEntryAlignment);