src/cpu/mips/vm/c1_LIRAssembler_mips.cpp

changeset 9144
cecfc245b19a
parent 9135
69fd39209afe
child 9145
ba534d861691
equal deleted inserted replaced
9143:239e32ede77d 9144:cecfc245b19a
294 294
295 295
296 int LIR_Assembler::check_icache() { 296 int LIR_Assembler::check_icache() {
297 Register receiver = FrameMap::receiver_opr->as_register(); 297 Register receiver = FrameMap::receiver_opr->as_register();
298 Register ic_klass = IC_Klass; 298 Register ic_klass = IC_Klass;
299
300 /*const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
301 const bool do_post_padding = VerifyOops || UseCompressedOops;
302 if (!do_post_padding) {
303 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
304 while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) {
305 __ nop();
306 }
307 }*/
308 299
309 int offset = __ offset(); 300 int offset = __ offset();
310 __ inline_cache_check(receiver, IC_Klass); 301 __ inline_cache_check(receiver, IC_Klass);
311 __ align(CodeEntryAlignment); 302 __ align(CodeEntryAlignment);
312 return offset; 303 return offset;

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