1.1 --- a/src/share/vm/opto/chaitin.cpp Thu Aug 15 11:59:19 2013 -0700
1.2 +++ b/src/share/vm/opto/chaitin.cpp Fri Aug 16 10:23:55 2013 +0200
1.3 @@ -40,10 +40,8 @@
1.4 #include "opto/opcodes.hpp"
1.5 #include "opto/rootnode.hpp"
1.6
1.7 -//=============================================================================
1.8 -
1.9 #ifndef PRODUCT
1.10 -void LRG::dump( ) const {
1.11 +void LRG::dump() const {
1.12 ttyLocker ttyl;
1.13 tty->print("%d ",num_regs());
1.14 _mask.dump();
1.15 @@ -94,7 +92,6 @@
1.16 }
1.17 #endif
1.18
1.19 -//------------------------------score------------------------------------------
1.20 // Compute score from cost and area. Low score is best to spill.
1.21 static double raw_score( double cost, double area ) {
1.22 return cost - (area*RegisterCostAreaRatio) * 1.52588e-5;
1.23 @@ -125,7 +122,6 @@
1.24 return score;
1.25 }
1.26
1.27 -//------------------------------LRG_List---------------------------------------
1.28 LRG_List::LRG_List( uint max ) : _cnt(max), _max(max), _lidxs(NEW_RESOURCE_ARRAY(uint,max)) {
1.29 memset( _lidxs, 0, sizeof(uint)*max );
1.30 }
1.31 @@ -211,7 +207,6 @@
1.32 return next;
1.33 }
1.34
1.35 -//------------------------------Chaitin----------------------------------------
1.36 PhaseChaitin::PhaseChaitin(uint unique, PhaseCFG &cfg, Matcher &matcher)
1.37 : PhaseRegAlloc(unique, cfg, matcher,
1.38 #ifndef PRODUCT
1.39 @@ -232,31 +227,31 @@
1.40 {
1.41 NOT_PRODUCT( Compile::TracePhase t3("ctorChaitin", &_t_ctorChaitin, TimeCompiler); )
1.42
1.43 - _high_frequency_lrg = MIN2(float(OPTO_LRG_HIGH_FREQ), _cfg._outer_loop_freq);
1.44 + _high_frequency_lrg = MIN2(float(OPTO_LRG_HIGH_FREQ), _cfg.get_outer_loop_frequency());
1.45
1.46 // Build a list of basic blocks, sorted by frequency
1.47 - _blks = NEW_RESOURCE_ARRAY( Block *, _cfg._num_blocks );
1.48 + _blks = NEW_RESOURCE_ARRAY(Block *, _cfg.number_of_blocks());
1.49 // Experiment with sorting strategies to speed compilation
1.50 double cutoff = BLOCK_FREQUENCY(1.0); // Cutoff for high frequency bucket
1.51 Block **buckets[NUMBUCKS]; // Array of buckets
1.52 uint buckcnt[NUMBUCKS]; // Array of bucket counters
1.53 double buckval[NUMBUCKS]; // Array of bucket value cutoffs
1.54 for (uint i = 0; i < NUMBUCKS; i++) {
1.55 - buckets[i] = NEW_RESOURCE_ARRAY(Block *, _cfg._num_blocks);
1.56 + buckets[i] = NEW_RESOURCE_ARRAY(Block *, _cfg.number_of_blocks());
1.57 buckcnt[i] = 0;
1.58 // Bump by three orders of magnitude each time
1.59 cutoff *= 0.001;
1.60 buckval[i] = cutoff;
1.61 - for (uint j = 0; j < _cfg._num_blocks; j++) {
1.62 + for (uint j = 0; j < _cfg.number_of_blocks(); j++) {
1.63 buckets[i][j] = NULL;
1.64 }
1.65 }
1.66 // Sort blocks into buckets
1.67 - for (uint i = 0; i < _cfg._num_blocks; i++) {
1.68 + for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
1.69 for (uint j = 0; j < NUMBUCKS; j++) {
1.70 - if ((j == NUMBUCKS - 1) || (_cfg._blocks[i]->_freq > buckval[j])) {
1.71 + if ((j == NUMBUCKS - 1) || (_cfg.get_block(i)->_freq > buckval[j])) {
1.72 // Assign block to end of list for appropriate bucket
1.73 - buckets[j][buckcnt[j]++] = _cfg._blocks[i];
1.74 + buckets[j][buckcnt[j]++] = _cfg.get_block(i);
1.75 break; // kick out of inner loop
1.76 }
1.77 }
1.78 @@ -269,10 +264,9 @@
1.79 }
1.80 }
1.81
1.82 - assert(blkcnt == _cfg._num_blocks, "Block array not totally filled");
1.83 + assert(blkcnt == _cfg.number_of_blocks(), "Block array not totally filled");
1.84 }
1.85
1.86 -//------------------------------Union------------------------------------------
1.87 // union 2 sets together.
1.88 void PhaseChaitin::Union( const Node *src_n, const Node *dst_n ) {
1.89 uint src = _lrg_map.find(src_n);
1.90 @@ -285,7 +279,6 @@
1.91 _lrg_map.uf_map(dst, src);
1.92 }
1.93
1.94 -//------------------------------new_lrg----------------------------------------
1.95 void PhaseChaitin::new_lrg(const Node *x, uint lrg) {
1.96 // Make the Node->LRG mapping
1.97 _lrg_map.extend(x->_idx,lrg);
1.98 @@ -311,7 +304,6 @@
1.99 return true;
1.100 }
1.101
1.102 -//------------------------------compact----------------------------------------
1.103 // Renumber the live ranges to compact them. Makes the IFG smaller.
1.104 void PhaseChaitin::compact() {
1.105 // Current the _uf_map contains a series of short chains which are headed
1.106 @@ -677,20 +669,19 @@
1.107 C->set_indexSet_arena(NULL); // ResourceArea is at end of scope
1.108 }
1.109
1.110 -//------------------------------de_ssa-----------------------------------------
1.111 void PhaseChaitin::de_ssa() {
1.112 // Set initial Names for all Nodes. Most Nodes get the virtual register
1.113 // number. A few get the ZERO live range number. These do not
1.114 // get allocated, but instead rely on correct scheduling to ensure that
1.115 // only one instance is simultaneously live at a time.
1.116 uint lr_counter = 1;
1.117 - for( uint i = 0; i < _cfg._num_blocks; i++ ) {
1.118 - Block *b = _cfg._blocks[i];
1.119 - uint cnt = b->_nodes.size();
1.120 + for( uint i = 0; i < _cfg.number_of_blocks(); i++ ) {
1.121 + Block* block = _cfg.get_block(i);
1.122 + uint cnt = block->_nodes.size();
1.123
1.124 // Handle all the normal Nodes in the block
1.125 for( uint j = 0; j < cnt; j++ ) {
1.126 - Node *n = b->_nodes[j];
1.127 + Node *n = block->_nodes[j];
1.128 // Pre-color to the zero live range, or pick virtual register
1.129 const RegMask &rm = n->out_RegMask();
1.130 _lrg_map.map(n->_idx, rm.is_NotEmpty() ? lr_counter++ : 0);
1.131 @@ -701,52 +692,55 @@
1.132 }
1.133
1.134
1.135 -//------------------------------gather_lrg_masks-------------------------------
1.136 // Gather LiveRanGe information, including register masks. Modification of
1.137 // cisc spillable in_RegMasks should not be done before AggressiveCoalesce.
1.138 void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) {
1.139
1.140 // Nail down the frame pointer live range
1.141 - uint fp_lrg = _lrg_map.live_range_id(_cfg._root->in(1)->in(TypeFunc::FramePtr));
1.142 + uint fp_lrg = _lrg_map.live_range_id(_cfg.get_root_node()->in(1)->in(TypeFunc::FramePtr));
1.143 lrgs(fp_lrg)._cost += 1e12; // Cost is infinite
1.144
1.145 // For all blocks
1.146 - for( uint i = 0; i < _cfg._num_blocks; i++ ) {
1.147 - Block *b = _cfg._blocks[i];
1.148 + for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
1.149 + Block* block = _cfg.get_block(i);
1.150
1.151 // For all instructions
1.152 - for( uint j = 1; j < b->_nodes.size(); j++ ) {
1.153 - Node *n = b->_nodes[j];
1.154 + for (uint j = 1; j < block->_nodes.size(); j++) {
1.155 + Node* n = block->_nodes[j];
1.156 uint input_edge_start =1; // Skip control most nodes
1.157 - if( n->is_Mach() ) input_edge_start = n->as_Mach()->oper_input_base();
1.158 + if (n->is_Mach()) {
1.159 + input_edge_start = n->as_Mach()->oper_input_base();
1.160 + }
1.161 uint idx = n->is_Copy();
1.162
1.163 // Get virtual register number, same as LiveRanGe index
1.164 uint vreg = _lrg_map.live_range_id(n);
1.165 - LRG &lrg = lrgs(vreg);
1.166 - if( vreg ) { // No vreg means un-allocable (e.g. memory)
1.167 + LRG& lrg = lrgs(vreg);
1.168 + if (vreg) { // No vreg means un-allocable (e.g. memory)
1.169
1.170 // Collect has-copy bit
1.171 - if( idx ) {
1.172 + if (idx) {
1.173 lrg._has_copy = 1;
1.174 uint clidx = _lrg_map.live_range_id(n->in(idx));
1.175 - LRG ©_src = lrgs(clidx);
1.176 + LRG& copy_src = lrgs(clidx);
1.177 copy_src._has_copy = 1;
1.178 }
1.179
1.180 // Check for float-vs-int live range (used in register-pressure
1.181 // calculations)
1.182 const Type *n_type = n->bottom_type();
1.183 - if (n_type->is_floatingpoint())
1.184 + if (n_type->is_floatingpoint()) {
1.185 lrg._is_float = 1;
1.186 + }
1.187
1.188 // Check for twice prior spilling. Once prior spilling might have
1.189 // spilled 'soft', 2nd prior spill should have spilled 'hard' and
1.190 // further spilling is unlikely to make progress.
1.191 - if( _spilled_once.test(n->_idx) ) {
1.192 + if (_spilled_once.test(n->_idx)) {
1.193 lrg._was_spilled1 = 1;
1.194 - if( _spilled_twice.test(n->_idx) )
1.195 + if (_spilled_twice.test(n->_idx)) {
1.196 lrg._was_spilled2 = 1;
1.197 + }
1.198 }
1.199
1.200 #ifndef PRODUCT
1.201 @@ -783,16 +777,18 @@
1.202
1.203 // Check for bound register masks
1.204 const RegMask &lrgmask = lrg.mask();
1.205 - if (lrgmask.is_bound(ireg))
1.206 + if (lrgmask.is_bound(ireg)) {
1.207 lrg._is_bound = 1;
1.208 + }
1.209
1.210 // Check for maximum frequency value
1.211 - if (lrg._maxfreq < b->_freq)
1.212 - lrg._maxfreq = b->_freq;
1.213 + if (lrg._maxfreq < block->_freq) {
1.214 + lrg._maxfreq = block->_freq;
1.215 + }
1.216
1.217 // Check for oop-iness, or long/double
1.218 // Check for multi-kill projection
1.219 - switch( ireg ) {
1.220 + switch (ireg) {
1.221 case MachProjNode::fat_proj:
1.222 // Fat projections have size equal to number of registers killed
1.223 lrg.set_num_regs(rm.Size());
1.224 @@ -962,7 +958,7 @@
1.225 // AggressiveCoalesce. This effectively pre-virtual-splits
1.226 // around uncommon uses of common defs.
1.227 const RegMask &rm = n->in_RegMask(k);
1.228 - if (!after_aggressive && _cfg.get_block_for_node(n->in(k))->_freq > 1000 * b->_freq) {
1.229 + if (!after_aggressive && _cfg.get_block_for_node(n->in(k))->_freq > 1000 * block->_freq) {
1.230 // Since we are BEFORE aggressive coalesce, leave the register
1.231 // mask untrimmed by the call. This encourages more coalescing.
1.232 // Later, AFTER aggressive, this live range will have to spill
1.233 @@ -1006,8 +1002,9 @@
1.234 }
1.235
1.236 // Check for maximum frequency value
1.237 - if( lrg._maxfreq < b->_freq )
1.238 - lrg._maxfreq = b->_freq;
1.239 + if (lrg._maxfreq < block->_freq) {
1.240 + lrg._maxfreq = block->_freq;
1.241 + }
1.242
1.243 } // End for all allocated inputs
1.244 } // end for all instructions
1.245 @@ -1029,7 +1026,6 @@
1.246 }
1.247 }
1.248
1.249 -//------------------------------set_was_low------------------------------------
1.250 // Set the was-lo-degree bit. Conservative coalescing should not change the
1.251 // colorability of the graph. If any live range was of low-degree before
1.252 // coalescing, it should Simplify. This call sets the was-lo-degree bit.
1.253 @@ -1066,7 +1062,6 @@
1.254
1.255 #define REGISTER_CONSTRAINED 16
1.256
1.257 -//------------------------------cache_lrg_info---------------------------------
1.258 // Compute cost/area ratio, in case we spill. Build the lo-degree list.
1.259 void PhaseChaitin::cache_lrg_info( ) {
1.260
1.261 @@ -1100,7 +1095,6 @@
1.262 }
1.263 }
1.264
1.265 -//------------------------------Pre-Simplify-----------------------------------
1.266 // Simplify the IFG by removing LRGs of low degree that have NO copies
1.267 void PhaseChaitin::Pre_Simplify( ) {
1.268
1.269 @@ -1151,7 +1145,6 @@
1.270 // No more lo-degree no-copy live ranges to simplify
1.271 }
1.272
1.273 -//------------------------------Simplify---------------------------------------
1.274 // Simplify the IFG by removing LRGs of low degree.
1.275 void PhaseChaitin::Simplify( ) {
1.276
1.277 @@ -1288,7 +1281,6 @@
1.278
1.279 }
1.280
1.281 -//------------------------------is_legal_reg-----------------------------------
1.282 // Is 'reg' register legal for 'lrg'?
1.283 static bool is_legal_reg(LRG &lrg, OptoReg::Name reg, int chunk) {
1.284 if (reg >= chunk && reg < (chunk + RegMask::CHUNK_SIZE) &&
1.285 @@ -1315,7 +1307,6 @@
1.286 return false;
1.287 }
1.288
1.289 -//------------------------------bias_color-------------------------------------
1.290 // Choose a color using the biasing heuristic
1.291 OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) {
1.292
1.293 @@ -1377,7 +1368,6 @@
1.294 return OptoReg::add( reg, chunk );
1.295 }
1.296
1.297 -//------------------------------choose_color-----------------------------------
1.298 // Choose a color in the current chunk
1.299 OptoReg::Name PhaseChaitin::choose_color( LRG &lrg, int chunk ) {
1.300 assert( C->in_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP-1)), "must not allocate stack0 (inside preserve area)");
1.301 @@ -1399,7 +1389,6 @@
1.302 return lrg.mask().find_last_elem();
1.303 }
1.304
1.305 -//------------------------------Select-----------------------------------------
1.306 // Select colors by re-inserting LRGs back into the IFG. LRGs are re-inserted
1.307 // in reverse order of removal. As long as nothing of hi-degree was yanked,
1.308 // everything going back is guaranteed a color. Select that color. If some
1.309 @@ -1574,8 +1563,6 @@
1.310 return spill_reg-LRG::SPILL_REG; // Return number of spills
1.311 }
1.312
1.313 -
1.314 -//------------------------------copy_was_spilled-------------------------------
1.315 // Copy 'was_spilled'-edness from the source Node to the dst Node.
1.316 void PhaseChaitin::copy_was_spilled( Node *src, Node *dst ) {
1.317 if( _spilled_once.test(src->_idx) ) {
1.318 @@ -1588,14 +1575,12 @@
1.319 }
1.320 }
1.321
1.322 -//------------------------------set_was_spilled--------------------------------
1.323 // Set the 'spilled_once' or 'spilled_twice' flag on a node.
1.324 void PhaseChaitin::set_was_spilled( Node *n ) {
1.325 if( _spilled_once.test_set(n->_idx) )
1.326 _spilled_twice.set(n->_idx);
1.327 }
1.328
1.329 -//------------------------------fixup_spills-----------------------------------
1.330 // Convert Ideal spill instructions into proper FramePtr + offset Loads and
1.331 // Stores. Use-def chains are NOT preserved, but Node->LRG->reg maps are.
1.332 void PhaseChaitin::fixup_spills() {
1.333 @@ -1605,16 +1590,16 @@
1.334 NOT_PRODUCT( Compile::TracePhase t3("fixupSpills", &_t_fixupSpills, TimeCompiler); )
1.335
1.336 // Grab the Frame Pointer
1.337 - Node *fp = _cfg._broot->head()->in(1)->in(TypeFunc::FramePtr);
1.338 + Node *fp = _cfg.get_root_block()->head()->in(1)->in(TypeFunc::FramePtr);
1.339
1.340 // For all blocks
1.341 - for( uint i = 0; i < _cfg._num_blocks; i++ ) {
1.342 - Block *b = _cfg._blocks[i];
1.343 + for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
1.344 + Block* block = _cfg.get_block(i);
1.345
1.346 // For all instructions in block
1.347 - uint last_inst = b->end_idx();
1.348 - for( uint j = 1; j <= last_inst; j++ ) {
1.349 - Node *n = b->_nodes[j];
1.350 + uint last_inst = block->end_idx();
1.351 + for (uint j = 1; j <= last_inst; j++) {
1.352 + Node* n = block->_nodes[j];
1.353
1.354 // Dead instruction???
1.355 assert( n->outcnt() != 0 ||// Nothing dead after post alloc
1.356 @@ -1651,7 +1636,7 @@
1.357 assert( cisc->oper_input_base() == 2, "Only adding one edge");
1.358 cisc->ins_req(1,src); // Requires a memory edge
1.359 }
1.360 - b->_nodes.map(j,cisc); // Insert into basic block
1.361 + block->_nodes.map(j,cisc); // Insert into basic block
1.362 n->subsume_by(cisc, C); // Correct graph
1.363 //
1.364 ++_used_cisc_instructions;
1.365 @@ -1677,7 +1662,6 @@
1.366 } // End of for all blocks
1.367 }
1.368
1.369 -//------------------------------find_base_for_derived--------------------------
1.370 // Helper to stretch above; recursively discover the base Node for a
1.371 // given derived Node. Easy for AddP-related machine nodes, but needs
1.372 // to be recursive for derived Phis.
1.373 @@ -1707,7 +1691,7 @@
1.374 // Initialize it once and make it shared:
1.375 // set control to _root and place it into Start block
1.376 // (where top() node is placed).
1.377 - base->init_req(0, _cfg._root);
1.378 + base->init_req(0, _cfg.get_root_node());
1.379 Block *startb = _cfg.get_block_for_node(C->top());
1.380 startb->_nodes.insert(startb->find_node(C->top()), base );
1.381 _cfg.map_node_to_block(base, startb);
1.382 @@ -1716,7 +1700,7 @@
1.383 if (_lrg_map.live_range_id(base) == 0) {
1.384 new_lrg(base, maxlrg++);
1.385 }
1.386 - assert(base->in(0) == _cfg._root && _cfg.get_block_for_node(base) == _cfg.get_block_for_node(C->top()), "base NULL should be shared");
1.387 + assert(base->in(0) == _cfg.get_root_node() && _cfg.get_block_for_node(base) == _cfg.get_block_for_node(C->top()), "base NULL should be shared");
1.388 derived_base_map[derived->_idx] = base;
1.389 return base;
1.390 }
1.391 @@ -1779,8 +1763,6 @@
1.392 return base;
1.393 }
1.394
1.395 -
1.396 -//------------------------------stretch_base_pointer_live_ranges---------------
1.397 // At each Safepoint, insert extra debug edges for each pair of derived value/
1.398 // base pointer that is live across the Safepoint for oopmap building. The
1.399 // edge pairs get added in after sfpt->jvmtail()->oopoff(), but are in the
1.400 @@ -1792,14 +1774,14 @@
1.401 memset( derived_base_map, 0, sizeof(Node*)*C->unique() );
1.402
1.403 // For all blocks in RPO do...
1.404 - for( uint i=0; i<_cfg._num_blocks; i++ ) {
1.405 - Block *b = _cfg._blocks[i];
1.406 + for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
1.407 + Block* block = _cfg.get_block(i);
1.408 // Note use of deep-copy constructor. I cannot hammer the original
1.409 // liveout bits, because they are needed by the following coalesce pass.
1.410 - IndexSet liveout(_live->live(b));
1.411 + IndexSet liveout(_live->live(block));
1.412
1.413 - for( uint j = b->end_idx() + 1; j > 1; j-- ) {
1.414 - Node *n = b->_nodes[j-1];
1.415 + for (uint j = block->end_idx() + 1; j > 1; j--) {
1.416 + Node* n = block->_nodes[j - 1];
1.417
1.418 // Pre-split compares of loop-phis. Loop-phis form a cycle we would
1.419 // like to see in the same register. Compare uses the loop-phi and so
1.420 @@ -1814,7 +1796,7 @@
1.421 Node *phi = n->in(1);
1.422 if( phi->is_Phi() && phi->as_Phi()->region()->is_Loop() ) {
1.423 Block *phi_block = _cfg.get_block_for_node(phi);
1.424 - if (_cfg.get_block_for_node(phi_block->pred(2)) == b) {
1.425 + if (_cfg.get_block_for_node(phi_block->pred(2)) == block) {
1.426 const RegMask *mask = C->matcher()->idealreg2spillmask[Op_RegI];
1.427 Node *spill = new (C) MachSpillCopyNode( phi, *mask, *mask );
1.428 insert_proj( phi_block, 1, spill, maxlrg++ );
1.429 @@ -1868,7 +1850,7 @@
1.430 if ((_lrg_map.live_range_id(base) >= _lrg_map.max_lrg_id() || // (Brand new base (hence not live) or
1.431 !liveout.member(_lrg_map.live_range_id(base))) && // not live) AND
1.432 (_lrg_map.live_range_id(base) > 0) && // not a constant
1.433 - _cfg.get_block_for_node(base) != b) { // base not def'd in blk)
1.434 + _cfg.get_block_for_node(base) != block) { // base not def'd in blk)
1.435 // Base pointer is not currently live. Since I stretched
1.436 // the base pointer to here and it crosses basic-block
1.437 // boundaries, the global live info is now incorrect.
1.438 @@ -1903,15 +1885,12 @@
1.439 return must_recompute_live != 0;
1.440 }
1.441
1.442 -
1.443 -//------------------------------add_reference----------------------------------
1.444 // Extend the node to LRG mapping
1.445
1.446 void PhaseChaitin::add_reference(const Node *node, const Node *old_node) {
1.447 _lrg_map.extend(node->_idx, _lrg_map.live_range_id(old_node));
1.448 }
1.449
1.450 -//------------------------------dump-------------------------------------------
1.451 #ifndef PRODUCT
1.452 void PhaseChaitin::dump(const Node *n) const {
1.453 uint r = (n->_idx < _lrg_map.size()) ? _lrg_map.find_const(n) : 0;
1.454 @@ -2017,8 +1996,9 @@
1.455 _matcher._new_SP, _framesize );
1.456
1.457 // For all blocks
1.458 - for( uint i = 0; i < _cfg._num_blocks; i++ )
1.459 - dump(_cfg._blocks[i]);
1.460 + for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
1.461 + dump(_cfg.get_block(i));
1.462 + }
1.463 // End of per-block dump
1.464 tty->print("\n");
1.465
1.466 @@ -2059,7 +2039,6 @@
1.467 tty->print_cr("");
1.468 }
1.469
1.470 -//------------------------------dump_degree_lists------------------------------
1.471 void PhaseChaitin::dump_degree_lists() const {
1.472 // Dump lo-degree list
1.473 tty->print("Lo degree: ");
1.474 @@ -2080,7 +2059,6 @@
1.475 tty->print_cr("");
1.476 }
1.477
1.478 -//------------------------------dump_simplified--------------------------------
1.479 void PhaseChaitin::dump_simplified() const {
1.480 tty->print("Simplified: ");
1.481 for( uint i = _simplified; i; i = lrgs(i)._next )
1.482 @@ -2099,7 +2077,6 @@
1.483 return buf+strlen(buf);
1.484 }
1.485
1.486 -//------------------------------dump_register----------------------------------
1.487 // Dump a register name into a buffer. Be intelligent if we get called
1.488 // before allocation is complete.
1.489 char *PhaseChaitin::dump_register( const Node *n, char *buf ) const {
1.490 @@ -2133,7 +2110,6 @@
1.491 return buf+strlen(buf);
1.492 }
1.493
1.494 -//----------------------dump_for_spill_split_recycle--------------------------
1.495 void PhaseChaitin::dump_for_spill_split_recycle() const {
1.496 if( WizardMode && (PrintCompilation || PrintOpto) ) {
1.497 // Display which live ranges need to be split and the allocator's state
1.498 @@ -2149,7 +2125,6 @@
1.499 }
1.500 }
1.501
1.502 -//------------------------------dump_frame------------------------------------
1.503 void PhaseChaitin::dump_frame() const {
1.504 const char *fp = OptoReg::regname(OptoReg::c_frame_pointer);
1.505 const TypeTuple *domain = C->tf()->domain();
1.506 @@ -2255,17 +2230,16 @@
1.507 tty->print_cr("#");
1.508 }
1.509
1.510 -//------------------------------dump_bb----------------------------------------
1.511 void PhaseChaitin::dump_bb( uint pre_order ) const {
1.512 tty->print_cr("---dump of B%d---",pre_order);
1.513 - for( uint i = 0; i < _cfg._num_blocks; i++ ) {
1.514 - Block *b = _cfg._blocks[i];
1.515 - if( b->_pre_order == pre_order )
1.516 - dump(b);
1.517 + for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
1.518 + Block* block = _cfg.get_block(i);
1.519 + if (block->_pre_order == pre_order) {
1.520 + dump(block);
1.521 + }
1.522 }
1.523 }
1.524
1.525 -//------------------------------dump_lrg---------------------------------------
1.526 void PhaseChaitin::dump_lrg( uint lidx, bool defs_only ) const {
1.527 tty->print_cr("---dump of L%d---",lidx);
1.528
1.529 @@ -2287,17 +2261,17 @@
1.530 tty->cr();
1.531 }
1.532 // For all blocks
1.533 - for( uint i = 0; i < _cfg._num_blocks; i++ ) {
1.534 - Block *b = _cfg._blocks[i];
1.535 + for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
1.536 + Block* block = _cfg.get_block(i);
1.537 int dump_once = 0;
1.538
1.539 // For all instructions
1.540 - for( uint j = 0; j < b->_nodes.size(); j++ ) {
1.541 - Node *n = b->_nodes[j];
1.542 + for( uint j = 0; j < block->_nodes.size(); j++ ) {
1.543 + Node *n = block->_nodes[j];
1.544 if (_lrg_map.find_const(n) == lidx) {
1.545 if (!dump_once++) {
1.546 tty->cr();
1.547 - b->dump_head(&_cfg);
1.548 + block->dump_head(&_cfg);
1.549 }
1.550 dump(n);
1.551 continue;
1.552 @@ -2312,7 +2286,7 @@
1.553 if (_lrg_map.find_const(m) == lidx) {
1.554 if (!dump_once++) {
1.555 tty->cr();
1.556 - b->dump_head(&_cfg);
1.557 + block->dump_head(&_cfg);
1.558 }
1.559 dump(n);
1.560 }
1.561 @@ -2324,7 +2298,6 @@
1.562 }
1.563 #endif // not PRODUCT
1.564
1.565 -//------------------------------print_chaitin_statistics-------------------------------
1.566 int PhaseChaitin::_final_loads = 0;
1.567 int PhaseChaitin::_final_stores = 0;
1.568 int PhaseChaitin::_final_memoves= 0;
