1.1 --- a/src/cpu/mips/vm/mips_64.ad Tue Feb 28 09:53:43 2017 -0500
1.2 +++ b/src/cpu/mips/vm/mips_64.ad Tue Feb 28 10:29:54 2017 -0500
1.3 @@ -2827,44 +2827,6 @@
1.4 }
1.5 %}
1.6
1.7 - enc_class store_L_immL_enc (memory mem, immL src) %{
1.8 - MacroAssembler _masm(&cbuf);
1.9 - int base = $mem$$base;
1.10 - int index = $mem$$index;
1.11 - int scale = $mem$$scale;
1.12 - int disp = $mem$$disp;
1.13 - long imm = $src$$constant;
1.14 -
1.15 - if( index != 0 ) {
1.16 - if (scale == 0) {
1.17 - __ daddu(AT, as_Register(base), as_Register(index));
1.18 - } else {
1.19 - __ dsll(AT, as_Register(index), scale);
1.20 - __ daddu(AT, as_Register(base), AT);
1.21 - }
1.22 - if( Assembler::is_simm16(disp) ) {
1.23 - __ li(T9, imm);
1.24 - __ sd(T9, AT, disp);
1.25 - } else {
1.26 - __ move(T9, disp);
1.27 - __ addu(AT, AT, T9);
1.28 - __ li(T9, imm);
1.29 - __ sd(T9, AT, 0);
1.30 - }
1.31 - } else {
1.32 - if( Assembler::is_simm16(disp) ) {
1.33 - __ move(AT, as_Register(base));
1.34 - __ li(T9, imm);
1.35 - __ sd(T9, AT, disp);
1.36 - } else {
1.37 - __ move(T9, disp);
1.38 - __ addu(AT, as_Register(base), T9);
1.39 - __ li(T9, imm);
1.40 - __ sd(T9, AT, 0);
1.41 - }
1.42 - }
1.43 - %}
1.44 -
1.45 enc_class load_F_enc (regF dst, memory mem) %{
1.46 MacroAssembler _masm(&cbuf);
1.47 int base = $mem$$base;
1.48 @@ -5886,7 +5848,6 @@
1.49
1.50 // Store Long
1.51 instruct storeL_reg(memory mem, mRegL src) %{
1.52 - predicate(!((StoreLNode*)n)->require_atomic_access());
1.53 match(Set mem (StoreL mem src));
1.54
1.55 ins_cost(200);
1.56 @@ -5895,60 +5856,6 @@
1.57 ins_pipe( ialu_storeL );
1.58 %}
1.59
1.60 -//FIXME:volatile! atomic!
1.61 -// Volatile Store Long. Must be atomic, so move it into
1.62 -// the FP TOS and then do a 64-bit FIST. Has to probe the
1.63 -// target address before the store (for null-ptr checks)
1.64 -// so the memory operand is used twice in the encoding.
1.65 -instruct storeL_reg_atomic(memory mem, mRegL src) %{
1.66 - predicate(((StoreLNode*)n)->require_atomic_access());
1.67 - match(Set mem (StoreL mem src));
1.68 -
1.69 - ins_cost(200);
1.70 - format %{ "sw $mem, $src #@storeL_reg_atomic\n" %}
1.71 - ins_encode %{
1.72 - Register src = as_Register($src$$reg);
1.73 -
1.74 - int base = $mem$$base;
1.75 - int index = $mem$$index;
1.76 - int scale = $mem$$scale;
1.77 - int disp = $mem$$disp;
1.78 -
1.79 - if( index != 0 ) {
1.80 - if( Assembler::is_simm16(disp) ) {
1.81 - if (scale == 0) {
1.82 - __ addu(AT, as_Register(base), as_Register(index));
1.83 - } else {
1.84 - __ dsll(AT, as_Register(index), scale);
1.85 - __ addu(AT, as_Register(base), AT);
1.86 - }
1.87 - __ sd(src, AT, disp);
1.88 - } else {
1.89 - if (scale == 0) {
1.90 - __ addu(AT, as_Register(base), as_Register(index));
1.91 - } else {
1.92 - __ dsll(AT, as_Register(index), scale);
1.93 - __ addu(AT, as_Register(base), AT);
1.94 - }
1.95 - __ move(T9, disp);
1.96 - __ addu(AT, AT, T9);
1.97 - __ sd(src, AT, 0);
1.98 - }
1.99 - } else {
1.100 - if( Assembler::is_simm16(disp) ) {
1.101 - __ move(AT, as_Register(base));
1.102 - __ sd(src, AT, disp);
1.103 - } else {
1.104 - __ move(AT, as_Register(base));
1.105 - __ move(T9, disp);
1.106 - __ addu(AT, AT, T9);
1.107 - __ sd(src, AT, 0);
1.108 - }
1.109 - }
1.110 -
1.111 - %}
1.112 - ins_pipe( ialu_storeL );
1.113 -%}
1.114
1.115 instruct storeL_immL0(memory mem, immL0 zero) %{
1.116 match(Set mem (StoreL mem zero));
1.117 @@ -5959,15 +5866,6 @@
1.118 ins_pipe( ialu_storeL );
1.119 %}
1.120
1.121 -instruct storeL_imm(memory mem, immL src) %{
1.122 - match(Set mem (StoreL mem src));
1.123 -
1.124 - ins_cost(200);
1.125 - format %{ "sw $mem, $src #@storeL_imm" %}
1.126 - ins_encode(store_L_immL_enc(mem, src));
1.127 - ins_pipe( ialu_storeL );
1.128 -%}
1.129 -
1.130 // Load Compressed Pointer
1.131 instruct loadN(mRegN dst, memory mem)
1.132 %{
