1.1 --- a/src/cpu/sparc/vm/sparc.ad Fri Feb 27 08:34:19 2009 -0800
1.2 +++ b/src/cpu/sparc/vm/sparc.ad Fri Feb 27 13:27:09 2009 -0800
1.3 @@ -189,7 +189,7 @@
1.4 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
1.5 // wants 0-63, so we have to convert every time we want to use fp regs
1.6 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
1.7 -// 255 is a flag meaning 'dont go here'.
1.8 +// 255 is a flag meaning "don't go here".
1.9 // I believe we can't handle callee-save doubles D32 and up until
1.10 // the place in the sparc stack crawler that asserts on the 255 is
1.11 // fixed up.
1.12 @@ -462,7 +462,7 @@
1.13
1.14 // Macros to extract hi & lo halves from a long pair.
1.15 // G0 is not part of any long pair, so assert on that.
1.16 -// Prevents accidently using G1 instead of G0.
1.17 +// Prevents accidentally using G1 instead of G0.
1.18 #define LONG_HI_REG(x) (x)
1.19 #define LONG_LO_REG(x) (x)
1.20
1.21 @@ -1431,7 +1431,7 @@
1.22
1.23 #ifndef _LP64
1.24 // In the LP64 build, all registers can be moved as aligned/adjacent
1.25 - // pairs, so there's never any need to move the high bits seperately.
1.26 + // pairs, so there's never any need to move the high bits separately.
1.27 // The 32-bit builds have to deal with the 32-bit ABI which can force
1.28 // all sorts of silly alignment problems.
1.29
1.30 @@ -1624,7 +1624,7 @@
1.31 Register temp_reg = G3;
1.32 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1.33
1.34 - // Load klass from reciever
1.35 + // Load klass from receiver
1.36 __ load_klass(O0, temp_reg);
1.37 // Compare against expected klass
1.38 __ cmp(temp_reg, G5_ic_reg);
1.39 @@ -4149,7 +4149,7 @@
1.40
1.41 //----------OPERAND CLASSES----------------------------------------------------
1.42 // Operand Classes are groups of operands that are used to simplify
1.43 -// instruction definitions by not requiring the AD writer to specify seperate
1.44 +// instruction definitions by not requiring the AD writer to specify separate
1.45 // instructions for every form of operand when the instruction accepts
1.46 // multiple operand types with the same basic encoding and format. The classic
1.47 // case of this is memory operands.
1.48 @@ -6847,7 +6847,7 @@
1.49 ins_pipe(sdiv_reg_reg);
1.50 %}
1.51
1.52 -// Magic constant, reciprical of 10
1.53 +// Magic constant, reciprocal of 10
1.54 instruct loadConI_x66666667(iRegIsafe dst) %{
1.55 effect( DEF dst );
1.56
1.57 @@ -6857,7 +6857,7 @@
1.58 ins_pipe(ialu_hi_lo_reg);
1.59 %}
1.60
1.61 -// Register Shift Right Arithmatic Long by 32-63
1.62 +// Register Shift Right Arithmetic Long by 32-63
1.63 instruct sra_31( iRegI dst, iRegI src ) %{
1.64 effect( DEF dst, USE src );
1.65 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
1.66 @@ -9048,7 +9048,7 @@
1.67 // These must follow all instruction definitions as they use the names
1.68 // defined in the instructions definitions.
1.69 //
1.70 -// peepmatch ( root_instr_name [preceeding_instruction]* );
1.71 +// peepmatch ( root_instr_name [preceding_instruction]* );
1.72 //
1.73 // peepconstraint %{
1.74 // (instruction_number.operand_name relational_op instruction_number.operand_name
