1.1 --- a/src/share/vm/opto/chaitin.cpp Thu Jun 14 14:59:52 2012 -0700
1.2 +++ b/src/share/vm/opto/chaitin.cpp Fri Jun 15 01:25:19 2012 -0700
1.3 @@ -75,6 +75,7 @@
1.4 // Flags
1.5 if( _is_oop ) tty->print("Oop ");
1.6 if( _is_float ) tty->print("Float ");
1.7 + if( _is_vector ) tty->print("Vector ");
1.8 if( _was_spilled1 ) tty->print("Spilled ");
1.9 if( _was_spilled2 ) tty->print("Spilled2 ");
1.10 if( _direct_conflict ) tty->print("Direct_conflict ");
1.11 @@ -479,16 +480,18 @@
1.12
1.13 // Move important info out of the live_arena to longer lasting storage.
1.14 alloc_node_regs(_names.Size());
1.15 - for( uint i=0; i < _names.Size(); i++ ) {
1.16 - if( _names[i] ) { // Live range associated with Node?
1.17 - LRG &lrg = lrgs( _names[i] );
1.18 - if( lrg.num_regs() == 1 ) {
1.19 - _node_regs[i].set1( lrg.reg() );
1.20 + for (uint i=0; i < _names.Size(); i++) {
1.21 + if (_names[i]) { // Live range associated with Node?
1.22 + LRG &lrg = lrgs(_names[i]);
1.23 + if (!lrg.alive()) {
1.24 + _node_regs[i].set_bad();
1.25 + } else if (lrg.num_regs() == 1) {
1.26 + _node_regs[i].set1(lrg.reg());
1.27 } else { // Must be a register-pair
1.28 - if( !lrg._fat_proj ) { // Must be aligned adjacent register pair
1.29 + if (!lrg._fat_proj) { // Must be aligned adjacent register pair
1.30 // Live ranges record the highest register in their mask.
1.31 // We want the low register for the AD file writer's convenience.
1.32 - _node_regs[i].set2( OptoReg::add(lrg.reg(),-1) );
1.33 + _node_regs[i].set2( OptoReg::add(lrg.reg(),(1-lrg.num_regs())) );
1.34 } else { // Misaligned; extract 2 bits
1.35 OptoReg::Name hi = lrg.reg(); // Get hi register
1.36 lrg.Remove(hi); // Yank from mask
1.37 @@ -568,7 +571,7 @@
1.38 // Check for float-vs-int live range (used in register-pressure
1.39 // calculations)
1.40 const Type *n_type = n->bottom_type();
1.41 - if( n_type->is_floatingpoint() )
1.42 + if (n_type->is_floatingpoint())
1.43 lrg._is_float = 1;
1.44
1.45 // Check for twice prior spilling. Once prior spilling might have
1.46 @@ -599,18 +602,28 @@
1.47 // Limit result register mask to acceptable registers
1.48 const RegMask &rm = n->out_RegMask();
1.49 lrg.AND( rm );
1.50 - // Check for bound register masks
1.51 - const RegMask &lrgmask = lrg.mask();
1.52 - if( lrgmask.is_bound1() || lrgmask.is_bound2() )
1.53 - lrg._is_bound = 1;
1.54 -
1.55 - // Check for maximum frequency value
1.56 - if( lrg._maxfreq < b->_freq )
1.57 - lrg._maxfreq = b->_freq;
1.58
1.59 int ireg = n->ideal_reg();
1.60 assert( !n->bottom_type()->isa_oop_ptr() || ireg == Op_RegP,
1.61 "oops must be in Op_RegP's" );
1.62 +
1.63 + // Check for vector live range (only if vector register is used).
1.64 + // On SPARC vector uses RegD which could be misaligned so it is not
1.65 + // processes as vector in RA.
1.66 + if (RegMask::is_vector(ireg))
1.67 + lrg._is_vector = 1;
1.68 + assert(n_type->isa_vect() == NULL || lrg._is_vector || ireg == Op_RegD,
1.69 + "vector must be in vector registers");
1.70 +
1.71 + // Check for bound register masks
1.72 + const RegMask &lrgmask = lrg.mask();
1.73 + if (lrgmask.is_bound(ireg))
1.74 + lrg._is_bound = 1;
1.75 +
1.76 + // Check for maximum frequency value
1.77 + if (lrg._maxfreq < b->_freq)
1.78 + lrg._maxfreq = b->_freq;
1.79 +
1.80 // Check for oop-iness, or long/double
1.81 // Check for multi-kill projection
1.82 switch( ireg ) {
1.83 @@ -689,7 +702,7 @@
1.84 // AND changes how we count interferences. A mis-aligned
1.85 // double can interfere with TWO aligned pairs, or effectively
1.86 // FOUR registers!
1.87 - if( rm.is_misaligned_Pair() ) {
1.88 + if (rm.is_misaligned_pair()) {
1.89 lrg._fat_proj = 1;
1.90 lrg._is_bound = 1;
1.91 }
1.92 @@ -706,6 +719,33 @@
1.93 lrg.set_reg_pressure(1);
1.94 #endif
1.95 break;
1.96 + case Op_VecS:
1.97 + assert(Matcher::vector_size_supported(T_BYTE,4), "sanity");
1.98 + assert(RegMask::num_registers(Op_VecS) == RegMask::SlotsPerVecS, "sanity");
1.99 + lrg.set_num_regs(RegMask::SlotsPerVecS);
1.100 + lrg.set_reg_pressure(1);
1.101 + break;
1.102 + case Op_VecD:
1.103 + assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecD), "sanity");
1.104 + assert(RegMask::num_registers(Op_VecD) == RegMask::SlotsPerVecD, "sanity");
1.105 + assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecD), "vector should be aligned");
1.106 + lrg.set_num_regs(RegMask::SlotsPerVecD);
1.107 + lrg.set_reg_pressure(1);
1.108 + break;
1.109 + case Op_VecX:
1.110 + assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecX), "sanity");
1.111 + assert(RegMask::num_registers(Op_VecX) == RegMask::SlotsPerVecX, "sanity");
1.112 + assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecX), "vector should be aligned");
1.113 + lrg.set_num_regs(RegMask::SlotsPerVecX);
1.114 + lrg.set_reg_pressure(1);
1.115 + break;
1.116 + case Op_VecY:
1.117 + assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecY), "sanity");
1.118 + assert(RegMask::num_registers(Op_VecY) == RegMask::SlotsPerVecY, "sanity");
1.119 + assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecY), "vector should be aligned");
1.120 + lrg.set_num_regs(RegMask::SlotsPerVecY);
1.121 + lrg.set_reg_pressure(1);
1.122 + break;
1.123 default:
1.124 ShouldNotReachHere();
1.125 }
1.126 @@ -763,24 +803,38 @@
1.127 } else {
1.128 lrg.AND( rm );
1.129 }
1.130 +
1.131 // Check for bound register masks
1.132 const RegMask &lrgmask = lrg.mask();
1.133 - if( lrgmask.is_bound1() || lrgmask.is_bound2() )
1.134 + int kreg = n->in(k)->ideal_reg();
1.135 + bool is_vect = RegMask::is_vector(kreg);
1.136 + assert(n->in(k)->bottom_type()->isa_vect() == NULL ||
1.137 + is_vect || kreg == Op_RegD,
1.138 + "vector must be in vector registers");
1.139 + if (lrgmask.is_bound(kreg))
1.140 lrg._is_bound = 1;
1.141 +
1.142 // If this use of a double forces a mis-aligned double,
1.143 // flag as '_fat_proj' - really flag as allowing misalignment
1.144 // AND changes how we count interferences. A mis-aligned
1.145 // double can interfere with TWO aligned pairs, or effectively
1.146 // FOUR registers!
1.147 - if( lrg.num_regs() == 2 && !lrg._fat_proj && rm.is_misaligned_Pair() ) {
1.148 +#ifdef ASSERT
1.149 + if (is_vect) {
1.150 + assert(lrgmask.is_aligned_sets(lrg.num_regs()), "vector should be aligned");
1.151 + assert(!lrg._fat_proj, "sanity");
1.152 + assert(RegMask::num_registers(kreg) == lrg.num_regs(), "sanity");
1.153 + }
1.154 +#endif
1.155 + if (!is_vect && lrg.num_regs() == 2 && !lrg._fat_proj && rm.is_misaligned_pair()) {
1.156 lrg._fat_proj = 1;
1.157 lrg._is_bound = 1;
1.158 }
1.159 // if the LRG is an unaligned pair, we will have to spill
1.160 // so clear the LRG's register mask if it is not already spilled
1.161 - if ( !n->is_SpillCopy() &&
1.162 - (lrg._def == NULL || lrg.is_multidef() || !lrg._def->is_SpillCopy()) &&
1.163 - lrgmask.is_misaligned_Pair()) {
1.164 + if (!is_vect && !n->is_SpillCopy() &&
1.165 + (lrg._def == NULL || lrg.is_multidef() || !lrg._def->is_SpillCopy()) &&
1.166 + lrgmask.is_misaligned_pair()) {
1.167 lrg.Clear();
1.168 }
1.169
1.170 @@ -793,12 +847,14 @@
1.171 } // end for all blocks
1.172
1.173 // Final per-liverange setup
1.174 - for( uint i2=0; i2<_maxlrg; i2++ ) {
1.175 + for (uint i2=0; i2<_maxlrg; i2++) {
1.176 LRG &lrg = lrgs(i2);
1.177 - if( lrg.num_regs() == 2 && !lrg._fat_proj )
1.178 - lrg.ClearToPairs();
1.179 + assert(!lrg._is_vector || !lrg._fat_proj, "sanity");
1.180 + if (lrg.num_regs() > 1 && !lrg._fat_proj) {
1.181 + lrg.clear_to_sets();
1.182 + }
1.183 lrg.compute_set_mask_size();
1.184 - if( lrg.not_free() ) { // Handle case where we lose from the start
1.185 + if (lrg.not_free()) { // Handle case where we lose from the start
1.186 lrg.set_reg(OptoReg::Name(LRG::SPILL_REG));
1.187 lrg._direct_conflict = 1;
1.188 }
1.189 @@ -1104,22 +1160,17 @@
1.190 // Choose a color which is legal for him
1.191 RegMask tempmask = lrg.mask();
1.192 tempmask.AND(lrgs(copy_lrg).mask());
1.193 - OptoReg::Name reg;
1.194 - if( lrg.num_regs() == 1 ) {
1.195 - reg = tempmask.find_first_elem();
1.196 - } else {
1.197 - tempmask.ClearToPairs();
1.198 - reg = tempmask.find_first_pair();
1.199 - }
1.200 - if( OptoReg::is_valid(reg) )
1.201 + tempmask.clear_to_sets(lrg.num_regs());
1.202 + OptoReg::Name reg = tempmask.find_first_set(lrg.num_regs());
1.203 + if (OptoReg::is_valid(reg))
1.204 return reg;
1.205 }
1.206 }
1.207
1.208 // If no bias info exists, just go with the register selection ordering
1.209 - if( lrg.num_regs() == 2 ) {
1.210 - // Find an aligned pair
1.211 - return OptoReg::add(lrg.mask().find_first_pair(),chunk);
1.212 + if (lrg._is_vector || lrg.num_regs() == 2) {
1.213 + // Find an aligned set
1.214 + return OptoReg::add(lrg.mask().find_first_set(lrg.num_regs()),chunk);
1.215 }
1.216
1.217 // CNC - Fun hack. Alternate 1st and 2nd selection. Enables post-allocate
1.218 @@ -1149,6 +1200,7 @@
1.219 // Use a heuristic to "bias" the color choice
1.220 return bias_color(lrg, chunk);
1.221
1.222 + assert(!lrg._is_vector, "should be not vector here" );
1.223 assert( lrg.num_regs() >= 2, "dead live ranges do not color" );
1.224
1.225 // Fat-proj case or misaligned double argument.
1.226 @@ -1238,14 +1290,16 @@
1.227 }
1.228 //assert(is_allstack == lrg->mask().is_AllStack(), "nbrs must not change AllStackedness");
1.229 // Aligned pairs need aligned masks
1.230 - if( lrg->num_regs() == 2 && !lrg->_fat_proj )
1.231 - lrg->ClearToPairs();
1.232 + assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity");
1.233 + if (lrg->num_regs() > 1 && !lrg->_fat_proj) {
1.234 + lrg->clear_to_sets();
1.235 + }
1.236
1.237 // Check if a color is available and if so pick the color
1.238 OptoReg::Name reg = choose_color( *lrg, chunk );
1.239 #ifdef SPARC
1.240 debug_only(lrg->compute_set_mask_size());
1.241 - assert(lrg->num_regs() != 2 || lrg->is_bound() || is_even(reg-1), "allocate all doubles aligned");
1.242 + assert(lrg->num_regs() < 2 || lrg->is_bound() || is_even(reg-1), "allocate all doubles aligned");
1.243 #endif
1.244
1.245 //---------------
1.246 @@ -1277,17 +1331,16 @@
1.247 // If the live range is not bound, then we actually had some choices
1.248 // to make. In this case, the mask has more bits in it than the colors
1.249 // chosen. Restrict the mask to just what was picked.
1.250 - if( lrg->num_regs() == 1 ) { // Size 1 live range
1.251 + int n_regs = lrg->num_regs();
1.252 + assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity");
1.253 + if (n_regs == 1 || !lrg->_fat_proj) {
1.254 + assert(!lrg->_is_vector || n_regs <= RegMask::SlotsPerVecY, "sanity");
1.255 lrg->Clear(); // Clear the mask
1.256 lrg->Insert(reg); // Set regmask to match selected reg
1.257 - lrg->set_mask_size(1);
1.258 - } else if( !lrg->_fat_proj ) {
1.259 - // For pairs, also insert the low bit of the pair
1.260 - assert( lrg->num_regs() == 2, "unbound fatproj???" );
1.261 - lrg->Clear(); // Clear the mask
1.262 - lrg->Insert(reg); // Set regmask to match selected reg
1.263 - lrg->Insert(OptoReg::add(reg,-1));
1.264 - lrg->set_mask_size(2);
1.265 + // For vectors and pairs, also insert the low bit of the pair
1.266 + for (int i = 1; i < n_regs; i++)
1.267 + lrg->Insert(OptoReg::add(reg,-i));
1.268 + lrg->set_mask_size(n_regs);
1.269 } else { // Else fatproj
1.270 // mask must be equal to fatproj bits, by definition
1.271 }
1.272 @@ -1860,12 +1913,20 @@
1.273 sprintf(buf,"L%d",lidx); // No register binding yet
1.274 } else if( !lidx ) { // Special, not allocated value
1.275 strcpy(buf,"Special");
1.276 - } else if( (lrgs(lidx).num_regs() == 1)
1.277 - ? !lrgs(lidx).mask().is_bound1()
1.278 - : !lrgs(lidx).mask().is_bound2() ) {
1.279 - sprintf(buf,"L%d",lidx); // No register binding yet
1.280 - } else { // Hah! We have a bound machine register
1.281 - print_reg( lrgs(lidx).reg(), this, buf );
1.282 + } else {
1.283 + if (lrgs(lidx)._is_vector) {
1.284 + if (lrgs(lidx).mask().is_bound_set(lrgs(lidx).num_regs()))
1.285 + print_reg( lrgs(lidx).reg(), this, buf ); // a bound machine register
1.286 + else
1.287 + sprintf(buf,"L%d",lidx); // No register binding yet
1.288 + } else if( (lrgs(lidx).num_regs() == 1)
1.289 + ? lrgs(lidx).mask().is_bound1()
1.290 + : lrgs(lidx).mask().is_bound_pair() ) {
1.291 + // Hah! We have a bound machine register
1.292 + print_reg( lrgs(lidx).reg(), this, buf );
1.293 + } else {
1.294 + sprintf(buf,"L%d",lidx); // No register binding yet
1.295 + }
1.296 }
1.297 }
1.298 return buf+strlen(buf);
