1.1 --- a/src/cpu/x86/vm/x86_32.ad Thu Jun 14 14:59:52 2012 -0700
1.2 +++ b/src/cpu/x86/vm/x86_32.ad Fri Jun 15 01:25:19 2012 -0700
1.3 @@ -74,9 +74,6 @@
1.4 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
1.5 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
1.6
1.7 -// Special Registers
1.8 -reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad());
1.9 -
1.10 // Float registers. We treat TOS/FPR0 special. It is invisible to the
1.11 // allocator, and only shows up in the encodings.
1.12 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
1.13 @@ -105,27 +102,6 @@
1.14 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
1.15 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
1.16
1.17 -// XMM registers. 128-bit registers or 4 words each, labeled a-d.
1.18 -// Word a in each register holds a Float, words ab hold a Double.
1.19 -// We currently do not use the SIMD capabilities, so registers cd
1.20 -// are unused at the moment.
1.21 -reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
1.22 -reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
1.23 -reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
1.24 -reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
1.25 -reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
1.26 -reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
1.27 -reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
1.28 -reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
1.29 -reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
1.30 -reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
1.31 -reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
1.32 -reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
1.33 -reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
1.34 -reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
1.35 -reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
1.36 -reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
1.37 -
1.38 // Specify priority of register selection within phases of register
1.39 // allocation. Highest priority is first. A useful heuristic is to
1.40 // give registers a low priority when they are required by machine
1.41 @@ -138,15 +114,6 @@
1.42 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
1.43 FPR6L, FPR6H, FPR7L, FPR7H );
1.44
1.45 -alloc_class chunk1( XMM0a, XMM0b,
1.46 - XMM1a, XMM1b,
1.47 - XMM2a, XMM2b,
1.48 - XMM3a, XMM3b,
1.49 - XMM4a, XMM4b,
1.50 - XMM5a, XMM5b,
1.51 - XMM6a, XMM6b,
1.52 - XMM7a, XMM7b, EFLAGS);
1.53 -
1.54
1.55 //----------Architecture Description Register Classes--------------------------
1.56 // Several register classes are automatically defined based upon information in
1.57 @@ -159,12 +126,12 @@
1.58 // Class for all registers
1.59 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
1.60 // Class for general registers
1.61 -reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
1.62 +reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
1.63 // Class for general registers which may be used for implicit null checks on win95
1.64 // Also safe for use by tailjump. We don't want to allocate in rbp,
1.65 -reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
1.66 +reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
1.67 // Class of "X" registers
1.68 -reg_class x_reg(EBX, ECX, EDX, EAX);
1.69 +reg_class int_x_reg(EBX, ECX, EDX, EAX);
1.70 // Class of registers that can appear in an address with no offset.
1.71 // EBP and ESP require an extra instruction byte for zero offset.
1.72 // Used in fast-unlock
1.73 @@ -193,8 +160,6 @@
1.74 reg_class sp_reg(ESP);
1.75 // Singleton class for instruction pointer
1.76 // reg_class ip_reg(EIP);
1.77 -// Singleton class for condition codes
1.78 -reg_class int_flags(EFLAGS);
1.79 // Class of integer register pairs
1.80 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
1.81 // Class of integer register pairs that aligns with calling convention
1.82 @@ -206,29 +171,18 @@
1.83 // Floating point registers. Notice FPR0 is not a choice.
1.84 // FPR0 is not ever allocated; we use clever encodings to fake
1.85 // a 2-address instructions out of Intels FP stack.
1.86 -reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
1.87 -
1.88 -// make a register class for SSE registers
1.89 -reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a);
1.90 -
1.91 -// make a double register class for SSE2 registers
1.92 -reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b,
1.93 - XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b );
1.94 -
1.95 -reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
1.96 - FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
1.97 - FPR7L,FPR7H );
1.98 -
1.99 -reg_class flt_reg0( FPR1L );
1.100 -reg_class dbl_reg0( FPR1L,FPR1H );
1.101 -reg_class dbl_reg1( FPR2L,FPR2H );
1.102 -reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
1.103 - FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
1.104 -
1.105 -// XMM6 and XMM7 could be used as temporary registers for long, float and
1.106 -// double values for SSE2.
1.107 -reg_class xdb_reg6( XMM6a,XMM6b );
1.108 -reg_class xdb_reg7( XMM7a,XMM7b );
1.109 +reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
1.110 +
1.111 +reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
1.112 + FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
1.113 + FPR7L,FPR7H );
1.114 +
1.115 +reg_class fp_flt_reg0( FPR1L );
1.116 +reg_class fp_dbl_reg0( FPR1L,FPR1H );
1.117 +reg_class fp_dbl_reg1( FPR2L,FPR2H );
1.118 +reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
1.119 + FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
1.120 +
1.121 %}
1.122
1.123
1.124 @@ -412,7 +366,7 @@
1.125 }
1.126 }
1.127
1.128 - // eRegI ereg, memory mem) %{ // emit_reg_mem
1.129 + // rRegI ereg, memory mem) %{ // emit_reg_mem
1.130 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) {
1.131 // There is no index & no scale, use form without SIB byte
1.132 if ((index == 0x4) &&
1.133 @@ -787,7 +741,7 @@
1.134 #endif
1.135 }
1.136 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1.137 - // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes.
1.138 + // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
1.139 return size+5+offset_size;
1.140 }
1.141
1.142 @@ -821,7 +775,7 @@
1.143 }
1.144 #endif
1.145 }
1.146 - // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes.
1.147 + // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
1.148 // Only MOVAPS SSE prefix uses 1 byte.
1.149 int sz = 4;
1.150 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
1.151 @@ -903,6 +857,108 @@
1.152 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
1.153 }
1.154
1.155 +// Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
1.156 +static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
1.157 + int src_hi, int dst_hi, uint ireg, outputStream* st);
1.158 +
1.159 +static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
1.160 + int stack_offset, int reg, uint ireg, outputStream* st);
1.161 +
1.162 +static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset,
1.163 + int dst_offset, uint ireg, outputStream* st) {
1.164 + int calc_size = 0;
1.165 + int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
1.166 + int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
1.167 + switch (ireg) {
1.168 + case Op_VecS:
1.169 + calc_size = 3+src_offset_size + 3+dst_offset_size;
1.170 + break;
1.171 + case Op_VecD:
1.172 + calc_size = 3+src_offset_size + 3+dst_offset_size;
1.173 + src_offset += 4;
1.174 + dst_offset += 4;
1.175 + src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
1.176 + dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
1.177 + calc_size += 3+src_offset_size + 3+dst_offset_size;
1.178 + break;
1.179 + case Op_VecX:
1.180 + calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
1.181 + break;
1.182 + case Op_VecY:
1.183 + calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
1.184 + break;
1.185 + default:
1.186 + ShouldNotReachHere();
1.187 + }
1.188 + if (cbuf) {
1.189 + MacroAssembler _masm(cbuf);
1.190 + int offset = __ offset();
1.191 + switch (ireg) {
1.192 + case Op_VecS:
1.193 + __ pushl(Address(rsp, src_offset));
1.194 + __ popl (Address(rsp, dst_offset));
1.195 + break;
1.196 + case Op_VecD:
1.197 + __ pushl(Address(rsp, src_offset));
1.198 + __ popl (Address(rsp, dst_offset));
1.199 + __ pushl(Address(rsp, src_offset+4));
1.200 + __ popl (Address(rsp, dst_offset+4));
1.201 + break;
1.202 + case Op_VecX:
1.203 + __ movdqu(Address(rsp, -16), xmm0);
1.204 + __ movdqu(xmm0, Address(rsp, src_offset));
1.205 + __ movdqu(Address(rsp, dst_offset), xmm0);
1.206 + __ movdqu(xmm0, Address(rsp, -16));
1.207 + break;
1.208 + case Op_VecY:
1.209 + __ vmovdqu(Address(rsp, -32), xmm0);
1.210 + __ vmovdqu(xmm0, Address(rsp, src_offset));
1.211 + __ vmovdqu(Address(rsp, dst_offset), xmm0);
1.212 + __ vmovdqu(xmm0, Address(rsp, -32));
1.213 + break;
1.214 + default:
1.215 + ShouldNotReachHere();
1.216 + }
1.217 + int size = __ offset() - offset;
1.218 + assert(size == calc_size, "incorrect size calculattion");
1.219 + return size;
1.220 +#ifndef PRODUCT
1.221 + } else if (!do_size) {
1.222 + switch (ireg) {
1.223 + case Op_VecS:
1.224 + st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t"
1.225 + "popl [rsp + #%d]",
1.226 + src_offset, dst_offset);
1.227 + break;
1.228 + case Op_VecD:
1.229 + st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1.230 + "popq [rsp + #%d]\n\t"
1.231 + "pushl [rsp + #%d]\n\t"
1.232 + "popq [rsp + #%d]",
1.233 + src_offset, dst_offset, src_offset+4, dst_offset+4);
1.234 + break;
1.235 + case Op_VecX:
1.236 + st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t"
1.237 + "movdqu xmm0, [rsp + #%d]\n\t"
1.238 + "movdqu [rsp + #%d], xmm0\n\t"
1.239 + "movdqu xmm0, [rsp - #16]",
1.240 + src_offset, dst_offset);
1.241 + break;
1.242 + case Op_VecY:
1.243 + st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
1.244 + "vmovdqu xmm0, [rsp + #%d]\n\t"
1.245 + "vmovdqu [rsp + #%d], xmm0\n\t"
1.246 + "vmovdqu xmm0, [rsp - #32]",
1.247 + src_offset, dst_offset);
1.248 + break;
1.249 + default:
1.250 + ShouldNotReachHere();
1.251 + }
1.252 +#endif
1.253 + }
1.254 + return calc_size;
1.255 +}
1.256 +
1.257 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
1.258 // Get registers to move
1.259 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1.260 @@ -923,6 +979,29 @@
1.261 if( src_first == dst_first && src_second == dst_second )
1.262 return size; // Self copy, no move
1.263
1.264 + if (bottom_type()->isa_vect() != NULL) {
1.265 + uint ireg = ideal_reg();
1.266 + assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1.267 + assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity");
1.268 + assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
1.269 + if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1.270 + // mem -> mem
1.271 + int src_offset = ra_->reg2offset(src_first);
1.272 + int dst_offset = ra_->reg2offset(dst_first);
1.273 + return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st);
1.274 + } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1.275 + return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st);
1.276 + } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1.277 + int stack_offset = ra_->reg2offset(dst_first);
1.278 + return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st);
1.279 + } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) {
1.280 + int stack_offset = ra_->reg2offset(src_first);
1.281 + return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st);
1.282 + } else {
1.283 + ShouldNotReachHere();
1.284 + }
1.285 + }
1.286 +
1.287 // --------------------------------------
1.288 // Check for mem-mem move. push/pop to move.
1.289 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1.290 @@ -1313,16 +1392,6 @@
1.291 return true;
1.292 }
1.293
1.294 -// Vector width in bytes
1.295 -const uint Matcher::vector_width_in_bytes(void) {
1.296 - return UseSSE >= 2 ? 8 : 0;
1.297 -}
1.298 -
1.299 -// Vector ideal reg
1.300 -const uint Matcher::vector_ideal_reg(void) {
1.301 - return Op_RegD;
1.302 -}
1.303 -
1.304 // Is this branch offset short enough that a short branch can be used?
1.305 //
1.306 // NOTE: If the platform does not provide any short branch variants, then
1.307 @@ -1452,7 +1521,7 @@
1.308 // arguments in those registers not be available to the callee.
1.309 bool Matcher::can_be_java_arg( int reg ) {
1.310 if( reg == ECX_num || reg == EDX_num ) return true;
1.311 - if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true;
1.312 + if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true;
1.313 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1.314 return false;
1.315 }
1.316 @@ -1565,16 +1634,16 @@
1.317 emit_opcode(cbuf,0x66);
1.318 %}
1.319
1.320 - enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
1.321 + enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1.322 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1.323 %}
1.324
1.325 - enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many)
1.326 + enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many)
1.327 emit_opcode(cbuf,$opcode$$constant);
1.328 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1.329 %}
1.330
1.331 - enc_class mov_r32_imm0( eRegI dst ) %{
1.332 + enc_class mov_r32_imm0( rRegI dst ) %{
1.333 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1.334 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1.335 %}
1.336 @@ -1621,7 +1690,7 @@
1.337 %}
1.338
1.339 // Dense encoding for older common ops
1.340 - enc_class Opc_plus(immI opcode, eRegI reg) %{
1.341 + enc_class Opc_plus(immI opcode, rRegI reg) %{
1.342 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1.343 %}
1.344
1.345 @@ -1637,7 +1706,7 @@
1.346 }
1.347 %}
1.348
1.349 - enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m
1.350 + enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m
1.351 // Emit primary opcode and set sign-extend bit
1.352 // Check for 8-bit immediate, and set sign extend bit in opcode
1.353 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1.354 @@ -1682,7 +1751,7 @@
1.355 else emit_d32(cbuf,con);
1.356 %}
1.357
1.358 - enc_class OpcSReg (eRegI dst) %{ // BSWAP
1.359 + enc_class OpcSReg (rRegI dst) %{ // BSWAP
1.360 emit_cc(cbuf, $secondary, $dst$$reg );
1.361 %}
1.362
1.363 @@ -1700,7 +1769,7 @@
1.364 emit_rm(cbuf, 0x3, destlo, desthi);
1.365 %}
1.366
1.367 - enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1.368 + enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1.369 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1.370 %}
1.371
1.372 @@ -1891,20 +1960,20 @@
1.373 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1.374 // %}
1.375
1.376 - enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1.377 + enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1.378 $$$emit8$primary;
1.379 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1.380 $$$emit8$shift$$constant;
1.381 %}
1.382
1.383 - enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate
1.384 + enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate
1.385 // Load immediate does not have a zero or sign extended version
1.386 // for 8-bit immediates
1.387 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1.388 $$$emit32$src$$constant;
1.389 %}
1.390
1.391 - enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate
1.392 + enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate
1.393 // Load immediate does not have a zero or sign extended version
1.394 // for 8-bit immediates
1.395 emit_opcode(cbuf, $primary + $dst$$reg);
1.396 @@ -1943,15 +2012,15 @@
1.397
1.398
1.399 // Encode a reg-reg copy. If it is useless, then empty encoding.
1.400 - enc_class enc_Copy( eRegI dst, eRegI src ) %{
1.401 + enc_class enc_Copy( rRegI dst, rRegI src ) %{
1.402 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1.403 %}
1.404
1.405 - enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{
1.406 + enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{
1.407 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1.408 %}
1.409
1.410 - enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
1.411 + enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1.412 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1.413 %}
1.414
1.415 @@ -1973,7 +2042,7 @@
1.416 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
1.417 %}
1.418
1.419 - enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{
1.420 + enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{
1.421 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
1.422 %}
1.423
1.424 @@ -2068,7 +2137,7 @@
1.425 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
1.426 %}
1.427
1.428 - enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem
1.429 + enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem
1.430 int reg_encoding = $ereg$$reg;
1.431 int base = $mem$$base;
1.432 int index = $mem$$index;
1.433 @@ -2132,7 +2201,7 @@
1.434
1.435 // Clone of RegMem but accepts an extra parameter to access each
1.436 // half of a double in memory; it never needs relocation info.
1.437 - enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{
1.438 + enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{
1.439 emit_opcode(cbuf,$opcode$$constant);
1.440 int reg_encoding = $rm_reg$$reg;
1.441 int base = $mem$$base;
1.442 @@ -2168,7 +2237,7 @@
1.443 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
1.444 %}
1.445
1.446 - enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea
1.447 + enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea
1.448 int reg_encoding = $dst$$reg;
1.449 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
1.450 int index = 0x04; // 0x04 indicates no index
1.451 @@ -2178,7 +2247,7 @@
1.452 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
1.453 %}
1.454
1.455 - enc_class min_enc (eRegI dst, eRegI src) %{ // MIN
1.456 + enc_class min_enc (rRegI dst, rRegI src) %{ // MIN
1.457 // Compare dst,src
1.458 emit_opcode(cbuf,0x3B);
1.459 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1.460 @@ -2190,7 +2259,7 @@
1.461 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1.462 %}
1.463
1.464 - enc_class max_enc (eRegI dst, eRegI src) %{ // MAX
1.465 + enc_class max_enc (rRegI dst, rRegI src) %{ // MAX
1.466 // Compare dst,src
1.467 emit_opcode(cbuf,0x3B);
1.468 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1.469 @@ -2221,7 +2290,7 @@
1.470 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
1.471 %}
1.472
1.473 - enc_class neg_reg(eRegI dst) %{
1.474 + enc_class neg_reg(rRegI dst) %{
1.475 // NEG $dst
1.476 emit_opcode(cbuf,0xF7);
1.477 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
1.478 @@ -2251,7 +2320,7 @@
1.479 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
1.480 %}
1.481
1.482 - enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
1.483 + enc_class enc_cmpLTP_mem(rRegI p, rRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
1.484 int tmpReg = $tmp$$reg;
1.485
1.486 // SUB $p,$q
1.487 @@ -2390,12 +2459,12 @@
1.488 %}
1.489
1.490 // Special case for moving an integer register to a stack slot.
1.491 - enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS
1.492 + enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS
1.493 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
1.494 %}
1.495
1.496 // Special case for moving a register to a stack slot.
1.497 - enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS
1.498 + enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS
1.499 // Opcode already emitted
1.500 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
1.501 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
1.502 @@ -2640,7 +2709,7 @@
1.503 // equal_result = 0;
1.504 // nan_result = -1;
1.505
1.506 - enc_class CmpF_Result(eRegI dst) %{
1.507 + enc_class CmpF_Result(rRegI dst) %{
1.508 // fnstsw_ax();
1.509 emit_opcode( cbuf, 0xDF);
1.510 emit_opcode( cbuf, 0xE0);
1.511 @@ -2685,7 +2754,7 @@
1.512 // done:
1.513 %}
1.514
1.515 - enc_class convert_int_long( regL dst, eRegI src ) %{
1.516 + enc_class convert_int_long( regL dst, rRegI src ) %{
1.517 // mov $dst.lo,$src
1.518 int dst_encoding = $dst$$reg;
1.519 int src_encoding = $src$$reg;
1.520 @@ -2754,7 +2823,7 @@
1.521 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
1.522 %}
1.523
1.524 - enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{
1.525 + enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{
1.526 // Basic idea: lo(result) = lo(x_lo * y_lo)
1.527 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
1.528 // MOV $tmp,$src.lo
1.529 @@ -2780,7 +2849,7 @@
1.530 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
1.531 %}
1.532
1.533 - enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{
1.534 + enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{
1.535 // Basic idea: lo(result) = lo(src * y_lo)
1.536 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
1.537 // IMUL $tmp,EDX,$src
1.538 @@ -2836,7 +2905,7 @@
1.539 emit_d8(cbuf, 4*4);
1.540 %}
1.541
1.542 - enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{
1.543 + enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{
1.544 // MOV $tmp,$src.lo
1.545 emit_opcode(cbuf, 0x8B);
1.546 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
1.547 @@ -2857,7 +2926,7 @@
1.548 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
1.549 %}
1.550
1.551 - enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{
1.552 + enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{
1.553 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
1.554 emit_opcode( cbuf, 0x3B );
1.555 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
1.556 @@ -2869,7 +2938,7 @@
1.557 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
1.558 %}
1.559
1.560 - enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{
1.561 + enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{
1.562 // XOR $tmp,$tmp
1.563 emit_opcode(cbuf,0x33); // XOR
1.564 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
1.565 @@ -3762,9 +3831,9 @@
1.566 // in SSE2+ mode we want to keep the FPU stack clean so pretend
1.567 // that C functions return float and double results in XMM0.
1.568 if( ideal_reg == Op_RegD && UseSSE>=2 )
1.569 - return OptoRegPair(XMM0b_num,XMM0a_num);
1.570 + return OptoRegPair(XMM0b_num,XMM0_num);
1.571 if( ideal_reg == Op_RegF && UseSSE>=2 )
1.572 - return OptoRegPair(OptoReg::Bad,XMM0a_num);
1.573 + return OptoRegPair(OptoReg::Bad,XMM0_num);
1.574
1.575 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
1.576 %}
1.577 @@ -3775,9 +3844,9 @@
1.578 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
1.579 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
1.580 if( ideal_reg == Op_RegD && UseSSE>=2 )
1.581 - return OptoRegPair(XMM0b_num,XMM0a_num);
1.582 + return OptoRegPair(XMM0b_num,XMM0_num);
1.583 if( ideal_reg == Op_RegF && UseSSE>=1 )
1.584 - return OptoRegPair(OptoReg::Bad,XMM0a_num);
1.585 + return OptoRegPair(OptoReg::Bad,XMM0_num);
1.586 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
1.587 %}
1.588
1.589 @@ -4147,8 +4216,8 @@
1.590
1.591 // Register Operands
1.592 // Integer Register
1.593 -operand eRegI() %{
1.594 - constraint(ALLOC_IN_RC(e_reg));
1.595 +operand rRegI() %{
1.596 + constraint(ALLOC_IN_RC(int_reg));
1.597 match(RegI);
1.598 match(xRegI);
1.599 match(eAXRegI);
1.600 @@ -4163,8 +4232,8 @@
1.601 %}
1.602
1.603 // Subset of Integer Register
1.604 -operand xRegI(eRegI reg) %{
1.605 - constraint(ALLOC_IN_RC(x_reg));
1.606 +operand xRegI(rRegI reg) %{
1.607 + constraint(ALLOC_IN_RC(int_x_reg));
1.608 match(reg);
1.609 match(eAXRegI);
1.610 match(eBXRegI);
1.611 @@ -4179,7 +4248,7 @@
1.612 operand eAXRegI(xRegI reg) %{
1.613 constraint(ALLOC_IN_RC(eax_reg));
1.614 match(reg);
1.615 - match(eRegI);
1.616 + match(rRegI);
1.617
1.618 format %{ "EAX" %}
1.619 interface(REG_INTER);
1.620 @@ -4189,7 +4258,7 @@
1.621 operand eBXRegI(xRegI reg) %{
1.622 constraint(ALLOC_IN_RC(ebx_reg));
1.623 match(reg);
1.624 - match(eRegI);
1.625 + match(rRegI);
1.626
1.627 format %{ "EBX" %}
1.628 interface(REG_INTER);
1.629 @@ -4198,7 +4267,7 @@
1.630 operand eCXRegI(xRegI reg) %{
1.631 constraint(ALLOC_IN_RC(ecx_reg));
1.632 match(reg);
1.633 - match(eRegI);
1.634 + match(rRegI);
1.635
1.636 format %{ "ECX" %}
1.637 interface(REG_INTER);
1.638 @@ -4207,7 +4276,7 @@
1.639 operand eDXRegI(xRegI reg) %{
1.640 constraint(ALLOC_IN_RC(edx_reg));
1.641 match(reg);
1.642 - match(eRegI);
1.643 + match(rRegI);
1.644
1.645 format %{ "EDX" %}
1.646 interface(REG_INTER);
1.647 @@ -4216,7 +4285,7 @@
1.648 operand eDIRegI(xRegI reg) %{
1.649 constraint(ALLOC_IN_RC(edi_reg));
1.650 match(reg);
1.651 - match(eRegI);
1.652 + match(rRegI);
1.653
1.654 format %{ "EDI" %}
1.655 interface(REG_INTER);
1.656 @@ -4263,7 +4332,7 @@
1.657 operand eSIRegI(xRegI reg) %{
1.658 constraint(ALLOC_IN_RC(esi_reg));
1.659 match(reg);
1.660 - match(eRegI);
1.661 + match(rRegI);
1.662
1.663 format %{ "ESI" %}
1.664 interface(REG_INTER);
1.665 @@ -4284,7 +4353,7 @@
1.666 %}
1.667
1.668 operand eRegP() %{
1.669 - constraint(ALLOC_IN_RC(e_reg));
1.670 + constraint(ALLOC_IN_RC(int_reg));
1.671 match(RegP);
1.672 match(eAXRegP);
1.673 match(eBXRegP);
1.674 @@ -4297,7 +4366,7 @@
1.675
1.676 // On windows95, EBP is not safe to use for implicit null tests.
1.677 operand eRegP_no_EBP() %{
1.678 - constraint(ALLOC_IN_RC(e_reg_no_rbp));
1.679 + constraint(ALLOC_IN_RC(int_reg_no_rbp));
1.680 match(RegP);
1.681 match(eAXRegP);
1.682 match(eBXRegP);
1.683 @@ -4477,7 +4546,7 @@
1.684 // Float register operands
1.685 operand regDPR() %{
1.686 predicate( UseSSE < 2 );
1.687 - constraint(ALLOC_IN_RC(dbl_reg));
1.688 + constraint(ALLOC_IN_RC(fp_dbl_reg));
1.689 match(RegD);
1.690 match(regDPR1);
1.691 match(regDPR2);
1.692 @@ -4487,7 +4556,7 @@
1.693
1.694 operand regDPR1(regDPR reg) %{
1.695 predicate( UseSSE < 2 );
1.696 - constraint(ALLOC_IN_RC(dbl_reg0));
1.697 + constraint(ALLOC_IN_RC(fp_dbl_reg0));
1.698 match(reg);
1.699 format %{ "FPR1" %}
1.700 interface(REG_INTER);
1.701 @@ -4495,7 +4564,7 @@
1.702
1.703 operand regDPR2(regDPR reg) %{
1.704 predicate( UseSSE < 2 );
1.705 - constraint(ALLOC_IN_RC(dbl_reg1));
1.706 + constraint(ALLOC_IN_RC(fp_dbl_reg1));
1.707 match(reg);
1.708 format %{ "FPR2" %}
1.709 interface(REG_INTER);
1.710 @@ -4503,45 +4572,16 @@
1.711
1.712 operand regnotDPR1(regDPR reg) %{
1.713 predicate( UseSSE < 2 );
1.714 - constraint(ALLOC_IN_RC(dbl_notreg0));
1.715 + constraint(ALLOC_IN_RC(fp_dbl_notreg0));
1.716 match(reg);
1.717 format %{ %}
1.718 interface(REG_INTER);
1.719 %}
1.720
1.721 -// XMM Double register operands
1.722 -operand regD() %{
1.723 - predicate( UseSSE>=2 );
1.724 - constraint(ALLOC_IN_RC(xdb_reg));
1.725 - match(RegD);
1.726 - match(regD6);
1.727 - match(regD7);
1.728 - format %{ %}
1.729 - interface(REG_INTER);
1.730 -%}
1.731 -
1.732 -// XMM6 double register operands
1.733 -operand regD6(regD reg) %{
1.734 - predicate( UseSSE>=2 );
1.735 - constraint(ALLOC_IN_RC(xdb_reg6));
1.736 - match(reg);
1.737 - format %{ "XMM6" %}
1.738 - interface(REG_INTER);
1.739 -%}
1.740 -
1.741 -// XMM7 double register operands
1.742 -operand regD7(regD reg) %{
1.743 - predicate( UseSSE>=2 );
1.744 - constraint(ALLOC_IN_RC(xdb_reg7));
1.745 - match(reg);
1.746 - format %{ "XMM7" %}
1.747 - interface(REG_INTER);
1.748 -%}
1.749 -
1.750 // Float register operands
1.751 operand regFPR() %{
1.752 predicate( UseSSE < 2 );
1.753 - constraint(ALLOC_IN_RC(flt_reg));
1.754 + constraint(ALLOC_IN_RC(fp_flt_reg));
1.755 match(RegF);
1.756 match(regFPR1);
1.757 format %{ %}
1.758 @@ -4551,21 +4591,30 @@
1.759 // Float register operands
1.760 operand regFPR1(regFPR reg) %{
1.761 predicate( UseSSE < 2 );
1.762 - constraint(ALLOC_IN_RC(flt_reg0));
1.763 + constraint(ALLOC_IN_RC(fp_flt_reg0));
1.764 match(reg);
1.765 format %{ "FPR1" %}
1.766 interface(REG_INTER);
1.767 %}
1.768
1.769 -// XMM register operands
1.770 +// XMM Float register operands
1.771 operand regF() %{
1.772 predicate( UseSSE>=1 );
1.773 - constraint(ALLOC_IN_RC(xmm_reg));
1.774 + constraint(ALLOC_IN_RC(float_reg));
1.775 match(RegF);
1.776 format %{ %}
1.777 interface(REG_INTER);
1.778 %}
1.779
1.780 +// XMM Double register operands
1.781 +operand regD() %{
1.782 + predicate( UseSSE>=2 );
1.783 + constraint(ALLOC_IN_RC(double_reg));
1.784 + match(RegD);
1.785 + format %{ %}
1.786 + interface(REG_INTER);
1.787 +%}
1.788 +
1.789
1.790 //----------Memory Operands----------------------------------------------------
1.791 // Direct Memory Operand
1.792 @@ -4583,7 +4632,7 @@
1.793
1.794 // Indirect Memory Operand
1.795 operand indirect(eRegP reg) %{
1.796 - constraint(ALLOC_IN_RC(e_reg));
1.797 + constraint(ALLOC_IN_RC(int_reg));
1.798 match(reg);
1.799
1.800 format %{ "[$reg]" %}
1.801 @@ -4622,7 +4671,7 @@
1.802 %}
1.803
1.804 // Indirect Memory Plus Long Offset Operand
1.805 -operand indOffset32X(eRegI reg, immP off) %{
1.806 +operand indOffset32X(rRegI reg, immP off) %{
1.807 match(AddP off reg);
1.808
1.809 format %{ "[$reg + $off]" %}
1.810 @@ -4635,7 +4684,7 @@
1.811 %}
1.812
1.813 // Indirect Memory Plus Index Register Plus Offset Operand
1.814 -operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{
1.815 +operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{
1.816 match(AddP (AddP reg ireg) off);
1.817
1.818 op_cost(10);
1.819 @@ -4649,7 +4698,7 @@
1.820 %}
1.821
1.822 // Indirect Memory Plus Index Register Plus Offset Operand
1.823 -operand indIndex(eRegP reg, eRegI ireg) %{
1.824 +operand indIndex(eRegP reg, rRegI ireg) %{
1.825 match(AddP reg ireg);
1.826
1.827 op_cost(10);
1.828 @@ -4667,7 +4716,7 @@
1.829 // // -------------------------------------------------------------------------
1.830 // // Scaled Memory Operands
1.831 // // Indirect Memory Times Scale Plus Offset Operand
1.832 -// operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{
1.833 +// operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{
1.834 // match(AddP off (LShiftI ireg scale));
1.835 //
1.836 // op_cost(10);
1.837 @@ -4681,7 +4730,7 @@
1.838 // %}
1.839
1.840 // Indirect Memory Times Scale Plus Index Register
1.841 -operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{
1.842 +operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{
1.843 match(AddP reg (LShiftI ireg scale));
1.844
1.845 op_cost(10);
1.846 @@ -4695,7 +4744,7 @@
1.847 %}
1.848
1.849 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
1.850 -operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{
1.851 +operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{
1.852 match(AddP (AddP reg (LShiftI ireg scale)) off);
1.853
1.854 op_cost(10);
1.855 @@ -4823,7 +4872,7 @@
1.856 // Indirect Memory Operand
1.857 operand indirect_win95_safe(eRegP_no_EBP reg)
1.858 %{
1.859 - constraint(ALLOC_IN_RC(e_reg));
1.860 + constraint(ALLOC_IN_RC(int_reg));
1.861 match(reg);
1.862
1.863 op_cost(100);
1.864 @@ -4867,7 +4916,7 @@
1.865 %}
1.866
1.867 // Indirect Memory Plus Index Register Plus Offset Operand
1.868 -operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off)
1.869 +operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off)
1.870 %{
1.871 match(AddP (AddP reg ireg) off);
1.872
1.873 @@ -4882,7 +4931,7 @@
1.874 %}
1.875
1.876 // Indirect Memory Times Scale Plus Index Register
1.877 -operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale)
1.878 +operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale)
1.879 %{
1.880 match(AddP reg (LShiftI ireg scale));
1.881
1.882 @@ -4897,7 +4946,7 @@
1.883 %}
1.884
1.885 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
1.886 -operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale)
1.887 +operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale)
1.888 %{
1.889 match(AddP (AddP reg (LShiftI ireg scale)) off);
1.890
1.891 @@ -5086,7 +5135,7 @@
1.892 // Or: _mem if it requires the big decoder and a memory unit.
1.893
1.894 // Integer ALU reg operation
1.895 -pipe_class ialu_reg(eRegI dst) %{
1.896 +pipe_class ialu_reg(rRegI dst) %{
1.897 single_instruction;
1.898 dst : S4(write);
1.899 dst : S3(read);
1.900 @@ -5104,7 +5153,7 @@
1.901 %}
1.902
1.903 // Integer ALU reg operation using big decoder
1.904 -pipe_class ialu_reg_fat(eRegI dst) %{
1.905 +pipe_class ialu_reg_fat(rRegI dst) %{
1.906 single_instruction;
1.907 dst : S4(write);
1.908 dst : S3(read);
1.909 @@ -5122,7 +5171,7 @@
1.910 %}
1.911
1.912 // Integer ALU reg-reg operation
1.913 -pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{
1.914 +pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{
1.915 single_instruction;
1.916 dst : S4(write);
1.917 src : S3(read);
1.918 @@ -5140,7 +5189,7 @@
1.919 %}
1.920
1.921 // Integer ALU reg-reg operation
1.922 -pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{
1.923 +pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{
1.924 single_instruction;
1.925 dst : S4(write);
1.926 src : S3(read);
1.927 @@ -5158,7 +5207,7 @@
1.928 %}
1.929
1.930 // Integer ALU reg-mem operation
1.931 -pipe_class ialu_reg_mem(eRegI dst, memory mem) %{
1.932 +pipe_class ialu_reg_mem(rRegI dst, memory mem) %{
1.933 single_instruction;
1.934 dst : S5(write);
1.935 mem : S3(read);
1.936 @@ -5187,7 +5236,7 @@
1.937 %}
1.938
1.939 // Integer Store to Memory
1.940 -pipe_class ialu_mem_reg(memory mem, eRegI src) %{
1.941 +pipe_class ialu_mem_reg(memory mem, rRegI src) %{
1.942 single_instruction;
1.943 mem : S3(read);
1.944 src : S5(read);
1.945 @@ -5216,7 +5265,7 @@
1.946 %}
1.947
1.948 // Integer ALU0 reg-reg operation
1.949 -pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{
1.950 +pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{
1.951 single_instruction;
1.952 dst : S4(write);
1.953 src : S3(read);
1.954 @@ -5225,7 +5274,7 @@
1.955 %}
1.956
1.957 // Integer ALU0 reg-mem operation
1.958 -pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{
1.959 +pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{
1.960 single_instruction;
1.961 dst : S5(write);
1.962 mem : S3(read);
1.963 @@ -5235,7 +5284,7 @@
1.964 %}
1.965
1.966 // Integer ALU reg-reg operation
1.967 -pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{
1.968 +pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{
1.969 single_instruction;
1.970 cr : S4(write);
1.971 src1 : S3(read);
1.972 @@ -5245,7 +5294,7 @@
1.973 %}
1.974
1.975 // Integer ALU reg-imm operation
1.976 -pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{
1.977 +pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{
1.978 single_instruction;
1.979 cr : S4(write);
1.980 src1 : S3(read);
1.981 @@ -5254,7 +5303,7 @@
1.982 %}
1.983
1.984 // Integer ALU reg-mem operation
1.985 -pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{
1.986 +pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{
1.987 single_instruction;
1.988 cr : S4(write);
1.989 src1 : S3(read);
1.990 @@ -5265,7 +5314,7 @@
1.991 %}
1.992
1.993 // Conditional move reg-reg
1.994 -pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{
1.995 +pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{
1.996 instruction_count(4);
1.997 y : S4(read);
1.998 q : S3(read);
1.999 @@ -5274,7 +5323,7 @@
1.1000 %}
1.1001
1.1002 // Conditional move reg-reg
1.1003 -pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{
1.1004 +pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{
1.1005 single_instruction;
1.1006 dst : S4(write);
1.1007 src : S3(read);
1.1008 @@ -5283,7 +5332,7 @@
1.1009 %}
1.1010
1.1011 // Conditional move reg-mem
1.1012 -pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{
1.1013 +pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{
1.1014 single_instruction;
1.1015 dst : S4(write);
1.1016 src : S3(read);
1.1017 @@ -5534,7 +5583,7 @@
1.1018 // in the encode section of the architecture description.
1.1019
1.1020 //----------BSWAP-Instruction--------------------------------------------------
1.1021 -instruct bytes_reverse_int(eRegI dst) %{
1.1022 +instruct bytes_reverse_int(rRegI dst) %{
1.1023 match(Set dst (ReverseBytesI dst));
1.1024
1.1025 format %{ "BSWAP $dst" %}
1.1026 @@ -5555,7 +5604,7 @@
1.1027 ins_pipe( ialu_reg_reg);
1.1028 %}
1.1029
1.1030 -instruct bytes_reverse_unsigned_short(eRegI dst, eFlagsReg cr) %{
1.1031 +instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{
1.1032 match(Set dst (ReverseBytesUS dst));
1.1033 effect(KILL cr);
1.1034
1.1035 @@ -5568,7 +5617,7 @@
1.1036 ins_pipe( ialu_reg );
1.1037 %}
1.1038
1.1039 -instruct bytes_reverse_short(eRegI dst, eFlagsReg cr) %{
1.1040 +instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{
1.1041 match(Set dst (ReverseBytesS dst));
1.1042 effect(KILL cr);
1.1043
1.1044 @@ -5584,7 +5633,7 @@
1.1045
1.1046 //---------- Zeros Count Instructions ------------------------------------------
1.1047
1.1048 -instruct countLeadingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
1.1049 +instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
1.1050 predicate(UseCountLeadingZerosInstruction);
1.1051 match(Set dst (CountLeadingZerosI src));
1.1052 effect(KILL cr);
1.1053 @@ -5596,7 +5645,7 @@
1.1054 ins_pipe(ialu_reg);
1.1055 %}
1.1056
1.1057 -instruct countLeadingZerosI_bsr(eRegI dst, eRegI src, eFlagsReg cr) %{
1.1058 +instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{
1.1059 predicate(!UseCountLeadingZerosInstruction);
1.1060 match(Set dst (CountLeadingZerosI src));
1.1061 effect(KILL cr);
1.1062 @@ -5621,7 +5670,7 @@
1.1063 ins_pipe(ialu_reg);
1.1064 %}
1.1065
1.1066 -instruct countLeadingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
1.1067 +instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
1.1068 predicate(UseCountLeadingZerosInstruction);
1.1069 match(Set dst (CountLeadingZerosL src));
1.1070 effect(TEMP dst, KILL cr);
1.1071 @@ -5644,7 +5693,7 @@
1.1072 ins_pipe(ialu_reg);
1.1073 %}
1.1074
1.1075 -instruct countLeadingZerosL_bsr(eRegI dst, eRegL src, eFlagsReg cr) %{
1.1076 +instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{
1.1077 predicate(!UseCountLeadingZerosInstruction);
1.1078 match(Set dst (CountLeadingZerosL src));
1.1079 effect(TEMP dst, KILL cr);
1.1080 @@ -5680,7 +5729,7 @@
1.1081 ins_pipe(ialu_reg);
1.1082 %}
1.1083
1.1084 -instruct countTrailingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
1.1085 +instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
1.1086 match(Set dst (CountTrailingZerosI src));
1.1087 effect(KILL cr);
1.1088
1.1089 @@ -5699,7 +5748,7 @@
1.1090 ins_pipe(ialu_reg);
1.1091 %}
1.1092
1.1093 -instruct countTrailingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
1.1094 +instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
1.1095 match(Set dst (CountTrailingZerosL src));
1.1096 effect(TEMP dst, KILL cr);
1.1097
1.1098 @@ -5731,7 +5780,7 @@
1.1099
1.1100 //---------- Population Count Instructions -------------------------------------
1.1101
1.1102 -instruct popCountI(eRegI dst, eRegI src, eFlagsReg cr) %{
1.1103 +instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{
1.1104 predicate(UsePopCountInstruction);
1.1105 match(Set dst (PopCountI src));
1.1106 effect(KILL cr);
1.1107 @@ -5743,7 +5792,7 @@
1.1108 ins_pipe(ialu_reg);
1.1109 %}
1.1110
1.1111 -instruct popCountI_mem(eRegI dst, memory mem, eFlagsReg cr) %{
1.1112 +instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{
1.1113 predicate(UsePopCountInstruction);
1.1114 match(Set dst (PopCountI (LoadI mem)));
1.1115 effect(KILL cr);
1.1116 @@ -5756,7 +5805,7 @@
1.1117 %}
1.1118
1.1119 // Note: Long.bitCount(long) returns an int.
1.1120 -instruct popCountL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
1.1121 +instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
1.1122 predicate(UsePopCountInstruction);
1.1123 match(Set dst (PopCountL src));
1.1124 effect(KILL cr, TEMP tmp, TEMP dst);
1.1125 @@ -5773,7 +5822,7 @@
1.1126 %}
1.1127
1.1128 // Note: Long.bitCount(long) returns an int.
1.1129 -instruct popCountL_mem(eRegI dst, memory mem, eRegI tmp, eFlagsReg cr) %{
1.1130 +instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{
1.1131 predicate(UsePopCountInstruction);
1.1132 match(Set dst (PopCountL (LoadL mem)));
1.1133 effect(KILL cr, TEMP tmp, TEMP dst);
1.1134 @@ -5877,7 +5926,7 @@
1.1135 %}
1.1136
1.1137 // Load Short (16bit signed)
1.1138 -instruct loadS(eRegI dst, memory mem) %{
1.1139 +instruct loadS(rRegI dst, memory mem) %{
1.1140 match(Set dst (LoadS mem));
1.1141
1.1142 ins_cost(125);
1.1143 @@ -5891,7 +5940,7 @@
1.1144 %}
1.1145
1.1146 // Load Short (16 bit signed) to Byte (8 bit signed)
1.1147 -instruct loadS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
1.1148 +instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
1.1149 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
1.1150
1.1151 ins_cost(125);
1.1152 @@ -5922,7 +5971,7 @@
1.1153 %}
1.1154
1.1155 // Load Unsigned Short/Char (16bit unsigned)
1.1156 -instruct loadUS(eRegI dst, memory mem) %{
1.1157 +instruct loadUS(rRegI dst, memory mem) %{
1.1158 match(Set dst (LoadUS mem));
1.1159
1.1160 ins_cost(125);
1.1161 @@ -5936,7 +5985,7 @@
1.1162 %}
1.1163
1.1164 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
1.1165 -instruct loadUS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
1.1166 +instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
1.1167 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
1.1168
1.1169 ins_cost(125);
1.1170 @@ -5997,7 +6046,7 @@
1.1171 %}
1.1172
1.1173 // Load Integer
1.1174 -instruct loadI(eRegI dst, memory mem) %{
1.1175 +instruct loadI(rRegI dst, memory mem) %{
1.1176 match(Set dst (LoadI mem));
1.1177
1.1178 ins_cost(125);
1.1179 @@ -6011,7 +6060,7 @@
1.1180 %}
1.1181
1.1182 // Load Integer (32 bit signed) to Byte (8 bit signed)
1.1183 -instruct loadI2B(eRegI dst, memory mem, immI_24 twentyfour) %{
1.1184 +instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
1.1185 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
1.1186
1.1187 ins_cost(125);
1.1188 @@ -6023,7 +6072,7 @@
1.1189 %}
1.1190
1.1191 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
1.1192 -instruct loadI2UB(eRegI dst, memory mem, immI_255 mask) %{
1.1193 +instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
1.1194 match(Set dst (AndI (LoadI mem) mask));
1.1195
1.1196 ins_cost(125);
1.1197 @@ -6035,7 +6084,7 @@
1.1198 %}
1.1199
1.1200 // Load Integer (32 bit signed) to Short (16 bit signed)
1.1201 -instruct loadI2S(eRegI dst, memory mem, immI_16 sixteen) %{
1.1202 +instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
1.1203 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
1.1204
1.1205 ins_cost(125);
1.1206 @@ -6047,7 +6096,7 @@
1.1207 %}
1.1208
1.1209 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
1.1210 -instruct loadI2US(eRegI dst, memory mem, immI_65535 mask) %{
1.1211 +instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
1.1212 match(Set dst (AndI (LoadI mem) mask));
1.1213
1.1214 ins_cost(125);
1.1215 @@ -6208,7 +6257,7 @@
1.1216 %}
1.1217
1.1218 // Load Range
1.1219 -instruct loadRange(eRegI dst, memory mem) %{
1.1220 +instruct loadRange(rRegI dst, memory mem) %{
1.1221 match(Set dst (LoadRange mem));
1.1222
1.1223 ins_cost(125);
1.1224 @@ -6305,66 +6354,6 @@
1.1225 ins_pipe( fpu_reg_mem );
1.1226 %}
1.1227
1.1228 -// Load Aligned Packed Byte to XMM register
1.1229 -instruct loadA8B(regD dst, memory mem) %{
1.1230 - predicate(UseSSE>=1);
1.1231 - match(Set dst (Load8B mem));
1.1232 - ins_cost(125);
1.1233 - format %{ "MOVQ $dst,$mem\t! packed8B" %}
1.1234 - ins_encode %{
1.1235 - __ movq($dst$$XMMRegister, $mem$$Address);
1.1236 - %}
1.1237 - ins_pipe( pipe_slow );
1.1238 -%}
1.1239 -
1.1240 -// Load Aligned Packed Short to XMM register
1.1241 -instruct loadA4S(regD dst, memory mem) %{
1.1242 - predicate(UseSSE>=1);
1.1243 - match(Set dst (Load4S mem));
1.1244 - ins_cost(125);
1.1245 - format %{ "MOVQ $dst,$mem\t! packed4S" %}
1.1246 - ins_encode %{
1.1247 - __ movq($dst$$XMMRegister, $mem$$Address);
1.1248 - %}
1.1249 - ins_pipe( pipe_slow );
1.1250 -%}
1.1251 -
1.1252 -// Load Aligned Packed Char to XMM register
1.1253 -instruct loadA4C(regD dst, memory mem) %{
1.1254 - predicate(UseSSE>=1);
1.1255 - match(Set dst (Load4C mem));
1.1256 - ins_cost(125);
1.1257 - format %{ "MOVQ $dst,$mem\t! packed4C" %}
1.1258 - ins_encode %{
1.1259 - __ movq($dst$$XMMRegister, $mem$$Address);
1.1260 - %}
1.1261 - ins_pipe( pipe_slow );
1.1262 -%}
1.1263 -
1.1264 -// Load Aligned Packed Integer to XMM register
1.1265 -instruct load2IU(regD dst, memory mem) %{
1.1266 - predicate(UseSSE>=1);
1.1267 - match(Set dst (Load2I mem));
1.1268 - ins_cost(125);
1.1269 - format %{ "MOVQ $dst,$mem\t! packed2I" %}
1.1270 - ins_encode %{
1.1271 - __ movq($dst$$XMMRegister, $mem$$Address);
1.1272 - %}
1.1273 - ins_pipe( pipe_slow );
1.1274 -%}
1.1275 -
1.1276 -// Load Aligned Packed Single to XMM
1.1277 -instruct loadA2F(regD dst, memory mem) %{
1.1278 - predicate(UseSSE>=1);
1.1279 - match(Set dst (Load2F mem));
1.1280 - ins_cost(145);
1.1281 - format %{ "MOVQ $dst,$mem\t! packed2F" %}
1.1282 - ins_encode %{
1.1283 - __ movq($dst$$XMMRegister, $mem$$Address);
1.1284 - %}
1.1285 - ins_pipe( pipe_slow );
1.1286 -%}
1.1287 -
1.1288 // Load Effective Address
1.1289 instruct leaP8(eRegP dst, indOffset8 mem) %{
1.1290 match(Set dst mem);
1.1291 @@ -6417,7 +6406,7 @@
1.1292 %}
1.1293
1.1294 // Load Constant
1.1295 -instruct loadConI(eRegI dst, immI src) %{
1.1296 +instruct loadConI(rRegI dst, immI src) %{
1.1297 match(Set dst src);
1.1298
1.1299 format %{ "MOV $dst,$src" %}
1.1300 @@ -6426,7 +6415,7 @@
1.1301 %}
1.1302
1.1303 // Load Constant zero
1.1304 -instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{
1.1305 +instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{
1.1306 match(Set dst src);
1.1307 effect(KILL cr);
1.1308
1.1309 @@ -6594,7 +6583,7 @@
1.1310 %}
1.1311
1.1312 // Load Stack Slot
1.1313 -instruct loadSSI(eRegI dst, stackSlotI src) %{
1.1314 +instruct loadSSI(rRegI dst, stackSlotI src) %{
1.1315 match(Set dst src);
1.1316 ins_cost(125);
1.1317
1.1318 @@ -6821,7 +6810,7 @@
1.1319 %}
1.1320
1.1321 // Store Char/Short
1.1322 -instruct storeC(memory mem, eRegI src) %{
1.1323 +instruct storeC(memory mem, rRegI src) %{
1.1324 match(Set mem (StoreC mem src));
1.1325
1.1326 ins_cost(125);
1.1327 @@ -6832,7 +6821,7 @@
1.1328 %}
1.1329
1.1330 // Store Integer
1.1331 -instruct storeI(memory mem, eRegI src) %{
1.1332 +instruct storeI(memory mem, rRegI src) %{
1.1333 match(Set mem (StoreI mem src));
1.1334
1.1335 ins_cost(125);
1.1336 @@ -6976,42 +6965,6 @@
1.1337 ins_pipe( ialu_mem_imm );
1.1338 %}
1.1339
1.1340 -// Store Aligned Packed Byte XMM register to memory
1.1341 -instruct storeA8B(memory mem, regD src) %{
1.1342 - predicate(UseSSE>=1);
1.1343 - match(Set mem (Store8B mem src));
1.1344 - ins_cost(145);
1.1345 - format %{ "MOVQ $mem,$src\t! packed8B" %}
1.1346 - ins_encode %{
1.1347 - __ movq($mem$$Address, $src$$XMMRegister);
1.1348 - %}
1.1349 - ins_pipe( pipe_slow );
1.1350 -%}
1.1351 -
1.1352 -// Store Aligned Packed Char/Short XMM register to memory
1.1353 -instruct storeA4C(memory mem, regD src) %{
1.1354 - predicate(UseSSE>=1);
1.1355 - match(Set mem (Store4C mem src));
1.1356 - ins_cost(145);
1.1357 - format %{ "MOVQ $mem,$src\t! packed4C" %}
1.1358 - ins_encode %{
1.1359 - __ movq($mem$$Address, $src$$XMMRegister);
1.1360 - %}
1.1361 - ins_pipe( pipe_slow );
1.1362 -%}
1.1363 -
1.1364 -// Store Aligned Packed Integer XMM register to memory
1.1365 -instruct storeA2I(memory mem, regD src) %{
1.1366 - predicate(UseSSE>=1);
1.1367 - match(Set mem (Store2I mem src));
1.1368 - ins_cost(145);
1.1369 - format %{ "MOVQ $mem,$src\t! packed2I" %}
1.1370 - ins_encode %{
1.1371 - __ movq($mem$$Address, $src$$XMMRegister);
1.1372 - %}
1.1373 - ins_pipe( pipe_slow );
1.1374 -%}
1.1375 -
1.1376 // Store CMS card-mark Immediate
1.1377 instruct storeImmCM(memory mem, immI8 src) %{
1.1378 match(Set mem (StoreCM mem src));
1.1379 @@ -7073,18 +7026,6 @@
1.1380 ins_pipe( pipe_slow );
1.1381 %}
1.1382
1.1383 -// Store Aligned Packed Single Float XMM register to memory
1.1384 -instruct storeA2F(memory mem, regD src) %{
1.1385 - predicate(UseSSE>=1);
1.1386 - match(Set mem (Store2F mem src));
1.1387 - ins_cost(145);
1.1388 - format %{ "MOVQ $mem,$src\t! packed2F" %}
1.1389 - ins_encode %{
1.1390 - __ movq($mem$$Address, $src$$XMMRegister);
1.1391 - %}
1.1392 - ins_pipe( pipe_slow );
1.1393 -%}
1.1394 -
1.1395 // Store Float
1.1396 instruct storeFPR( memory mem, regFPR1 src) %{
1.1397 predicate(UseSSE==0);
1.1398 @@ -7146,7 +7087,7 @@
1.1399 %}
1.1400
1.1401 // Store Integer to stack slot
1.1402 -instruct storeSSI(stackSlotI dst, eRegI src) %{
1.1403 +instruct storeSSI(stackSlotI dst, rRegI src) %{
1.1404 match(Set dst src);
1.1405
1.1406 ins_cost(100);
1.1407 @@ -7271,7 +7212,7 @@
1.1408 ins_pipe(empty);
1.1409 %}
1.1410
1.1411 -instruct castP2X(eRegI dst, eRegP src ) %{
1.1412 +instruct castP2X(rRegI dst, eRegP src ) %{
1.1413 match(Set dst (CastP2X src));
1.1414 ins_cost(50);
1.1415 format %{ "MOV $dst, $src\t# CastP2X" %}
1.1416 @@ -7281,7 +7222,7 @@
1.1417
1.1418 //----------Conditional Move---------------------------------------------------
1.1419 // Conditional move
1.1420 -instruct jmovI_reg(cmpOp cop, eFlagsReg cr, eRegI dst, eRegI src) %{
1.1421 +instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{
1.1422 predicate(!VM_Version::supports_cmov() );
1.1423 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
1.1424 ins_cost(200);
1.1425 @@ -7298,7 +7239,7 @@
1.1426 ins_pipe( pipe_cmov_reg );
1.1427 %}
1.1428
1.1429 -instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src) %{
1.1430 +instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{
1.1431 predicate(!VM_Version::supports_cmov() );
1.1432 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
1.1433 ins_cost(200);
1.1434 @@ -7315,7 +7256,7 @@
1.1435 ins_pipe( pipe_cmov_reg );
1.1436 %}
1.1437
1.1438 -instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{
1.1439 +instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{
1.1440 predicate(VM_Version::supports_cmov() );
1.1441 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
1.1442 ins_cost(200);
1.1443 @@ -7325,7 +7266,7 @@
1.1444 ins_pipe( pipe_cmov_reg );
1.1445 %}
1.1446
1.1447 -instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src ) %{
1.1448 +instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{
1.1449 predicate(VM_Version::supports_cmov() );
1.1450 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
1.1451 ins_cost(200);
1.1452 @@ -7335,7 +7276,7 @@
1.1453 ins_pipe( pipe_cmov_reg );
1.1454 %}
1.1455
1.1456 -instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, eRegI src ) %{
1.1457 +instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{
1.1458 predicate(VM_Version::supports_cmov() );
1.1459 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
1.1460 ins_cost(200);
1.1461 @@ -7345,7 +7286,7 @@
1.1462 %}
1.1463
1.1464 // Conditional move
1.1465 -instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{
1.1466 +instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{
1.1467 predicate(VM_Version::supports_cmov() );
1.1468 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
1.1469 ins_cost(250);
1.1470 @@ -7356,7 +7297,7 @@
1.1471 %}
1.1472
1.1473 // Conditional move
1.1474 -instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{
1.1475 +instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{
1.1476 predicate(VM_Version::supports_cmov() );
1.1477 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
1.1478 ins_cost(250);
1.1479 @@ -7366,7 +7307,7 @@
1.1480 ins_pipe( pipe_cmov_mem );
1.1481 %}
1.1482
1.1483 -instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, memory src) %{
1.1484 +instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{
1.1485 predicate(VM_Version::supports_cmov() );
1.1486 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
1.1487 ins_cost(250);
1.1488 @@ -7620,7 +7561,7 @@
1.1489 //----------Arithmetic Instructions--------------------------------------------
1.1490 //----------Addition Instructions----------------------------------------------
1.1491 // Integer Addition Instructions
1.1492 -instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
1.1493 +instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
1.1494 match(Set dst (AddI dst src));
1.1495 effect(KILL cr);
1.1496
1.1497 @@ -7631,7 +7572,7 @@
1.1498 ins_pipe( ialu_reg_reg );
1.1499 %}
1.1500
1.1501 -instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
1.1502 +instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
1.1503 match(Set dst (AddI dst src));
1.1504 effect(KILL cr);
1.1505
1.1506 @@ -7641,7 +7582,7 @@
1.1507 ins_pipe( ialu_reg );
1.1508 %}
1.1509
1.1510 -instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
1.1511 +instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
1.1512 predicate(UseIncDec);
1.1513 match(Set dst (AddI dst src));
1.1514 effect(KILL cr);
1.1515 @@ -7653,7 +7594,7 @@
1.1516 ins_pipe( ialu_reg );
1.1517 %}
1.1518
1.1519 -instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{
1.1520 +instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{
1.1521 match(Set dst (AddI src0 src1));
1.1522 ins_cost(110);
1.1523
1.1524 @@ -7673,7 +7614,7 @@
1.1525 ins_pipe( ialu_reg_reg );
1.1526 %}
1.1527
1.1528 -instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{
1.1529 +instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{
1.1530 predicate(UseIncDec);
1.1531 match(Set dst (AddI dst src));
1.1532 effect(KILL cr);
1.1533 @@ -7685,7 +7626,7 @@
1.1534 ins_pipe( ialu_reg );
1.1535 %}
1.1536
1.1537 -instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{
1.1538 +instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{
1.1539 match(Set dst (AddP dst src));
1.1540 effect(KILL cr);
1.1541
1.1542 @@ -7707,7 +7648,7 @@
1.1543 ins_pipe( ialu_reg );
1.1544 %}
1.1545
1.1546 -instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
1.1547 +instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
1.1548 match(Set dst (AddI dst (LoadI src)));
1.1549 effect(KILL cr);
1.1550
1.1551 @@ -7718,7 +7659,7 @@
1.1552 ins_pipe( ialu_reg_mem );
1.1553 %}
1.1554
1.1555 -instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
1.1556 +instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
1.1557 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
1.1558 effect(KILL cr);
1.1559
1.1560 @@ -7780,7 +7721,7 @@
1.1561 ins_pipe( empty );
1.1562 %}
1.1563
1.1564 -instruct castII( eRegI dst ) %{
1.1565 +instruct castII( rRegI dst ) %{
1.1566 match(Set dst (CastII dst));
1.1567 format %{ "#castII of $dst" %}
1.1568 ins_encode( /*empty encoding*/ );
1.1569 @@ -7814,7 +7755,7 @@
1.1570
1.1571 // Conditional-store of an int value.
1.1572 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
1.1573 -instruct storeIConditional( memory mem, eAXRegI oldval, eRegI newval, eFlagsReg cr ) %{
1.1574 +instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{
1.1575 match(Set cr (StoreIConditional mem (Binary oldval newval)));
1.1576 effect(KILL oldval);
1.1577 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
1.1578 @@ -7847,7 +7788,7 @@
1.1579
1.1580 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
1.1581
1.1582 -instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
1.1583 +instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
1.1584 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
1.1585 effect(KILL cr, KILL oldval);
1.1586 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
1.1587 @@ -7860,7 +7801,7 @@
1.1588 ins_pipe( pipe_cmpxchg );
1.1589 %}
1.1590
1.1591 -instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
1.1592 +instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
1.1593 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
1.1594 effect(KILL cr, KILL oldval);
1.1595 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
1.1596 @@ -7872,7 +7813,7 @@
1.1597 ins_pipe( pipe_cmpxchg );
1.1598 %}
1.1599
1.1600 -instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
1.1601 +instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
1.1602 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
1.1603 effect(KILL cr, KILL oldval);
1.1604 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
1.1605 @@ -7886,7 +7827,7 @@
1.1606
1.1607 //----------Subtraction Instructions-------------------------------------------
1.1608 // Integer Subtraction Instructions
1.1609 -instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
1.1610 +instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
1.1611 match(Set dst (SubI dst src));
1.1612 effect(KILL cr);
1.1613
1.1614 @@ -7897,7 +7838,7 @@
1.1615 ins_pipe( ialu_reg_reg );
1.1616 %}
1.1617
1.1618 -instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
1.1619 +instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
1.1620 match(Set dst (SubI dst src));
1.1621 effect(KILL cr);
1.1622
1.1623 @@ -7908,7 +7849,7 @@
1.1624 ins_pipe( ialu_reg );
1.1625 %}
1.1626
1.1627 -instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
1.1628 +instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
1.1629 match(Set dst (SubI dst (LoadI src)));
1.1630 effect(KILL cr);
1.1631
1.1632 @@ -7919,7 +7860,7 @@
1.1633 ins_pipe( ialu_reg_mem );
1.1634 %}
1.1635
1.1636 -instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
1.1637 +instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
1.1638 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
1.1639 effect(KILL cr);
1.1640
1.1641 @@ -7931,7 +7872,7 @@
1.1642 %}
1.1643
1.1644 // Subtract from a pointer
1.1645 -instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{
1.1646 +instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{
1.1647 match(Set dst (AddP dst (SubI zero src)));
1.1648 effect(KILL cr);
1.1649
1.1650 @@ -7942,7 +7883,7 @@
1.1651 ins_pipe( ialu_reg_reg );
1.1652 %}
1.1653
1.1654 -instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{
1.1655 +instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
1.1656 match(Set dst (SubI zero dst));
1.1657 effect(KILL cr);
1.1658
1.1659 @@ -7957,7 +7898,7 @@
1.1660 //----------Multiplication/Division Instructions-------------------------------
1.1661 // Integer Multiplication Instructions
1.1662 // Multiply Register
1.1663 -instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
1.1664 +instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
1.1665 match(Set dst (MulI dst src));
1.1666 effect(KILL cr);
1.1667
1.1668 @@ -7970,7 +7911,7 @@
1.1669 %}
1.1670
1.1671 // Multiply 32-bit Immediate
1.1672 -instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{
1.1673 +instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
1.1674 match(Set dst (MulI src imm));
1.1675 effect(KILL cr);
1.1676
1.1677 @@ -8026,7 +7967,7 @@
1.1678 %}
1.1679
1.1680 // Multiply Memory 32-bit Immediate
1.1681 -instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{
1.1682 +instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{
1.1683 match(Set dst (MulI (LoadI src) imm));
1.1684 effect(KILL cr);
1.1685
1.1686 @@ -8038,7 +7979,7 @@
1.1687 %}
1.1688
1.1689 // Multiply Memory
1.1690 -instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{
1.1691 +instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{
1.1692 match(Set dst (MulI dst (LoadI src)));
1.1693 effect(KILL cr);
1.1694
1.1695 @@ -8075,7 +8016,7 @@
1.1696 %}
1.1697
1.1698 // Multiply Register Long
1.1699 -instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
1.1700 +instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
1.1701 match(Set dst (MulL dst src));
1.1702 effect(KILL cr, TEMP tmp);
1.1703 ins_cost(4*100+3*400);
1.1704 @@ -8093,7 +8034,7 @@
1.1705 %}
1.1706
1.1707 // Multiply Register Long where the left operand's high 32 bits are zero
1.1708 -instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
1.1709 +instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
1.1710 predicate(is_operand_hi32_zero(n->in(1)));
1.1711 match(Set dst (MulL dst src));
1.1712 effect(KILL cr, TEMP tmp);
1.1713 @@ -8114,7 +8055,7 @@
1.1714 %}
1.1715
1.1716 // Multiply Register Long where the right operand's high 32 bits are zero
1.1717 -instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
1.1718 +instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
1.1719 predicate(is_operand_hi32_zero(n->in(2)));
1.1720 match(Set dst (MulL dst src));
1.1721 effect(KILL cr, TEMP tmp);
1.1722 @@ -8150,7 +8091,7 @@
1.1723 %}
1.1724
1.1725 // Multiply Register Long by small constant
1.1726 -instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{
1.1727 +instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
1.1728 match(Set dst (MulL dst src));
1.1729 effect(KILL cr, TEMP tmp);
1.1730 ins_cost(2*100+2*400);
1.1731 @@ -8248,7 +8189,7 @@
1.1732 %}
1.1733
1.1734 // Divide Register Long (no special case since divisor != -1)
1.1735 -instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlagsReg cr ) %{
1.1736 +instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
1.1737 match(Set dst (DivL dst imm));
1.1738 effect( TEMP tmp, TEMP tmp2, KILL cr );
1.1739 ins_cost(1000);
1.1740 @@ -8319,7 +8260,7 @@
1.1741 %}
1.1742
1.1743 // Remainder Register Long (remainder fit into 32 bits)
1.1744 -instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlagsReg cr ) %{
1.1745 +instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
1.1746 match(Set dst (ModL dst imm));
1.1747 effect( TEMP tmp, TEMP tmp2, KILL cr );
1.1748 ins_cost(1000);
1.1749 @@ -8387,7 +8328,7 @@
1.1750
1.1751 // Integer Shift Instructions
1.1752 // Shift Left by one
1.1753 -instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
1.1754 +instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
1.1755 match(Set dst (LShiftI dst shift));
1.1756 effect(KILL cr);
1.1757
1.1758 @@ -8399,7 +8340,7 @@
1.1759 %}
1.1760
1.1761 // Shift Left by 8-bit immediate
1.1762 -instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
1.1763 +instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
1.1764 match(Set dst (LShiftI dst shift));
1.1765 effect(KILL cr);
1.1766
1.1767 @@ -8411,7 +8352,7 @@
1.1768 %}
1.1769
1.1770 // Shift Left by variable
1.1771 -instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
1.1772 +instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
1.1773 match(Set dst (LShiftI dst shift));
1.1774 effect(KILL cr);
1.1775
1.1776 @@ -8423,7 +8364,7 @@
1.1777 %}
1.1778
1.1779 // Arithmetic shift right by one
1.1780 -instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
1.1781 +instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
1.1782 match(Set dst (RShiftI dst shift));
1.1783 effect(KILL cr);
1.1784
1.1785 @@ -8445,7 +8386,7 @@
1.1786 %}
1.1787
1.1788 // Arithmetic Shift Right by 8-bit immediate
1.1789 -instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
1.1790 +instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
1.1791 match(Set dst (RShiftI dst shift));
1.1792 effect(KILL cr);
1.1793
1.1794 @@ -8468,7 +8409,7 @@
1.1795 %}
1.1796
1.1797 // Arithmetic Shift Right by variable
1.1798 -instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
1.1799 +instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
1.1800 match(Set dst (RShiftI dst shift));
1.1801 effect(KILL cr);
1.1802
1.1803 @@ -8480,7 +8421,7 @@
1.1804 %}
1.1805
1.1806 // Logical shift right by one
1.1807 -instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
1.1808 +instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
1.1809 match(Set dst (URShiftI dst shift));
1.1810 effect(KILL cr);
1.1811
1.1812 @@ -8492,7 +8433,7 @@
1.1813 %}
1.1814
1.1815 // Logical Shift Right by 8-bit immediate
1.1816 -instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
1.1817 +instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
1.1818 match(Set dst (URShiftI dst shift));
1.1819 effect(KILL cr);
1.1820
1.1821 @@ -8506,7 +8447,7 @@
1.1822
1.1823 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
1.1824 // This idiom is used by the compiler for the i2b bytecode.
1.1825 -instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour) %{
1.1826 +instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{
1.1827 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
1.1828
1.1829 size(3);
1.1830 @@ -8519,7 +8460,7 @@
1.1831
1.1832 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
1.1833 // This idiom is used by the compiler the i2s bytecode.
1.1834 -instruct i2s(eRegI dst, xRegI src, immI_16 sixteen) %{
1.1835 +instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{
1.1836 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
1.1837
1.1838 size(3);
1.1839 @@ -8532,7 +8473,7 @@
1.1840
1.1841
1.1842 // Logical Shift Right by variable
1.1843 -instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
1.1844 +instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
1.1845 match(Set dst (URShiftI dst shift));
1.1846 effect(KILL cr);
1.1847
1.1848 @@ -8548,7 +8489,7 @@
1.1849 //----------Integer Logical Instructions---------------------------------------
1.1850 // And Instructions
1.1851 // And Register with Register
1.1852 -instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
1.1853 +instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
1.1854 match(Set dst (AndI dst src));
1.1855 effect(KILL cr);
1.1856
1.1857 @@ -8560,7 +8501,7 @@
1.1858 %}
1.1859
1.1860 // And Register with Immediate
1.1861 -instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
1.1862 +instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
1.1863 match(Set dst (AndI dst src));
1.1864 effect(KILL cr);
1.1865
1.1866 @@ -8572,7 +8513,7 @@
1.1867 %}
1.1868
1.1869 // And Register with Memory
1.1870 -instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
1.1871 +instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
1.1872 match(Set dst (AndI dst (LoadI src)));
1.1873 effect(KILL cr);
1.1874
1.1875 @@ -8584,7 +8525,7 @@
1.1876 %}
1.1877
1.1878 // And Memory with Register
1.1879 -instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
1.1880 +instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
1.1881 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
1.1882 effect(KILL cr);
1.1883
1.1884 @@ -8610,7 +8551,7 @@
1.1885
1.1886 // Or Instructions
1.1887 // Or Register with Register
1.1888 -instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
1.1889 +instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
1.1890 match(Set dst (OrI dst src));
1.1891 effect(KILL cr);
1.1892
1.1893 @@ -8621,7 +8562,7 @@
1.1894 ins_pipe( ialu_reg_reg );
1.1895 %}
1.1896
1.1897 -instruct orI_eReg_castP2X(eRegI dst, eRegP src, eFlagsReg cr) %{
1.1898 +instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{
1.1899 match(Set dst (OrI dst (CastP2X src)));
1.1900 effect(KILL cr);
1.1901
1.1902 @@ -8634,7 +8575,7 @@
1.1903
1.1904
1.1905 // Or Register with Immediate
1.1906 -instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
1.1907 +instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
1.1908 match(Set dst (OrI dst src));
1.1909 effect(KILL cr);
1.1910
1.1911 @@ -8646,7 +8587,7 @@
1.1912 %}
1.1913
1.1914 // Or Register with Memory
1.1915 -instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
1.1916 +instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
1.1917 match(Set dst (OrI dst (LoadI src)));
1.1918 effect(KILL cr);
1.1919
1.1920 @@ -8658,7 +8599,7 @@
1.1921 %}
1.1922
1.1923 // Or Memory with Register
1.1924 -instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
1.1925 +instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
1.1926 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
1.1927 effect(KILL cr);
1.1928
1.1929 @@ -8684,7 +8625,7 @@
1.1930
1.1931 // ROL/ROR
1.1932 // ROL expand
1.1933 -instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
1.1934 +instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
1.1935 effect(USE_DEF dst, USE shift, KILL cr);
1.1936
1.1937 format %{ "ROL $dst, $shift" %}
1.1938 @@ -8693,7 +8634,7 @@
1.1939 ins_pipe( ialu_reg );
1.1940 %}
1.1941
1.1942 -instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
1.1943 +instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
1.1944 effect(USE_DEF dst, USE shift, KILL cr);
1.1945
1.1946 format %{ "ROL $dst, $shift" %}
1.1947 @@ -8713,7 +8654,7 @@
1.1948 // end of ROL expand
1.1949
1.1950 // ROL 32bit by one once
1.1951 -instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
1.1952 +instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
1.1953 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
1.1954
1.1955 expand %{
1.1956 @@ -8722,7 +8663,7 @@
1.1957 %}
1.1958
1.1959 // ROL 32bit var by imm8 once
1.1960 -instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
1.1961 +instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
1.1962 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
1.1963 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
1.1964
1.1965 @@ -8750,7 +8691,7 @@
1.1966 %}
1.1967
1.1968 // ROR expand
1.1969 -instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
1.1970 +instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
1.1971 effect(USE_DEF dst, USE shift, KILL cr);
1.1972
1.1973 format %{ "ROR $dst, $shift" %}
1.1974 @@ -8759,7 +8700,7 @@
1.1975 ins_pipe( ialu_reg );
1.1976 %}
1.1977
1.1978 -instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
1.1979 +instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
1.1980 effect (USE_DEF dst, USE shift, KILL cr);
1.1981
1.1982 format %{ "ROR $dst, $shift" %}
1.1983 @@ -8779,7 +8720,7 @@
1.1984 // end of ROR expand
1.1985
1.1986 // ROR right once
1.1987 -instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
1.1988 +instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
1.1989 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
1.1990
1.1991 expand %{
1.1992 @@ -8788,7 +8729,7 @@
1.1993 %}
1.1994
1.1995 // ROR 32bit by immI8 once
1.1996 -instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
1.1997 +instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
1.1998 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
1.1999 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
1.2000
1.2001 @@ -8817,7 +8758,7 @@
1.2002
1.2003 // Xor Instructions
1.2004 // Xor Register with Register
1.2005 -instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
1.2006 +instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
1.2007 match(Set dst (XorI dst src));
1.2008 effect(KILL cr);
1.2009
1.2010 @@ -8829,7 +8770,7 @@
1.2011 %}
1.2012
1.2013 // Xor Register with Immediate -1
1.2014 -instruct xorI_eReg_im1(eRegI dst, immI_M1 imm) %{
1.2015 +instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{
1.2016 match(Set dst (XorI dst imm));
1.2017
1.2018 size(2);
1.2019 @@ -8841,7 +8782,7 @@
1.2020 %}
1.2021
1.2022 // Xor Register with Immediate
1.2023 -instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
1.2024 +instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
1.2025 match(Set dst (XorI dst src));
1.2026 effect(KILL cr);
1.2027
1.2028 @@ -8853,7 +8794,7 @@
1.2029 %}
1.2030
1.2031 // Xor Register with Memory
1.2032 -instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
1.2033 +instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
1.2034 match(Set dst (XorI dst (LoadI src)));
1.2035 effect(KILL cr);
1.2036
1.2037 @@ -8865,7 +8806,7 @@
1.2038 %}
1.2039
1.2040 // Xor Memory with Register
1.2041 -instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
1.2042 +instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
1.2043 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
1.2044 effect(KILL cr);
1.2045
1.2046 @@ -8890,14 +8831,14 @@
1.2047
1.2048 //----------Convert Int to Boolean---------------------------------------------
1.2049
1.2050 -instruct movI_nocopy(eRegI dst, eRegI src) %{
1.2051 +instruct movI_nocopy(rRegI dst, rRegI src) %{
1.2052 effect( DEF dst, USE src );
1.2053 format %{ "MOV $dst,$src" %}
1.2054 ins_encode( enc_Copy( dst, src) );
1.2055 ins_pipe( ialu_reg_reg );
1.2056 %}
1.2057
1.2058 -instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{
1.2059 +instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{
1.2060 effect( USE_DEF dst, USE src, KILL cr );
1.2061
1.2062 size(4);
1.2063 @@ -8908,7 +8849,7 @@
1.2064 ins_pipe( ialu_reg_reg_long );
1.2065 %}
1.2066
1.2067 -instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{
1.2068 +instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{
1.2069 match(Set dst (Conv2B src));
1.2070
1.2071 expand %{
1.2072 @@ -8917,14 +8858,14 @@
1.2073 %}
1.2074 %}
1.2075
1.2076 -instruct movP_nocopy(eRegI dst, eRegP src) %{
1.2077 +instruct movP_nocopy(rRegI dst, eRegP src) %{
1.2078 effect( DEF dst, USE src );
1.2079 format %{ "MOV $dst,$src" %}
1.2080 ins_encode( enc_Copy( dst, src) );
1.2081 ins_pipe( ialu_reg_reg );
1.2082 %}
1.2083
1.2084 -instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{
1.2085 +instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{
1.2086 effect( USE_DEF dst, USE src, KILL cr );
1.2087 format %{ "NEG $dst\n\t"
1.2088 "ADC $dst,$src" %}
1.2089 @@ -8933,7 +8874,7 @@
1.2090 ins_pipe( ialu_reg_reg_long );
1.2091 %}
1.2092
1.2093 -instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{
1.2094 +instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{
1.2095 match(Set dst (Conv2B src));
1.2096
1.2097 expand %{
1.2098 @@ -8958,7 +8899,7 @@
1.2099 ins_pipe( pipe_slow );
1.2100 %}
1.2101
1.2102 -instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{
1.2103 +instruct cmpLTMask0( rRegI dst, immI0 zero, eFlagsReg cr ) %{
1.2104 match(Set dst (CmpLTMask dst zero));
1.2105 effect( DEF dst, KILL cr );
1.2106 ins_cost(100);
1.2107 @@ -9430,7 +9371,7 @@
1.2108 %}
1.2109
1.2110 // Compare vs zero into -1,0,1
1.2111 -instruct cmpDPR_0(eRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
1.2112 +instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
1.2113 predicate(UseSSE<=1);
1.2114 match(Set dst (CmpD3 src1 zero));
1.2115 effect(KILL cr, KILL rax);
1.2116 @@ -9444,7 +9385,7 @@
1.2117 %}
1.2118
1.2119 // Compare into -1,0,1
1.2120 -instruct cmpDPR_reg(eRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
1.2121 +instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
1.2122 predicate(UseSSE<=1);
1.2123 match(Set dst (CmpD3 src1 src2));
1.2124 effect(KILL cr, KILL rax);
1.2125 @@ -10222,7 +10163,7 @@
1.2126 %}
1.2127
1.2128 // Compare vs zero into -1,0,1
1.2129 -instruct cmpFPR_0(eRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
1.2130 +instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
1.2131 predicate(UseSSE == 0);
1.2132 match(Set dst (CmpF3 src1 zero));
1.2133 effect(KILL cr, KILL rax);
1.2134 @@ -10236,7 +10177,7 @@
1.2135 %}
1.2136
1.2137 // Compare into -1,0,1
1.2138 -instruct cmpFPR_reg(eRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
1.2139 +instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
1.2140 predicate(UseSSE == 0);
1.2141 match(Set dst (CmpF3 src1 src2));
1.2142 effect(KILL cr, KILL rax);
1.2143 @@ -11156,7 +11097,7 @@
1.2144 ins_pipe( fpu_reg_mem );
1.2145 %}
1.2146
1.2147 -instruct convI2D_reg(regD dst, eRegI src) %{
1.2148 +instruct convI2D_reg(regD dst, rRegI src) %{
1.2149 predicate( UseSSE>=2 && !UseXmmI2D );
1.2150 match(Set dst (ConvI2D src));
1.2151 format %{ "CVTSI2SD $dst,$src" %}
1.2152 @@ -11176,7 +11117,7 @@
1.2153 ins_pipe( pipe_slow );
1.2154 %}
1.2155
1.2156 -instruct convXI2D_reg(regD dst, eRegI src)
1.2157 +instruct convXI2D_reg(regD dst, rRegI src)
1.2158 %{
1.2159 predicate( UseSSE>=2 && UseXmmI2D );
1.2160 match(Set dst (ConvI2D src));
1.2161 @@ -11264,7 +11205,7 @@
1.2162 %}
1.2163
1.2164 // Convert an int to a float in xmm; no rounding step needed.
1.2165 -instruct convI2F_reg(regF dst, eRegI src) %{
1.2166 +instruct convI2F_reg(regF dst, rRegI src) %{
1.2167 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
1.2168 match(Set dst (ConvI2F src));
1.2169 format %{ "CVTSI2SS $dst, $src" %}
1.2170 @@ -11274,7 +11215,7 @@
1.2171 ins_pipe( pipe_slow );
1.2172 %}
1.2173
1.2174 - instruct convXI2F_reg(regF dst, eRegI src)
1.2175 + instruct convXI2F_reg(regF dst, rRegI src)
1.2176 %{
1.2177 predicate( UseSSE>=2 && UseXmmI2F );
1.2178 match(Set dst (ConvI2F src));
1.2179 @@ -11288,7 +11229,7 @@
1.2180 ins_pipe(pipe_slow); // XXX
1.2181 %}
1.2182
1.2183 -instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{
1.2184 +instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{
1.2185 match(Set dst (ConvI2L src));
1.2186 effect(KILL cr);
1.2187 ins_cost(375);
1.2188 @@ -11300,7 +11241,7 @@
1.2189 %}
1.2190
1.2191 // Zero-extend convert int to long
1.2192 -instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{
1.2193 +instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{
1.2194 match(Set dst (AndL (ConvI2L src) mask) );
1.2195 effect( KILL flags );
1.2196 ins_cost(250);
1.2197 @@ -11380,7 +11321,7 @@
1.2198 ins_pipe( pipe_slow );
1.2199 %}
1.2200
1.2201 -instruct convL2I_reg( eRegI dst, eRegL src ) %{
1.2202 +instruct convL2I_reg( rRegI dst, eRegL src ) %{
1.2203 match(Set dst (ConvL2I src));
1.2204 effect( DEF dst, USE src );
1.2205 format %{ "MOV $dst,$src.lo" %}
1.2206 @@ -11389,7 +11330,7 @@
1.2207 %}
1.2208
1.2209
1.2210 -instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{
1.2211 +instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
1.2212 match(Set dst (MoveF2I src));
1.2213 effect( DEF dst, USE src );
1.2214 ins_cost(100);
1.2215 @@ -11424,7 +11365,7 @@
1.2216 ins_pipe( pipe_slow );
1.2217 %}
1.2218
1.2219 -instruct MoveF2I_reg_reg_sse(eRegI dst, regF src) %{
1.2220 +instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{
1.2221 predicate(UseSSE>=2);
1.2222 match(Set dst (MoveF2I src));
1.2223 effect( DEF dst, USE src );
1.2224 @@ -11436,7 +11377,7 @@
1.2225 ins_pipe( pipe_slow );
1.2226 %}
1.2227
1.2228 -instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{
1.2229 +instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
1.2230 match(Set dst (MoveI2F src));
1.2231 effect( DEF dst, USE src );
1.2232
1.2233 @@ -11476,7 +11417,7 @@
1.2234 ins_pipe( pipe_slow );
1.2235 %}
1.2236
1.2237 -instruct MoveI2F_reg_reg_sse(regF dst, eRegI src) %{
1.2238 +instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{
1.2239 predicate(UseSSE>=2);
1.2240 match(Set dst (MoveI2F src));
1.2241 effect( DEF dst, USE src );
1.2242 @@ -11610,186 +11551,6 @@
1.2243 ins_pipe( pipe_slow );
1.2244 %}
1.2245
1.2246 -// Replicate scalar to packed byte (1 byte) values in xmm
1.2247 -instruct Repl8B_reg(regD dst, regD src) %{
1.2248 - predicate(UseSSE>=2);
1.2249 - match(Set dst (Replicate8B src));
1.2250 - format %{ "MOVDQA $dst,$src\n\t"
1.2251 - "PUNPCKLBW $dst,$dst\n\t"
1.2252 - "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
1.2253 - ins_encode %{
1.2254 - if ($dst$$reg != $src$$reg) {
1.2255 - __ movdqa($dst$$XMMRegister, $src$$XMMRegister);
1.2256 - }
1.2257 - __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister);
1.2258 - __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
1.2259 - %}
1.2260 - ins_pipe( pipe_slow );
1.2261 -%}
1.2262 -
1.2263 -// Replicate scalar to packed byte (1 byte) values in xmm
1.2264 -instruct Repl8B_eRegI(regD dst, eRegI src) %{
1.2265 - predicate(UseSSE>=2);
1.2266 - match(Set dst (Replicate8B src));
1.2267 - format %{ "MOVD $dst,$src\n\t"
1.2268 - "PUNPCKLBW $dst,$dst\n\t"
1.2269 - "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
1.2270 - ins_encode %{
1.2271 - __ movdl($dst$$XMMRegister, $src$$Register);
1.2272 - __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister);
1.2273 - __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
1.2274 - %}
1.2275 - ins_pipe( pipe_slow );
1.2276 -%}
1.2277 -
1.2278 -// Replicate scalar zero to packed byte (1 byte) values in xmm
1.2279 -instruct Repl8B_immI0(regD dst, immI0 zero) %{
1.2280 - predicate(UseSSE>=2);
1.2281 - match(Set dst (Replicate8B zero));
1.2282 - format %{ "PXOR $dst,$dst\t! replicate8B" %}
1.2283 - ins_encode %{
1.2284 - __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
1.2285 - %}
1.2286 - ins_pipe( fpu_reg_reg );
1.2287 -%}
1.2288 -
1.2289 -// Replicate scalar to packed shore (2 byte) values in xmm
1.2290 -instruct Repl4S_reg(regD dst, regD src) %{
1.2291 - predicate(UseSSE>=2);
1.2292 - match(Set dst (Replicate4S src));
1.2293 - format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
1.2294 - ins_encode %{
1.2295 - __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00);
1.2296 - %}
1.2297 - ins_pipe( fpu_reg_reg );
1.2298 -%}
1.2299 -
1.2300 -// Replicate scalar to packed shore (2 byte) values in xmm
1.2301 -instruct Repl4S_eRegI(regD dst, eRegI src) %{
1.2302 - predicate(UseSSE>=2);
1.2303 - match(Set dst (Replicate4S src));
1.2304 - format %{ "MOVD $dst,$src\n\t"
1.2305 - "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
1.2306 - ins_encode %{
1.2307 - __ movdl($dst$$XMMRegister, $src$$Register);
1.2308 - __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
1.2309 - %}
1.2310 - ins_pipe( fpu_reg_reg );
1.2311 -%}
1.2312 -
1.2313 -// Replicate scalar zero to packed short (2 byte) values in xmm
1.2314 -instruct Repl4S_immI0(regD dst, immI0 zero) %{
1.2315 - predicate(UseSSE>=2);
1.2316 - match(Set dst (Replicate4S zero));
1.2317 - format %{ "PXOR $dst,$dst\t! replicate4S" %}
1.2318 - ins_encode %{
1.2319 - __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
1.2320 - %}
1.2321 - ins_pipe( fpu_reg_reg );
1.2322 -%}
1.2323 -
1.2324 -// Replicate scalar to packed char (2 byte) values in xmm
1.2325 -instruct Repl4C_reg(regD dst, regD src) %{
1.2326 - predicate(UseSSE>=2);
1.2327 - match(Set dst (Replicate4C src));
1.2328 - format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
1.2329 - ins_encode %{
1.2330 - __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00);
1.2331 - %}
1.2332 - ins_pipe( fpu_reg_reg );
1.2333 -%}
1.2334 -
1.2335 -// Replicate scalar to packed char (2 byte) values in xmm
1.2336 -instruct Repl4C_eRegI(regD dst, eRegI src) %{
1.2337 - predicate(UseSSE>=2);
1.2338 - match(Set dst (Replicate4C src));
1.2339 - format %{ "MOVD $dst,$src\n\t"
1.2340 - "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
1.2341 - ins_encode %{
1.2342 - __ movdl($dst$$XMMRegister, $src$$Register);
1.2343 - __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
1.2344 - %}
1.2345 - ins_pipe( fpu_reg_reg );
1.2346 -%}
1.2347 -
1.2348 -// Replicate scalar zero to packed char (2 byte) values in xmm
1.2349 -instruct Repl4C_immI0(regD dst, immI0 zero) %{
1.2350 - predicate(UseSSE>=2);
1.2351 - match(Set dst (Replicate4C zero));
1.2352 - format %{ "PXOR $dst,$dst\t! replicate4C" %}
1.2353 - ins_encode %{
1.2354 - __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
1.2355 - %}
1.2356 - ins_pipe( fpu_reg_reg );
1.2357 -%}
1.2358 -
1.2359 -// Replicate scalar to packed integer (4 byte) values in xmm
1.2360 -instruct Repl2I_reg(regD dst, regD src) %{
1.2361 - predicate(UseSSE>=2);
1.2362 - match(Set dst (Replicate2I src));
1.2363 - format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
1.2364 - ins_encode %{
1.2365 - __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00);
1.2366 - %}
1.2367 - ins_pipe( fpu_reg_reg );
1.2368 -%}
1.2369 -
1.2370 -// Replicate scalar to packed integer (4 byte) values in xmm
1.2371 -instruct Repl2I_eRegI(regD dst, eRegI src) %{
1.2372 - predicate(UseSSE>=2);
1.2373 - match(Set dst (Replicate2I src));
1.2374 - format %{ "MOVD $dst,$src\n\t"
1.2375 - "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
1.2376 - ins_encode %{
1.2377 - __ movdl($dst$$XMMRegister, $src$$Register);
1.2378 - __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
1.2379 - %}
1.2380 - ins_pipe( fpu_reg_reg );
1.2381 -%}
1.2382 -
1.2383 -// Replicate scalar zero to packed integer (2 byte) values in xmm
1.2384 -instruct Repl2I_immI0(regD dst, immI0 zero) %{
1.2385 - predicate(UseSSE>=2);
1.2386 - match(Set dst (Replicate2I zero));
1.2387 - format %{ "PXOR $dst,$dst\t! replicate2I" %}
1.2388 - ins_encode %{
1.2389 - __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
1.2390 - %}
1.2391 - ins_pipe( fpu_reg_reg );
1.2392 -%}
1.2393 -
1.2394 -// Replicate scalar to packed single precision floating point values in xmm
1.2395 -instruct Repl2F_reg(regD dst, regD src) %{
1.2396 - predicate(UseSSE>=2);
1.2397 - match(Set dst (Replicate2F src));
1.2398 - format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
1.2399 - ins_encode %{
1.2400 - __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0);
1.2401 - %}
1.2402 - ins_pipe( fpu_reg_reg );
1.2403 -%}
1.2404 -
1.2405 -// Replicate scalar to packed single precision floating point values in xmm
1.2406 -instruct Repl2F_regF(regD dst, regF src) %{
1.2407 - predicate(UseSSE>=2);
1.2408 - match(Set dst (Replicate2F src));
1.2409 - format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
1.2410 - ins_encode %{
1.2411 - __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0);
1.2412 - %}
1.2413 - ins_pipe( fpu_reg_reg );
1.2414 -%}
1.2415 -
1.2416 -// Replicate scalar to packed single precision floating point values in xmm
1.2417 -instruct Repl2F_immF0(regD dst, immF0 zero) %{
1.2418 - predicate(UseSSE>=2);
1.2419 - match(Set dst (Replicate2F zero));
1.2420 - format %{ "PXOR $dst,$dst\t! replicate2F" %}
1.2421 - ins_encode %{
1.2422 - __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
1.2423 - %}
1.2424 - ins_pipe( fpu_reg_reg );
1.2425 -%}
1.2426
1.2427 // =======================================================================
1.2428 // fast clearing of an array
1.2429 @@ -11898,7 +11659,7 @@
1.2430
1.2431 //----------Control Flow Instructions------------------------------------------
1.2432 // Signed compare Instructions
1.2433 -instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{
1.2434 +instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{
1.2435 match(Set cr (CmpI op1 op2));
1.2436 effect( DEF cr, USE op1, USE op2 );
1.2437 format %{ "CMP $op1,$op2" %}
1.2438 @@ -11907,7 +11668,7 @@
1.2439 ins_pipe( ialu_cr_reg_reg );
1.2440 %}
1.2441
1.2442 -instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{
1.2443 +instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{
1.2444 match(Set cr (CmpI op1 op2));
1.2445 effect( DEF cr, USE op1 );
1.2446 format %{ "CMP $op1,$op2" %}
1.2447 @@ -11918,7 +11679,7 @@
1.2448 %}
1.2449
1.2450 // Cisc-spilled version of cmpI_eReg
1.2451 -instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{
1.2452 +instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{
1.2453 match(Set cr (CmpI op1 (LoadI op2)));
1.2454
1.2455 format %{ "CMP $op1,$op2" %}
1.2456 @@ -11928,7 +11689,7 @@
1.2457 ins_pipe( ialu_cr_reg_mem );
1.2458 %}
1.2459
1.2460 -instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{
1.2461 +instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{
1.2462 match(Set cr (CmpI src zero));
1.2463 effect( DEF cr, USE src );
1.2464
1.2465 @@ -11938,7 +11699,7 @@
1.2466 ins_pipe( ialu_cr_reg_imm );
1.2467 %}
1.2468
1.2469 -instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{
1.2470 +instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{
1.2471 match(Set cr (CmpI (AndI src con) zero));
1.2472
1.2473 format %{ "TEST $src,$con" %}
1.2474 @@ -11947,7 +11708,7 @@
1.2475 ins_pipe( ialu_cr_reg_imm );
1.2476 %}
1.2477
1.2478 -instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{
1.2479 +instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{
1.2480 match(Set cr (CmpI (AndI src mem) zero));
1.2481
1.2482 format %{ "TEST $src,$mem" %}
1.2483 @@ -11958,7 +11719,7 @@
1.2484
1.2485 // Unsigned compare Instructions; really, same as signed except they
1.2486 // produce an eFlagsRegU instead of eFlagsReg.
1.2487 -instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{
1.2488 +instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{
1.2489 match(Set cr (CmpU op1 op2));
1.2490
1.2491 format %{ "CMPu $op1,$op2" %}
1.2492 @@ -11967,7 +11728,7 @@
1.2493 ins_pipe( ialu_cr_reg_reg );
1.2494 %}
1.2495
1.2496 -instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{
1.2497 +instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{
1.2498 match(Set cr (CmpU op1 op2));
1.2499
1.2500 format %{ "CMPu $op1,$op2" %}
1.2501 @@ -11977,7 +11738,7 @@
1.2502 %}
1.2503
1.2504 // // Cisc-spilled version of cmpU_eReg
1.2505 -instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{
1.2506 +instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{
1.2507 match(Set cr (CmpU op1 (LoadI op2)));
1.2508
1.2509 format %{ "CMPu $op1,$op2" %}
1.2510 @@ -11988,7 +11749,7 @@
1.2511 %}
1.2512
1.2513 // // Cisc-spilled version of cmpU_eReg
1.2514 -//instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{
1.2515 +//instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{
1.2516 // match(Set cr (CmpU (LoadI op1) op2));
1.2517 //
1.2518 // format %{ "CMPu $op1,$op2" %}
1.2519 @@ -11997,7 +11758,7 @@
1.2520 // ins_encode( OpcP, RegMem( op1, op2) );
1.2521 //%}
1.2522
1.2523 -instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{
1.2524 +instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{
1.2525 match(Set cr (CmpU src zero));
1.2526
1.2527 format %{ "TESTu $src,$src" %}
1.2528 @@ -12093,7 +11854,7 @@
1.2529 // *** Min and Max using the conditional move are slower than the
1.2530 // *** branch version on a Pentium III.
1.2531 // // Conditional move for min
1.2532 -//instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
1.2533 +//instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
1.2534 // effect( USE_DEF op2, USE op1, USE cr );
1.2535 // format %{ "CMOVlt $op2,$op1\t! min" %}
1.2536 // opcode(0x4C,0x0F);
1.2537 @@ -12102,7 +11863,7 @@
1.2538 //%}
1.2539 //
1.2540 //// Min Register with Register (P6 version)
1.2541 -//instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{
1.2542 +//instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{
1.2543 // predicate(VM_Version::supports_cmov() );
1.2544 // match(Set op2 (MinI op1 op2));
1.2545 // ins_cost(200);
1.2546 @@ -12114,7 +11875,7 @@
1.2547 //%}
1.2548
1.2549 // Min Register with Register (generic version)
1.2550 -instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
1.2551 +instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
1.2552 match(Set dst (MinI dst src));
1.2553 effect(KILL flags);
1.2554 ins_cost(300);
1.2555 @@ -12129,7 +11890,7 @@
1.2556 // *** Min and Max using the conditional move are slower than the
1.2557 // *** branch version on a Pentium III.
1.2558 // // Conditional move for max
1.2559 -//instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
1.2560 +//instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
1.2561 // effect( USE_DEF op2, USE op1, USE cr );
1.2562 // format %{ "CMOVgt $op2,$op1\t! max" %}
1.2563 // opcode(0x4F,0x0F);
1.2564 @@ -12138,7 +11899,7 @@
1.2565 //%}
1.2566 //
1.2567 // // Max Register with Register (P6 version)
1.2568 -//instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{
1.2569 +//instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{
1.2570 // predicate(VM_Version::supports_cmov() );
1.2571 // match(Set op2 (MaxI op1 op2));
1.2572 // ins_cost(200);
1.2573 @@ -12150,7 +11911,7 @@
1.2574 //%}
1.2575
1.2576 // Max Register with Register (generic version)
1.2577 -instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
1.2578 +instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
1.2579 match(Set dst (MaxI dst src));
1.2580 effect(KILL flags);
1.2581 ins_cost(300);
1.2582 @@ -12211,7 +11972,7 @@
1.2583 // ============================================================================
1.2584 // Branch Instructions
1.2585 // Jump Table
1.2586 -instruct jumpXtnd(eRegI switch_val) %{
1.2587 +instruct jumpXtnd(rRegI switch_val) %{
1.2588 match(Jump switch_val);
1.2589 ins_cost(350);
1.2590 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
1.2591 @@ -12629,7 +12390,7 @@
1.2592 // Manifest a CmpL result in the normal flags. Only good for LT or GE
1.2593 // compares. Can be used for LE or GT compares by reversing arguments.
1.2594 // NOT GOOD FOR EQ/NE tests.
1.2595 -instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{
1.2596 +instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{
1.2597 match( Set flags (CmpL src1 src2 ));
1.2598 effect( TEMP tmp );
1.2599 ins_cost(300);
1.2600 @@ -12675,7 +12436,7 @@
1.2601 %}
1.2602
1.2603 // Compare 2 longs and CMOVE ints.
1.2604 -instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{
1.2605 +instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{
1.2606 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
1.2607 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
1.2608 ins_cost(200);
1.2609 @@ -12685,7 +12446,7 @@
1.2610 ins_pipe( pipe_cmov_reg );
1.2611 %}
1.2612
1.2613 -instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{
1.2614 +instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{
1.2615 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
1.2616 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
1.2617 ins_cost(250);
1.2618 @@ -12746,7 +12507,7 @@
1.2619
1.2620 //======
1.2621 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
1.2622 -instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{
1.2623 +instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{
1.2624 match( Set flags (CmpL src zero ));
1.2625 effect(TEMP tmp);
1.2626 ins_cost(200);
1.2627 @@ -12803,7 +12564,7 @@
1.2628 %}
1.2629
1.2630 // Compare 2 longs and CMOVE ints.
1.2631 -instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{
1.2632 +instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{
1.2633 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
1.2634 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
1.2635 ins_cost(200);
1.2636 @@ -12813,7 +12574,7 @@
1.2637 ins_pipe( pipe_cmov_reg );
1.2638 %}
1.2639
1.2640 -instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{
1.2641 +instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{
1.2642 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
1.2643 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
1.2644 ins_cost(250);
1.2645 @@ -12875,7 +12636,7 @@
1.2646 //======
1.2647 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
1.2648 // Same as cmpL_reg_flags_LEGT except must negate src
1.2649 -instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{
1.2650 +instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{
1.2651 match( Set flags (CmpL src zero ));
1.2652 effect( TEMP tmp );
1.2653 ins_cost(300);
1.2654 @@ -12889,7 +12650,7 @@
1.2655 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
1.2656 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
1.2657 // requires a commuted test to get the same result.
1.2658 -instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{
1.2659 +instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{
1.2660 match( Set flags (CmpL src1 src2 ));
1.2661 effect( TEMP tmp );
1.2662 ins_cost(300);
1.2663 @@ -12936,7 +12697,7 @@
1.2664 %}
1.2665
1.2666 // Compare 2 longs and CMOVE ints.
1.2667 -instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{
1.2668 +instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{
1.2669 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
1.2670 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
1.2671 ins_cost(200);
1.2672 @@ -12946,7 +12707,7 @@
1.2673 ins_pipe( pipe_cmov_reg );
1.2674 %}
1.2675
1.2676 -instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{
1.2677 +instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{
1.2678 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
1.2679 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
1.2680 ins_cost(250);
1.2681 @@ -13275,11 +13036,11 @@
1.2682 // ---------EXAMPLE----------------------------------------------------------
1.2683 //
1.2684 // // pertinent parts of existing instructions in architecture description
1.2685 -// instruct movI(eRegI dst, eRegI src) %{
1.2686 +// instruct movI(rRegI dst, rRegI src) %{
1.2687 // match(Set dst (CopyI src));
1.2688 // %}
1.2689 //
1.2690 -// instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
1.2691 +// instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
1.2692 // match(Set dst (AddI dst src));
1.2693 // effect(KILL cr);
1.2694 // %}
1.2695 @@ -13324,11 +13085,11 @@
1.2696 // %}
1.2697
1.2698 // // Change load of spilled value to only a spill
1.2699 -// instruct storeI(memory mem, eRegI src) %{
1.2700 +// instruct storeI(memory mem, rRegI src) %{
1.2701 // match(Set mem (StoreI mem src));
1.2702 // %}
1.2703 //
1.2704 -// instruct loadI(eRegI dst, memory mem) %{
1.2705 +// instruct loadI(rRegI dst, memory mem) %{
1.2706 // match(Set dst (LoadI mem));
1.2707 // %}
1.2708 //
