1.1 --- a/src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp Wed Sep 19 16:50:26 2012 -0700
1.2 +++ b/src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp Thu Sep 20 16:49:17 2012 +0200
1.3 @@ -1315,7 +1315,13 @@
1.4
1.5 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1.6 Register reg = addr->base()->as_register();
1.7 - return Address(reg, addr->disp());
1.8 + LIR_Opr index = addr->index();
1.9 + if (index->is_illegal()) {
1.10 + return Address(reg, addr->disp());
1.11 + } else {
1.12 + assert (addr->disp() == 0, "unsupported address mode");
1.13 + return Address(reg, index->as_pointer_register());
1.14 + }
1.15 }
1.16
1.17
1.18 @@ -3438,7 +3444,28 @@
1.19 }
1.20 }
1.21
1.22 -
1.23 -
1.24 +void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
1.25 + LIR_Address* addr = src->as_address_ptr();
1.26 +
1.27 + assert(data == dest, "swap uses only 2 operands");
1.28 + assert (code == lir_xchg, "no xadd on sparc");
1.29 +
1.30 + if (data->type() == T_INT) {
1.31 + __ swap(as_Address(addr), data->as_register());
1.32 + } else if (data->is_oop()) {
1.33 + Register obj = data->as_register();
1.34 + Register narrow = tmp->as_register();
1.35 +#ifdef _LP64
1.36 + assert(UseCompressedOops, "swap is 32bit only");
1.37 + __ encode_heap_oop(obj, narrow);
1.38 + __ swap(as_Address(addr), narrow);
1.39 + __ decode_heap_oop(narrow, obj);
1.40 +#else
1.41 + __ swap(as_Address(addr), obj);
1.42 +#endif
1.43 + } else {
1.44 + ShouldNotReachHere();
1.45 + }
1.46 +}
1.47
1.48 #undef __
