src/cpu/x86/vm/x86_64.ad

changeset 2683
7e88bdae86ec
parent 2602
41d4973cf100
child 2686
b40d4fa697bf
     1.1 --- a/src/cpu/x86/vm/x86_64.ad	Fri Mar 25 18:19:22 2011 -0400
     1.2 +++ b/src/cpu/x86/vm/x86_64.ad	Fri Mar 25 09:35:39 2011 +0100
     1.3 @@ -2000,6 +2000,10 @@
     1.4  // into registers?  True for Intel but false for most RISCs
     1.5  const bool Matcher::clone_shift_expressions = true;
     1.6  
     1.7 +// Do we need to mask the count passed to shift instructions or does
     1.8 +// the cpu only look at the lower 5/6 bits anyway?
     1.9 +const bool Matcher::need_masked_shift_count = false;
    1.10 +
    1.11  bool Matcher::narrow_oop_use_complex_address() {
    1.12    assert(UseCompressedOops, "only for compressed oops code");
    1.13    return (LogMinObjAlignmentInBytes <= 3);

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