diff -r b2949bf39900 -r 7e88bdae86ec src/cpu/x86/vm/x86_64.ad
--- a/src/cpu/x86/vm/x86_64.ad	Fri Mar 25 18:19:22 2011 -0400
+++ b/src/cpu/x86/vm/x86_64.ad	Fri Mar 25 09:35:39 2011 +0100
@@ -2000,6 +2000,10 @@
 // into registers?  True for Intel but false for most RISCs
 const bool Matcher::clone_shift_expressions = true;
 
+// Do we need to mask the count passed to shift instructions or does
+// the cpu only look at the lower 5/6 bits anyway?
+const bool Matcher::need_masked_shift_count = false;
+
 bool Matcher::narrow_oop_use_complex_address() {
   assert(UseCompressedOops, "only for compressed oops code");
   return (LogMinObjAlignmentInBytes <= 3);