1.1 --- a/src/cpu/x86/vm/x86_64.ad Wed May 28 21:06:24 2008 -0700
1.2 +++ b/src/cpu/x86/vm/x86_64.ad Thu May 29 12:04:14 2008 -0700
1.3 @@ -5202,15 +5202,15 @@
1.4 %}
1.5 %}
1.6
1.7 -// Indirect Memory Times Scale Plus Index Register Plus Offset Operand
1.8 -operand indIndexScaleOffsetComp(rRegN src, immL32 off, r12RegL base) %{
1.9 +// Indirect Narrow Oop Plus Offset Operand
1.10 +operand indNarrowOopOffset(rRegN src, immL32 off) %{
1.11 constraint(ALLOC_IN_RC(ptr_reg));
1.12 - match(AddP (DecodeN src base) off);
1.13 + match(AddP (DecodeN src) off);
1.14
1.15 op_cost(10);
1.16 - format %{"[$base + $src << 3 + $off] (compressed)" %}
1.17 + format %{"[R12 + $src << 3 + $off] (compressed oop addressing)" %}
1.18 interface(MEMORY_INTER) %{
1.19 - base($base);
1.20 + base(0xc); // R12
1.21 index($src);
1.22 scale(0x3);
1.23 disp($off);
1.24 @@ -5365,7 +5365,7 @@
1.25
1.26 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
1.27 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset,
1.28 - indIndexScaleOffsetComp);
1.29 + indNarrowOopOffset);
1.30
1.31 //----------PIPELINE-----------------------------------------------------------
1.32 // Rules which define the behavior of the target architectures pipeline.
