Mercurial > jdk8-mips64-public > hotspot / file diff

     1.1 --- a/src/cpu/mips/vm/mips_64.ad	Tue Feb 28 11:35:32 2017 -0500
     1.2 +++ b/src/cpu/mips/vm/mips_64.ad	Tue Feb 28 12:02:36 2017 -0500
     1.3 @@ -2305,6 +2305,61 @@
     1.4       }
     1.5    %}
     1.6  
     1.7 +  enc_class store_C0_enc (memory mem) %{
     1.8 +     MacroAssembler _masm(&cbuf);
     1.9 +     int  base = $mem$$base;
    1.10 +     int  index = $mem$$index;
    1.11 +     int  scale = $mem$$scale;
    1.12 +     int  disp = $mem$$disp;
    1.13 +
    1.14 +     if( index != 0 ) {
    1.15 +        if( Assembler::is_simm16(disp) ) { 
    1.16 +           if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
    1.17 +              if (scale == 0) {
    1.18 +                 __ gsshx(R0, as_Register(base), as_Register(index), disp);
    1.19 +              } else {
    1.20 +                 __ dsll(AT, as_Register(index), scale);
    1.21 +                 __ gsshx(R0, as_Register(base), AT, disp);
    1.22 +              }
    1.23 +           } else {
    1.24 +              if (scale == 0) {
    1.25 +                 __ addu(AT, as_Register(base), as_Register(index));
    1.26 +              } else {
    1.27 +                 __ dsll(AT, as_Register(index), scale);
    1.28 +                 __ addu(AT, as_Register(base), AT);
    1.29 +              }
    1.30 +              __ sh(R0, AT, disp);
    1.31 +           }
    1.32 +        } else {
    1.33 +           if (scale == 0) {
    1.34 +              __ addu(AT, as_Register(base), as_Register(index));
    1.35 +           } else {
    1.36 +              __ dsll(AT, as_Register(index), scale);
    1.37 +              __ addu(AT, as_Register(base), AT);
    1.38 +           }
    1.39 +           __ move(T9, disp);
    1.40 +           if( UseLoongsonISA ) {
    1.41 +              __ gsshx(R0, AT, T9, 0);
    1.42 +           } else {
    1.43 +              __ addu(AT, AT, T9); 
    1.44 +              __ sh(R0, AT, 0);
    1.45 +           }
    1.46 +        }    
    1.47 +     } else {
    1.48 +        if( Assembler::is_simm16(disp) ) { 
    1.49 +           __ sh(R0, as_Register(base), disp);
    1.50 +        } else {
    1.51 +           __ move(T9, disp);   
    1.52 +           if( UseLoongsonISA ) {
    1.53 +              __ gsshx(R0, as_Register(base), T9, 0);
    1.54 +           } else {
    1.55 +              __ addu(AT, as_Register(base), T9); 
    1.56 +              __ sh(R0, AT, 0);
    1.57 +           }
    1.58 +        }    
    1.59 +     }
    1.60 +  %}
    1.61 +
    1.62    enc_class load_I_enc (mRegI dst, memory mem) %{
    1.63       MacroAssembler _masm(&cbuf);
    1.64       int  dst = $dst$$reg;
    1.65 @@ -11998,11 +12053,20 @@
    1.66    match(Set mem (StoreC mem src));
    1.67  
    1.68    ins_cost(125);
    1.69 -  format %{ "storeC  $src,$mem @ storeC" %}
    1.70 +  format %{ "storeC  $src, $mem @ storeC" %}
    1.71    ins_encode(store_C_reg_enc(mem, src));
    1.72    ins_pipe( ialu_loadI );
    1.73  %}
    1.74  
    1.75 +instruct storeC0(memory mem, immI0 zero) %{
    1.76 +  match(Set mem (StoreC mem zero));
    1.77 +
    1.78 +  ins_cost(125);
    1.79 +  format %{ "storeC  $zero, $mem @ storeC0" %}
    1.80 +  ins_encode(store_C0_enc(mem));
    1.81 +  ins_pipe( ialu_loadI );
    1.82 +%}
    1.83 +
    1.84  
    1.85  instruct loadConF0(regF dst, immF0 zero) %{
    1.86    match(Set dst zero);