1.1 --- a/src/cpu/sparc/vm/vm_version_sparc.hpp Thu Jul 21 08:38:25 2011 -0700
1.2 +++ b/src/cpu/sparc/vm/vm_version_sparc.hpp Thu Jul 21 11:25:07 2011 -0700
1.3 @@ -31,44 +31,46 @@
1.4 class VM_Version: public Abstract_VM_Version {
1.5 protected:
1.6 enum Feature_Flag {
1.7 - v8_instructions = 0,
1.8 - hardware_mul32 = 1,
1.9 - hardware_div32 = 2,
1.10 - hardware_fsmuld = 3,
1.11 - hardware_popc = 4,
1.12 - v9_instructions = 5,
1.13 - vis1_instructions = 6,
1.14 - vis2_instructions = 7,
1.15 - sun4v_instructions = 8,
1.16 + v8_instructions = 0,
1.17 + hardware_mul32 = 1,
1.18 + hardware_div32 = 2,
1.19 + hardware_fsmuld = 3,
1.20 + hardware_popc = 4,
1.21 + v9_instructions = 5,
1.22 + vis1_instructions = 6,
1.23 + vis2_instructions = 7,
1.24 + sun4v_instructions = 8,
1.25 blk_init_instructions = 9,
1.26 - fmaf_instructions = 10,
1.27 - fmau_instructions = 11,
1.28 - vis3_instructions = 12,
1.29 - sparc64_family = 13,
1.30 - T_family = 14,
1.31 - T1_model = 15
1.32 + fmaf_instructions = 10,
1.33 + fmau_instructions = 11,
1.34 + vis3_instructions = 12,
1.35 + sparc64_family = 13,
1.36 + T_family = 14,
1.37 + T1_model = 15,
1.38 + cbcond_instructions = 16
1.39 };
1.40
1.41 enum Feature_Flag_Set {
1.42 unknown_m = 0,
1.43 all_features_m = -1,
1.44
1.45 - v8_instructions_m = 1 << v8_instructions,
1.46 - hardware_mul32_m = 1 << hardware_mul32,
1.47 - hardware_div32_m = 1 << hardware_div32,
1.48 - hardware_fsmuld_m = 1 << hardware_fsmuld,
1.49 - hardware_popc_m = 1 << hardware_popc,
1.50 - v9_instructions_m = 1 << v9_instructions,
1.51 - vis1_instructions_m = 1 << vis1_instructions,
1.52 - vis2_instructions_m = 1 << vis2_instructions,
1.53 - sun4v_m = 1 << sun4v_instructions,
1.54 + v8_instructions_m = 1 << v8_instructions,
1.55 + hardware_mul32_m = 1 << hardware_mul32,
1.56 + hardware_div32_m = 1 << hardware_div32,
1.57 + hardware_fsmuld_m = 1 << hardware_fsmuld,
1.58 + hardware_popc_m = 1 << hardware_popc,
1.59 + v9_instructions_m = 1 << v9_instructions,
1.60 + vis1_instructions_m = 1 << vis1_instructions,
1.61 + vis2_instructions_m = 1 << vis2_instructions,
1.62 + sun4v_m = 1 << sun4v_instructions,
1.63 blk_init_instructions_m = 1 << blk_init_instructions,
1.64 - fmaf_instructions_m = 1 << fmaf_instructions,
1.65 - fmau_instructions_m = 1 << fmau_instructions,
1.66 - vis3_instructions_m = 1 << vis3_instructions,
1.67 - sparc64_family_m = 1 << sparc64_family,
1.68 - T_family_m = 1 << T_family,
1.69 - T1_model_m = 1 << T1_model,
1.70 + fmaf_instructions_m = 1 << fmaf_instructions,
1.71 + fmau_instructions_m = 1 << fmau_instructions,
1.72 + vis3_instructions_m = 1 << vis3_instructions,
1.73 + sparc64_family_m = 1 << sparc64_family,
1.74 + T_family_m = 1 << T_family,
1.75 + T1_model_m = 1 << T1_model,
1.76 + cbcond_instructions_m = 1 << cbcond_instructions,
1.77
1.78 generic_v8_m = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m,
1.79 generic_v9_m = generic_v8_m | v9_instructions_m,
1.80 @@ -111,20 +113,25 @@
1.81 static bool has_vis2() { return (_features & vis2_instructions_m) != 0; }
1.82 static bool has_vis3() { return (_features & vis3_instructions_m) != 0; }
1.83 static bool has_blk_init() { return (_features & blk_init_instructions_m) != 0; }
1.84 + static bool has_cbcond() { return (_features & cbcond_instructions_m) != 0; }
1.85
1.86 static bool supports_compare_and_exchange()
1.87 { return has_v9(); }
1.88
1.89 - static bool is_ultra3() { return (_features & ultra3_m) == ultra3_m; }
1.90 - static bool is_sun4v() { return (_features & sun4v_m) != 0; }
1.91 // Returns true if the platform is in the niagara line (T series)
1.92 // and newer than the niagara1.
1.93 static bool is_niagara_plus() { return is_T_family(_features) && !is_T1_model(_features); }
1.94 +
1.95 // Fujitsu SPARC64
1.96 static bool is_sparc64() { return (_features & sparc64_family_m) != 0; }
1.97
1.98 + static bool is_sun4v() { return (_features & sun4v_m) != 0; }
1.99 + static bool is_ultra3() { return (_features & ultra3_m) == ultra3_m && !is_sun4v() && !is_sparc64(); }
1.100 +
1.101 static bool has_fast_fxtof() { return is_niagara() || is_sparc64() || has_v9() && !is_ultra3(); }
1.102 static bool has_fast_idiv() { return is_niagara_plus() || is_sparc64(); }
1.103 + // T4 and newer Sparc have fast RDPC instruction.
1.104 + static bool has_fast_rdpc() { return is_niagara_plus() && has_cbcond(); }
1.105
1.106 static const char* cpu_features() { return _features_str; }
1.107
