1.1 --- a/src/cpu/sparc/vm/vm_version_sparc.hpp Tue Aug 16 11:53:57 2011 -0700
1.2 +++ b/src/cpu/sparc/vm/vm_version_sparc.hpp Tue Aug 16 16:59:46 2011 -0700
1.3 @@ -121,6 +121,7 @@
1.4 // Returns true if the platform is in the niagara line (T series)
1.5 // and newer than the niagara1.
1.6 static bool is_niagara_plus() { return is_T_family(_features) && !is_T1_model(_features); }
1.7 + static bool is_T4() { return is_T_family(_features) && has_cbcond(); }
1.8
1.9 // Fujitsu SPARC64
1.10 static bool is_sparc64() { return (_features & sparc64_family_m) != 0; }
1.11 @@ -130,13 +131,17 @@
1.12
1.13 static bool has_fast_fxtof() { return is_niagara() || is_sparc64() || has_v9() && !is_ultra3(); }
1.14 static bool has_fast_idiv() { return is_niagara_plus() || is_sparc64(); }
1.15 +
1.16 // T4 and newer Sparc have fast RDPC instruction.
1.17 - static bool has_fast_rdpc() { return is_niagara_plus() && has_cbcond(); }
1.18 + static bool has_fast_rdpc() { return is_T4(); }
1.19 +
1.20 + // T4 and newer Sparc have Most-Recently-Used (MRU) BIS.
1.21 + static bool has_mru_blk_init() { return has_blk_init() && is_T4(); }
1.22
1.23 static const char* cpu_features() { return _features_str; }
1.24
1.25 - static intx L1_data_cache_line_size() {
1.26 - return 64; // default prefetch block size on sparc
1.27 + static intx prefetch_data_size() {
1.28 + return is_T4() ? 32 : 64; // default prefetch block size on sparc
1.29 }
1.30
1.31 // Prefetch
