1.1 --- a/src/share/vm/utilities/globalDefinitions.hpp Tue Jan 07 17:24:59 2014 +0100
1.2 +++ b/src/share/vm/utilities/globalDefinitions.hpp Thu Jan 16 14:25:51 2014 +0100
1.3 @@ -398,6 +398,17 @@
1.4 #define PLATFORM_NATIVE_STACK_WALKING_SUPPORTED 1
1.5 #endif
1.6
1.7 +// To assure the IRIW property on processors that are not multiple copy
1.8 +// atomic, sync instructions must be issued between volatile reads to
1.9 +// assure their ordering, instead of after volatile stores.
1.10 +// (See "A Tutorial Introduction to the ARM and POWER Relaxed Memory Models"
1.11 +// by Luc Maranget, Susmit Sarkar and Peter Sewell, INRIA/Cambridge)
1.12 +#ifdef CPU_NOT_MULTIPLE_COPY_ATOMIC
1.13 +const bool support_IRIW_for_not_multiple_copy_atomic_cpu = true;
1.14 +#else
1.15 +const bool support_IRIW_for_not_multiple_copy_atomic_cpu = false;
1.16 +#endif
1.17 +
1.18 // The byte alignment to be used by Arena::Amalloc. See bugid 4169348.
1.19 // Note: this value must be a power of 2
1.20
