Mercurial > jdk8-mips64-public > hotspot / file comparison
comparison: src/share/vm/utilities/globalDefinitions.hpp
src/share/vm/utilities/globalDefinitions.hpp
- changeset 6502
- 3514ee402842
- parent 6485
- da862781b584
- child 6518
- 62c54fcc0a35
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| 6501:c668f307a4c0 | 6502:3514ee402842 |
|---|---|
| 394 * the platform specific globalDefinitions (above) | 394 * the platform specific globalDefinitions (above) |
| 395 * can set PLATFORM_NATIVE_STACK_WALKING_SUPPORTED to 0 | 395 * can set PLATFORM_NATIVE_STACK_WALKING_SUPPORTED to 0 |
| 396 */ | 396 */ |
| 397 #ifndef PLATFORM_NATIVE_STACK_WALKING_SUPPORTED | 397 #ifndef PLATFORM_NATIVE_STACK_WALKING_SUPPORTED |
| 398 #define PLATFORM_NATIVE_STACK_WALKING_SUPPORTED 1 | 398 #define PLATFORM_NATIVE_STACK_WALKING_SUPPORTED 1 |
| 399 #endif | |
| 400 | |
| 401 // To assure the IRIW property on processors that are not multiple copy | |
| 402 // atomic, sync instructions must be issued between volatile reads to | |
| 403 // assure their ordering, instead of after volatile stores. | |
| 404 // (See "A Tutorial Introduction to the ARM and POWER Relaxed Memory Models" | |
| 405 // by Luc Maranget, Susmit Sarkar and Peter Sewell, INRIA/Cambridge) | |
| 406 #ifdef CPU_NOT_MULTIPLE_COPY_ATOMIC | |
| 407 const bool support_IRIW_for_not_multiple_copy_atomic_cpu = true; | |
| 408 #else | |
| 409 const bool support_IRIW_for_not_multiple_copy_atomic_cpu = false; | |
| 399 #endif | 410 #endif |
| 400 | 411 |
| 401 // The byte alignment to be used by Arena::Amalloc. See bugid 4169348. | 412 // The byte alignment to be used by Arena::Amalloc. See bugid 4169348. |
| 402 // Note: this value must be a power of 2 | 413 // Note: this value must be a power of 2 |
| 403 | 414 |
