1.1 --- a/src/cpu/x86/vm/x86.ad Fri Jun 15 15:37:35 2018 +0000
1.2 +++ b/src/cpu/x86/vm/x86.ad Mon Jun 18 14:39:46 2018 -0700
1.3 @@ -1,5 +1,5 @@
1.4 //
1.5 -// Copyright (c) 2011, 2012, Oracle and/or its affiliates. All rights reserved.
1.6 +// Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved.
1.7 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1.8 //
1.9 // This code is free software; you can redistribute it and/or modify it
1.10 @@ -683,7 +683,7 @@
1.11 }
1.12
1.13 // Vector ideal reg corresponding to specidied size in bytes
1.14 -const int Matcher::vector_ideal_reg(int size) {
1.15 +const uint Matcher::vector_ideal_reg(int size) {
1.16 assert(MaxVectorSize >= size, "");
1.17 switch(size) {
1.18 case 4: return Op_VecS;
1.19 @@ -696,7 +696,7 @@
1.20 }
1.21
1.22 // Only lowest bits of xmm reg are used for vector shift count.
1.23 -const int Matcher::vector_shift_count_ideal_reg(int size) {
1.24 +const uint Matcher::vector_shift_count_ideal_reg(int size) {
1.25 return Op_VecS;
1.26 }
1.27
