1.1 --- a/src/cpu/x86/vm/x86_32.ad Thu Dec 02 17:21:12 2010 -0800
1.2 +++ b/src/cpu/x86/vm/x86_32.ad Fri Dec 03 01:34:31 2010 -0800
1.3 @@ -507,6 +507,25 @@
1.4
1.5
1.6 //=============================================================================
1.7 +const bool Matcher::constant_table_absolute_addressing = true;
1.8 +const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
1.9 +
1.10 +void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1.11 + // Empty encoding
1.12 +}
1.13 +
1.14 +uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1.15 + return 0;
1.16 +}
1.17 +
1.18 +#ifndef PRODUCT
1.19 +void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1.20 + st->print("# MachConstantBaseNode (empty encoding)");
1.21 +}
1.22 +#endif
1.23 +
1.24 +
1.25 +//=============================================================================
1.26 #ifndef PRODUCT
1.27 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1.28 Compile* C = ra_->C;
1.29 @@ -1320,29 +1339,6 @@
1.30 }
1.31
1.32
1.33 -static void emit_double_constant(CodeBuffer& cbuf, double x) {
1.34 - int mark = cbuf.insts()->mark_off();
1.35 - MacroAssembler _masm(&cbuf);
1.36 - address double_address = __ double_constant(x);
1.37 - cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1.38 - emit_d32_reloc(cbuf,
1.39 - (int)double_address,
1.40 - internal_word_Relocation::spec(double_address),
1.41 - RELOC_DISP32);
1.42 -}
1.43 -
1.44 -static void emit_float_constant(CodeBuffer& cbuf, float x) {
1.45 - int mark = cbuf.insts()->mark_off();
1.46 - MacroAssembler _masm(&cbuf);
1.47 - address float_address = __ float_constant(x);
1.48 - cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1.49 - emit_d32_reloc(cbuf,
1.50 - (int)float_address,
1.51 - internal_word_Relocation::spec(float_address),
1.52 - RELOC_DISP32);
1.53 -}
1.54 -
1.55 -
1.56 const bool Matcher::match_rule_supported(int opcode) {
1.57 if (!has_match_rule(opcode))
1.58 return false;
1.59 @@ -1354,22 +1350,6 @@
1.60 return regnum - 32; // The FP registers are in the second chunk
1.61 }
1.62
1.63 -bool is_positive_zero_float(jfloat f) {
1.64 - return jint_cast(f) == jint_cast(0.0F);
1.65 -}
1.66 -
1.67 -bool is_positive_one_float(jfloat f) {
1.68 - return jint_cast(f) == jint_cast(1.0F);
1.69 -}
1.70 -
1.71 -bool is_positive_zero_double(jdouble d) {
1.72 - return jlong_cast(d) == jlong_cast(0.0);
1.73 -}
1.74 -
1.75 -bool is_positive_one_double(jdouble d) {
1.76 - return jlong_cast(d) == jlong_cast(1.0);
1.77 -}
1.78 -
1.79 // This is UltraSparc specific, true just means we have fast l2f conversion
1.80 const bool Matcher::convL2FSupported(void) {
1.81 return true;
1.82 @@ -2036,67 +2016,6 @@
1.83 %}
1.84
1.85
1.86 - enc_class LdImmD (immD src) %{ // Load Immediate
1.87 - if( is_positive_zero_double($src$$constant)) {
1.88 - // FLDZ
1.89 - emit_opcode(cbuf,0xD9);
1.90 - emit_opcode(cbuf,0xEE);
1.91 - } else if( is_positive_one_double($src$$constant)) {
1.92 - // FLD1
1.93 - emit_opcode(cbuf,0xD9);
1.94 - emit_opcode(cbuf,0xE8);
1.95 - } else {
1.96 - emit_opcode(cbuf,0xDD);
1.97 - emit_rm(cbuf, 0x0, 0x0, 0x5);
1.98 - emit_double_constant(cbuf, $src$$constant);
1.99 - }
1.100 - %}
1.101 -
1.102 -
1.103 - enc_class LdImmF (immF src) %{ // Load Immediate
1.104 - if( is_positive_zero_float($src$$constant)) {
1.105 - emit_opcode(cbuf,0xD9);
1.106 - emit_opcode(cbuf,0xEE);
1.107 - } else if( is_positive_one_float($src$$constant)) {
1.108 - emit_opcode(cbuf,0xD9);
1.109 - emit_opcode(cbuf,0xE8);
1.110 - } else {
1.111 - $$$emit8$primary;
1.112 - // Load immediate does not have a zero or sign extended version
1.113 - // for 8-bit immediates
1.114 - // First load to TOS, then move to dst
1.115 - emit_rm(cbuf, 0x0, 0x0, 0x5);
1.116 - emit_float_constant(cbuf, $src$$constant);
1.117 - }
1.118 - %}
1.119 -
1.120 - enc_class LdImmX (regX dst, immXF con) %{ // Load Immediate
1.121 - emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1.122 - emit_float_constant(cbuf, $con$$constant);
1.123 - %}
1.124 -
1.125 - enc_class LdImmXD (regXD dst, immXD con) %{ // Load Immediate
1.126 - emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1.127 - emit_double_constant(cbuf, $con$$constant);
1.128 - %}
1.129 -
1.130 - enc_class load_conXD (regXD dst, immXD con) %{ // Load double constant
1.131 - // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con)
1.132 - emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
1.133 - emit_opcode(cbuf, 0x0F);
1.134 - emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
1.135 - emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1.136 - emit_double_constant(cbuf, $con$$constant);
1.137 - %}
1.138 -
1.139 - enc_class Opc_MemImm_F(immF src) %{
1.140 - cbuf.set_insts_mark();
1.141 - $$$emit8$primary;
1.142 - emit_rm(cbuf, 0x0, $secondary, 0x5);
1.143 - emit_float_constant(cbuf, $src$$constant);
1.144 - %}
1.145 -
1.146 -
1.147 enc_class MovI2X_reg(regX dst, eRegI src) %{
1.148 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
1.149 emit_opcode(cbuf, 0x0F );
1.150 @@ -4801,7 +4720,7 @@
1.151 interface(CONST_INTER);
1.152 %}
1.153
1.154 -// Double Immediate
1.155 +// Double Immediate one
1.156 operand immD1() %{
1.157 predicate( UseSSE<=1 && n->getd() == 1.0 );
1.158 match(ConD);
1.159 @@ -4844,7 +4763,17 @@
1.160
1.161 // Float Immediate zero
1.162 operand immF0() %{
1.163 - predicate( UseSSE == 0 && n->getf() == 0.0 );
1.164 + predicate(UseSSE == 0 && n->getf() == 0.0F);
1.165 + match(ConF);
1.166 +
1.167 + op_cost(5);
1.168 + format %{ %}
1.169 + interface(CONST_INTER);
1.170 +%}
1.171 +
1.172 +// Float Immediate one
1.173 +operand immF1() %{
1.174 + predicate(UseSSE == 0 && n->getf() == 1.0F);
1.175 match(ConF);
1.176
1.177 op_cost(5);
1.178 @@ -7215,24 +7144,53 @@
1.179 %}
1.180
1.181 // The instruction usage is guarded by predicate in operand immF().
1.182 -instruct loadConF(regF dst, immF src) %{
1.183 - match(Set dst src);
1.184 +instruct loadConF(regF dst, immF con) %{
1.185 + match(Set dst con);
1.186 ins_cost(125);
1.187 -
1.188 - format %{ "FLD_S ST,$src\n\t"
1.189 + format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
1.190 "FSTP $dst" %}
1.191 - opcode(0xD9, 0x00); /* D9 /0 */
1.192 - ins_encode(LdImmF(src), Pop_Reg_F(dst) );
1.193 - ins_pipe( fpu_reg_con );
1.194 + ins_encode %{
1.195 + __ fld_s($constantaddress($con));
1.196 + __ fstp_d($dst$$reg);
1.197 + %}
1.198 + ins_pipe(fpu_reg_con);
1.199 +%}
1.200 +
1.201 +// The instruction usage is guarded by predicate in operand immF0().
1.202 +instruct loadConF0(regF dst, immF0 con) %{
1.203 + match(Set dst con);
1.204 + ins_cost(125);
1.205 + format %{ "FLDZ ST\n\t"
1.206 + "FSTP $dst" %}
1.207 + ins_encode %{
1.208 + __ fldz();
1.209 + __ fstp_d($dst$$reg);
1.210 + %}
1.211 + ins_pipe(fpu_reg_con);
1.212 +%}
1.213 +
1.214 +// The instruction usage is guarded by predicate in operand immF1().
1.215 +instruct loadConF1(regF dst, immF1 con) %{
1.216 + match(Set dst con);
1.217 + ins_cost(125);
1.218 + format %{ "FLD1 ST\n\t"
1.219 + "FSTP $dst" %}
1.220 + ins_encode %{
1.221 + __ fld1();
1.222 + __ fstp_d($dst$$reg);
1.223 + %}
1.224 + ins_pipe(fpu_reg_con);
1.225 %}
1.226
1.227 // The instruction usage is guarded by predicate in operand immXF().
1.228 instruct loadConX(regX dst, immXF con) %{
1.229 match(Set dst con);
1.230 ins_cost(125);
1.231 - format %{ "MOVSS $dst,[$con]" %}
1.232 - ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), LdImmX(dst, con));
1.233 - ins_pipe( pipe_slow );
1.234 + format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
1.235 + ins_encode %{
1.236 + __ movflt($dst$$XMMRegister, $constantaddress($con));
1.237 + %}
1.238 + ins_pipe(pipe_slow);
1.239 %}
1.240
1.241 // The instruction usage is guarded by predicate in operand immXF0().
1.242 @@ -7240,28 +7198,63 @@
1.243 match(Set dst src);
1.244 ins_cost(100);
1.245 format %{ "XORPS $dst,$dst\t# float 0.0" %}
1.246 - ins_encode( Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
1.247 - ins_pipe( pipe_slow );
1.248 + ins_encode %{
1.249 + __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
1.250 + %}
1.251 + ins_pipe(pipe_slow);
1.252 %}
1.253
1.254 // The instruction usage is guarded by predicate in operand immD().
1.255 -instruct loadConD(regD dst, immD src) %{
1.256 - match(Set dst src);
1.257 +instruct loadConD(regD dst, immD con) %{
1.258 + match(Set dst con);
1.259 ins_cost(125);
1.260
1.261 - format %{ "FLD_D ST,$src\n\t"
1.262 + format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
1.263 "FSTP $dst" %}
1.264 - ins_encode(LdImmD(src), Pop_Reg_D(dst) );
1.265 - ins_pipe( fpu_reg_con );
1.266 + ins_encode %{
1.267 + __ fld_d($constantaddress($con));
1.268 + __ fstp_d($dst$$reg);
1.269 + %}
1.270 + ins_pipe(fpu_reg_con);
1.271 +%}
1.272 +
1.273 +// The instruction usage is guarded by predicate in operand immD0().
1.274 +instruct loadConD0(regD dst, immD0 con) %{
1.275 + match(Set dst con);
1.276 + ins_cost(125);
1.277 +
1.278 + format %{ "FLDZ ST\n\t"
1.279 + "FSTP $dst" %}
1.280 + ins_encode %{
1.281 + __ fldz();
1.282 + __ fstp_d($dst$$reg);
1.283 + %}
1.284 + ins_pipe(fpu_reg_con);
1.285 +%}
1.286 +
1.287 +// The instruction usage is guarded by predicate in operand immD1().
1.288 +instruct loadConD1(regD dst, immD1 con) %{
1.289 + match(Set dst con);
1.290 + ins_cost(125);
1.291 +
1.292 + format %{ "FLD1 ST\n\t"
1.293 + "FSTP $dst" %}
1.294 + ins_encode %{
1.295 + __ fld1();
1.296 + __ fstp_d($dst$$reg);
1.297 + %}
1.298 + ins_pipe(fpu_reg_con);
1.299 %}
1.300
1.301 // The instruction usage is guarded by predicate in operand immXD().
1.302 instruct loadConXD(regXD dst, immXD con) %{
1.303 match(Set dst con);
1.304 ins_cost(125);
1.305 - format %{ "MOVSD $dst,[$con]" %}
1.306 - ins_encode(load_conXD(dst, con));
1.307 - ins_pipe( pipe_slow );
1.308 + format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
1.309 + ins_encode %{
1.310 + __ movdbl($dst$$XMMRegister, $constantaddress($con));
1.311 + %}
1.312 + ins_pipe(pipe_slow);
1.313 %}
1.314
1.315 // The instruction usage is guarded by predicate in operand immXD0().
1.316 @@ -10303,41 +10296,45 @@
1.317 ins_pipe( fpu_reg_mem );
1.318 %}
1.319
1.320 -instruct addD_reg_imm1(regD dst, immD1 src) %{
1.321 +instruct addD_reg_imm1(regD dst, immD1 con) %{
1.322 predicate(UseSSE<=1);
1.323 - match(Set dst (AddD dst src));
1.324 + match(Set dst (AddD dst con));
1.325 ins_cost(125);
1.326 format %{ "FLD1\n\t"
1.327 "DADDp $dst,ST" %}
1.328 - opcode(0xDE, 0x00);
1.329 - ins_encode( LdImmD(src),
1.330 - OpcP, RegOpc(dst) );
1.331 - ins_pipe( fpu_reg );
1.332 -%}
1.333 -
1.334 -instruct addD_reg_imm(regD dst, immD src) %{
1.335 + ins_encode %{
1.336 + __ fld1();
1.337 + __ faddp($dst$$reg);
1.338 + %}
1.339 + ins_pipe(fpu_reg);
1.340 +%}
1.341 +
1.342 +instruct addD_reg_imm(regD dst, immD con) %{
1.343 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
1.344 - match(Set dst (AddD dst src));
1.345 + match(Set dst (AddD dst con));
1.346 ins_cost(200);
1.347 - format %{ "FLD_D [$src]\n\t"
1.348 + format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
1.349 "DADDp $dst,ST" %}
1.350 - opcode(0xDE, 0x00); /* DE /0 */
1.351 - ins_encode( LdImmD(src),
1.352 - OpcP, RegOpc(dst));
1.353 - ins_pipe( fpu_reg_mem );
1.354 + ins_encode %{
1.355 + __ fld_d($constantaddress($con));
1.356 + __ faddp($dst$$reg);
1.357 + %}
1.358 + ins_pipe(fpu_reg_mem);
1.359 %}
1.360
1.361 instruct addD_reg_imm_round(stackSlotD dst, regD src, immD con) %{
1.362 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
1.363 match(Set dst (RoundDouble (AddD src con)));
1.364 ins_cost(200);
1.365 - format %{ "FLD_D [$con]\n\t"
1.366 + format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
1.367 "DADD ST,$src\n\t"
1.368 "FSTP_D $dst\t# D-round" %}
1.369 - opcode(0xD8, 0x00); /* D8 /0 */
1.370 - ins_encode( LdImmD(con),
1.371 - OpcP, RegOpc(src), Pop_Mem_D(dst));
1.372 - ins_pipe( fpu_mem_reg_con );
1.373 + ins_encode %{
1.374 + __ fld_d($constantaddress($con));
1.375 + __ fadd($src$$reg);
1.376 + __ fstp_d(Address(rsp, $dst$$disp));
1.377 + %}
1.378 + ins_pipe(fpu_mem_reg_con);
1.379 %}
1.380
1.381 // Add two double precision floating point values in xmm
1.382 @@ -10352,9 +10349,11 @@
1.383 instruct addXD_imm(regXD dst, immXD con) %{
1.384 predicate(UseSSE>=2);
1.385 match(Set dst (AddD dst con));
1.386 - format %{ "ADDSD $dst,[$con]" %}
1.387 - ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), LdImmXD(dst, con) );
1.388 - ins_pipe( pipe_slow );
1.389 + format %{ "ADDSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
1.390 + ins_encode %{
1.391 + __ addsd($dst$$XMMRegister, $constantaddress($con));
1.392 + %}
1.393 + ins_pipe(pipe_slow);
1.394 %}
1.395
1.396 instruct addXD_mem(regXD dst, memory mem) %{
1.397 @@ -10377,9 +10376,11 @@
1.398 instruct subXD_imm(regXD dst, immXD con) %{
1.399 predicate(UseSSE>=2);
1.400 match(Set dst (SubD dst con));
1.401 - format %{ "SUBSD $dst,[$con]" %}
1.402 - ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), LdImmXD(dst, con) );
1.403 - ins_pipe( pipe_slow );
1.404 + format %{ "SUBSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
1.405 + ins_encode %{
1.406 + __ subsd($dst$$XMMRegister, $constantaddress($con));
1.407 + %}
1.408 + ins_pipe(pipe_slow);
1.409 %}
1.410
1.411 instruct subXD_mem(regXD dst, memory mem) %{
1.412 @@ -10402,9 +10403,11 @@
1.413 instruct mulXD_imm(regXD dst, immXD con) %{
1.414 predicate(UseSSE>=2);
1.415 match(Set dst (MulD dst con));
1.416 - format %{ "MULSD $dst,[$con]" %}
1.417 - ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), LdImmXD(dst, con) );
1.418 - ins_pipe( pipe_slow );
1.419 + format %{ "MULSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
1.420 + ins_encode %{
1.421 + __ mulsd($dst$$XMMRegister, $constantaddress($con));
1.422 + %}
1.423 + ins_pipe(pipe_slow);
1.424 %}
1.425
1.426 instruct mulXD_mem(regXD dst, memory mem) %{
1.427 @@ -10428,9 +10431,11 @@
1.428 instruct divXD_imm(regXD dst, immXD con) %{
1.429 predicate(UseSSE>=2);
1.430 match(Set dst (DivD dst con));
1.431 - format %{ "DIVSD $dst,[$con]" %}
1.432 - ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), LdImmXD(dst, con));
1.433 - ins_pipe( pipe_slow );
1.434 + format %{ "DIVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
1.435 + ins_encode %{
1.436 + __ divsd($dst$$XMMRegister, $constantaddress($con));
1.437 + %}
1.438 + ins_pipe(pipe_slow);
1.439 %}
1.440
1.441 instruct divXD_mem(regXD dst, memory mem) %{
1.442 @@ -10481,16 +10486,17 @@
1.443 ins_pipe( fpu_reg_reg );
1.444 %}
1.445
1.446 -instruct mulD_reg_imm(regD dst, immD src) %{
1.447 +instruct mulD_reg_imm(regD dst, immD con) %{
1.448 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
1.449 - match(Set dst (MulD dst src));
1.450 + match(Set dst (MulD dst con));
1.451 ins_cost(200);
1.452 - format %{ "FLD_D [$src]\n\t"
1.453 + format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
1.454 "DMULp $dst,ST" %}
1.455 - opcode(0xDE, 0x1); /* DE /1 */
1.456 - ins_encode( LdImmD(src),
1.457 - OpcP, RegOpc(dst) );
1.458 - ins_pipe( fpu_reg_mem );
1.459 + ins_encode %{
1.460 + __ fld_d($constantaddress($con));
1.461 + __ fmulp($dst$$reg);
1.462 + %}
1.463 + ins_pipe(fpu_reg_mem);
1.464 %}
1.465
1.466
1.467 @@ -11224,9 +11230,11 @@
1.468 instruct addX_imm(regX dst, immXF con) %{
1.469 predicate(UseSSE>=1);
1.470 match(Set dst (AddF dst con));
1.471 - format %{ "ADDSS $dst,[$con]" %}
1.472 - ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), LdImmX(dst, con) );
1.473 - ins_pipe( pipe_slow );
1.474 + format %{ "ADDSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
1.475 + ins_encode %{
1.476 + __ addss($dst$$XMMRegister, $constantaddress($con));
1.477 + %}
1.478 + ins_pipe(pipe_slow);
1.479 %}
1.480
1.481 instruct addX_mem(regX dst, memory mem) %{
1.482 @@ -11249,9 +11257,11 @@
1.483 instruct subX_imm(regX dst, immXF con) %{
1.484 predicate(UseSSE>=1);
1.485 match(Set dst (SubF dst con));
1.486 - format %{ "SUBSS $dst,[$con]" %}
1.487 - ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), LdImmX(dst, con) );
1.488 - ins_pipe( pipe_slow );
1.489 + format %{ "SUBSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
1.490 + ins_encode %{
1.491 + __ subss($dst$$XMMRegister, $constantaddress($con));
1.492 + %}
1.493 + ins_pipe(pipe_slow);
1.494 %}
1.495
1.496 instruct subX_mem(regX dst, memory mem) %{
1.497 @@ -11274,9 +11284,11 @@
1.498 instruct mulX_imm(regX dst, immXF con) %{
1.499 predicate(UseSSE>=1);
1.500 match(Set dst (MulF dst con));
1.501 - format %{ "MULSS $dst,[$con]" %}
1.502 - ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), LdImmX(dst, con) );
1.503 - ins_pipe( pipe_slow );
1.504 + format %{ "MULSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
1.505 + ins_encode %{
1.506 + __ mulss($dst$$XMMRegister, $constantaddress($con));
1.507 + %}
1.508 + ins_pipe(pipe_slow);
1.509 %}
1.510
1.511 instruct mulX_mem(regX dst, memory mem) %{
1.512 @@ -11299,9 +11311,11 @@
1.513 instruct divX_imm(regX dst, immXF con) %{
1.514 predicate(UseSSE>=1);
1.515 match(Set dst (DivF dst con));
1.516 - format %{ "DIVSS $dst,[$con]" %}
1.517 - ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), LdImmX(dst, con) );
1.518 - ins_pipe( pipe_slow );
1.519 + format %{ "DIVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
1.520 + ins_encode %{
1.521 + __ divss($dst$$XMMRegister, $constantaddress($con));
1.522 + %}
1.523 + ins_pipe(pipe_slow);
1.524 %}
1.525
1.526 instruct divX_mem(regX dst, memory mem) %{
1.527 @@ -11456,31 +11470,33 @@
1.528
1.529
1.530 // Spill to obtain 24-bit precision
1.531 -instruct addF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
1.532 +instruct addF24_reg_imm(stackSlotF dst, regF src, immF con) %{
1.533 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
1.534 - match(Set dst (AddF src1 src2));
1.535 - format %{ "FLD $src1\n\t"
1.536 - "FADD $src2\n\t"
1.537 + match(Set dst (AddF src con));
1.538 + format %{ "FLD $src\n\t"
1.539 + "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
1.540 "FSTP_S $dst" %}
1.541 - opcode(0xD8, 0x00); /* D8 /0 */
1.542 - ins_encode( Push_Reg_F(src1),
1.543 - Opc_MemImm_F(src2),
1.544 - Pop_Mem_F(dst));
1.545 - ins_pipe( fpu_mem_reg_con );
1.546 + ins_encode %{
1.547 + __ fld_s($src$$reg - 1); // FLD ST(i-1)
1.548 + __ fadd_s($constantaddress($con));
1.549 + __ fstp_s(Address(rsp, $dst$$disp));
1.550 + %}
1.551 + ins_pipe(fpu_mem_reg_con);
1.552 %}
1.553 //
1.554 // This instruction does not round to 24-bits
1.555 -instruct addF_reg_imm(regF dst, regF src1, immF src2) %{
1.556 +instruct addF_reg_imm(regF dst, regF src, immF con) %{
1.557 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
1.558 - match(Set dst (AddF src1 src2));
1.559 - format %{ "FLD $src1\n\t"
1.560 - "FADD $src2\n\t"
1.561 - "FSTP_S $dst" %}
1.562 - opcode(0xD8, 0x00); /* D8 /0 */
1.563 - ins_encode( Push_Reg_F(src1),
1.564 - Opc_MemImm_F(src2),
1.565 - Pop_Reg_F(dst));
1.566 - ins_pipe( fpu_reg_reg_con );
1.567 + match(Set dst (AddF src con));
1.568 + format %{ "FLD $src\n\t"
1.569 + "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
1.570 + "FSTP $dst" %}
1.571 + ins_encode %{
1.572 + __ fld_s($src$$reg - 1); // FLD ST(i-1)
1.573 + __ fadd_s($constantaddress($con));
1.574 + __ fstp_d($dst$$reg);
1.575 + %}
1.576 + ins_pipe(fpu_reg_reg_con);
1.577 %}
1.578
1.579 // Spill to obtain 24-bit precision
1.580 @@ -11559,29 +11575,35 @@
1.581 %}
1.582
1.583 // Spill to obtain 24-bit precision
1.584 -instruct mulF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
1.585 +instruct mulF24_reg_imm(stackSlotF dst, regF src, immF con) %{
1.586 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
1.587 - match(Set dst (MulF src1 src2));
1.588 -
1.589 - format %{ "FMULc $dst,$src1,$src2" %}
1.590 - opcode(0xD8, 0x1); /* D8 /1*/
1.591 - ins_encode( Push_Reg_F(src1),
1.592 - Opc_MemImm_F(src2),
1.593 - Pop_Mem_F(dst));
1.594 - ins_pipe( fpu_mem_reg_con );
1.595 + match(Set dst (MulF src con));
1.596 +
1.597 + format %{ "FLD $src\n\t"
1.598 + "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
1.599 + "FSTP_S $dst" %}
1.600 + ins_encode %{
1.601 + __ fld_s($src$$reg - 1); // FLD ST(i-1)
1.602 + __ fmul_s($constantaddress($con));
1.603 + __ fstp_s(Address(rsp, $dst$$disp));
1.604 + %}
1.605 + ins_pipe(fpu_mem_reg_con);
1.606 %}
1.607 //
1.608 // This instruction does not round to 24-bits
1.609 -instruct mulF_reg_imm(regF dst, regF src1, immF src2) %{
1.610 +instruct mulF_reg_imm(regF dst, regF src, immF con) %{
1.611 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
1.612 - match(Set dst (MulF src1 src2));
1.613 -
1.614 - format %{ "FMULc $dst. $src1, $src2" %}
1.615 - opcode(0xD8, 0x1); /* D8 /1*/
1.616 - ins_encode( Push_Reg_F(src1),
1.617 - Opc_MemImm_F(src2),
1.618 - Pop_Reg_F(dst));
1.619 - ins_pipe( fpu_reg_reg_con );
1.620 + match(Set dst (MulF src con));
1.621 +
1.622 + format %{ "FLD $src\n\t"
1.623 + "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
1.624 + "FSTP $dst" %}
1.625 + ins_encode %{
1.626 + __ fld_s($src$$reg - 1); // FLD ST(i-1)
1.627 + __ fmul_s($constantaddress($con));
1.628 + __ fstp_d($dst$$reg);
1.629 + %}
1.630 + ins_pipe(fpu_reg_reg_con);
1.631 %}
1.632
1.633
1.634 @@ -12939,16 +12961,11 @@
1.635 instruct jumpXtnd(eRegI switch_val) %{
1.636 match(Jump switch_val);
1.637 ins_cost(350);
1.638 -
1.639 - format %{ "JMP [table_base](,$switch_val,1)\n\t" %}
1.640 -
1.641 - ins_encode %{
1.642 - address table_base = __ address_table_constant(_index2label);
1.643 -
1.644 + format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
1.645 + ins_encode %{
1.646 // Jump to Address(table_base + switch_reg)
1.647 - InternalAddress table(table_base);
1.648 Address index(noreg, $switch_val$$Register, Address::times_1);
1.649 - __ jump(ArrayAddress(table, index));
1.650 + __ jump(ArrayAddress($constantaddress, index));
1.651 %}
1.652 ins_pc_relative(1);
1.653 ins_pipe(pipe_jmp);
