1.1 --- a/src/cpu/mips/vm/mips_64.ad Fri Feb 17 20:37:47 2017 +0800
1.2 +++ b/src/cpu/mips/vm/mips_64.ad Sat Feb 18 08:51:49 2017 +0800
1.3 @@ -2606,27 +2606,65 @@
1.4 int disp = $mem$$disp;
1.5
1.6 if( index != 0 ) {
1.7 - if (scale == 0) {
1.8 - __ daddu(AT, as_Register(base), as_Register(index));
1.9 - } else {
1.10 - __ dsll(AT, as_Register(index), scale);
1.11 - __ daddu(AT, as_Register(base), AT);
1.12 - }
1.13 - if( Assembler::is_simm16(disp) ) {
1.14 - __ sd(as_Register(src), AT, disp);
1.15 - } else {
1.16 - __ move(T9, disp);
1.17 - __ daddu(AT, AT, T9);
1.18 - __ sd(as_Register(src), AT, 0);
1.19 - }
1.20 + if ( UseLoongsonISA ){
1.21 + if ( Assembler::is_simm(disp, 8) ) {
1.22 + if ( scale == 0 ) {
1.23 + __ gssdx(as_Register(src), as_Register(base), as_Register(index), disp);
1.24 + } else {
1.25 + __ dsll(AT, as_Register(index), scale);
1.26 + __ gssdx(as_Register(src), as_Register(base), AT, disp);
1.27 + }
1.28 + } else if ( Assembler::is_simm16(disp) ) {
1.29 + if ( scale == 0 ) {
1.30 + __ daddu(AT, as_Register(base), as_Register(index));
1.31 + } else {
1.32 + __ dsll(AT, as_Register(index), scale);
1.33 + __ daddu(AT, as_Register(base), AT);
1.34 + }
1.35 + __ sd(as_Register(src), AT, disp);
1.36 + } else {
1.37 + if ( scale == 0 ) {
1.38 + __ move(T9, disp);
1.39 + __ daddu(AT, as_Register(index), T9);
1.40 + } else {
1.41 + __ dsll(AT, as_Register(index), scale);
1.42 + __ move(T9, disp);
1.43 + __ daddu(AT, AT, T9);
1.44 + }
1.45 + __ gssdx(as_Register(src), as_Register(base), AT, 0);
1.46 + }
1.47 + } else { //not use loongson isa
1.48 + if (scale == 0) {
1.49 + __ daddu(AT, as_Register(base), as_Register(index));
1.50 + } else {
1.51 + __ dsll(AT, as_Register(index), scale);
1.52 + __ daddu(AT, as_Register(base), AT);
1.53 + }
1.54 + if( Assembler::is_simm16(disp) ) {
1.55 + __ sd(as_Register(src), AT, disp);
1.56 + } else {
1.57 + __ move(T9, disp);
1.58 + __ daddu(AT, AT, T9);
1.59 + __ sd(as_Register(src), AT, 0);
1.60 + }
1.61 + }
1.62 } else {
1.63 - if( Assembler::is_simm16(disp) ) {
1.64 - __ sd(as_Register(src), as_Register(base), disp);
1.65 - } else {
1.66 - __ move(T9, disp);
1.67 - __ daddu(AT, as_Register(base), T9);
1.68 - __ sd(as_Register(src), AT, 0);
1.69 - }
1.70 + if ( UseLoongsonISA ) {
1.71 + if ( Assembler::is_simm16(disp) ) {
1.72 + __ sd(as_Register(src), as_Register(base), disp);
1.73 + } else {
1.74 + __ move(T9, disp);
1.75 + __ gssdx(as_Register(src), as_Register(base), T9, 0);
1.76 + }
1.77 + } else {
1.78 + if( Assembler::is_simm16(disp) ) {
1.79 + __ sd(as_Register(src), as_Register(base), disp);
1.80 + } else {
1.81 + __ move(T9, disp);
1.82 + __ daddu(AT, as_Register(base), T9);
1.83 + __ sd(as_Register(src), AT, 0);
1.84 + }
1.85 + }
1.86 }
1.87 %}
1.88
