1.1 --- a/src/cpu/mips/vm/mips_64.ad Fri Feb 17 17:22:14 2017 +0800 1.2 +++ b/src/cpu/mips/vm/mips_64.ad Fri Feb 17 20:37:47 2017 +0800 1.3 @@ -2538,21 +2538,29 @@ 1.4 if ( Assembler::is_simm(disp, 8) ) { 1.5 if ( scale != 0 ) { 1.6 __ dsll(AT, as_Register(index), scale); 1.7 + __ gsldx(as_Register(dst), as_Register(base), AT, disp); 1.8 } else { 1.9 - __ move(AT, as_Register(index)); 1.10 + __ gsldx(as_Register(dst), as_Register(base), as_Register(index), disp); 1.11 } 1.12 - __ gsldx(as_Register(dst), as_Register(base), AT, disp); 1.13 - } else { 1.14 + } else if ( Assembler::is_simm16(disp) ){ 1.15 if ( scale != 0 ) { 1.16 __ dsll(AT, as_Register(index), scale); 1.17 - __ move(T9, disp); 1.18 - __ daddu(AT, AT, T9); 1.19 + __ daddu(AT, AT, as_Register(base)); 1.20 } else { 1.21 - __ move(T9, disp); 1.22 - __ daddu(AT, as_Register(index), T9); 1.23 + __ daddu(AT, as_Register(index), as_Register(base)); 1.24 } 1.25 - __ gsldx(as_Register(dst), as_Register(base), AT, 0); 1.26 - } 1.27 + __ ld(as_Register(dst), AT, disp); 1.28 + } else { 1.29 + if ( scale != 0 ) { 1.30 + __ dsll(AT, as_Register(index), scale); 1.31 + __ move(T9, disp); 1.32 + __ daddu(AT, AT, T9); 1.33 + } else { 1.34 + __ move(T9, disp); 1.35 + __ daddu(AT, as_Register(index), T9); 1.36 + } 1.37 + __ gsldx(as_Register(dst), as_Register(base), AT, 0); 1.38 + } 1.39 } else { //not use loongson isa 1.40 if (scale == 0) { 1.41 __ daddu(AT, as_Register(base), as_Register(index)); 1.42 @@ -2570,9 +2578,7 @@ 1.43 } 1.44 } else { 1.45 if ( UseLoongsonISA ) { 1.46 - if( Assembler::is_simm(disp, 8) ) { 1.47 - __ gsldx(as_Register(dst), as_Register(base), R0, disp); 1.48 - } else if ( Assembler::is_simm16(disp) ){ 1.49 + if ( Assembler::is_simm16(disp) ){ 1.50 __ ld(as_Register(dst), as_Register(base), disp); 1.51 } else { 1.52 __ li(T9, disp); 1.53 @@ -2633,27 +2639,65 @@ 1.54 int disp = $mem$$disp; 1.55 1.56 if( index != 0 ) { 1.57 - if (scale == 0) { 1.58 - __ daddu(AT, as_Register(base), as_Register(index)); 1.59 - } else { 1.60 - __ dsll(AT, as_Register(index), scale); 1.61 - __ daddu(AT, as_Register(base), AT); 1.62 - } 1.63 - if( Assembler::is_simm16(disp) ) { 1.64 - __ sw(as_Register(src), AT, disp); 1.65 - } else { 1.66 - __ move(T9, disp); 1.67 - __ addu(AT, AT, T9); 1.68 - __ sw(as_Register(src), AT, 0); 1.69 - } 1.70 + if ( UseLoongsonISA ){ 1.71 + if ( Assembler::is_simm(disp, 8) ) { 1.72 + if ( scale == 0 ) { 1.73 + __ gsswx(as_Register(src), as_Register(base), as_Register(index), disp); 1.74 + } else { 1.75 + __ dsll(AT, as_Register(index), scale); 1.76 + __ gsswx(as_Register(src), as_Register(base), AT, disp); 1.77 + } 1.78 + } else if ( Assembler::is_simm16(disp) ) { 1.79 + if ( scale == 0 ) { 1.80 + __ daddu(AT, as_Register(base), as_Register(index)); 1.81 + } else { 1.82 + __ dsll(AT, as_Register(index), scale); 1.83 + __ daddu(AT, as_Register(base), AT); 1.84 + } 1.85 + __ sw(as_Register(src), AT, disp); 1.86 + } else { 1.87 + if ( scale == 0 ) { 1.88 + __ move(T9, disp); 1.89 + __ daddu(AT, as_Register(index), T9); 1.90 + } else { 1.91 + __ dsll(AT, as_Register(index), scale); 1.92 + __ move(T9, disp); 1.93 + __ daddu(AT, AT, T9); 1.94 + } 1.95 + __ gsswx(as_Register(src), as_Register(base), AT, 0); 1.96 + } 1.97 + } else { //not use loongson isa 1.98 + if (scale == 0) { 1.99 + __ daddu(AT, as_Register(base), as_Register(index)); 1.100 + } else { 1.101 + __ dsll(AT, as_Register(index), scale); 1.102 + __ daddu(AT, as_Register(base), AT); 1.103 + } 1.104 + if( Assembler::is_simm16(disp) ) { 1.105 + __ sw(as_Register(src), AT, disp); 1.106 + } else { 1.107 + __ move(T9, disp); 1.108 + __ addu(AT, AT, T9); 1.109 + __ sw(as_Register(src), AT, 0); 1.110 + } 1.111 + } 1.112 } else { 1.113 - if( Assembler::is_simm16(disp) ) { 1.114 - __ sw(as_Register(src), as_Register(base), disp); 1.115 - } else { 1.116 - __ move(T9, disp); 1.117 - __ addu(AT, as_Register(base), T9); 1.118 - __ sw(as_Register(src), AT, 0); 1.119 - } 1.120 + if ( UseLoongsonISA ) { 1.121 + if ( Assembler::is_simm16(disp) ) { 1.122 + __ sw(as_Register(src), as_Register(base), disp); 1.123 + } else { 1.124 + __ move(T9, disp); 1.125 + __ gsswx(as_Register(src), as_Register(base), T9, 0); 1.126 + } 1.127 + } else { 1.128 + if( Assembler::is_simm16(disp) ) { 1.129 + __ sw(as_Register(src), as_Register(base), disp); 1.130 + } else { 1.131 + __ move(T9, disp); 1.132 + __ addu(AT, as_Register(base), T9); 1.133 + __ sw(as_Register(src), AT, 0); 1.134 + } 1.135 + } 1.136 } 1.137 %} 1.138