1.1 --- a/src/cpu/mips/vm/mips_64.ad Thu Jul 11 19:58:29 2019 +0800 1.2 +++ b/src/cpu/mips/vm/mips_64.ad Mon Jul 22 15:51:01 2019 +0800 1.3 @@ -13436,11 +13436,10 @@ 1.4 __ move(AT, as_Register(base)); 1.5 } 1.6 if( Assembler::is_simm16(disp) ) { 1.7 - __ daddiu(AT, as_Register(base), disp); 1.8 __ daddiu(AT, AT, disp); 1.9 } else { 1.10 __ move(T9, disp); 1.11 - __ daddu(AT, as_Register(base), T9); 1.12 + __ daddu(AT, AT, T9); 1.13 } 1.14 __ pref(0, AT, 0); //hint: 0:load 1.15 %} 1.16 @@ -13468,11 +13467,10 @@ 1.17 __ move(AT, as_Register(base)); 1.18 } 1.19 if( Assembler::is_simm16(disp) ) { 1.20 - __ daddiu(AT, as_Register(base), disp); 1.21 __ daddiu(AT, AT, disp); 1.22 } else { 1.23 __ move(T9, disp); 1.24 - __ daddu(AT, as_Register(base), T9); 1.25 + __ daddu(AT, AT, T9); 1.26 } 1.27 __ pref(1, AT, 0); //hint: 1:store 1.28 %}