1.1 --- a/src/cpu/x86/vm/x86_64.ad Wed Oct 16 10:52:41 2013 +0200
1.2 +++ b/src/cpu/x86/vm/x86_64.ad Tue Nov 05 17:38:04 2013 -0800
1.3 @@ -529,7 +529,7 @@
1.4 if (rspec.reloc()->type() == relocInfo::oop_type &&
1.5 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
1.6 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop");
1.7 - assert(oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
1.8 + assert(cast_to_oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
1.9 }
1.10 #endif
1.11 cbuf.relocate(cbuf.insts_mark(), rspec, format);
1.12 @@ -556,7 +556,7 @@
1.13 if (rspec.reloc()->type() == relocInfo::oop_type &&
1.14 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
1.15 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop");
1.16 - assert(oop(d64)->is_oop() && (ScavengeRootsInCode || !oop(d64)->is_scavengable()),
1.17 + assert(cast_to_oop(d64)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d64)->is_scavengable()),
1.18 "cannot embed scavengable oops in code");
1.19 }
1.20 #endif
1.21 @@ -1391,7 +1391,7 @@
1.22 #ifndef PRODUCT
1.23 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1.24 {
1.25 - if (UseCompressedKlassPointers) {
1.26 + if (UseCompressedClassPointers) {
1.27 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1.28 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1.29 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1.30 @@ -1408,7 +1408,7 @@
1.31 {
1.32 MacroAssembler masm(&cbuf);
1.33 uint insts_size = cbuf.insts_size();
1.34 - if (UseCompressedKlassPointers) {
1.35 + if (UseCompressedClassPointers) {
1.36 masm.load_klass(rscratch1, j_rarg0);
1.37 masm.cmpptr(rax, rscratch1);
1.38 } else {
1.39 @@ -1557,7 +1557,7 @@
1.40 }
1.41
1.42 bool Matcher::narrow_klass_use_complex_address() {
1.43 - assert(UseCompressedKlassPointers, "only for compressed klass code");
1.44 + assert(UseCompressedClassPointers, "only for compressed klass code");
1.45 return (LogKlassAlignmentInBytes <= 3);
1.46 }
1.47
1.48 @@ -1649,6 +1649,18 @@
1.49 return PTR_RBP_REG_mask();
1.50 }
1.51
1.52 +const RegMask Matcher::mathExactI_result_proj_mask() {
1.53 + return INT_RAX_REG_mask();
1.54 +}
1.55 +
1.56 +const RegMask Matcher::mathExactL_result_proj_mask() {
1.57 + return LONG_RAX_REG_mask();
1.58 +}
1.59 +
1.60 +const RegMask Matcher::mathExactI_flags_proj_mask() {
1.61 + return INT_FLAGS_mask();
1.62 +}
1.63 +
1.64 %}
1.65
1.66 //----------ENCODING BLOCK-----------------------------------------------------
1.67 @@ -4133,6 +4145,8 @@
1.68 greater_equal(0xD, "ge");
1.69 less_equal(0xE, "le");
1.70 greater(0xF, "g");
1.71 + overflow(0x0, "o");
1.72 + no_overflow(0x1, "no");
1.73 %}
1.74 %}
1.75
1.76 @@ -4151,6 +4165,8 @@
1.77 greater_equal(0x3, "nb");
1.78 less_equal(0x6, "be");
1.79 greater(0x7, "nbe");
1.80 + overflow(0x0, "o");
1.81 + no_overflow(0x1, "no");
1.82 %}
1.83 %}
1.84
1.85 @@ -4170,6 +4186,8 @@
1.86 greater_equal(0x3, "nb");
1.87 less_equal(0x6, "be");
1.88 greater(0x7, "nbe");
1.89 + overflow(0x0, "o");
1.90 + no_overflow(0x1, "no");
1.91 %}
1.92 %}
1.93
1.94 @@ -4187,6 +4205,8 @@
1.95 greater_equal(0x3, "nb");
1.96 less_equal(0x6, "be");
1.97 greater(0x7, "nbe");
1.98 + overflow(0x0, "o");
1.99 + no_overflow(0x1, "no");
1.100 %}
1.101 %}
1.102
1.103 @@ -6922,6 +6942,82 @@
1.104 //----------Arithmetic Instructions--------------------------------------------
1.105 //----------Addition Instructions----------------------------------------------
1.106
1.107 +instruct addExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr)
1.108 +%{
1.109 + match(AddExactI dst src);
1.110 + effect(DEF cr);
1.111 +
1.112 + format %{ "addl $dst, $src\t# addExact int" %}
1.113 + ins_encode %{
1.114 + __ addl($dst$$Register, $src$$Register);
1.115 + %}
1.116 + ins_pipe(ialu_reg_reg);
1.117 +%}
1.118 +
1.119 +instruct addExactI_rReg_imm(rax_RegI dst, immI src, rFlagsReg cr)
1.120 +%{
1.121 + match(AddExactI dst src);
1.122 + effect(DEF cr);
1.123 +
1.124 + format %{ "addl $dst, $src\t# addExact int" %}
1.125 + ins_encode %{
1.126 + __ addl($dst$$Register, $src$$constant);
1.127 + %}
1.128 + ins_pipe(ialu_reg_reg);
1.129 +%}
1.130 +
1.131 +instruct addExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
1.132 +%{
1.133 + match(AddExactI dst (LoadI src));
1.134 + effect(DEF cr);
1.135 +
1.136 + ins_cost(125); // XXX
1.137 + format %{ "addl $dst, $src\t# addExact int" %}
1.138 + ins_encode %{
1.139 + __ addl($dst$$Register, $src$$Address);
1.140 + %}
1.141 +
1.142 + ins_pipe(ialu_reg_mem);
1.143 +%}
1.144 +
1.145 +instruct addExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr)
1.146 +%{
1.147 + match(AddExactL dst src);
1.148 + effect(DEF cr);
1.149 +
1.150 + format %{ "addq $dst, $src\t# addExact long" %}
1.151 + ins_encode %{
1.152 + __ addq($dst$$Register, $src$$Register);
1.153 + %}
1.154 + ins_pipe(ialu_reg_reg);
1.155 +%}
1.156 +
1.157 +instruct addExactL_rReg_imm(rax_RegL dst, immL32 src, rFlagsReg cr)
1.158 +%{
1.159 + match(AddExactL dst src);
1.160 + effect(DEF cr);
1.161 +
1.162 + format %{ "addq $dst, $src\t# addExact long" %}
1.163 + ins_encode %{
1.164 + __ addq($dst$$Register, $src$$constant);
1.165 + %}
1.166 + ins_pipe(ialu_reg_reg);
1.167 +%}
1.168 +
1.169 +instruct addExactL_rReg_mem(rax_RegL dst, memory src, rFlagsReg cr)
1.170 +%{
1.171 + match(AddExactL dst (LoadL src));
1.172 + effect(DEF cr);
1.173 +
1.174 + ins_cost(125); // XXX
1.175 + format %{ "addq $dst, $src\t# addExact long" %}
1.176 + ins_encode %{
1.177 + __ addq($dst$$Register, $src$$Address);
1.178 + %}
1.179 +
1.180 + ins_pipe(ialu_reg_mem);
1.181 +%}
1.182 +
1.183 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
1.184 %{
1.185 match(Set dst (AddI dst src));
1.186 @@ -7534,6 +7630,80 @@
1.187 ins_pipe(ialu_mem_imm);
1.188 %}
1.189
1.190 +instruct subExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr)
1.191 +%{
1.192 + match(SubExactI dst src);
1.193 + effect(DEF cr);
1.194 +
1.195 + format %{ "subl $dst, $src\t# subExact int" %}
1.196 + ins_encode %{
1.197 + __ subl($dst$$Register, $src$$Register);
1.198 + %}
1.199 + ins_pipe(ialu_reg_reg);
1.200 +%}
1.201 +
1.202 +instruct subExactI_rReg_imm(rax_RegI dst, immI src, rFlagsReg cr)
1.203 +%{
1.204 + match(SubExactI dst src);
1.205 + effect(DEF cr);
1.206 +
1.207 + format %{ "subl $dst, $src\t# subExact int" %}
1.208 + ins_encode %{
1.209 + __ subl($dst$$Register, $src$$constant);
1.210 + %}
1.211 + ins_pipe(ialu_reg_reg);
1.212 +%}
1.213 +
1.214 +instruct subExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
1.215 +%{
1.216 + match(SubExactI dst (LoadI src));
1.217 + effect(DEF cr);
1.218 +
1.219 + ins_cost(125);
1.220 + format %{ "subl $dst, $src\t# subExact int" %}
1.221 + ins_encode %{
1.222 + __ subl($dst$$Register, $src$$Address);
1.223 + %}
1.224 + ins_pipe(ialu_reg_mem);
1.225 +%}
1.226 +
1.227 +instruct subExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr)
1.228 +%{
1.229 + match(SubExactL dst src);
1.230 + effect(DEF cr);
1.231 +
1.232 + format %{ "subq $dst, $src\t# subExact long" %}
1.233 + ins_encode %{
1.234 + __ subq($dst$$Register, $src$$Register);
1.235 + %}
1.236 + ins_pipe(ialu_reg_reg);
1.237 +%}
1.238 +
1.239 +instruct subExactL_rReg_imm(rax_RegL dst, immL32 src, rFlagsReg cr)
1.240 +%{
1.241 + match(SubExactL dst (LoadL src));
1.242 + effect(DEF cr);
1.243 +
1.244 + format %{ "subq $dst, $src\t# subExact long" %}
1.245 + ins_encode %{
1.246 + __ subq($dst$$Register, $src$$constant);
1.247 + %}
1.248 + ins_pipe(ialu_reg_reg);
1.249 +%}
1.250 +
1.251 +instruct subExactL_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
1.252 +%{
1.253 + match(SubExactI dst src);
1.254 + effect(DEF cr);
1.255 +
1.256 + ins_cost(125);
1.257 + format %{ "subq $dst, $src\t# subExact long" %}
1.258 + ins_encode %{
1.259 + __ subq($dst$$Register, $src$$Address);
1.260 + %}
1.261 + ins_pipe(ialu_reg_mem);
1.262 +%}
1.263 +
1.264 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
1.265 %{
1.266 match(Set dst (SubL dst src));
1.267 @@ -7650,6 +7820,30 @@
1.268 ins_pipe(ialu_reg);
1.269 %}
1.270
1.271 +instruct negExactI_rReg(rax_RegI dst, rFlagsReg cr)
1.272 +%{
1.273 + match(NegExactI dst);
1.274 + effect(KILL cr);
1.275 +
1.276 + format %{ "negl $dst\t# negExact int" %}
1.277 + ins_encode %{
1.278 + __ negl($dst$$Register);
1.279 + %}
1.280 + ins_pipe(ialu_reg);
1.281 +%}
1.282 +
1.283 +instruct negExactL_rReg(rax_RegL dst, rFlagsReg cr)
1.284 +%{
1.285 + match(NegExactL dst);
1.286 + effect(KILL cr);
1.287 +
1.288 + format %{ "negq $dst\t# negExact long" %}
1.289 + ins_encode %{
1.290 + __ negq($dst$$Register);
1.291 + %}
1.292 + ins_pipe(ialu_reg);
1.293 +%}
1.294 +
1.295
1.296 //----------Multiplication/Division Instructions-------------------------------
1.297 // Integer Multiplication Instructions
1.298 @@ -7767,6 +7961,86 @@
1.299 ins_pipe(ialu_reg_reg_alu0);
1.300 %}
1.301
1.302 +
1.303 +instruct mulExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr)
1.304 +%{
1.305 + match(MulExactI dst src);
1.306 + effect(DEF cr);
1.307 +
1.308 + ins_cost(300);
1.309 + format %{ "imull $dst, $src\t# mulExact int" %}
1.310 + ins_encode %{
1.311 + __ imull($dst$$Register, $src$$Register);
1.312 + %}
1.313 + ins_pipe(ialu_reg_reg_alu0);
1.314 +%}
1.315 +
1.316 +
1.317 +instruct mulExactI_rReg_imm(rax_RegI dst, rRegI src, immI imm, rFlagsReg cr)
1.318 +%{
1.319 + match(MulExactI src imm);
1.320 + effect(DEF cr);
1.321 +
1.322 + ins_cost(300);
1.323 + format %{ "imull $dst, $src, $imm\t# mulExact int" %}
1.324 + ins_encode %{
1.325 + __ imull($dst$$Register, $src$$Register, $imm$$constant);
1.326 + %}
1.327 + ins_pipe(ialu_reg_reg_alu0);
1.328 +%}
1.329 +
1.330 +instruct mulExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
1.331 +%{
1.332 + match(MulExactI dst (LoadI src));
1.333 + effect(DEF cr);
1.334 +
1.335 + ins_cost(350);
1.336 + format %{ "imull $dst, $src\t# mulExact int" %}
1.337 + ins_encode %{
1.338 + __ imull($dst$$Register, $src$$Address);
1.339 + %}
1.340 + ins_pipe(ialu_reg_mem_alu0);
1.341 +%}
1.342 +
1.343 +instruct mulExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr)
1.344 +%{
1.345 + match(MulExactL dst src);
1.346 + effect(DEF cr);
1.347 +
1.348 + ins_cost(300);
1.349 + format %{ "imulq $dst, $src\t# mulExact long" %}
1.350 + ins_encode %{
1.351 + __ imulq($dst$$Register, $src$$Register);
1.352 + %}
1.353 + ins_pipe(ialu_reg_reg_alu0);
1.354 +%}
1.355 +
1.356 +instruct mulExactL_rReg_imm(rax_RegL dst, rRegL src, immL32 imm, rFlagsReg cr)
1.357 +%{
1.358 + match(MulExactL src imm);
1.359 + effect(DEF cr);
1.360 +
1.361 + ins_cost(300);
1.362 + format %{ "imulq $dst, $src, $imm\t# mulExact long" %}
1.363 + ins_encode %{
1.364 + __ imulq($dst$$Register, $src$$Register, $imm$$constant);
1.365 + %}
1.366 + ins_pipe(ialu_reg_reg_alu0);
1.367 +%}
1.368 +
1.369 +instruct mulExactL_rReg_mem(rax_RegL dst, memory src, rFlagsReg cr)
1.370 +%{
1.371 + match(MulExactL dst (LoadL src));
1.372 + effect(DEF cr);
1.373 +
1.374 + ins_cost(350);
1.375 + format %{ "imulq $dst, $src\t# mulExact long" %}
1.376 + ins_encode %{
1.377 + __ imulq($dst$$Register, $src$$Address);
1.378 + %}
1.379 + ins_pipe(ialu_reg_mem_alu0);
1.380 +%}
1.381 +
1.382 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
1.383 rFlagsReg cr)
1.384 %{
