527 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) { |
527 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) { |
528 #ifdef ASSERT |
528 #ifdef ASSERT |
529 if (rspec.reloc()->type() == relocInfo::oop_type && |
529 if (rspec.reloc()->type() == relocInfo::oop_type && |
530 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) { |
530 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) { |
531 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop"); |
531 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop"); |
532 assert(oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code"); |
532 assert(cast_to_oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code"); |
533 } |
533 } |
534 #endif |
534 #endif |
535 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
535 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
536 cbuf.insts()->emit_int32(d32); |
536 cbuf.insts()->emit_int32(d32); |
537 } |
537 } |
554 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) { |
554 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) { |
555 #ifdef ASSERT |
555 #ifdef ASSERT |
556 if (rspec.reloc()->type() == relocInfo::oop_type && |
556 if (rspec.reloc()->type() == relocInfo::oop_type && |
557 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) { |
557 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) { |
558 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop"); |
558 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop"); |
559 assert(oop(d64)->is_oop() && (ScavengeRootsInCode || !oop(d64)->is_scavengable()), |
559 assert(cast_to_oop(d64)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d64)->is_scavengable()), |
560 "cannot embed scavengable oops in code"); |
560 "cannot embed scavengable oops in code"); |
561 } |
561 } |
562 #endif |
562 #endif |
563 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
563 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
564 cbuf.insts()->emit_int64(d64); |
564 cbuf.insts()->emit_int64(d64); |
1389 |
1389 |
1390 //============================================================================= |
1390 //============================================================================= |
1391 #ifndef PRODUCT |
1391 #ifndef PRODUCT |
1392 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const |
1392 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const |
1393 { |
1393 { |
1394 if (UseCompressedKlassPointers) { |
1394 if (UseCompressedClassPointers) { |
1395 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass"); |
1395 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass"); |
1396 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1"); |
1396 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1"); |
1397 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check"); |
1397 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check"); |
1398 } else { |
1398 } else { |
1399 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t" |
1399 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t" |
1406 |
1406 |
1407 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const |
1407 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const |
1408 { |
1408 { |
1409 MacroAssembler masm(&cbuf); |
1409 MacroAssembler masm(&cbuf); |
1410 uint insts_size = cbuf.insts_size(); |
1410 uint insts_size = cbuf.insts_size(); |
1411 if (UseCompressedKlassPointers) { |
1411 if (UseCompressedClassPointers) { |
1412 masm.load_klass(rscratch1, j_rarg0); |
1412 masm.load_klass(rscratch1, j_rarg0); |
1413 masm.cmpptr(rax, rscratch1); |
1413 masm.cmpptr(rax, rscratch1); |
1414 } else { |
1414 } else { |
1415 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes())); |
1415 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes())); |
1416 } |
1416 } |
1555 assert(UseCompressedOops, "only for compressed oops code"); |
1555 assert(UseCompressedOops, "only for compressed oops code"); |
1556 return (LogMinObjAlignmentInBytes <= 3); |
1556 return (LogMinObjAlignmentInBytes <= 3); |
1557 } |
1557 } |
1558 |
1558 |
1559 bool Matcher::narrow_klass_use_complex_address() { |
1559 bool Matcher::narrow_klass_use_complex_address() { |
1560 assert(UseCompressedKlassPointers, "only for compressed klass code"); |
1560 assert(UseCompressedClassPointers, "only for compressed klass code"); |
1561 return (LogKlassAlignmentInBytes <= 3); |
1561 return (LogKlassAlignmentInBytes <= 3); |
1562 } |
1562 } |
1563 |
1563 |
1564 // Is it better to copy float constants, or load them directly from |
1564 // Is it better to copy float constants, or load them directly from |
1565 // memory? Intel can load a float constant from a direct address, |
1565 // memory? Intel can load a float constant from a direct address, |
1645 return LONG_RDX_REG_mask(); |
1645 return LONG_RDX_REG_mask(); |
1646 } |
1646 } |
1647 |
1647 |
1648 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
1648 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
1649 return PTR_RBP_REG_mask(); |
1649 return PTR_RBP_REG_mask(); |
|
1650 } |
|
1651 |
|
1652 const RegMask Matcher::mathExactI_result_proj_mask() { |
|
1653 return INT_RAX_REG_mask(); |
|
1654 } |
|
1655 |
|
1656 const RegMask Matcher::mathExactL_result_proj_mask() { |
|
1657 return LONG_RAX_REG_mask(); |
|
1658 } |
|
1659 |
|
1660 const RegMask Matcher::mathExactI_flags_proj_mask() { |
|
1661 return INT_FLAGS_mask(); |
1650 } |
1662 } |
1651 |
1663 |
1652 %} |
1664 %} |
1653 |
1665 |
1654 //----------ENCODING BLOCK----------------------------------------------------- |
1666 //----------ENCODING BLOCK----------------------------------------------------- |
4131 not_equal(0x5, "ne"); |
4143 not_equal(0x5, "ne"); |
4132 less(0xC, "l"); |
4144 less(0xC, "l"); |
4133 greater_equal(0xD, "ge"); |
4145 greater_equal(0xD, "ge"); |
4134 less_equal(0xE, "le"); |
4146 less_equal(0xE, "le"); |
4135 greater(0xF, "g"); |
4147 greater(0xF, "g"); |
|
4148 overflow(0x0, "o"); |
|
4149 no_overflow(0x1, "no"); |
4136 %} |
4150 %} |
4137 %} |
4151 %} |
4138 |
4152 |
4139 // Comparison Code, unsigned compare. Used by FP also, with |
4153 // Comparison Code, unsigned compare. Used by FP also, with |
4140 // C2 (unordered) turned into GT or LT already. The other bits |
4154 // C2 (unordered) turned into GT or LT already. The other bits |
4149 not_equal(0x5, "ne"); |
4163 not_equal(0x5, "ne"); |
4150 less(0x2, "b"); |
4164 less(0x2, "b"); |
4151 greater_equal(0x3, "nb"); |
4165 greater_equal(0x3, "nb"); |
4152 less_equal(0x6, "be"); |
4166 less_equal(0x6, "be"); |
4153 greater(0x7, "nbe"); |
4167 greater(0x7, "nbe"); |
|
4168 overflow(0x0, "o"); |
|
4169 no_overflow(0x1, "no"); |
4154 %} |
4170 %} |
4155 %} |
4171 %} |
4156 |
4172 |
4157 |
4173 |
4158 // Floating comparisons that don't require any fixup for the unordered case |
4174 // Floating comparisons that don't require any fixup for the unordered case |
4168 not_equal(0x5, "ne"); |
4184 not_equal(0x5, "ne"); |
4169 less(0x2, "b"); |
4185 less(0x2, "b"); |
4170 greater_equal(0x3, "nb"); |
4186 greater_equal(0x3, "nb"); |
4171 less_equal(0x6, "be"); |
4187 less_equal(0x6, "be"); |
4172 greater(0x7, "nbe"); |
4188 greater(0x7, "nbe"); |
|
4189 overflow(0x0, "o"); |
|
4190 no_overflow(0x1, "no"); |
4173 %} |
4191 %} |
4174 %} |
4192 %} |
4175 |
4193 |
4176 |
4194 |
4177 // Floating comparisons that can be fixed up with extra conditional jumps |
4195 // Floating comparisons that can be fixed up with extra conditional jumps |
4185 not_equal(0x5, "ne"); |
4203 not_equal(0x5, "ne"); |
4186 less(0x2, "b"); |
4204 less(0x2, "b"); |
4187 greater_equal(0x3, "nb"); |
4205 greater_equal(0x3, "nb"); |
4188 less_equal(0x6, "be"); |
4206 less_equal(0x6, "be"); |
4189 greater(0x7, "nbe"); |
4207 greater(0x7, "nbe"); |
|
4208 overflow(0x0, "o"); |
|
4209 no_overflow(0x1, "no"); |
4190 %} |
4210 %} |
4191 %} |
4211 %} |
4192 |
4212 |
4193 |
4213 |
4194 //----------OPERAND CLASSES---------------------------------------------------- |
4214 //----------OPERAND CLASSES---------------------------------------------------- |
6920 %} |
6940 %} |
6921 |
6941 |
6922 //----------Arithmetic Instructions-------------------------------------------- |
6942 //----------Arithmetic Instructions-------------------------------------------- |
6923 //----------Addition Instructions---------------------------------------------- |
6943 //----------Addition Instructions---------------------------------------------- |
6924 |
6944 |
|
6945 instruct addExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr) |
|
6946 %{ |
|
6947 match(AddExactI dst src); |
|
6948 effect(DEF cr); |
|
6949 |
|
6950 format %{ "addl $dst, $src\t# addExact int" %} |
|
6951 ins_encode %{ |
|
6952 __ addl($dst$$Register, $src$$Register); |
|
6953 %} |
|
6954 ins_pipe(ialu_reg_reg); |
|
6955 %} |
|
6956 |
|
6957 instruct addExactI_rReg_imm(rax_RegI dst, immI src, rFlagsReg cr) |
|
6958 %{ |
|
6959 match(AddExactI dst src); |
|
6960 effect(DEF cr); |
|
6961 |
|
6962 format %{ "addl $dst, $src\t# addExact int" %} |
|
6963 ins_encode %{ |
|
6964 __ addl($dst$$Register, $src$$constant); |
|
6965 %} |
|
6966 ins_pipe(ialu_reg_reg); |
|
6967 %} |
|
6968 |
|
6969 instruct addExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr) |
|
6970 %{ |
|
6971 match(AddExactI dst (LoadI src)); |
|
6972 effect(DEF cr); |
|
6973 |
|
6974 ins_cost(125); // XXX |
|
6975 format %{ "addl $dst, $src\t# addExact int" %} |
|
6976 ins_encode %{ |
|
6977 __ addl($dst$$Register, $src$$Address); |
|
6978 %} |
|
6979 |
|
6980 ins_pipe(ialu_reg_mem); |
|
6981 %} |
|
6982 |
|
6983 instruct addExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr) |
|
6984 %{ |
|
6985 match(AddExactL dst src); |
|
6986 effect(DEF cr); |
|
6987 |
|
6988 format %{ "addq $dst, $src\t# addExact long" %} |
|
6989 ins_encode %{ |
|
6990 __ addq($dst$$Register, $src$$Register); |
|
6991 %} |
|
6992 ins_pipe(ialu_reg_reg); |
|
6993 %} |
|
6994 |
|
6995 instruct addExactL_rReg_imm(rax_RegL dst, immL32 src, rFlagsReg cr) |
|
6996 %{ |
|
6997 match(AddExactL dst src); |
|
6998 effect(DEF cr); |
|
6999 |
|
7000 format %{ "addq $dst, $src\t# addExact long" %} |
|
7001 ins_encode %{ |
|
7002 __ addq($dst$$Register, $src$$constant); |
|
7003 %} |
|
7004 ins_pipe(ialu_reg_reg); |
|
7005 %} |
|
7006 |
|
7007 instruct addExactL_rReg_mem(rax_RegL dst, memory src, rFlagsReg cr) |
|
7008 %{ |
|
7009 match(AddExactL dst (LoadL src)); |
|
7010 effect(DEF cr); |
|
7011 |
|
7012 ins_cost(125); // XXX |
|
7013 format %{ "addq $dst, $src\t# addExact long" %} |
|
7014 ins_encode %{ |
|
7015 __ addq($dst$$Register, $src$$Address); |
|
7016 %} |
|
7017 |
|
7018 ins_pipe(ialu_reg_mem); |
|
7019 %} |
|
7020 |
6925 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr) |
7021 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr) |
6926 %{ |
7022 %{ |
6927 match(Set dst (AddI dst src)); |
7023 match(Set dst (AddI dst src)); |
6928 effect(KILL cr); |
7024 effect(KILL cr); |
6929 |
7025 |
7532 opcode(0x81); /* Opcode 81 /5 id */ |
7628 opcode(0x81); /* Opcode 81 /5 id */ |
7533 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); |
7629 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); |
7534 ins_pipe(ialu_mem_imm); |
7630 ins_pipe(ialu_mem_imm); |
7535 %} |
7631 %} |
7536 |
7632 |
|
7633 instruct subExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr) |
|
7634 %{ |
|
7635 match(SubExactI dst src); |
|
7636 effect(DEF cr); |
|
7637 |
|
7638 format %{ "subl $dst, $src\t# subExact int" %} |
|
7639 ins_encode %{ |
|
7640 __ subl($dst$$Register, $src$$Register); |
|
7641 %} |
|
7642 ins_pipe(ialu_reg_reg); |
|
7643 %} |
|
7644 |
|
7645 instruct subExactI_rReg_imm(rax_RegI dst, immI src, rFlagsReg cr) |
|
7646 %{ |
|
7647 match(SubExactI dst src); |
|
7648 effect(DEF cr); |
|
7649 |
|
7650 format %{ "subl $dst, $src\t# subExact int" %} |
|
7651 ins_encode %{ |
|
7652 __ subl($dst$$Register, $src$$constant); |
|
7653 %} |
|
7654 ins_pipe(ialu_reg_reg); |
|
7655 %} |
|
7656 |
|
7657 instruct subExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr) |
|
7658 %{ |
|
7659 match(SubExactI dst (LoadI src)); |
|
7660 effect(DEF cr); |
|
7661 |
|
7662 ins_cost(125); |
|
7663 format %{ "subl $dst, $src\t# subExact int" %} |
|
7664 ins_encode %{ |
|
7665 __ subl($dst$$Register, $src$$Address); |
|
7666 %} |
|
7667 ins_pipe(ialu_reg_mem); |
|
7668 %} |
|
7669 |
|
7670 instruct subExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr) |
|
7671 %{ |
|
7672 match(SubExactL dst src); |
|
7673 effect(DEF cr); |
|
7674 |
|
7675 format %{ "subq $dst, $src\t# subExact long" %} |
|
7676 ins_encode %{ |
|
7677 __ subq($dst$$Register, $src$$Register); |
|
7678 %} |
|
7679 ins_pipe(ialu_reg_reg); |
|
7680 %} |
|
7681 |
|
7682 instruct subExactL_rReg_imm(rax_RegL dst, immL32 src, rFlagsReg cr) |
|
7683 %{ |
|
7684 match(SubExactL dst (LoadL src)); |
|
7685 effect(DEF cr); |
|
7686 |
|
7687 format %{ "subq $dst, $src\t# subExact long" %} |
|
7688 ins_encode %{ |
|
7689 __ subq($dst$$Register, $src$$constant); |
|
7690 %} |
|
7691 ins_pipe(ialu_reg_reg); |
|
7692 %} |
|
7693 |
|
7694 instruct subExactL_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr) |
|
7695 %{ |
|
7696 match(SubExactI dst src); |
|
7697 effect(DEF cr); |
|
7698 |
|
7699 ins_cost(125); |
|
7700 format %{ "subq $dst, $src\t# subExact long" %} |
|
7701 ins_encode %{ |
|
7702 __ subq($dst$$Register, $src$$Address); |
|
7703 %} |
|
7704 ins_pipe(ialu_reg_mem); |
|
7705 %} |
|
7706 |
7537 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr) |
7707 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr) |
7538 %{ |
7708 %{ |
7539 match(Set dst (SubL dst src)); |
7709 match(Set dst (SubL dst src)); |
7540 effect(KILL cr); |
7710 effect(KILL cr); |
7541 |
7711 |
7648 opcode(0xF7, 0x03); // Opcode F7 /3 |
7818 opcode(0xF7, 0x03); // Opcode F7 /3 |
7649 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); |
7819 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); |
7650 ins_pipe(ialu_reg); |
7820 ins_pipe(ialu_reg); |
7651 %} |
7821 %} |
7652 |
7822 |
|
7823 instruct negExactI_rReg(rax_RegI dst, rFlagsReg cr) |
|
7824 %{ |
|
7825 match(NegExactI dst); |
|
7826 effect(KILL cr); |
|
7827 |
|
7828 format %{ "negl $dst\t# negExact int" %} |
|
7829 ins_encode %{ |
|
7830 __ negl($dst$$Register); |
|
7831 %} |
|
7832 ins_pipe(ialu_reg); |
|
7833 %} |
|
7834 |
|
7835 instruct negExactL_rReg(rax_RegL dst, rFlagsReg cr) |
|
7836 %{ |
|
7837 match(NegExactL dst); |
|
7838 effect(KILL cr); |
|
7839 |
|
7840 format %{ "negq $dst\t# negExact long" %} |
|
7841 ins_encode %{ |
|
7842 __ negq($dst$$Register); |
|
7843 %} |
|
7844 ins_pipe(ialu_reg); |
|
7845 %} |
|
7846 |
7653 |
7847 |
7654 //----------Multiplication/Division Instructions------------------------------- |
7848 //----------Multiplication/Division Instructions------------------------------- |
7655 // Integer Multiplication Instructions |
7849 // Integer Multiplication Instructions |
7656 // Multiply Register |
7850 // Multiply Register |
7657 |
7851 |
7763 ins_cost(300); |
7957 ins_cost(300); |
7764 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %} |
7958 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %} |
7765 opcode(0xF7, 0x5); /* Opcode F7 /5 */ |
7959 opcode(0xF7, 0x5); /* Opcode F7 /5 */ |
7766 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); |
7960 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); |
7767 ins_pipe(ialu_reg_reg_alu0); |
7961 ins_pipe(ialu_reg_reg_alu0); |
|
7962 %} |
|
7963 |
|
7964 |
|
7965 instruct mulExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr) |
|
7966 %{ |
|
7967 match(MulExactI dst src); |
|
7968 effect(DEF cr); |
|
7969 |
|
7970 ins_cost(300); |
|
7971 format %{ "imull $dst, $src\t# mulExact int" %} |
|
7972 ins_encode %{ |
|
7973 __ imull($dst$$Register, $src$$Register); |
|
7974 %} |
|
7975 ins_pipe(ialu_reg_reg_alu0); |
|
7976 %} |
|
7977 |
|
7978 |
|
7979 instruct mulExactI_rReg_imm(rax_RegI dst, rRegI src, immI imm, rFlagsReg cr) |
|
7980 %{ |
|
7981 match(MulExactI src imm); |
|
7982 effect(DEF cr); |
|
7983 |
|
7984 ins_cost(300); |
|
7985 format %{ "imull $dst, $src, $imm\t# mulExact int" %} |
|
7986 ins_encode %{ |
|
7987 __ imull($dst$$Register, $src$$Register, $imm$$constant); |
|
7988 %} |
|
7989 ins_pipe(ialu_reg_reg_alu0); |
|
7990 %} |
|
7991 |
|
7992 instruct mulExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr) |
|
7993 %{ |
|
7994 match(MulExactI dst (LoadI src)); |
|
7995 effect(DEF cr); |
|
7996 |
|
7997 ins_cost(350); |
|
7998 format %{ "imull $dst, $src\t# mulExact int" %} |
|
7999 ins_encode %{ |
|
8000 __ imull($dst$$Register, $src$$Address); |
|
8001 %} |
|
8002 ins_pipe(ialu_reg_mem_alu0); |
|
8003 %} |
|
8004 |
|
8005 instruct mulExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr) |
|
8006 %{ |
|
8007 match(MulExactL dst src); |
|
8008 effect(DEF cr); |
|
8009 |
|
8010 ins_cost(300); |
|
8011 format %{ "imulq $dst, $src\t# mulExact long" %} |
|
8012 ins_encode %{ |
|
8013 __ imulq($dst$$Register, $src$$Register); |
|
8014 %} |
|
8015 ins_pipe(ialu_reg_reg_alu0); |
|
8016 %} |
|
8017 |
|
8018 instruct mulExactL_rReg_imm(rax_RegL dst, rRegL src, immL32 imm, rFlagsReg cr) |
|
8019 %{ |
|
8020 match(MulExactL src imm); |
|
8021 effect(DEF cr); |
|
8022 |
|
8023 ins_cost(300); |
|
8024 format %{ "imulq $dst, $src, $imm\t# mulExact long" %} |
|
8025 ins_encode %{ |
|
8026 __ imulq($dst$$Register, $src$$Register, $imm$$constant); |
|
8027 %} |
|
8028 ins_pipe(ialu_reg_reg_alu0); |
|
8029 %} |
|
8030 |
|
8031 instruct mulExactL_rReg_mem(rax_RegL dst, memory src, rFlagsReg cr) |
|
8032 %{ |
|
8033 match(MulExactL dst (LoadL src)); |
|
8034 effect(DEF cr); |
|
8035 |
|
8036 ins_cost(350); |
|
8037 format %{ "imulq $dst, $src\t# mulExact long" %} |
|
8038 ins_encode %{ |
|
8039 __ imulq($dst$$Register, $src$$Address); |
|
8040 %} |
|
8041 ins_pipe(ialu_reg_mem_alu0); |
7768 %} |
8042 %} |
7769 |
8043 |
7770 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, |
8044 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, |
7771 rFlagsReg cr) |
8045 rFlagsReg cr) |
7772 %{ |
8046 %{ |