1.1 --- a/src/cpu/x86/vm/x86_32.ad Tue Oct 01 11:06:35 2013 -0400 1.2 +++ b/src/cpu/x86/vm/x86_32.ad Thu Oct 03 16:38:21 2013 +0400 1.3 @@ -1534,6 +1534,14 @@ 1.4 return EBP_REG_mask(); 1.5 } 1.6 1.7 +const RegMask Matcher::mathExactI_result_proj_mask() { 1.8 + return EAX_REG_mask(); 1.9 +} 1.10 + 1.11 +const RegMask Matcher::mathExactI_flags_proj_mask() { 1.12 + return INT_FLAGS_mask(); 1.13 +} 1.14 + 1.15 // Returns true if the high 32 bits of the value is known to be zero. 1.16 bool is_operand_hi32_zero(Node* n) { 1.17 int opc = n->Opcode(); 1.18 @@ -4922,6 +4930,8 @@ 1.19 greater_equal(0xD, "ge"); 1.20 less_equal(0xE, "le"); 1.21 greater(0xF, "g"); 1.22 + overflow(0x0, "o"); 1.23 + no_overflow(0x1, "no"); 1.24 %} 1.25 %} 1.26 1.27 @@ -4939,6 +4949,8 @@ 1.28 greater_equal(0x3, "nb"); 1.29 less_equal(0x6, "be"); 1.30 greater(0x7, "nbe"); 1.31 + overflow(0x0, "o"); 1.32 + no_overflow(0x1, "no"); 1.33 %} 1.34 %} 1.35 1.36 @@ -4957,6 +4969,8 @@ 1.37 greater_equal(0x3, "nb"); 1.38 less_equal(0x6, "be"); 1.39 greater(0x7, "nbe"); 1.40 + overflow(0x0, "o"); 1.41 + no_overflow(0x1, "no"); 1.42 %} 1.43 %} 1.44 1.45 @@ -4974,6 +4988,8 @@ 1.46 greater_equal(0x3, "nb"); 1.47 less_equal(0x6, "be"); 1.48 greater(0x7, "nbe"); 1.49 + overflow(0x0, "o"); 1.50 + no_overflow(0x1, "no"); 1.51 %} 1.52 %} 1.53 1.54 @@ -4981,6 +4997,8 @@ 1.55 operand cmpOp_fcmov() %{ 1.56 match(Bool); 1.57 1.58 + predicate(n->as_Bool()->_test._test != BoolTest::overflow && 1.59 + n->as_Bool()->_test._test != BoolTest::no_overflow); 1.60 format %{ "" %} 1.61 interface(COND_INTER) %{ 1.62 equal (0x0C8); 1.63 @@ -4989,6 +5007,8 @@ 1.64 greater_equal(0x1C0); 1.65 less_equal (0x0D0); 1.66 greater (0x1D0); 1.67 + overflow(0x0, "o"); // not really supported by the instruction 1.68 + no_overflow(0x1, "no"); // not really supported by the instruction 1.69 %} 1.70 %} 1.71 1.72 @@ -5004,6 +5024,8 @@ 1.73 greater_equal(0xE, "le"); 1.74 less_equal(0xD, "ge"); 1.75 greater(0xC, "l"); 1.76 + overflow(0x0, "o"); 1.77 + no_overflow(0x1, "no"); 1.78 %} 1.79 %} 1.80 1.81 @@ -7496,6 +7518,31 @@ 1.82 1.83 //----------Arithmetic Instructions-------------------------------------------- 1.84 //----------Addition Instructions---------------------------------------------- 1.85 + 1.86 +instruct addExactI_rReg(eAXRegI dst, rRegI src, eFlagsReg cr) 1.87 +%{ 1.88 + match(AddExactI dst src); 1.89 + effect(DEF cr); 1.90 + 1.91 + format %{ "ADD $dst, $src\t# addExact int" %} 1.92 + ins_encode %{ 1.93 + __ addl($dst$$Register, $src$$Register); 1.94 + %} 1.95 + ins_pipe(ialu_reg_reg); 1.96 +%} 1.97 + 1.98 +instruct addExactI_rReg_imm(eAXRegI dst, immI src, eFlagsReg cr) 1.99 +%{ 1.100 + match(AddExactI dst src); 1.101 + effect(DEF cr); 1.102 + 1.103 + format %{ "ADD $dst, $src\t# addExact int" %} 1.104 + ins_encode %{ 1.105 + __ addl($dst$$Register, $src$$constant); 1.106 + %} 1.107 + ins_pipe(ialu_reg_reg); 1.108 +%} 1.109 + 1.110 // Integer Addition Instructions 1.111 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ 1.112 match(Set dst (AddI dst src));