src/cpu/sparc/vm/vm_version_sparc.cpp

changeset 6312
04d32e7fad07
parent 6198
55fb97c4c58d
child 6653
03214612e77e
     1.1 --- a/src/cpu/sparc/vm/vm_version_sparc.cpp	Fri Feb 14 16:17:22 2014 +0100
     1.2 +++ b/src/cpu/sparc/vm/vm_version_sparc.cpp	Tue Jan 14 17:46:48 2014 -0800
     1.3 @@ -234,7 +234,7 @@
     1.4    assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
     1.5  
     1.6    char buf[512];
     1.7 -  jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
     1.8 +  jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
     1.9                 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
    1.10                 (has_hardware_popc() ? ", popc" : ""),
    1.11                 (has_vis1() ? ", vis1" : ""),
    1.12 @@ -242,6 +242,7 @@
    1.13                 (has_vis3() ? ", vis3" : ""),
    1.14                 (has_blk_init() ? ", blk_init" : ""),
    1.15                 (has_cbcond() ? ", cbcond" : ""),
    1.16 +               (has_aes() ? ", aes" : ""),
    1.17                 (is_ultra3() ? ", ultra3" : ""),
    1.18                 (is_sun4v() ? ", sun4v" : ""),
    1.19                 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
    1.20 @@ -265,6 +266,41 @@
    1.21    if (!has_vis1()) // Drop to 0 if no VIS1 support
    1.22      UseVIS = 0;
    1.23  
    1.24 +  // T2 and above should have support for AES instructions
    1.25 +  if (has_aes()) {
    1.26 +    if (UseVIS > 0) { // AES intrinsics use FXOR instruction which is VIS1
    1.27 +      if (FLAG_IS_DEFAULT(UseAES)) {
    1.28 +        FLAG_SET_DEFAULT(UseAES, true);
    1.29 +      }
    1.30 +      if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
    1.31 +        FLAG_SET_DEFAULT(UseAESIntrinsics, true);
    1.32 +      }
    1.33 +      // we disable both the AES flags if either of them is disabled on the command line
    1.34 +      if (!UseAES || !UseAESIntrinsics) {
    1.35 +        FLAG_SET_DEFAULT(UseAES, false);
    1.36 +        FLAG_SET_DEFAULT(UseAESIntrinsics, false);
    1.37 +      }
    1.38 +    } else {
    1.39 +        if (UseAES || UseAESIntrinsics) {
    1.40 +          warning("SPARC AES intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
    1.41 +          if (UseAES) {
    1.42 +            FLAG_SET_DEFAULT(UseAES, false);
    1.43 +          }
    1.44 +          if (UseAESIntrinsics) {
    1.45 +            FLAG_SET_DEFAULT(UseAESIntrinsics, false);
    1.46 +          }
    1.47 +        }
    1.48 +    }
    1.49 +  } else if (UseAES || UseAESIntrinsics) {
    1.50 +    warning("AES instructions are not available on this CPU");
    1.51 +    if (UseAES) {
    1.52 +      FLAG_SET_DEFAULT(UseAES, false);
    1.53 +    }
    1.54 +    if (UseAESIntrinsics) {
    1.55 +      FLAG_SET_DEFAULT(UseAESIntrinsics, false);
    1.56 +    }
    1.57 +  }
    1.58 +
    1.59    if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
    1.60      (cache_line_size > ContendedPaddingWidth))
    1.61      ContendedPaddingWidth = cache_line_size;

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