1.1 --- a/src/cpu/sparc/vm/assembler_sparc.hpp Fri Feb 14 16:17:22 2014 +0100
1.2 +++ b/src/cpu/sparc/vm/assembler_sparc.hpp Tue Jan 14 17:46:48 2014 -0800
1.3 @@ -88,6 +88,7 @@
1.4 orncc_op3 = 0x16,
1.5 xnorcc_op3 = 0x17,
1.6 addccc_op3 = 0x18,
1.7 + aes4_op3 = 0x19,
1.8 umulcc_op3 = 0x1a,
1.9 smulcc_op3 = 0x1b,
1.10 subccc_op3 = 0x1c,
1.11 @@ -121,6 +122,8 @@
1.12 fpop1_op3 = 0x34,
1.13 fpop2_op3 = 0x35,
1.14 impdep1_op3 = 0x36,
1.15 + aes3_op3 = 0x36,
1.16 + flog3_op3 = 0x36,
1.17 impdep2_op3 = 0x37,
1.18 jmpl_op3 = 0x38,
1.19 rett_op3 = 0x39,
1.20 @@ -172,41 +175,56 @@
1.21
1.22 enum opfs {
1.23 // selected opfs
1.24 - fmovs_opf = 0x01,
1.25 - fmovd_opf = 0x02,
1.26 + fmovs_opf = 0x01,
1.27 + fmovd_opf = 0x02,
1.28
1.29 - fnegs_opf = 0x05,
1.30 - fnegd_opf = 0x06,
1.31 + fnegs_opf = 0x05,
1.32 + fnegd_opf = 0x06,
1.33
1.34 - fadds_opf = 0x41,
1.35 - faddd_opf = 0x42,
1.36 - fsubs_opf = 0x45,
1.37 - fsubd_opf = 0x46,
1.38 + fadds_opf = 0x41,
1.39 + faddd_opf = 0x42,
1.40 + fsubs_opf = 0x45,
1.41 + fsubd_opf = 0x46,
1.42
1.43 - fmuls_opf = 0x49,
1.44 - fmuld_opf = 0x4a,
1.45 - fdivs_opf = 0x4d,
1.46 - fdivd_opf = 0x4e,
1.47 + fmuls_opf = 0x49,
1.48 + fmuld_opf = 0x4a,
1.49 + fdivs_opf = 0x4d,
1.50 + fdivd_opf = 0x4e,
1.51
1.52 - fcmps_opf = 0x51,
1.53 - fcmpd_opf = 0x52,
1.54 + fcmps_opf = 0x51,
1.55 + fcmpd_opf = 0x52,
1.56
1.57 - fstox_opf = 0x81,
1.58 - fdtox_opf = 0x82,
1.59 - fxtos_opf = 0x84,
1.60 - fxtod_opf = 0x88,
1.61 - fitos_opf = 0xc4,
1.62 - fdtos_opf = 0xc6,
1.63 - fitod_opf = 0xc8,
1.64 - fstod_opf = 0xc9,
1.65 - fstoi_opf = 0xd1,
1.66 - fdtoi_opf = 0xd2,
1.67 + fstox_opf = 0x81,
1.68 + fdtox_opf = 0x82,
1.69 + fxtos_opf = 0x84,
1.70 + fxtod_opf = 0x88,
1.71 + fitos_opf = 0xc4,
1.72 + fdtos_opf = 0xc6,
1.73 + fitod_opf = 0xc8,
1.74 + fstod_opf = 0xc9,
1.75 + fstoi_opf = 0xd1,
1.76 + fdtoi_opf = 0xd2,
1.77
1.78 - mdtox_opf = 0x110,
1.79 - mstouw_opf = 0x111,
1.80 - mstosw_opf = 0x113,
1.81 - mxtod_opf = 0x118,
1.82 - mwtos_opf = 0x119
1.83 + mdtox_opf = 0x110,
1.84 + mstouw_opf = 0x111,
1.85 + mstosw_opf = 0x113,
1.86 + mxtod_opf = 0x118,
1.87 + mwtos_opf = 0x119,
1.88 +
1.89 + aes_kexpand0_opf = 0x130,
1.90 + aes_kexpand2_opf = 0x131
1.91 + };
1.92 +
1.93 + enum op5s {
1.94 + aes_eround01_op5 = 0x00,
1.95 + aes_eround23_op5 = 0x01,
1.96 + aes_dround01_op5 = 0x02,
1.97 + aes_dround23_op5 = 0x03,
1.98 + aes_eround01_l_op5 = 0x04,
1.99 + aes_eround23_l_op5 = 0x05,
1.100 + aes_dround01_l_op5 = 0x06,
1.101 + aes_dround23_l_op5 = 0x07,
1.102 + aes_kexpand1_op5 = 0x08
1.103 };
1.104
1.105 enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez };
1.106 @@ -427,6 +445,7 @@
1.107 static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); }
1.108 static int opf_low6( int w) { return u_field(w, 10, 5); }
1.109 static int opf_low5( int w) { return u_field(w, 9, 5); }
1.110 + static int op5( int x) { return u_field(x, 8, 5); }
1.111 static int trapcc( CC cc) { return u_field(cc, 12, 11); }
1.112 static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit
1.113 static int opf( int x) { return u_field(x, 13, 5); }
1.114 @@ -451,6 +470,7 @@
1.115 static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); };
1.116 static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
1.117 static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); };
1.118 + static int fs3(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 13, 9); };
1.119
1.120 // some float instructions use this encoding on the op3 field
1.121 static int alt_op3(int op, FloatRegisterImpl::Width w) {
1.122 @@ -559,6 +579,12 @@
1.123 return x & ((1 << 10) - 1);
1.124 }
1.125
1.126 + // AES crypto instructions supported only on certain processors
1.127 + static void aes_only() { assert( VM_Version::has_aes(), "This instruction only works on SPARC with AES instructions support"); }
1.128 +
1.129 + // instruction only in VIS1
1.130 + static void vis1_only() { assert( VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); }
1.131 +
1.132 // instruction only in VIS3
1.133 static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
1.134
1.135 @@ -682,6 +708,24 @@
1.136 void addccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.137
1.138
1.139 + // 4-operand AES instructions
1.140 +
1.141 + void aes_eround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_op5) | fs2(s2, FloatRegisterImpl::D) ); }
1.142 + void aes_eround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_op5) | fs2(s2, FloatRegisterImpl::D) ); }
1.143 + void aes_dround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_op5) | fs2(s2, FloatRegisterImpl::D) ); }
1.144 + void aes_dround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_op5) | fs2(s2, FloatRegisterImpl::D) ); }
1.145 + void aes_eround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
1.146 + void aes_eround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
1.147 + void aes_dround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
1.148 + void aes_dround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
1.149 + void aes_kexpand1( FloatRegister s1, FloatRegister s2, int imm5a, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | u_field(imm5a, 13, 9) | op5(aes_kexpand1_op5) | fs2(s2, FloatRegisterImpl::D) ); }
1.150 +
1.151 +
1.152 + // 3-operand AES instructions
1.153 +
1.154 + void aes_kexpand0( FloatRegister s1, FloatRegister s2, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand0_opf) | fs2(s2, FloatRegisterImpl::D) ); }
1.155 + void aes_kexpand2( FloatRegister s1, FloatRegister s2, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand2_opf) | fs2(s2, FloatRegisterImpl::D) ); }
1.156 +
1.157 // pp 136
1.158
1.159 inline void bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none);
1.160 @@ -784,6 +828,10 @@
1.161 void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); }
1.162 void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w)); }
1.163
1.164 + // FXORs/FXORd instructions
1.165 +
1.166 + void fxor( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(flog3_op3) | fs1(s1, w) | opf(0x6E - w) | fs2(s2, w)); }
1.167 +
1.168 // pp 164
1.169
1.170 void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); }
