1.1 --- a/src/cpu/mips/vm/macroAssembler_mips.cpp Thu Nov 16 17:27:00 2017 +0800
1.2 +++ b/src/cpu/mips/vm/macroAssembler_mips.cpp Mon Nov 13 15:49:42 2017 +0800
1.3 @@ -117,13 +117,10 @@
1.4 && special(pc[5]) == daddu_op)) { tty->print_cr("Not a branch label patch"); }
1.5
1.6 int offset = target - branch;
1.7 - if (!is_simm16(offset))
1.8 - {
1.9 + if (!is_simm16(offset)) {
1.10 pc[3] = (pc[3] & 0xffff0000) | high16(offset - 12);
1.11 pc[4] = (pc[4] & 0xffff0000) | low16(offset - 12);
1.12 - }
1.13 - else
1.14 - {
1.15 + } else {
1.16 /* revert to "beq + nop" */
1.17 CodeBuffer cb(branch, 4 * 10);
1.18 MacroAssembler masm(&cb);
1.19 @@ -141,12 +138,10 @@
1.20 }
1.21
1.22 #ifndef PRODUCT
1.23 - if (!is_simm16((target - branch - 4) >> 2))
1.24 - {
1.25 + if (!is_simm16((target - branch - 4) >> 2)) {
1.26 tty->print_cr("Illegal patching: target=0x%lx", target);
1.27 int *p = (int *)branch;
1.28 - for (int i = -10; i < 10; i++)
1.29 - {
1.30 + for (int i = -10; i < 10; i++) {
1.31 tty->print("0x%lx, ", p[i]);
1.32 }
1.33 tty->print_cr("");
1.34 @@ -265,17 +260,13 @@
1.35 return 6;
1.36 }
1.37
1.38 -void MacroAssembler::beq_far(Register rs, Register rt, address entry)
1.39 -{
1.40 +void MacroAssembler::beq_far(Register rs, Register rt, address entry) {
1.41 u_char * cur_pc = pc();
1.42
1.43 /* Jin: Near/Far jump */
1.44 - if(is_simm16((entry - pc() - 4) / 4))
1.45 - {
1.46 + if(is_simm16((entry - pc() - 4) / 4)) {
1.47 Assembler::beq(rs, rt, offset(entry));
1.48 - }
1.49 - else
1.50 - {
1.51 + } else {
1.52 Label not_jump;
1.53 bne(rs, rt, not_jump);
1.54 delayed()->nop();
1.55 @@ -288,8 +279,7 @@
1.56 }
1.57 }
1.58
1.59 -void MacroAssembler::beq_far(Register rs, Register rt, Label& L)
1.60 -{
1.61 +void MacroAssembler::beq_far(Register rs, Register rt, Label& L) {
1.62 if (L.is_bound()) {
1.63 beq_far(rs, rt, target(L));
1.64 } else {
1.65 @@ -306,17 +296,13 @@
1.66 }
1.67 }
1.68
1.69 -void MacroAssembler::bne_far(Register rs, Register rt, address entry)
1.70 -{
1.71 +void MacroAssembler::bne_far(Register rs, Register rt, address entry) {
1.72 u_char * cur_pc = pc();
1.73
1.74 /* Jin: Near/Far jump */
1.75 - if(is_simm16((entry - pc() - 4) / 4))
1.76 - {
1.77 + if(is_simm16((entry - pc() - 4) / 4)) {
1.78 Assembler::bne(rs, rt, offset(entry));
1.79 - }
1.80 - else
1.81 - {
1.82 + } else {
1.83 Label not_jump;
1.84 beq(rs, rt, not_jump);
1.85 delayed()->nop();
1.86 @@ -329,8 +315,7 @@
1.87 }
1.88 }
1.89
1.90 -void MacroAssembler::bne_far(Register rs, Register rt, Label& L)
1.91 -{
1.92 +void MacroAssembler::bne_far(Register rs, Register rt, Label& L) {
1.93 if (L.is_bound()) {
1.94 bne_far(rs, rt, target(L));
1.95 } else {
1.96 @@ -347,12 +332,11 @@
1.97 }
1.98 }
1.99
1.100 -void MacroAssembler::b_far(Label& L)
1.101 -{
1.102 +void MacroAssembler::b_far(Label& L) {
1.103 if (L.is_bound()) {
1.104 b_far(target(L));
1.105 } else {
1.106 - volatile address dest = target(L);
1.107 + volatile address dest = target(L);
1.108 /*
1.109 MacroAssembler::pd_patch_instruction branch=55651ed514, target=55651ef6d8
1.110 0x00000055651ed514: dadd at, ra, zero
1.111 @@ -366,31 +350,27 @@
1.112 0x00000055651ed530: jr t9
1.113 0x00000055651ed534: sll zero, zero, 0
1.114 */
1.115 - move(AT, RA);
1.116 - emit_long(insn_ORRI(regimm_op, 0, bgezal_op, 1));
1.117 - nop();
1.118 - lui(T9, 0); // to be patched
1.119 - ori(T9, T9, 0);
1.120 - daddu(T9, T9, RA);
1.121 - move(RA, AT);
1.122 - jr(T9);
1.123 + move(AT, RA);
1.124 + emit_long(insn_ORRI(regimm_op, 0, bgezal_op, 1));
1.125 + nop();
1.126 + lui(T9, 0); // to be patched
1.127 + ori(T9, T9, 0);
1.128 + daddu(T9, T9, RA);
1.129 + move(RA, AT);
1.130 + jr(T9);
1.131 }
1.132 }
1.133
1.134 -void MacroAssembler::b_far(address entry)
1.135 -{
1.136 +void MacroAssembler::b_far(address entry) {
1.137 u_char * cur_pc = pc();
1.138
1.139 /* Jin: Near/Far jump */
1.140 - if(is_simm16((entry - pc() - 4) / 4))
1.141 - {
1.142 + if(is_simm16((entry - pc() - 4) / 4)) {
1.143 b(offset(entry));
1.144 - }
1.145 - else
1.146 - {
1.147 + } else {
1.148 /* address must be bounded */
1.149 move(AT, RA);
1.150 - emit_long(insn_ORRI(regimm_op, 0, bgezal_op, 1));
1.151 + emit_long(insn_ORRI(regimm_op, 0, bgezal_op, 1));
1.152 nop();
1.153 li32(T9, entry - pc());
1.154 daddu(T9, T9, RA);
1.155 @@ -721,13 +701,9 @@
1.156 delayed()->nop();
1.157 }
1.158
1.159 -// NOTE: we dont increment the SP after call like the x86 version, maybe this is a problem, FIXME.
1.160 // the stack pointer adjustment is needed. see InterpreterMacroAssembler::super_call_VM_leaf
1.161 // this method will handle the stack problem, you need not to preserve the stack space for the argument now
1.162 -void MacroAssembler::call_VM_leaf_base(address entry_point,
1.163 - int number_of_arguments) {
1.164 - //call(RuntimeAddress(entry_point));
1.165 - //increment(rsp, number_of_arguments * wordSize);
1.166 +void MacroAssembler::call_VM_leaf_base(address entry_point, int number_of_arguments) {
1.167 Label L, E;
1.168
1.169 assert(number_of_arguments <= 4, "just check");
1.170 @@ -1158,7 +1134,7 @@
1.171 Register last_java_sp,
1.172 address entry_point,
1.173 int number_of_arguments,
1.174 - bool check_exceptions) {
1.175 + bool check_exceptions) {
1.176
1.177 address before_call_pc;
1.178 // determine java_thread register
1.179 @@ -1190,6 +1166,7 @@
1.180 move(A0, java_thread);
1.181 call(entry_point, relocInfo::runtime_call_type);
1.182 delayed()->nop();
1.183 + //MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
1.184
1.185 // restore the thread (cannot use the pushed argument since arguments
1.186 // may be overwritten by C code generated by an optimizing compiler);
1.187 @@ -1203,7 +1180,7 @@
1.188 get_thread(AT);
1.189 beq(java_thread, AT, L);
1.190 delayed()->nop();
1.191 - stop("MacroAssembler::call_VM_base: edi not callee saved?");
1.192 + stop("MacroAssembler::call_VM_base: TREG not callee saved?");
1.193 bind(L);
1.194 }
1.195 #endif
1.196 @@ -1474,7 +1451,6 @@
1.197 sd(last_java_sp, Address(thread, JavaThread::last_Java_sp_offset()));
1.198 }
1.199
1.200 -
1.201 //////////////////////////////////////////////////////////////////////////////////
1.202 #if INCLUDE_ALL_GCS
1.203
1.204 @@ -1621,7 +1597,7 @@
1.205 dsrl(AT, AT, HeapRegion::LogOfHRGrainBytes);
1.206 beq(AT, R0, done);
1.207 nop();
1.208 -
1.209 +
1.210
1.211 // crosses regions, storing NULL?
1.212 beq(new_val, R0, done);
1.213 @@ -1652,7 +1628,7 @@
1.214
1.215 // storing a region crossing, non-NULL oop, card is clean.
1.216 // dirty card and log.
1.217 - move(AT, (int)CardTableModRefBS::dirty_card_val());
1.218 + move(AT, (int)CardTableModRefBS::dirty_card_val());
1.219 sb(AT, card_addr, 0);
1.220
1.221 lw(AT, queue_index);
1.222 @@ -3219,23 +3195,23 @@
1.223 //for UseCompressedOops Option
1.224 void MacroAssembler::load_klass(Register dst, Register src) {
1.225 #ifdef _LP64
1.226 - if(UseCompressedClassPointers){
1.227 - lwu(dst, Address(src, oopDesc::klass_offset_in_bytes()));
1.228 - decode_klass_not_null(dst);
1.229 - } else
1.230 + if(UseCompressedClassPointers){
1.231 + lwu(dst, Address(src, oopDesc::klass_offset_in_bytes()));
1.232 + decode_klass_not_null(dst);
1.233 + } else
1.234 #endif
1.235 - ld(dst, src, oopDesc::klass_offset_in_bytes());
1.236 + ld(dst, src, oopDesc::klass_offset_in_bytes());
1.237 }
1.238
1.239 void MacroAssembler::store_klass(Register dst, Register src) {
1.240 #ifdef _LP64
1.241 - if(UseCompressedClassPointers){
1.242 + if(UseCompressedClassPointers){
1.243 encode_klass_not_null(src);
1.244 sw(src, dst, oopDesc::klass_offset_in_bytes());
1.245 - } else {
1.246 + } else {
1.247 #endif
1.248 sd(src, dst, oopDesc::klass_offset_in_bytes());
1.249 - }
1.250 + }
1.251 }
1.252
1.253 void MacroAssembler::load_prototype_header(Register dst, Register src) {
1.254 @@ -3251,30 +3227,30 @@
1.255 }
1.256
1.257 void MacroAssembler::load_heap_oop(Register dst, Address src) {
1.258 - if(UseCompressedOops){
1.259 - lwu(dst, src);
1.260 - decode_heap_oop(dst);
1.261 - } else{
1.262 - ld(dst, src);
1.263 - }
1.264 + if(UseCompressedOops){
1.265 + lwu(dst, src);
1.266 + decode_heap_oop(dst);
1.267 + } else {
1.268 + ld(dst, src);
1.269 + }
1.270 }
1.271
1.272 void MacroAssembler::store_heap_oop(Address dst, Register src){
1.273 - if(UseCompressedOops){
1.274 - assert(!dst.uses(src), "not enough registers");
1.275 - encode_heap_oop(src);
1.276 - sw(src, dst);
1.277 - } else{
1.278 - sd(src, dst);
1.279 - }
1.280 + if(UseCompressedOops){
1.281 + assert(!dst.uses(src), "not enough registers");
1.282 + encode_heap_oop(src);
1.283 + sw(src, dst);
1.284 + } else {
1.285 + sd(src, dst);
1.286 + }
1.287 }
1.288
1.289 void MacroAssembler::store_heap_oop_null(Address dst){
1.290 - if(UseCompressedOops){
1.291 - sw(R0, dst);
1.292 - } else{
1.293 - sd(R0, dst);
1.294 - }
1.295 + if(UseCompressedOops){
1.296 + sw(R0, dst);
1.297 + } else {
1.298 + sd(R0, dst);
1.299 + }
1.300 }
1.301
1.302 #ifdef ASSERT
1.303 @@ -3299,12 +3275,12 @@
1.304 return;
1.305 }
1.306
1.307 - movz(r, S5_heapbase, r);
1.308 - dsub(r, r, S5_heapbase);
1.309 - if (Universe::narrow_oop_shift() != 0) {
1.310 - assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
1.311 - shr(r, LogMinObjAlignmentInBytes);
1.312 - }
1.313 + movz(r, S5_heapbase, r);
1.314 + dsub(r, r, S5_heapbase);
1.315 + if (Universe::narrow_oop_shift() != 0) {
1.316 + assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
1.317 + shr(r, LogMinObjAlignmentInBytes);
1.318 + }
1.319 }
1.320
1.321 void MacroAssembler::encode_heap_oop(Register dst, Register src) {
1.322 @@ -3339,15 +3315,15 @@
1.323 }
1.324
1.325 void MacroAssembler::encode_heap_oop_not_null(Register r) {
1.326 - assert (UseCompressedOops, "should be compressed");
1.327 + assert (UseCompressedOops, "should be compressed");
1.328 #ifdef ASSERT
1.329 - if (CheckCompressedOops) {
1.330 - Label ok;
1.331 - bne(r, R0, ok);
1.332 - delayed()->nop();
1.333 - stop("null oop passed to encode_heap_oop_not_null");
1.334 - bind(ok);
1.335 - }
1.336 + if (CheckCompressedOops) {
1.337 + Label ok;
1.338 + bne(r, R0, ok);
1.339 + delayed()->nop();
1.340 + stop("null oop passed to encode_heap_oop_not_null");
1.341 + bind(ok);
1.342 + }
1.343 #endif
1.344 verify_oop(r, "broken oop in encode_heap_oop_not_null");
1.345 if (Universe::narrow_oop_base() != NULL) {
1.346 @@ -3361,32 +3337,32 @@
1.347 }
1.348
1.349 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
1.350 - assert (UseCompressedOops, "should be compressed");
1.351 + assert (UseCompressedOops, "should be compressed");
1.352 #ifdef ASSERT
1.353 - if (CheckCompressedOops) {
1.354 - Label ok;
1.355 - bne(src, R0, ok);
1.356 - delayed()->nop();
1.357 - stop("null oop passed to encode_heap_oop_not_null2");
1.358 - bind(ok);
1.359 + if (CheckCompressedOops) {
1.360 + Label ok;
1.361 + bne(src, R0, ok);
1.362 + delayed()->nop();
1.363 + stop("null oop passed to encode_heap_oop_not_null2");
1.364 + bind(ok);
1.365 + }
1.366 +#endif
1.367 + verify_oop(src, "broken oop in encode_heap_oop_not_null2");
1.368 +
1.369 + if (Universe::narrow_oop_base() != NULL) {
1.370 + dsub(dst, src, S5_heapbase);
1.371 + if (Universe::narrow_oop_shift() != 0) {
1.372 + assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
1.373 + shr(dst, LogMinObjAlignmentInBytes);
1.374 }
1.375 -#endif
1.376 - verify_oop(src, "broken oop in encode_heap_oop_not_null2");
1.377 -
1.378 - if (Universe::narrow_oop_base() != NULL) {
1.379 - dsub(dst, src, S5_heapbase);
1.380 - if (Universe::narrow_oop_shift() != 0) {
1.381 - assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
1.382 - shr(dst, LogMinObjAlignmentInBytes);
1.383 - }
1.384 + } else {
1.385 + if (Universe::narrow_oop_shift() != 0) {
1.386 + assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
1.387 + dsrl(dst, src, LogMinObjAlignmentInBytes);
1.388 } else {
1.389 - if (Universe::narrow_oop_shift() != 0) {
1.390 - assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
1.391 - dsrl(dst, src, LogMinObjAlignmentInBytes);
1.392 - } else {
1.393 - if (dst != src) move(dst, src);
1.394 - }
1.395 + if (dst != src) move(dst, src);
1.396 }
1.397 + }
1.398 }
1.399
1.400 void MacroAssembler::decode_heap_oop(Register r) {
1.401 @@ -3500,10 +3476,6 @@
1.402 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
1.403 shr(r, LogKlassAlignmentInBytes);
1.404 }
1.405 - // Not neccessary for MIPS at all.
1.406 - //if (Universe::narrow_klass_base() != NULL) {
1.407 - // reinit_heapbase();
1.408 - //}
1.409 }
1.410
1.411 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
1.412 @@ -3609,7 +3581,7 @@
1.413 if (value < 0) { incrementl(reg, -value); return; }
1.414 if (value == 0) { ; return; }
1.415
1.416 - if(Assembler::is_simm16(value)) {
1.417 + if (Assembler::is_simm16(value)) {
1.418 NOT_LP64(addiu(reg, reg, -value));
1.419 LP64_ONLY(move(AT, value); subu32(reg, reg, AT));
1.420 } else {
1.421 @@ -3686,14 +3658,12 @@
1.422 // We move this check to the front of the fast path because many
1.423 // type checks are in fact trivially successful in this manner,
1.424 // so we get a nicely predicted branch right at the start of the check.
1.425 - //cmpptr(sub_klass, super_klass);
1.426 - //local_jcc(Assembler::equal, *L_success);
1.427 beq(sub_klass, super_klass, *L_success);
1.428 delayed()->nop();
1.429 // Check the supertype display:
1.430 if (must_load_sco) {
1.431 // Positive movl does right thing on LP64.
1.432 - lwu(temp_reg, super_klass, sco_offset);
1.433 + lwu(temp_reg, super_klass, sco_offset);
1.434 super_check_offset = RegisterOrConstant(temp_reg);
1.435 }
1.436 dsll(AT, super_check_offset.register_or_noreg(), Address::times_1);
1.437 @@ -3712,39 +3682,39 @@
1.438 // Otherwise, it's the slow path for us (no success at this point).
1.439
1.440 if (super_check_offset.is_register()) {
1.441 - beq(super_klass, AT, *L_success);
1.442 - delayed()->nop();
1.443 - addi(AT, super_check_offset.as_register(), -sc_offset);
1.444 + beq(super_klass, AT, *L_success);
1.445 + delayed()->nop();
1.446 + addi(AT, super_check_offset.as_register(), -sc_offset);
1.447 if (L_failure == &L_fallthrough) {
1.448 - beq(AT, R0, *L_slow_path);
1.449 - delayed()->nop();
1.450 + beq(AT, R0, *L_slow_path);
1.451 + delayed()->nop();
1.452 } else {
1.453 - bne(AT, R0, *L_failure);
1.454 - delayed()->nop();
1.455 - b(*L_slow_path);
1.456 - delayed()->nop();
1.457 + bne(AT, R0, *L_failure);
1.458 + delayed()->nop();
1.459 + b(*L_slow_path);
1.460 + delayed()->nop();
1.461 }
1.462 } else if (super_check_offset.as_constant() == sc_offset) {
1.463 // Need a slow path; fast failure is impossible.
1.464 if (L_slow_path == &L_fallthrough) {
1.465 - beq(super_klass, AT, *L_success);
1.466 - delayed()->nop();
1.467 + beq(super_klass, AT, *L_success);
1.468 + delayed()->nop();
1.469 } else {
1.470 - bne(super_klass, AT, *L_slow_path);
1.471 - delayed()->nop();
1.472 - b(*L_success);
1.473 - delayed()->nop();
1.474 + bne(super_klass, AT, *L_slow_path);
1.475 + delayed()->nop();
1.476 + b(*L_success);
1.477 + delayed()->nop();
1.478 }
1.479 } else {
1.480 // No slow path; it's a fast decision.
1.481 if (L_failure == &L_fallthrough) {
1.482 - beq(super_klass, AT, *L_success);
1.483 - delayed()->nop();
1.484 + beq(super_klass, AT, *L_success);
1.485 + delayed()->nop();
1.486 } else {
1.487 - bne(super_klass, AT, *L_failure);
1.488 - delayed()->nop();
1.489 - b(*L_success);
1.490 - delayed()->nop();
1.491 + bne(super_klass, AT, *L_failure);
1.492 + delayed()->nop();
1.493 + b(*L_success);
1.494 + delayed()->nop();
1.495 }
1.496 }
1.497
1.498 @@ -3784,18 +3754,11 @@
1.499 // The repne_scan instruction uses fixed registers, which we must spill.
1.500 // Don't worry too much about pre-existing connections with the input regs.
1.501
1.502 -#if 0
1.503 - assert(sub_klass != T9, "killed reg"); // killed by mov(rax, super)
1.504 - assert(sub_klass != T1, "killed reg"); // killed by lea(rcx, &pst_counter)
1.505 -#endif
1.506 -
1.507 // Get super_klass value into rax (even if it was in rdi or rcx).
1.508 #ifndef PRODUCT
1.509 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
1.510 ExternalAddress pst_counter_addr((address) pst_counter);
1.511 NOT_LP64( incrementl(pst_counter_addr) );
1.512 - //LP64_ONLY( lea(rcx, pst_counter_addr) );
1.513 - //LP64_ONLY( incrementl(Address(rcx, 0)) );
1.514 #endif //PRODUCT
1.515
1.516 // We will consult the secondary-super array.
1.517 @@ -3834,6 +3797,7 @@
1.518
1.519 bind(L_fallthrough);
1.520 }
1.521 +
1.522 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
1.523 ld(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
1.524 sd(R0, Address(java_thread, JavaThread::vm_result_offset()));
1.525 @@ -3949,7 +3913,6 @@
1.526
1.527 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
1.528 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
1.529 -// lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
1.530 if (itable_index.is_constant()) {
1.531 set64(AT, (int)itable_index.is_constant());
1.532 dsll(AT, AT, (int)Address::times_ptr);
1.533 @@ -3959,11 +3922,6 @@
1.534 daddu(AT, AT, recv_klass);
1.535 daddiu(recv_klass, AT, itentry_off);
1.536
1.537 - // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
1.538 - // if (scan->interface() == intf) {
1.539 - // result = (klass + scan->offset() + itable_index);
1.540 - // }
1.541 - // }
1.542 Label search, found_method;
1.543
1.544 for (int peel = 1; peel >= 0; peel--) {
1.545 @@ -3994,7 +3952,6 @@
1.546
1.547 // Got a hit.
1.548 lw(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
1.549 - //ld(method_result, Address(recv_klass, scan_temp, Address::times_1));
1.550 if(UseLoongsonISA) {
1.551 gsldx(method_result, recv_klass, scan_temp, 0);
1.552 } else {
1.553 @@ -4003,7 +3960,6 @@
1.554 }
1.555 }
1.556
1.557 -
1.558 // virtual method calling
1.559 void MacroAssembler::lookup_virtual_method(Register recv_klass,
1.560 RegisterOrConstant vtable_index,
