1.1 --- a/src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp Wed Dec 22 02:02:53 2010 -0800
1.2 +++ b/src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp Mon Dec 27 21:51:31 2010 -0800
1.3 @@ -1705,8 +1705,7 @@
1.4 }
1.5
1.6
1.7 -void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) {
1.8 -
1.9 +void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1.10 Assembler::Condition acond;
1.11 switch (condition) {
1.12 case lir_cond_equal: acond = Assembler::equal; break;
1.13 @@ -1737,7 +1736,12 @@
1.14 ShouldNotReachHere();
1.15 }
1.16 Label skip;
1.17 - __ br(acond, false, Assembler::pt, skip);
1.18 +#ifdef _LP64
1.19 + if (type == T_INT) {
1.20 + __ br(acond, false, Assembler::pt, skip);
1.21 + } else
1.22 +#endif
1.23 + __ brx(acond, false, Assembler::pt, skip); // checks icc on 32bit and xcc on 64bit
1.24 if (opr1->is_constant() && opr1->type() == T_INT) {
1.25 Register dest = result->as_register();
1.26 if (Assembler::is_simm13(opr1->as_jint())) {
1.27 @@ -2688,6 +2692,11 @@
1.28 #ifdef _LP64
1.29 __ mov(cmp_value_lo, t1);
1.30 __ mov(new_value_lo, t2);
1.31 + // perform the compare and swap operation
1.32 + __ casx(addr, t1, t2);
1.33 + // generate condition code - if the swap succeeded, t2 ("new value" reg) was
1.34 + // overwritten with the original value in "addr" and will be equal to t1.
1.35 + __ cmp(t1, t2);
1.36 #else
1.37 // move high and low halves of long values into single registers
1.38 __ sllx(cmp_value_hi, 32, t1); // shift high half into temp reg
1.39 @@ -2696,13 +2705,15 @@
1.40 __ sllx(new_value_hi, 32, t2);
1.41 __ srl(new_value_lo, 0, new_value_lo);
1.42 __ or3(t2, new_value_lo, t2); // t2 holds 64-bit value to swap
1.43 -#endif
1.44 // perform the compare and swap operation
1.45 __ casx(addr, t1, t2);
1.46 // generate condition code - if the swap succeeded, t2 ("new value" reg) was
1.47 // overwritten with the original value in "addr" and will be equal to t1.
1.48 - __ cmp(t1, t2);
1.49 -
1.50 + // Produce icc flag for 32bit.
1.51 + __ sub(t1, t2, t2);
1.52 + __ srlx(t2, 32, t1);
1.53 + __ orcc(t2, t1, G0);
1.54 +#endif
1.55 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
1.56 Register addr = op->addr()->as_pointer_register();
1.57 Register cmp_value = op->cmp_value()->as_register();
